Z86D990 [ZILOG]
Low-Voltage Micro controllers with ADC; 低电压微控制器与ADC
| 型号： | Z86D990 |
| 厂家： | 
ZILOG, INC. |
| 描述： | Low-Voltage Micro controllers with ADC |
| 文件： | 总102页 (文件大小：1522K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Z86D990/Z86D991 OTP and
Z86L99X ROM
Low-Voltage Micro-
controllers with ADC
Preliminary Product Specification
PS003807-1002
ZiLOG Worldwide Headquarters • 532 Race Street • San Jose, CA 95126-3432
Telephone: 408.558.8500 • Fax: 408.558.8300 • www.ZiLOG.com
This publication is subject to replacement by a later edition. To determine whether
a later edition exists, or to request copies of publications, contact:
ZiLOG Worldwide Headquarters
532 Race Street
San Jose, CA 95126-3432
Telephone: 408.558.8500
Fax: 408.558.8300
www.ZiLOG.com
ZiLOG is a registered trademark of ZiLOG Inc. in the United States and in other countries. All other
products and/or service names mentioned herein may be trademarks of the companies with which
they are associated.
Document Disclaimer
© 2002 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices,
applications, or technology described is intended to suggest possible uses and may be superseded.
ZiLOG, INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF
ACCURACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS
DOCUMENT. ZiLOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY
INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR
TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. Except with the express written approval
ZiLOG, use of information, devices, or technology as critical components of life support systems is
not authorized. No licenses or other rights are conveyed, implicitly or otherwise, by this document
under any intellectual property rights.
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Z86D990/Z86D991 OTP and Z86L99X ROM
Low-Voltage Microcontrollers with ADC
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Table of Contents
Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Counter/Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Input/Output and Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Operating Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
User-Programmable Option Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pins Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Operational Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Central Processing Unit (CPU) Description . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Memory (ROM/OTP and RAM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Clock Circuit Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Reset Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Peripherals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Register Error Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Registers (Grouped by Function) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Standard Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Analog-to-Digital Converter Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 89
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Design Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Precharacterization Product . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
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List of Figures
Figure 1. Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 2. 48-Pin SSOP Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Figure 3. 40-Pin DIP Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Figure 4. 28-Pin SOIC/DIP Pin Assignment—User Mode . . . . . . . . . . . . . . . . 7
Figure 5. Program Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure 6. Standard Z8 Register File (Working Reg. Groups 0–F, Bank 0) . . . 13
Figure 7. Z8 Expanded Register File Architecture . . . . . . . . . . . . . . . . . . . . . 14
Figure 8. Interrupt Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure 9. External Interrupt Sources IRQ0–IRQ2 Block Diagram . . . . . . . . . . 17
Figure 10. IRQ Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 11. Interrupt Request Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 12. General Input/Output Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure 13. Analog Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 14. ADC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 15. Low-Pass Filter (with 8-MHz Crystal) . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 16. Active Glitch/Power Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 17. I-V Characteristics for the Current Sink Pad P43 . . . . . . . . . . . . . . 34
Figure 18. T Counter/Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
1
Figure 19. Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 20. Prescaler 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Figure 21. Counter/Timer 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 22. Timer Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
Figure 23. Starting the Count . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Figure 24. Counting Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 25. Timer Mode Register T
Operation . . . . . . . . . . . . . . . . . . . . . . . 40
OUT
Figure 26. Counter/Timer Output Using T
. . . . . . . . . . . . . . . . . . . . . . . . . 41
. . . . . . . . . . . . . . . . . . . . . . . . . . 41
OUT
Figure 27. Internal Clock Output Using T
OUT
Figure 28. Timer Mode Register T Operation . . . . . . . . . . . . . . . . . . . . . . . . 42
IN
Figure 29. Prescaler 1 T Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
IN
Figure 30. External Clock Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 31. Gated Clock Input Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 32. Triggered Clock Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 33. Counter/Timer Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 34. Transmit Mode Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
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Figure 35. Demodulation Mode Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 36. Test Load Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Figure 37. 48-Pin SSOP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 38. 40-Pin PDIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 39. 28-Pin PDIP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Figure 40. 28-Pin SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
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List of Tables
Table 1. Z86L99/Z86D99 Feature Comparison . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Table 3. Interrupt Types, Sources, and Vectors . . . . . . . . . . . . . . . . . . . . . . 15
Table 4. Interrupt Edge Select for External Interrupts . . . . . . . . . . . . . . . . . . 17
Table 5. Control and Status Register Reset Conditions . . . . . . . . . . . . . . . . 20
Table 6. Clock Status in Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 7. Special Port Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table 8. Active Glitch/Filter Specifications (Preliminary) . . . . . . . . . . . . . . . . 32
Table 9. Current Sink Pad P43 Specifications (Preliminary) . . . . . . . . . . . . . 33
Table 10. I/O Port Registers (Group 0, Bank 0, Registers 0–F) . . . . . . . . . . . 52
Table 11. Timer Control Registers (Group 0, Bank D, Registers 0–F) . . . . . . 53
Table 12. Control and Status Registers (Group F, Bank 0,
Registers 0–F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Table 13. SMR and Port Mode Registers (Group 0, Bank F,
Registers 0–F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 14. Register Description Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Table 15. FLAGS Register [Group/Bank F0h, Register C (R252)] . . . . . . . . . 57
Table 16. RP Register [Group/Bank F0h, Register D (R253)] . . . . . . . . . . . . . 58
Table 17. SP Register [Group/Bank F0h, Register F (R255)] . . . . . . . . . . . . . 59
Table 18. LB Register (Group/Bank 0Dh, Register C) . . . . . . . . . . . . . . . . . . . 60
Table 19. ADCCTRL Register (Group/Bank 0Fh, Register 8) . . . . . . . . . . . . . 61
Table 20. ADCDATA Register (Group/Bank 00h, Register 7) . . . . . . . . . . . . . 62
Table 21. IMR (Group/Bank 0Fh, Register B) . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 22. IPR (Group/Bank 0Fh, Register 9) . . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 23. IRQ (Group/Bank 0Fh, Register A) . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 24. P456CON Register (Group/Bank 0Fh, Register 0) . . . . . . . . . . . . . 67
Table 25. P3M Register [Group/Bank F0h, Register 7 (R247)] . . . . . . . . . . . . 68
Table 26. P2 Register [Group/Bank 00h, Register 2 (R2)] . . . . . . . . . . . . . . . 68
Table 27. P2M Register [Group/Bank F0h, Register 6 (R246)] . . . . . . . . . . . . 68
Table 28. P4 Register [Group/Bank 00h, Register 4 (R4)] . . . . . . . . . . . . . . . 69
Table 29. P4M Register (Group/Bank 0Fh, Register 2) . . . . . . . . . . . . . . . . . . 69
Table 30. P5 Register [Group/Bank 00h, Register 5 (R5)] . . . . . . . . . . . . . . . 70
Table 31. P5M Register (Group/Bank 0Fh, Register 4) . . . . . . . . . . . . . . . . . . 70
Table 32. P6 Register [Group/Bank 00h, Register 6 (R6)] . . . . . . . . . . . . . . . 71
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Table 33. P6M Register (Group/Bank 0Fh, Register 6) . . . . . . . . . . . . . . . . . . 71
Table 34. T1 Register [Group/Bank F0h, Register 2 (R242)] . . . . . . . . . . . . . 72
Table 35. TMR Register [Group/Bank F0h, Register 1 (R241)] . . . . . . . . . . . . 72
Table 36. PRE1 Register [Group/Bank F0h, Register 3 (R243)] . . . . . . . . . . . 73
Table 37. CTR1 Register (In Transmit Mode)
(Group/Bank 0Dh, Register 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Table 38. CTR1 Register (in Demodulation Mode)
(Group/Bank 0Dh, Register 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 39. CTR3 Register (Group/Bank 0Dh, Register 3) . . . . . . . . . . . . . . . . 76
Table 40. CTR0 Register (Group/Bank 0Dh, Register 0) . . . . . . . . . . . . . . . . 77
Table 41. HI8 Register (Group/Bank 0Dh, Register B) . . . . . . . . . . . . . . . . . . 78
Table 42. LO8 Register (Group/Bank 0Dh, Register A) . . . . . . . . . . . . . . . . . . 78
Table 43. TC8H Register (Group/Bank 0Dh, Register 5) . . . . . . . . . . . . . . . . 79
Table 44. TC8L Register (Group/Bank 0Dh, Register 4) . . . . . . . . . . . . . . . . . 79
Table 45. CTR2 Register (Group/Bank 0Dh, Register 2) . . . . . . . . . . . . . . . . 80
Table 46. HI16 Register (Group/Bank 0Dh, Register 9) . . . . . . . . . . . . . . . . . 81
Table 47. LO16 Register (Group/Bank 0Dh, Register 8) . . . . . . . . . . . . . . . . . 81
Table 48. TC16H Register (Group/Bank 0Dh, Register 7) . . . . . . . . . . . . . . . 82
Table 49. TC16L Register (Group/Bank 0Dh, Register 6) . . . . . . . . . . . . . . . . 82
Table 50. SMR Register (Group/Bank 0Fh, Register B) . . . . . . . . . . . . . . . . . 83
Table 51. P2SMR Register (Group/Bank 0Fh, Register 1) . . . . . . . . . . . . . . . 84
Table 52. P5SMR Register (Group/Bank 0Fh, Register 5) . . . . . . . . . . . . . . . 84
Table 53. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 54. DC Characteristics for the Z86D99X (OTP Only) . . . . . . . . . . . . . . 87
Table 55. DC Characteristics for the Z86L99X (Mask Only) . . . . . . . . . . . . . . 88
Table 56. Analog-to-Digital Converter Characteristics . . . . . . . . . . . . . . . . . . . 89
Table 57. AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
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Architectural Overview
®
The Z86D99 is a low-voltage general-purpose one-time programmable (OTP) Z8
microcontroller with an integrated four-channel 8-bit sigma delta analog-to-digital
converter. The Z86L99 is the read-only memory (ROM) version of this controller.
The Z86D99/Z86L99 family is designed to be used in a wide variety of embedded
control applications including battery chargers, home appliances, infrared (IR)
remote controls, security systems, and wireless keyboards.
It has three counter/timers, a general-purpose 8-bit counter/timer with a 6-bit pres-
caler and an 8-bit/16-bit counter/timer pair that can be used individually for gen-
eral-purpose timing or as a pair to automate the generation and reception of
complex pulses or signals. Unique features of the Z86D99/Z86L99 family of prod-
ucts include 489 bytes of general-purpose random-access memory (RAM), 256
bytes of which are mapped into the program memory space and can be used to
store data variables or as executable RAM, a low-battery detection flag, and a
controlled current output pin, which is a regulated current source that sinks a pre-
defined current (I
microcontrollers.
). Table 1 highlights the basic product features of these
CCO
Table 1. Z86L99/Z86D99 Feature Comparison
Memory
(Bytes)
Operating
Voltage (V)
Watch-Dog
Timer
Pins
40/48
28
I/O
32
24
32
24
24
24
ADC
Timers
Z86D990
Z86D991
Z86L990
Z86L991
Z86L996
Z86L997
32K OTP
32K OTP
16K ROM
16K ROM
4K ROM
8K ROM
3.0–5.5
3.0–5.5
2.3–5.5
2.3–5.5
2.3–5.5
2.3–5.5
4 channel
3
3
3
3
3
3
Yes
Yes
Yes
Yes
Yes
Yes
—
40/48
28
4 channel
—
—
—
28
28
The Z8 microcontroller core offers more flexibility and performance than accumu-
lator-based microcontrollers. All 256 general-purpose registers, including dedi-
cated input/output (I/O) port registers, can be used as accumulators. This unique
register-to-register architecture avoids accumulator bottlenecks for high code effi-
ciency. The registers can be used as address pointers for indirect addressing, as
index registers, or for implementing an on-chip stack.
The Z8 has a sophisticated interrupt structure and automatically saves the pro-
gram counter and status flags on the stack for fast context-switching. Speed of
execution and smooth programming are also supported by a “working register
area” with short 4-bit register addresses.
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The Z8 instruction set, consisting of 43 basic instructions, is optimized for high-
code density and reduced execution time. It is similar in form to the ZiLOG Z80
instruction set. The eight instruction types and six addressing modes together
with the ability to operate on bits, 4-bit nibbles or binary coded decimal (BCD) dig-
its, 8-bit bytes, and 16-bit words, make for a code-efficient, flexible microcontroller.
Features
•
Four-channel, 8-bit sigma delta analog-to-digital (A/D) converter with external
voltage references (not available in the 28-pin configuration)
•
•
•
Two independent analog comparators
Controlled current output
489 bytes of RAM
–
–
233 bytes of general-purpose register-based RAM
256 bytes of RAM mapped into the program memory space that can be
used as data RAM or executable RAM
•
•
32 Kbytes of OTP memory (Z86D99X)
16 Kbytes of ROM (Z86L99X)
Counter/Timers
•
Special architecture to automate generation and reception of complex pulses
or signals:
–
–
–
Programmable 8-bit counter/timer (T8) with two 8-bit capture registers and
two 8-bit load registers
Programmable 16-bit counter/timer (T16) with one 16-bit capture register
pair and one 16-bit load register pair
Programmable input glitch filter for pulse reception
•
One general-purpose 8-bit counter/timer (T1) with 6-bit prescaler
Input/Output and Interrupts
•
Thirty-two I/Os, twenty-nine of which are bidirectional I/Os with programmable
resistive pull-up transistors (24 I/Os are available in the 28-pin configuration)
Sixteen I/Os are selectable as stop-mode recovery sources
Six interrupt vectors with nine interrupt sources
•
•
–
–
Three external sources
Two comparator interrupts
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–
–
Three timer interrupts
One low-battery detector flag
Operating Characteristics
•
•
•
•
8-MHz operation
3.0 V to 5.5 V operating voltage (Z86D990/Z86D991)
2.3 V to 5.5 V operating voltage (Z86L990/Z86L991)
Low power consumption with three standby modes:
–
–
–
Stop
Halt
Low Voltage Standby
•
•
Low-battery detection flag
Low-voltage protection circuit (also known as V , or voltage brownout,
circuit)
BO
•
Watch-dog timer and power-on reset circuits
User-Programmable Option Bits
•
•
•
•
•
•
•
•
•
•
•
Clock source—RC/other (LC, resonator, or crystal)
Watch-dog timer permanently enable
32-kHz crystal
Port 20–27 pull-up resistive transistor
Port 40–42 pull-up resistive transistor
Port 44–47 pull-up resistive transistor
Port 50–51 pull-up resistive transistor
Port 54–57 pull-up resistive transistor
Port 60–63 pull-up resistive transistor (not available in Z86D991/Z86L991)
Port 64–67 pull-up resistive transistor (not available in Z86D991/Z86L991)
P43 high impedance in STOP mode (available in OTP only)
Force P43 to output a 1 in the open-drain configuration
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Functional Block Diagram
Figure 1 shows the functional block diagram for the microcontrollers.
Expanded
Register File
Register File
256 x 8-bit
8
VDD_padring***
VDD_CORE
Program
Memory
Power Filter
7
††
Port 2
Machine
Timing
XTAL 1
XTAL 2
Z8 Core
256 Bytes
0
7
and
Instruction
Control
P52 P53
CIN2 CREF2
Two Analog
Comparators
Port 4
0
*
Controlled
Current
Output
P43
CIN1 CREF1
P51 P50
8
7
Port 5
16-Bit C/T
(Modulation)
8-Bit C/T
(General)
8-Bit C/T
(Carrier)
0
7
ADC0/P44
ADC1/P45
ADC2/P46
ADC3/P47
8-Bit A/D†
MUX
Port 6
**
V
V
Ref–
Ref+
†ADC is only in the Z86L990/Z86D990.
††Program memory is as follows:
0
*Controlled Current Output
Z86D990
Z86D991
Z86L990
Z86L991
32K OTP
32K OTP
16K ROM
16K ROM
**P6 is only in the Z86L990/Z86D990.
***In the 28-pin package, V
DD_padring
are bonded together.
and V
DD_CORE
Figure 1. Functional Block Diagram
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Pin Descriptions
Figure 2 through Figure 4 show the pin names and locations.
P62
P63
P25
P26
P27
NC
1
2
3
4
5
48
47
P61
P60
P24
P23
P22
NC
46
45
44
6
7
8
9
10
11
12
43
42
41
AVSS
NC
VREF-
P21
P20
P43
VSS
VSS
P42
P41
P40
P50
P56
NC
P44
P45
P46
P47
VREF+
40
39
38
37
Z86D990/
Z86L990
13
14
36
35
34
AVDD
VDD_CORE
VDD_padring
15
16
33
32
31
30
29
281
27
26
25
17
18
19
XTAL2
XTAL1
NC
NC
P57
P55
P67
P66
P65
P51
P52
P53
P54
20
21
22
23
24
P64
Notes:
1. Both V pins must be connected to ground.
SS
2. NC is no connection to the die.
3. AV must be connected to V
and a 10-µF capacitor for good A/D conversion.
DD_CORE
DD
4. Power must be connected to V
power filter.
. Current passes to V
through the internal
DD_padring
DD_CORE
Figure 2. 48-Pin SSOP Pin Assignments
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P62
P63
P25
P26
P27
P61
40
P60
39
1
2
3
4
5
6
P24
P23
P22
P21
38
37
36
35
34
33
32
Z86D990/
Z86L990
AVSS
V
P20
7
Ref–
P44/ADC0
P45/ADC1
P46/ADC2
P47/ADC3
P43/Combined T8 T16 Output
8
9
V
SS
10
11
12
13
14
31
30
29
28
27
26
25
24
23
22
21
P42
P41/T16 Output
P40/T8 Output
P50/CREF1
P56/T1 Timer Output
P57
P55/COUT2
P67
P66
V
Ref+
AVDD/VDD_CORE
VDD_padring
15
16
XTAL2
XTAL1
P51/CIN1/Captive Timer Input
P52/CIN2/T1 Timer Input (TIN)
P53/CREF2
17
18
19
20
P65
P64
P54/COUT1
Notes:
1. AV must be connected to V
and a 10-µF capacitor for good A/D conversion.
DD
DD_CORE
2. Power must be connected to V
power filter.
. Current passes to V
through the internal
DD_CORE
DD_padring
Figure 3. 40-Pin DIP Pin Assignment
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P25
P26
P27
1
2
3
4
5
6
7
8
28
27
26
25
24
23
22
21
20
19
18
17
16
15
P24
P23
P22
P21
P44/ADC0
P45/ADC1
P46/ADC2
P47/ADC3
Z86D991/
Z86L991
P20
P43/Combined T8 T16 Output
VSS**
VDD
*
P42
9
XTAL2
XTAL1
P41/T16 Output
P40/T8 Output
P50/CREF1
P56/T1 Timer Output
P57
10
11
12
13
14
P51/CIN1/Capture Timer Input
P52/CIN2/T1 Timer Input
P53/CREF2
P54/COUT1
P55/COUT2
Notes:
1. P43 is a controlled current output.
2. P54, P55, P56, and P57 are high drive
outputs.
* V = V
+ V
+ AV
DD_padring DD
DD
DD_CORE
Figure 4. 28-Pin SOIC/DIP Pin Assignment—User Mode
Pins Configuration
Table 2 describes the pins.
Table 2. Pin Descriptions
Pin #
28
40
48
Symbol
P20
PDIP/SOIC PDIP SSOP Direction Description
24
25
26
27
28
1
34
35
36
37
38
3
40
41
44
45
46
3
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
Port 2 Bit 0
P21
Port 2 Bit 1
P22
Port 2 Bit 2
P23
Port 2 Bit 3
P24
Port 2 Bit 4
P25
Port 2 Bit 5
P26
2
4
4
Port 2 Bit 6
P27
3
5
5
Port 2 Bit 7
P40
19
29
34
Port 4 Bit 0, T8 Output
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Low-Voltage Microcontrollers with ADC
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Table 2. Pin Descriptions (Continued)
Pin #
28
40
48
Symbol
P41
PDIP/SOIC PDIP SSOP Direction Description
20
21
23
4
30
31
33
8
35
36
39
9
I/O
Port 4 Bit 1, T16 Output
Port 4 Bit 2
P42
I/O
P43
Output
I/O
T8/T16 Output, Controlled current output
Port 4 Bit 4, A/D Channel 0*
Port 4 Bit 5, A/D Channel 1*
Port 4 Bit 6, A/D Channel 2*
Port 4 Bit 7, A/D Channel 3*
Port 5 Bit 0, Comparator 1 reference
Port 5 Bit 1, Capture timer input, IRQ2
Port 5 Bit 2, Timer 1 timer input, IRQ0
Port 5 Bit 3, Comparator 2 reference, IRQ1
Port 5 Bit 4, High drive output
Port 5 Bit 5, High drive output
Port 5 Bit 6, Timer 1 output, High drive output
Port 5 Bit 7, High drive output
Port 6 Bit 0
P44
P45
5
9
10
11
12
33
20
21
22
23
28
32
29
47
48
1
I/O
P46
6
10
11
28
17
18
19
20
25
27
26
39
40
1
I/O
P47
7
I/O
P50, CREF1 18
I/O
P51, CIN1
P52, CIN2
11
12
I/O
Input
Input
I/O
P53, CREF2 13
P54
14
15
17
16
P55
I/O
P56
I/O
P57
I/O
P60
I/O
P61
I/O
Port 6 Bit 1
P62
I/O
Port 6 Bit 2
P63
2
2
I/O
Port 6 Bit 3
P64
21
22
23
24
16
15
13
13
6
24
25
26
27
18
17
14
15
7
I/O
Port 6 Bit 4
P65
I/O
Port 6 Bit 5
P66
I/O
Port 6 Bit 6
P67
I/O
Port 6 Bit 7
XTAL1
XTAL2
AVDD
VDD_CORE
AVSS
VRef–
VRef+
VDD_padring
VSS
10
9
Input
Output
Crystal, Oscillator clock
Crystal, Oscillator clock
Analog power supply
Z8 core power supply
Analog ground
7
8
Input
Input
A/D converter lower reference
A/D converter upper reference
Power supply (pad ring)
Ground
12
14
32
13
16
37, 38
8**
22**
Notes:
*A/D converter is not available in the 28-pin configuration.
**In the 28-pin configuration, all three (core, pad ring, and analog) powers are tied together.
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Operational Description
Central Processing Unit (CPU) Description
The Z8 architecture is characterized by a flexible I/O scheme, an efficient register
and address space structure and a number of ancillary features for cost-sensitive,
high-volume embedded control applications. ROM-based products are geared for
high-volume production (where the software is stable) and one-time programma-
ble equivalents for prototyping as well as volume production where time to market
or code flexibility is critical.
Architecture Type
The Z8 register-oriented architecture centers around an internal register file com-
posed of 256 consecutive bytes, known as the standard register file. The standard
register file consists of 4 I/O port registers (R2, R4, R5, and R6), 12 control and
status registers, 233 general-purpose registers, and 7 registers reserved for future
expansion. In addition to the standard register file, the Z86D99/Z86L99 family
uses 21 control and status registers located in the Z8 expanded register file. Any
general-purpose register can be used as an accumulator and address pointer or
an index, data, or stack register.
All active registers can be referenced or modified by any instruction that accesses
an 8-bit register, without the requirement for special instructions. Registers
accessed as 16 bits are treated as even-odd register pairs. In this case, the data’s
most significant byte (MSB) is stored in the even-numbered register, while the
least significant byte (LSB) goes into the next higher odd-numbered register.
The Z8 CPU has an instruction set designed for the large register file. The instruc-
tion set provides a full compliment of 8-bit arithmetic and logical operations. BCD
operations are supported using a decimal adjustment of binary values, and 16-bit
quantities for addresses and counters can be incremented and decremented. Bit
manipulation and Rotate and Shift instructions complete the data-manipulation
capabilities of the Z8 CPU. No special I/O instructions are necessary because the
I/O is mapped into the register file.
CPU Control Registers
The standard Z8 control registers govern the operation of the CPU. Any instruc-
tion which references the register file can access these control registers. The fol-
lowing are available control registers:
•
•
•
Register Pointer (RP)
Stack Pointer (SP)
Program Control Flags (FLAGS)
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Low-Voltage Microcontrollers with ADC
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•
•
•
Interrupt Control (IPR, IMR, and IRQ)
Stop Mode Recovery (SMR, P2SMR, and P5SMR)
Low-Battery Detect (LB) Flag
The Z8 uses a 16-bit Program Counter (PC) to determine the sequence of current
program instructions. The PC is not an addressable register.
Peripheral registers are used to transfer data, configure the operating mode, and
control the operation of the on-chip peripherals. Any instruction that references
the register file can access the peripheral registers. The following are peripheral
control registers:
•
•
•
•
•
Analog/Digital Converter (ADCCTRL and ADCDATA)
T1 Timer/Counter (TMR, T1, and PRE1)
T8 Timer/Counter (CTR0, HI8, LO8, TC8H, and TC8L)
T16 Timer/Counter (CTR2, HI16, LO16, TC16H, and TC16L)
T8/T16 Control Registers (CTR1and CTR3)
In addition, the four port registers are considered to be peripheral registers. The
following are port control registers:
•
•
•
•
•
Port Configuration Registers (P456CON and P3M)
Port 2 Control and Mode Registers (P2 and P2M)
Port 4 Control and Mode Registers (P4 and P4M)
Port 5 Control and Mode Registers (P5 and P5M)
Port 6 Control and Mode Registers (P6 and P6M)
The functions and applications of the control and peripheral registers are
explained in “Control and Status Registers” on page 52.
Memory (ROM/OTP and RAM)
There are four basic address spaces available to support a wide range of configu-
rations:
•
•
•
•
Program memory (on-chip)
Standard register file
Expanded register file
Executable RAM
The Z8 standard register file totals up to 256 consecutive bytes organized as 16
groups of 16 eight-bit registers. These registers consist of I/O port registers,
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general-purpose RAM registers, and control and status registers. Every RAM reg-
ister acts like an accumulator, speeding instruction execution and maximizing cod-
ing efficiency. Working register groups allow fast context switching.
The standard register file of the Z8 (known as Bank 0) has been expanded to form
16 expanded register file (ERF) banks. The expanded register file allows for addi-
tional system control registers and for the mapping of additional peripheral
devices into the register area. Each ERF bank can potentially consist of up to 256
registers (the same amount as in the standard register file) that can then be
divided into 16 working register groups. Currently, only Group 0 of ERF Banks F
and D (0Fhand 0Dh) has been implemented.
In addition to the standard program memory and the RAM register files, the
Z86D99/Z86L99 family also has 256 bytes of executable RAM that has been
mapped into the upper 256 bytes of the program memory address space (FF00h–
FFFFh). Data can be written to the executable RAM by using the LDC instruction.
Program Memory Structure
The first 12 bytes of program memory are reserved for the interrupt vectors.
These locations contain six 16-bit vectors that correspond to the six available
interrupts (IRQ through IRQ .) Address 12 (0Ch) up to 32,767 (7FFFh) consists of
0
5
on-chip one-time programmable memory. The Z86L99X only has the 4K/8K/16K
ROM size.
After any reset operation (power-on reset, watch-dog timer time out, and stop
mode recovery), program execution resumes with the initial instruction fetch from
location 000Ch. After a reset, the first routine executed must be one that initializes
the control registers to the required system configuration.
A unique feature of the Z86D99/Z86L99 family is the presence of 256 bytes of on-
chip executable RAM. This random-access memory is in addition to the standard
Z8 register file memory available on all Z8 microcontrollers. As illustrated in
Figure 5, the executable RAM is mapped into the upper 256 bytes of the 64K pro-
gram memory address space (FF00h–FFFFh). Data can be written to the execut-
able RAM by using the LDC instruction.
Memory locations between 8000hand FEFFhhave not been implemented on the
Z86D99X microcontrollers.
The Z86D99/Z86L99 family does not have the capability of accessing external
memory.
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Location (Hex)
FFFF
256 bytes
Executable RAM
FF00
Not Implemented
3FFF/7FFF
(ROM)/(OTP)
PROGRAM
MEMORY
000C
Location of the first byte of the initial instruction executed after
RESET
000B
000A
0009
0008
0007
0006
0005
0004
0003
0002
0001
0000
IRQ5 (lower byte)
IRQ5 (upper byte)
IRQ4 (lower byte)
IRQ4 (upper byte)
IRQ3 (lower byte)
IRQ3 (upper byte)
IRQ2 (lower byte)
IRQ2 (upper byte)
IRQ1 (lower byte)
IRQ1 (upper byte)
IRQ0 (lower byte)
IRQ0 (upper byte)
Figure 5. Program Memory Map
Z8 Standard Register File (Bank 0)
Bank 0 of the Z8 expanded register file architecture is known as the standard reg-
ister file of the Z8. As shown in Figure 6, the Z8 standard register file consists of
16 groups of sixteen 8-bit registers known as Working Register (WR) groups.
Working Register Group F contains various control and status registers. The lower
half of Working Register Group 0 consists of I/O port registers (R0 to R7), the
upper eight registers are available for use as general-purpose RAM registers.
Working Register Group 1 through Group E of the standard register file are avail-
able to be used as general-purpose RAM registers. The user can use 233 bytes of
general-purpose RAM registers in the standard Z8 register file (Bank 0).
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Grp/Bnk Reg
Working Register Group Function
(F0h)
(E0h)
(D0h)
(C0h)
(B0h)
(A0h)
(90h)
(80h)
(70h)
(60h)
(50h)
(40h)
(30h)
(20h)
(10h)
r0 to 15 Control and Status Registers
r0 to 15 General-purpose RAM registers
r0 to 15 General-purpose RAM registers
r0 to 15 General-purpose RAM registers
r0 to 15 General-purpose RAM registers
r0 to 15 General-purpose RAM registers
r0 to 15 General-purpose RAM registers
r0 to 15 General-purpose RAM registers
r0 to 15 General-purpose RAM registers
r0 to 15 General-purpose RAM registers
r0 to 15 General-purpose RAM registers
r0 to 15 General-purpose RAM registers
r0 to 15 General-purpose RAM registers
r0 to 15 General-purpose RAM registers
r0 to 15 General-purpose RAM registers
r8 to 15 General-purpose RAM registers
(00h)
r0 to 7
I/O Port Registers
Figure 6. Standard Z8 Register File (Working Reg. Groups 0–F, Bank 0)
Z8 Expanded Register File
In addition to the Standard Z8 Register File (Bank 0), Expanded Register File
Banks F and D of Working Register Group 0 have been implemented on the
Z86D99/Z86L99. Figure 7 illustrates the Z8 Expanded Register File architecture.
These two expanded register file banks of Working Register Group 0 provide a
total of 32 additional RAM control and status registers. The Z86D99/Z86L99 fam-
ily has implemented 21 of the 32 available registers.
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Z8 Expanded Register Files
Z8 Standard Register File
Group 0, Bank F
F
Control and Status Reg.
E
D
C
B
A
9
Stop Mode
Recovery and
Port Mode
General-Purpose
Registers
RAM Registers
Working
Register
Groups
8
7
Bank F
6
Group 0, Bank D
5
4
3
Timer
Control
Registers
2
1
Banks 2 through C are
Reserved—Not Implemented
(Bank E is also reserved)
0
I/O Port Registers
Bank 0
Figure 7. Z8 Expanded Register File Architecture
Clock Circuit Description
The Z8 derives its timing from on-board clock circuitry connected to pins XTAL1
and XTAL2. The clock circuitry consists of an oscillator, a divide-by-two shaping
circuit, and a clock buffer. The oscillator’s input is XTAL1, and the oscillator’s out-
put is XTAL2. The clock can be driven by a crystal, a ceramic resonator, LC clock,
RC, or an external clock source.
Clock Control
The Z8 offers software control of the internal system clock using programming
register bits in the SMR register. This register selects the clock divide value and
determines the mode of STOP Mode Recovery.
The default setting is external clock divide-by-two. When bits 1 and 0 of the SMR
register are set to 0, the System Clock (SCLK) and Timer Clock (TCLK) are equal
to the external clock frequency divided by two.
When bit 1 of the SMR register is set to 1, then SCLK and TCLK equal the exter-
nal clock frequency. Refer to Table 53 on page 85 for the maximum clock fre-
quency.
A divide-by-16 prescaler of SCLK and TCLK allows the user to selectively reduce
device power consumption during normal processor execution (under SCLK con-
trol) and/or HALT mode, where TCLK sources counter/timers and interrupt logic.
Combining the divide-by-two circuitry with the divide-by-16 prescaler allows the
external clock to be divided by 32.
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Interrupts
The Z86D99/Z86L99 family allows up to six different interrupts, three external and
three internal, from nine possible sources. The six interrupts are assigned as fol-
lows:
•
Three edge-triggered external interrupts (P51, P52, and P53), two of which
are shared with the two analog comparators
•
•
•
One internal interrupt assigned to the T8 Timer
One internal interrupt assigned to the T16 Timer
One internal interrupt shared between the Low-Battery Detect flag and the T1
Timer
Table 3 presents the interrupt types, the interrupt sources, and the location of the
specific interrupt vectors.
Table 3. Interrupt Types, Sources, and Vectors
Vector
Name
Source
Location Comments
IRQ0
P52 (F/R), Comparator 2 0,1
External interrupt (P52) is triggered by
either rising or falling edge; internal
interrupt generated by Comparator 2
is mapped into IRQ0
IRQ1
IRQ2
P53 (F)
2,3
External interrupt (P53) is triggered by
a falling edge
P51 (R/F), Comparator 1 4,5
External interrupt (P51) is triggered by
either a rising or falling edge; internal
interrupt generated by Comparator 1
is mapped into IRQ2
IRQ3
IRQ4
IRQ5
T16 Timer
T8 Timer
6,7
Internal interrupt
Internal interrupt
8,9
LVD, T1 Timer
10,11
Internal interrupt, LVD flag is
multiplexed with T1 Timer End-of-
Count interrupt
Notes:
F = Falling-edge triggered; R = Rising-edge triggered.
When LVD is enabled, IRQ5 is triggered only by low-voltage detection. Timer
1 does not generate an interrupt.
These interrupts can be masked and their priorities set by using the Interrupt
Mask Register (IMR) and Interrupt Priority Register (IPR) (Figure 8.) When more
than one interrupt is pending, priorities are resolved by a priority encoder, con-
trolled by the IPR.
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EI Instruction
Interrupt Request Register
(IRQ,FAH)
S
R
Reset
Power-On Reset (POR)
Figure 8. Interrupt Block Diagram
Interrupt requests are stored in the Interrupt Request Register (IRQ), which can
also be used for polling. When an interrupt request is granted, the Z8 enters an
“interrupt machine cycle” that globally disables all other interrupts, saves the pro-
gram counter (the address of the next instruction to be executed) and status flags,
and finally branches to the vector location for the interrupt granted. It is only at this
point that control passes to the interrupt service routine for the specific interrupt.
All six interrupts can be globally disabled by resetting the master Interrupt Enable
(bit 7 of the IMR) with a Disable Interrupts (DI) instruction. Interrupts are globally
enabled by setting the same bit with an Enable Interrupts (EI) instruction.
Descriptions of three interrupt control registers—the Interrupt Request Register,
the Interrupt Mask Register, and the Interrupt Priority Register—are provided in
“Register Summary” on page 52. The Z8 family supports both vectored and polled
interrupt handling.
External Interrupt Sources
External sources involve interrupt request lines P51, P52, and P53 (IRQ , IRQ ,
2
0
and IRQ , respectively.) IRQ , IRQ , and IRQ are generated by a transition on
1
0
1
2
the corresponding port pin. As shown in Figure 9, when the appropriate port pin
(P51, P52, or P53) transitions, the first flip-flop is set. The next two flip-flops syn-
chronize the request to the internal clock and delay it by two internal clock peri-
ods. The output of the most recent flip-flop (IRQ , IRQ , or IRQ ) sets the
0
1
2
corresponding Interrupt Request Register bit.
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Figure 9. External Interrupt Sources IRQ0–IRQ2 Block Diagram
The programming bits for the Interrupt Edge Select function are located in the IRQ
register, bits 6 and 7. The configuration of these bits and the resulting interrupt
edge is shown in Table 4.
Table 4. Interrupt Edge Select for External Interrupts
Interrupt Request Register
Interrupt Edge
Bit 7
Bit 6
IRQ2 (P51)
IRQ0 (P52)
Falling
0
0
1
1
0
1
0
1
Falling
Falling
Rising
Rising
Falling
Rising/Falling Rising/Falling
Note:
Although interrupts are edge triggered, minimum interrupt
request Low and High times must be observed for proper
operation. See “Electrical Characteristics” on page 85 for exact
timing requirements (T IL, T IH) on external interrupt
W
W
requests.
Internal Interrupt Sources
Internal sources are ORed with the external sources, so that either an internal or
external source can trigger the interrupt.
Interrupt Request Register Logic and Timing
Figure 10 shows the logic diagram for the Interrupt Request Register. The leading
edge of an interrupt request sets the first flip-flop. It remains set until the interrupt
requests are sampled.
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Figure 10. IRQ Logic
Internal interrupt requests are sampled during the most recent clock cycle before
an Op Code fetch (see Figure 11.) External interrupt requests are sampled two
internal clocks earlier than internal interrupt requests because of the synchroniz-
ing flip-flops shown in Figure 9.
Figure 11. Interrupt Request Timing
At sample time, the interrupt request is transferred to the second flip-flop shown in
Figure 10, which drives the interrupt mask and priority logic. When an interrupt
cycle occurs, this flip-flop is reset only for the highest priority level that is enabled.
The user has direct access to the second flip-flop by reading and writing to the
IRQ. The IRQ is read by specifying it as the source register of an instruction, and
the IRQ is written by specifying it as the destination register.
Interrupt Initialization
After RESET, all interrupts are disabled and must be re-initialized before vectored
or polled interrupt processing can begin. The Interrupt Priority Register, Interrupt
Mask Register, and Interrupt Request Register must be initialized, in that order, to
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start the interrupt process. However, the IPR does not have to be initialized for
polled processing.
Interrupts must be globally enabled using the EI instruction. Setting bit 7 of the
IMR is not sufficient. Subsequent to this EI instruction, interrupts can be enabled
either by IMR manipulation or by use of the EI instruction, with equivalent effects.
Additionally, interrupts must be disabled by executing a DI instruction before the
IPRs or IMRs can be modified. Interrupts can then be enabled by executing an EI
instruction.
IRQ Software Interrupt Generation
IRQ can be used to generate software interrupts by specifying IRQ as the destina-
tion of any instruction referencing the Z8 Standard Register File. These Software
Interrupts (SWIs) are controlled in the same manner as hardware-generated
requests (the IPR and the IMR control the priority and enabling of each SWI level).
To generate a SWI, the request bit in the IRQ is set as follows:
OR
IRQ, #NUMBER
where the immediate data, NUMBER, has a 1 in the bit position corresponding to
the appropriate level of the SWI.
For example, for an SWI on IRQ5, NUMBER has a 1 in bit 5. With this instruction,
if the interrupt system is globally enabled, IRQ5 is enabled, and there are no
higher priority pending requests, control is transferred to the service routine
pointed to by the IRQ5 vector.
Reset Conditions
A system reset overrides all other operating conditions and puts the Z8 into a
known state. The control and status registers are reset to their default conditions
after a power-on reset (POR) or a Watch-Dog Timer (WDT) time-out while in RUN
mode. The control and status registers are not reset to their default conditions
after Stop Mode Recovery (SMR) while in HALT or STOP mode.
General-purpose registers are undefined after the device is powered up. Reset-
ting the Z8 does not affect the contents of the general-purpose registers. The reg-
isters keep their most recent value after any reset, as long as the reset occurs in
the specified V operating range. Registers do not keep their most recent state
CC
from a V reset, if V drops below V (see Table 54 on page 87).
LV
CC
RAM
Following a reset (see Table 5), the first routine executed must be one that initial-
izes the control registers to the required system configuration.
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Table 5. Control and Status Register Reset Conditions
Address
Reset Value
Register Function
Register Pointer
Stack Pointer
Grp/Bnk Register Symbol
R/W 7
R/W 0
R/W X
R/W X
R/W 1
6
0
X
X
1
0
0
0
0
0
0
1
X
1
X
1
X
1
X
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
5
0
X
X
1
0
0
0
0
0
0
1
X
1
X
1
X
1
X
1
0
0
0
4
0
X
X
1
0
0
0
0
0
0
1
X
1
X
1
X
1
X
1
0
0
0
3
0
X
X
1
0
0
0
0
0
0
1
X
1
X
2
0
X
X
X
0
0
0
0
0
1
1
X
1
X
1
0
X
X
0
0
0
0
0
0
1
1
X
1
X
1
X
1
X
1
0
1
0
0
X
0
0
X
X
0
0
0
0
0
0
1
1
X
1
X
1
X
1
X
1
0
1
0
0
X
0
0
0
0
0
0
0
0
0
0
F0h
F0h
r13 (R253) RP
r15 (R255) SP
r12 (R252) Flags
Program Control Flags F0h
Low Battery Detect
ADC Control
0Dh
0Fh
00h
F0h
F0h
F0h
0Fh
F0h
00h
F0h
00h
0Fh
00h
0Fh
00h
0Fh
F0h
F0h
F0h
0Dh
0Dh
0Dh
0Dh
0Dh
0Dh
0Dh
0Dh
0Dh
0Dh
0Dh
0Dh
r12
LB
r8
ADCCTRL R/W 0
ADCDATA 0
ADC Data
r7 (R7)
R
Interrupt Mask
Interrupt Priority
Interrupt Request
Port Configuration (A)
Port Configuration (B)
Port 2 Data
r11 (R251) IMR
r9 (R249) IPR
r10 (R250) IRQ
R/W 0
W
0
R/W 0
R/W 0
r0
P456CON
r7 (R247) P3M
W
1
r2 (R2)
P2
R/W X
Port 2 Mode
r6 (R246) P2M
W
1
Port 4 Data
r4 (R4)
r2
P4
R/W X
R/W 1
R/W X
R/W 1
R/W X
R/W 1
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
Port 4 Mode
P4M
P5
1** 1
Port 5 Data
r5 (R5)
r4
X
1
X
1
0
0
0
0
X
X
1
X
1
0
0
0
0
X
Port 5 Mode
P5M
P6
Port 6 Data
r6 (R6)
r6
Port 6 Mode
P6M
T1 Timer Data
T1 Timer Mode
T1 Timer Prescale
T8/T16 Control (A)
T8/T16 Control (B)
T8 Timer Control
T8 High Capture
T8 Low Capture
T8 High Load
r2 (R242) T1
r1 (R241) TMR
r3 (R243) PRE1
r1
r3
r0
r11
r10
r5
r4
r2
r9
r8
r7
r6
CTR1
CTR3
CTR0
HI8†
0* 0*
0*
X
0* 0* 0* 0* 0*
RW
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LO8†
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
R/W 0
TC8H†
TC8L†
CTR2
HI16†
LO16†
TC16H†
TC16L†
T8 Low Load
T16 Timer Control
T16 High Capture
T16 Low Capture
T16 High Load
T16 Low Load
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Table 5. Control and Status Register Reset Conditions (Continued)
Address
Reset Value
Register Function
Stop Mode Recovery
Port 2 SMR Source
Port 5 SMR Source
Notes:
Grp/Bnk Register Symbol
R/W 7
R/W 0
R/W 0
R/W 0
6
0
0
0
5
1
0
0
4
0
0
0
3
0
0
0
2
0
0
0
1
0
0
0
0
0
0
0
0Fh
0Fh
0Fh
r11
r1
SMR
P2SMR
r5
P5SMR
†This register is not reset following Stop Mode Recovery (SMR).
*This bit is not reset following SMR.
X means this bit is undefined at POR and is not reset following SMR.
**In OTP, the default for P43 is open-drain output at power up; you need to
initialize the P43 data. In the mask part, the P43 output is disabled until it is
configured as output.
Power-On Reset
A POR (cold start) always resets the Z8 control and status registers to their default
conditions. A POR sets bit 7 of the Stop Mode Recovery register to 0 to indicate
that a cold start has occurred.
A timer circuit clocked by a dedicated on-board RC oscillator is used for the
Power-On Reset Timer (TPOR) function. The POR time is specified as T
.
POR
T
time allows V and the oscillator circuit to stabilize before instruction exe-
POR
CC
cution begins.
The POR delay timer circuit is a one-shot timer triggered by one of three condi-
tions:
•
Power Fail to Power OK status including recovery from Low Voltage (V
Standby mode
LV)
•
•
STOP-Mode Recovery (when bit 5 of the SMR register = 1)
WDT time-out
Under normal operating conditions, a stop mode recovery event always triggers
the POR delay timer. This delay is necessary to allow the external oscillator time
to stabilize. When using an RC or LC oscillator (with a low Q factor), the shorter
wake-up time means the delay can be eliminated.
Bit 5 of the SMR register selects whether the POR timer delay is used after Stop-
Mode Recovery or is bypassed. If bit 5 =1, then the POR timer delay is used. If bit
5 = 0, then the POR timer delay is bypassed. In this case, the SMR source must
be held in the recovery state for 5 TpC to pass the Reset signal internally.
Watch-Dog Timer (WDT)
The WDT is a retriggerable one-shot timer that resets the Z8 if it reaches its
terminal count. When operating in the RUN modes, a WDT reset is functionally
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equivalent to a hardware POR reset. If the mask option of the permanently
enabled watch-dog timer is selected, it runs when power up. If the option is not
selected, the WDT is initially enabled by executing the WDT instruction and
refreshed on subsequent executions of the WDT instruction.
The WDT instruction does not affect the Zero (Z), Sign (S), and Overflow (V) flags.
Permanently enabled WDTs are always enabled, and the WDT instruction is used
to refresh it. The WDT cannot be disabled after it has been initially enabled. The
WDT is off during both HALT and STOP modes.
The WDT circuit is driven by an on-board RC oscillator. The time-out period for the
WDT is fixed to a typical value (see Table 57 on page 90).
Power Management
In addition to the standard RUN mode, the Z8 supports three power-down modes
to minimize device current consumption. The following three modes are sup-
ported:
•
•
•
HALT
STOP
Low-Voltage Standby
Table 6 shows the status of the internal CPU clock (SCLK), the internal Timer
clock (TCLK), the external oscillator, and the Watch-Dog Timer during the RUN
mode and three low-power modes.
Table 6. Clock Status in Operating Modes
Operating Mode
RUN
SCLK TCLK External OSC WDT*
On
Off
Off
On
On
Off
Off
On
On
Off
Off
On
Off
Off
Off
HALT
STOP
Low-Voltage Standby Off
Note: * When WDT is enabled by the mask option bit
Using the Power-Down Modes
In order to enter HALT or STOP mode, it is necessary to first flush the instruction
pipeline to avoid suspending execution in mid-instruction. You can flush the
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instruction pipeline by executing a NOP (Op Code = FFh) immediately before the
appropriate sleep instruction. For example:
Mnemonic Comment
Op Code
FFh
NOP
; clear the pipeline
; enter STOP mode
6Fh
STOP
or
Mnemonic Comment
Op Code
FFh
NOP
; clear the pipeline
; enter HALT mode
7Fh
HALT
HALT
HALT mode suspends instruction execution and turns off the internal CPU clock
(SCLK). The on-chip oscillator circuit remains active, so the internal Timer clock
(TCLK) continues to run and is applied to the counter/timers and interrupt logic.
An interrupt request, either internally or externally generated, must be executed
(enabled) to exit HALT mode. After the interrupt service routine, the program con-
tinues from the instruction immediately following the HALT.
The HALT mode can also be exited by a POR. In this case, the program execution
restarts at the reset address 000Ch.
STOP
STOP mode provides the lowest possible device standby current. This instruction
turns off both the internal CPU clock (SCLK) and internal Timer clock (TCLK) and
reduces the standby current to the minimum.
The STOP mode is terminated by a POR or SMR source. Terminating the STOP
mode causes the processor to restart the application program at address 000Ch.
Note:
When the STOP instruction is executed, the microcontroller goes into the
STOP mode despite any state/change of the state of the port. The ports
need to be checked immediately before the NOP and STOP instructions to
ensure the right input logic before waiting for the change of the ports.
Stop Mode Recovery Sources
Exiting STOP mode using an SMR source is greatly simplified in the Z86D99/
Z86L99 family. The Z86D99/Z86L99 family of products allows 16 individual I/O
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pins (Ports 2 and 5) to be used as stop-mode recovery sources. The STOP mode
is exited when one of these SMR sources is toggled. A transition from either low to
high or high to low on any pin of Port 2 or Port 5 if the pin is identified as an SMR
source will effect an SMR.
There are three registers that control STOP mode recovery:
•
•
•
Stop Mode Recovery
Port 2 Stop Mode Recovery (P2SMR)
Port 5 Stop Mode Recovery (P5SMR)
The functions and applications of these registers are explained in “Stop-Mode
Recovery Control Registers” on page 82.
Low-Voltage Standby
An on-chip voltage comparator checks that the V level is at the required level
CC
for correct operation of the Z8. When V falls below the low-voltage trip voltage
CC
(V ), reset is globally driven, and then the device is put in a low-current standby
LV
mode with the external oscillator stopped. If the V remains above V
, the
CC
RAM
RAM content is preserved.
When the power level rises above the V level, the device performs a POR and
LV
functions normally.
The minimum operating voltage varies with temperature and operating frequency,
while V varies with temperature only.
LV
I/O Ports
The Z86D99/Z86L99 family has up to 32 lines dedicated to input and output in the
40-pin configuration. These lines are grouped into four 8-bit ports known as Port
2, Port 4, Port 5, and Port 6. All four ports are bit programmable as either inputs or
outputs with the exception of P52, P53, and P43. P52 and P53 are input only as
they are used in OTP programming. P43 is the controlled current output and is
therefore output only.
All ports have push-pull CMOS outputs. In addition, the push-pull outputs can be
turned off for open-drain operation using the P456CON register.
Internal resistive pull-up transistors are available as a user-defined OTP/mask
option on all ports. For Ports 4, 5, and 6, the pull-ups are nibble selectable. For
Port 2, the pull-up option applies to all eight I/O lines.
Note:
Internal pull-ups are disabled on any given pin or group of port
pins when those pins are programmed as outputs.
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Mode Registers
Each port has an associated Mode Register that determines the port’s functions
and allows dynamic change in port functions during program execution. Port and
Mode Registers are mapped into the Standard Register File. Because of their
close association, Port and Mode Registers are treated like any other general-pur-
pose register. There are no special instructions for port manipulation. Any instruc-
tion that addresses a register can address the ports. Data can be directly
accessed in the Port Register, with no extra moves.
Input and Output Registers
Each of the four ports (Ports 2, 4, 5, and 6) has an input register, an output regis-
ter, and associated buffer and control logic. Because there are separate input and
output registers associated with each port, writing bits defined as inputs store the
data in the output register. This data cannot be read as long as the bits are defined
as inputs. However, if the bits are reconfigured as output, the data stored in the
output register is reflected on the output pins and can then be read. This mecha-
nism allows the user to initialize the outputs before driving their loads.
Because port inputs are asynchronous to the Z8 internal clock, a READ operation
could occur during an input transition. In this case, the logic level might be uncer-
tain (somewhere between a logic 1 and 0).
General Port I/O
The eight I/O lines of each port (except P43, P52, and P53) can be configured
under software control to be either input or output, independently. Bits pro-
grammed as outputs can be globally programmed as either push-pull or open-
drain. See Figure 12.
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OTP/Mask
Option
Pull-Up
VCC
Open-Drain
I/O
*
Pad
Out
In
Note: * Pull-up resistance is
about 200 KΩ at 2.3 V and
75 KΩ at 5.0 V with +50%
tolerance.
Figure 12. General Input/Output Pin
Read/Write Operations
The ports are accessed as general-purpose registers. Port registers are written by
specifying the port register as an instruction’s destination register. Writing to a port
causes data to be stored in the output register of the port, and reflected externally
on any bit configured as an output.
Ports are read by specifying the port register as the source register of an instruc-
tion. When an output bit is read, data on the external pin is returned. Under normal
loading conditions, returning data on the external pin is equivalent to reading the
output register. However, if a bit is defined as an open-drain output, the data
returned is the value forced on the output pin by the external system. This value
might not be the same as the data in the output register. Reading input bits also
returns data on the external pins.
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Special Functions
Table 7 defines the special functions of Ports 4 and 5.
Table 7. Special Port Pin Functions
Function
Pin
Signal
Configuration Register
P456CON
Analog Comparator Inputs
P51
P52
P50
P53
P54
P55
P44
P45
P46
P47
P52
P53
P51
P52
P51
P56
P40
P41
P43
CIN1
CIN2
P456CON
Analog Comparator
References
CREF1
CREF2
COUT1
COUT2
ADC0
ADC1
ADC2
ADC3
IRQ0
Analog Comparator Outputs
ADC Channels
ADCCTRL
ADCCTRL
ADCCTRL
ADCCTRL
External Interrupts
IMR and IRQ
IMR and IRQ
IMR and IRQ
TMR and PRE1
IRQ1
IRQ2
T
IN External Clock Input
TIN
Capture Timer Input
T1 Timer Output
T8 Output
Demodulator_Input CTR1
T1OUT
TMR
P40_Out
P41_Out
P43_Out
CTR0
CTR2
CTR1
T16 Output
Combined T8/T16 Output
Controlled Current Output
ZiLOG Test Mode
P41
P42
DSn Enable
ASn Enable
P456CON
P456CON
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Peripherals
Analog Comparators
The Z86D99/Z86L99 family includes two independent on-chip general-purpose
analog comparators as shown in Figure 13. The comparators are multiplexed with
a digital input signal by the P456CON register. They can also be used to generate
interrupts IRQ0 and IRQ2. The comparators are turned off in STOP mode.
IRQ2, P51 Data Latch
P51
+
–
(CIN1)
P50
(CREF1)
P456CON
Bit5 1 = comparator
0 = digital
Comparator 1
IRQ0, P52 Data Latch
P52
(CIN2)
+
–
P456CON
Bit4 1 = comparator
0 = digital
P53
(CREF2)
Comparator 2
Figure 13. Analog Comparators
Analog/Digital Converter (ADC)
The Z86D99/Z86L99 family incorporates an 8-bit ADC that uses a sigma delta
architecture (Figure 14) comprised of a modulator and a digital filter. The input is
selected (bit 3,2 from ADCCTRL) with an analog mux from 4 (P47–P44) pins that
can be configured as analog inputs (bit 7–4 from ADCCTRL).
Note:
Whenever an input pin has an analog value, the digital input
buffer has to be disabled in order to reduce the current through
the device.
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Figure 14. ADC Block Diagram
The low-pass filter transfer function is presented in Figure 15 with the –3-dB fre-
quency given by the formula:
f3db = 0.0021 fADC
where f
is the sampling frequency of the modulator.
ADC
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Filter response
0
2
4
6
8
10
12
14
16
18
20
0
0.5
1
1.5
2
2.5
log10(f)
3
3.5
4
4.5
5
Figure 15. Low-Pass Filter (with 8-MHz Crystal)
The sampling frequency of the modulator f
can be selected between f
and
ADC
SCLK
f
/2 (bit1 from ADCCTRL). Reducing the clock frequency lowers the power
SCLK
dissipated in the ADC block.
The ADC can be enabled or disabled. When enabled, the Σ∆ converter tracks the
input voltage. When switching between the channels (step response), the
required time to reach the final value is given by the time constant of the low-pass
filter:
2
2
952
Tdelay = -------- = --------------------------- = ----------
f3db 0.0021fADC fADC
When available, the reference for the ADC is set externally with the V
pins. The output code represents the following ratio:
and V
ref-
ref+
Vin – VRef-
------------------------------
× 256
Dout
=
VRef+ – VRef-
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Though the ADC functions for smaller input voltage range (V
–V
), the noise
Ref-
Ref+
and offsets remain constant over the specified electrical range. The errors of the
converter increase due to small input signals.
For fast access to the output of the ADC, the current data is available in the ADC
result register (r8, bank00).
To reduce the interference between the digital part and the analog part, separate
AV and AV pins are available on the packages where the ADC can be used.
SS
DD
Note:
In the smaller packages, which do not support the ADC, the
user must keep the converter not active in order to not have
power dissipated in the ADC block. By default, ADC is off.
Active Glitch Filter
The Z86D99/Z86L99 family incorporates an active power/glitch filter that can be
used to improve the quality of the power supply when the device is operating in
noisy environments. The chips use three separate power buses:
•
pad ring power bus (all the output drivers plus the crystal/RC oscillator) called
V
DD_padring
•
•
core power bus (all digital circuitry) called V
DD_CORE
analog power bus (all analog circuitry) called AV
DD
Depending on the pin availability, one or more of the power buses are connected
together.
The active power filter can be used in the packages that have the V separate.
DD
Figure 16 shows the internal schematic.
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Z86D99/Z86L99
Figure 16. Active Glitch/Power Filter
When the internal power/glitch filter is not used, both V
and V
DD_CORE
DD_padring
must be connected together externally to the power supply.
When the internal circuitry is used, the V has to be connected to the
DD_padring
power supply and the V
has to be connected to an external energy stor-
DD_CORE
age capacitor (1−10 µF range). The core is connected only to this capacitor during
power supply glitches.
Table 8 describes the active glitch/filter specifications.
Table 8. Active Glitch/Filter Specifications (Preliminary)
Parameter
Max
Min
Condition
Diff. stage gain
Diff. stage bandwidth
Rise time
75 dB
15 MHz
255 ns
214 ns
10 Ω
50 mV pulse
50 mV pulse
Fall time
R
dson
On the wafer level, all three power buses are available. Depending on the number
of pins of the package, one or more power buses are connected together.
The active glitch/power filter effectively increases the noise immunity for battery-
operated designs where the controller is driving high current loads (for example,
IR LED).
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Controlled Current Output
P43 is an open-drain output-only pin on the Z86D990/D991, but it can be config-
ured as output or Tristate High Impedance on the Z86L990/L991. To function
properly, Bit 3 of P4M must be set to zero to configure the pin as an open-drain
output. For the Z86L990/L991 after reset, P43 defaults to Tristate High Impedance
while the Z86D990/D991 P43 is always configured as output. The data at Port 4
must be initialized as it is undefined at power-on reset.
The current output is a controlled current source that is controlled by the output of
the value of P43 (see Table 9). P43 cannot be configured as input, and if P43 is
read, P43 always returns the state of the output value (1 for no sink and 0 for
sink).
P43 uses internal current reference and will draw current if it outputs a low logic
even without external connection. This applies to both Run mode and Stop mode.
Table 9. Current Sink Pad P43 Specifications (Preliminary)
Parameter
Rise time
Fall time
Min
Max
Conditions
LED load
LED load
@27C
0.4 µ
0.02 µ
0.54 V
0.2 µ
V
outmin
Comparator response
Regulated current
Internal resistance
80 mA
120 mA
80 Ω
The pad driver can function in two modes:
•
controlled current output, when the voltage on the pad is over a minimum
value
Vpad > Voutmin
•
resistive pull down when the driver cannot regulate the current; in this mode,
the gate of the NMOS pull down is raised to the power rail.
The I-V characteristics of the pad are presented in Figure 17.
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Figure 17. I-V Characteristics for the Current Sink Pad P43
The CPU reads the mode of the pad driver by reading bit number 2 from the LB
register. This bit is the output of a Set-Reset flip-flop that sets whenever the volt-
age on the pad is lower than V
register.
and is reset by a CPU write to the respective
outmin
T1 Timer
The Z86D99/Z86L99 family provides one general-purpose 8-bit counter/timer, T ,
1
driven by its own 6-bit prescaler, PRE . The T counter/timer is independent of the
1
1
processor instruction sequence, which relieves software from time-critical opera-
tions such as interval timing and event counting.
The T counter/timer operates in either single-pass or continuous mode. At the
1
end-of-count, counting either stops or the initial value is reloaded and counting
continues. Under software control, new values are loaded immediately or when
the end-of-count is reached. Software also controls the counting mode, how the
counter/timer is started or stopped, and the counter/timer’s use of I/O lines. Both
the counter and prescaler registers can be altered while the counter/timer is run-
ning.
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Counter/timer 1 is driven by a timer clock generated by dividing the internal clock
by four. The divide-by-four stage, the 6-bit prescaler, and the 8-bit counter/timer
form a synchronous 16-bit divide chain. Counter/timer T can also be driven by an
1
external input (T ) using Port P52. Port P5 can serve as a timer output (T )
IN
6
OUT
through which T or the internal clock can be output. The timer output toggles at
1
the end-of-count. Figure 18 is a block diagram of the counter/timer.
OSC
+2
Internal
Clock
T
P5
OUT
+2
6
External Clock
Clock
Logic
IRQ5
8-Bit
6-Bit
Down Counter
Down Counter
+4
Internal Clock
Gated Clock
Triggered Clock
T1
T1
PRE1
Initial Value
Register
Initial Value
Register
Current Value
Register
Read
Internal Data Bus
Write
Write
T P3
IN
1
Figure 18. T Counter/Timer Block Diagram
1
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The counter/timer, prescaler, and associated mode registers are mapped into the
register file as shown in Figure 19. The software uses the counter/timer as a gen-
eral-purpose register, which eliminates the need for special instructions.
DEC
Hex identifiers
243
242
241
T1 prescaler
Timer/counter 1
Timer mode
F3 PRE1
F2 T1
F1 TMR
Figure 19. Register File
Prescaler and Counter/Timer
The prescaler PRE (F3h) consists of an 8-bit register and a 6-bit down-counter as
1
shown in Figure 18 on page 35. The prescaler register is a read-write register.
Figure 20 shows the prescaler register.
R243 PRE1
Prescaler 1 Register
(F3h; Read/Write)
D
D
D
D
D
D
D
D
0
7
6
5
4
3
2
1
Count mode
1 = T modulo-N
1
0 = T single pass
1
Clock source
1 = T internal
1
0 = T external (T )
1
IN
Prescaler modulo
(range: 1–64 decimal,
01h–00h)
Figure 20. Prescaler 1 Register
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The six most significant bits (D –D ) of PRE hold the prescaler count modulo, a
2
7
1
value from 11 to 64 decimal. The prescaler register also contains control bits that
specify T counting modes. These bits also indicate whether the clock source for
1
T is internal or external.
1
The counter/timer T (F2h) consists of an 8-bit down-counter, a write-only register
1
that holds the initial count value, and a read-only register that holds the current
count value (see Figure 18 on page 35). The initial value can range from 1 to 256
decimal (01h, 02h, ..., 00h). Figure 21 illustrates the counter/timer register.
R242 T1
Counter/Timer 1 Register
(F2h; Read/Write)
D
D
D
D
D
D
D
D
0
7
6
5
4
3
2
1
Initial value when written
(range 1–256 decimal, 01h–00h)
Current value when read
Figure 21. Counter/Timer 1 Register
Counter/Timer Operation
Under software control, T is started and stopped using the Timer Mode register
1
(F1h) bits D –D : a Load bit and an Enable Count bit. See Figure 22.
2
3
R241 TMR
Timer Mode Register
(F1h; Read/Write)
D
D
D
D
0
3
2
1
Reserved
0 = No function
1 = Load T
1
0 = Disable T count
1
1 = Enable T count
1
Figure 22. Timer Mode Register
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Load and Enable Count Bits
Setting the Load bit D to 1transfers the initial values in the prescaler and the
2
counter/timer registers into their respective down-counters. The next internal clock
resets bit D to 0, readying the Load bit for the next load operation. The initial val-
2
ues can be loaded into the down-counters at any time. If the counter/timer is run-
ning, the counter/timer continues to run and starts the count over with the initial
value. Therefore, the Load bit actually functions as a software re-trigger.
The T counter/timer remains at rest as long as the Enable Count bit D is 0. To
1
3
enable counting, the Enable Count bit D must be set to 1. Counting actually starts
3
when the Enable Count bit is written by an instruction. The first decrement occurs
four internal clock periods after the Enable Count bit has been set.
The Load and Enable Count bits can be set at the same time. For example, using
the instruction OR TMR #%0Csets both D and D of TMR to 1. The initial values of
2
3
PRE and T are loaded into their respective counters, and the count is started
1
1
after the M2T2 machine state after the operand is fetched as shown in Figure 23.
M
M
M
M
3
1
2
n
T
T
T
T
T
T
T
T
T
T
T
T
3
1
2
3
1
2
3
1
2
3
1
2
#03 is fetched
TMR is written;
counter/timers
are loaded
first decrement
occurs four
clocks later
Figure 23. Starting the Count
Prescaler Operations
During counting, the programmed clock source drives the prescaler 6-bit counter.
The counter is counted down from the value specified by bits D –D of the corre-
2
7
sponding prescaler register, PRE or PRE (Figure 24). When the prescaler
0
1
counter reaches its end-of-count, the initial value is reloaded and counting contin-
ues. The prescaler never actually reaches zero. For example, if the prescaler is
set to divide by three, the count sequence is as follows:
3-2-1-3-2-1-3-2...
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R243 PRE1
Prescaler 1 Register
(F3h; Read/Write)
D
0
Count mode
1 = T modulo-N
1
0 = T single pass
1
Figure 24. Counting Modes
When the PRE register is loaded with 000000 in the six most significant bits, the
1
prescaler divides by 64. If that number is 000001, the prescaler does not divide
and passes its clock on to T .
1
Each time the prescaler reaches its end-of-count, a carry is generated, which
allows the counter/timer to decrement by one on the next timer clock input. When
T and PRE both reach their end-of-count, an interrupt request is generated—
1
1
IRQ for T . Depending on the counting mode selected, the counter/timer either
5
1
comes to rest with its value at 00h(single-pass mode), or the initial value is auto-
matically reloaded and counting continues (continuous mode). In single-pass
mode, the prescaler still continues to decrement when the timer T has reached
1
its end-of-count. The prescaler always starts from its programmed value upon
restarting the counter.
The counting modes are controlled by bit D of PRE , with D cleared to 0for sin-
0
1
0
gle-pass counting mode or set to 1for continuous mode.
The counter/timer can be stopped at any time by setting the Enable Count bit to 0
and restarted by setting the Enable Count bit back to 1. The T counter/timer con-
1
tinues its count value at the time it was stopped. The current value in the T
1
counter/timer can be read at any time without affecting the counting operation.
New initial values can be written to the prescaler or the counter/timer registers at
any time. These values are transferred to their respective down-counters on the
next load operation. If the counter/timer mode is continuous, the next load occurs
on the timer clock following an end-of-count. New initial values must be written
before the load operation because the prescaler always effectively operates in
continuous count mode.
If the value loaded in the T register is 01h, the timer is actually not timing or
1
counting at all; the timer is passing the prescaler end-of-count through. Because
the prescaler is continuously running, regardless of the single-pass/continuous
mode operation, the 8-bit timer continuously times out at the rate of the prescaler
end-of-count if the T timer value is programmed to 01h.
1
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The time interval (i) until end-of-count, is given by
i = t x p x v
where t is 8 divided by XTAL frequency, p is the prescaler value (1 – 64), and v is
the counter/timer value (1 – 256). The prescaler and counter/timer are true divide-
by-n counters.
T
Modes
OUT
The Timer Mode register TMR (F1h) (Figure 25) is used in conjunction with the
Port 5 Mode register P5M to configure P5 for T operation. In order for T to
OUT
6
OUT
function, P5 must be defined as an output line by setting P5M bit D to 0. Output
6
6
is controlled by one of the counter/timers (T or T ) or the internal clock.
0
1
R241 TMR
Timer Mode Register
(F1h; Read/Write)
D
D
D
2
7
6
0 = No function
1 = Load T
1
T
T
modes
off = 00
OUT
OUT
Reserved = 01
T out = 10
1
Internal clock out = 11
Figure 25. Timer Mode Register T
Operation
OUT
The P5 output is selected by TMR bits D and D . T is selected by setting D
6
7
6
1
7
and D to 1and 0, respectively. The counter/timer T
mode is turned off by set-
6
OUT
ting TMR bits D and D both to 0, freeing P3 to be a data output line.
7
6
6
T
is initialized to a logic 1 whenever the TMR Load bit D is set to 1.
2
OUT
At end-of-count, the interrupt request line IRQ clocks a toggle flip-flop. The out-
5
put of this flip-flop drives the T
line P5 . In all cases, when the counter/timer
OUT
6
reaches its end-of-count, T
toggles to its opposite state (see Figure 26). If, for
OUT
example, the counter/timer is in continuous counting mode, T
has a 50% duty
OUT
cycle output. You can control the duty cycle by varying the initial values after each
end-of-count.
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+2
T
OUT
P5
6
IRQ5 (T1 end-of-count)
Figure 26. Counter/Timer Output Using T
OUT
The internal clock can be selected as output instead of T by setting TMR bits D
1
7
and D both to 1. The internal clock (XTAL frequency/2) is then directly output on
6
P5 (Figure 27).
6
Internal clock
T
OSC
P5
6
+2
OUT
TMR
TMR
Figure 27. Internal Clock Output Using T
OUT
While programmed as T
, P5 cannot be modified by a write to port register P5.
6
OUT
However, the Z8 software can examine P5 ’s current output by reading the port
6
register.
T
Modes
IN
The Timer Mode register TMR (F1h) (Figure 28) is used in conjunction with the
Prescaler register PRE (F3h) (Figure 29) to configure P5 as T . T is used in
1
2
IN IN
conjunction with T in one of four modes:
1
•
•
•
•
External clock input
Gated internal clock
Triggered internal clock
Retriggerable internal clock
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R241 TMR
Timer Mode Register
(F1h; Read/Write)
D
D
4
5
T
modes
IN
External clock input = 00
Gate input = 01
Trigger input = 10
(non-retriggerable)
Trigger input = 11
(retriggerable)
Figure 28. Timer Mode Register T Operation
IN
R243 PRE1
Prescaler 1 Register
(F3h; Write Only)
D
1
Clock source
1 = T internal
1
0 = T external (T )
1
IN
Figure 29. Prescaler 1 T Operation
IN
The T counter/timer clock source must be configured for external by setting
1
PRE bit D to 0. The Timer Mode register bits D and D can then be used to
1
2
5
4
select the T operation.
IN
For T to start counting as a result of a T input, the Enable Count bit D in TMR
1
IN
3
must be set to 1. When using T as an external clock or a gate input, the initial
IN
values must be loaded into the down-counters by setting the Load bit D in TMR
2
to 1before counting begins. Initial values are automatically loaded in Trigger and
Retrigger modes, so software loading is unnecessary.
Configure P5 as an input line by setting P5M bit D to 1.
2
2
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Each High-to-Low transition on T generates interrupt request IRQ , regardless
IN
0
of the selected T mode or the enabled/disabled state of T . IRQ must therefore
IN
1
0
be masked or enabled according to the needs of the application.
External Clock Input Mode
The T External Clock Input mode (TMR bits D and D both set to 0) supports
IN
5
4
the counting of external events, where an event is considered to be a High-to-Low
transition on T (see Figure 30) occurrence (single-pass mode) or on every nth
IN
occurrence (continuous mode) of that event.
TMR
D –D = 00
5
4
T
clock
P5
D
D
PRE1
T1
IRQ5
IRQ0
IN
2
Internal clock
Figure 30. External Clock Input Mode
Gated Internal Clock Mode
The T Gated Internal Clock mode (TMR bits D and D set to 0and 1, respec-
IN
5
4
tively) measures the duration of an external event. In this mode, the T prescaler
1
is driven by the internal timer clock, gated by a High level on T (see Figure 31).
IN
T counts while T is High and stops counting when T is Low. Interrupt request
1
IN
IN
IRQ is generated on the High-to-Low transition of T , signaling the end of the
0
IN
gate input. Interrupt request IRQ is generated if T reaches its end-of-count.
5
1
OSC
+2
Internal clock
TMR
D –D = 01
5
4
IRQ5
IRQ0
PRE1
T1
+4
T
gate
IN
P5
D
D
2
Figure 31. Gated Clock Input Mode
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Triggered Input Mode
The T Triggered Input mode (TMR bits D and D set to 1and 0, respectively)
IN
5
4
causes T to start counting as the result of an external event (see Figure 32). T is
1
1
then loaded and clocked by the internal timer clock following the first High-to-Low
transition on the T input. Subsequent T transitions do not affect T . In the sin-
IN
IN
1
gle-pass mode, the Enable bit is reset whenever T reaches its end-of-count. Fur-
1
ther T transitions have no effect on T until software sets the Enable Count bit
IN
1
again. In continuous mode, when T is triggered, counting continues until software
1
resets the Enable Count bit. Interrupt request IRQ is generated when T reaches
5
1
its end-of-count.
OSC
+2
Internal clock
TMR
D = 1
5
IRQ5
PRE1
T1
+4
Edge
trigger
T
IN
P5
D
D
2
trigger
TMR
D –D = 11
5
4
IRQ0
Figure 32. Triggered Clock Mode
Retriggerable Input Mode
The T Retriggerable Input mode (TMR bits D and D both set to 1) causes T to
IN
5
4
1
load and start counting on every occurrence of a High-to-Low transition on T
IN
(see Figure 32). Interrupt request IRQ is generated if the programmed time inter-
5
val (determined by T prescaler and counter/timer register initial values) has
1
elapsed since the last High-to-Low transition on T . In single-pass mode, the
IN
end-of-count resets the Enable Count bit. Subsequent T transitions do not
IN
cause T to load and start counting until software sets the Enable Count bit again.
1
In continuous mode, counting continues when T is triggered until software resets
1
the Enable Count bit. When enabled, each High-to-Low T transition causes T to
IN
1
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reload and restart counting. Interrupt request IRQ is generated on every end-of-
5
count.
T8 and T16 Timer Operation
The T8 timer is a programmable 8-bit counter/timer with two 8-bit capture regis-
ters and two 8-bit load registers. The T16 timer is a programmable 16-bit counter/
timer with one 16-bit capture register pair and one 16-bit load register pair. See
Figure 33. The T8 and T16 counters/timers have two modes of operation:
•
The transmit mode is used to generate complex waveforms. There are two
submodes:
–
The normal mode can be used in single-pass or modulo-N (repeating)
mode.
–
The ping-pong mode is used when the T8 timer counts down, enables the
T16 timer that counts down, enabling T8, and so on, until the mode is
disabled.
•
The demodulation mode is used to capture and demodulate complex
waveforms.
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HI16
LO16
8
8
16-Bit
T16
Timer 16
1 2 4 8
Input
16
Clock
Divider
SCLK
Glitch
Filter
And/Or
Logic
T16 Clocked
8
8
Timer
8/16
TC16H
TC16L
LO8
8
HI8
8
Edge
Detect
Circuit
8-Bit
T8
Timer 8
1 2 4 8
8
8
TC8H
TC8L
Clock
Divider
SCLK
T8 Clock Divider
Figure 33. Counter/Timer Architecture
T8 Transmit Mode
Before T8 is enabled, the output of T8 depends on CTR1, D1. If CTR1, D1 is 0,
T8_OUT is 1. If CTR1, D1 is 1, T8_OUT is 0.
When T8 is enabled, the output T8_OUT switches to the initial value (CTR1 D1). If
the initial value (CTR1 D1) is 0, TC8L is loaded; otherwise, TC8H is loaded into
the counter. In single-pass mode (CTR0 D6), T8 counts down to 0 and stops,
T8_OUT toggles, the time-out status bit (CTR0 D5) is set, and a time-out interrupt
can be generated if it is enabled (CTR0 D1). In modulo-N mode, upon reaching
terminal count, T8_OUT is toggled, but no interrupt is generated. Then T8 loads a
new count (if T8_OUT level is 0), TC8L is loaded; if T8_OUT is 1, TC8H is loaded.
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T8 counts down to 0, toggles T8_OUT, sets the time-out status bit (CTR0 D5), and
generates an interrupt if enabled (CTR0 D1). This completes one cycle. T8 then
loads from TC8H or TC8L, according to the T8_OUT level, and repeats the cycle.
The user can modify the values in TC8H or TC8L at any time.The new values take
effect when they are loaded. Do not write these registers at the time the values
are to be loaded into the counter/timer. An initial count of 1 is not allowed. An ini-
tial count of 0 causes TC8 to count from 0 to FFhto FEh. Transition from 0 to FFh
is not a time-out condition (see Figure 34).
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T8 (8-Bit)
Transmit Mode
No
T8_Enable Bit Set
CTR0 D7
Yes
Reset T8_Enable Bit
1
0
CTR1 D1
Value
Load TC8H
Set T8_OUT
Load TC8L
Reset T8_OUT
Set Time-out Status Bit
(CTR0 D5) and Generate
Timeout_Int. if Enabled
Enable T8
No
T8_Timeout
Yes
Single Pass
Single
Pass?
Modulo-N
1
0
T8_OUT Value
Load TC8L
Reset T8_OUT
Load TC8H
Set T8_OUT
Enable T8
Set Time-out Status Bit
(CTR0 D5) and Generate
Timeout_Int. if Enabled
No
T8_Timeout
Yes
Disable T8
Figure 34. Transmit Mode Flowchart
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Note:
Do not use the same instructions for stopping the counter/
timers and setting the status bits. Two successive commands
are necessary—the first command for stopping counter/timers
and the second command for resetting the status bits—
because one counter/timer clock interval must complete for the
initiated event to actually occur.
T8 Demodulation Mode
Program TC8L and TC8H to FFh. After T8 is enabled, when the first edge (rising,
falling, or both, depending on CTR1 D5, D4) is detected, it starts to count down.
When a subsequent edge (rising, falling, or both, depending on CTR1 D5, D4) is
detected during counting, the current value of T8 is one’s complemented and put
into one of the capture registers. If T8 is a positive edge, data is placed in LO8. If
T8 is a negative edge, data is placed in H18. One of the edge-detect status bits
(CTR1 D1, D0) is set, and an interrupt can be generated if enabled (CTR0 D2).
Meanwhile, T8 is loaded with TC8H and starts counting again. If T8 reaches 0, the
time-out status bit (CTR0 D5) is set, and an interrupt can be generated if enabled
(CTR0 D1), and T8 continues counting from FFh(see Figure 35).
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T8 (8-Bit)
Demodulation Mode
T8 Enable
CTR0, D7
No
Yes
FFh→ TC8
First
Edge Present
No
Yes
Enable TC8
Disable TC8
T8_Enable
Bit Set
No
Yes
No
Edge Present
Yes
No
T8 Time Out
Yes
Set Edge Present Status
Bit and Trigger Data
Capture Int. if Enabled
Set Time-out Status
Bit and Trigger Time
Out Int. if Enabled
Continue Counting
Figure 35. Demodulation Mode Flowchart
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T16 Transit Mode
In normal or ping-pong mode, the output of T16, when not enabled, is dependent
on CTR1, D0. If CTR1, D0 is a 0, T16_OUT is a 1; if CTR1, D0 is a 1, T16_OUT is
0. The user can force the output of T16 to either a 0 or 1, whether it is enabled or
not, by programming CTR1 D3, D2 to a 10 or 11.
When T16 is enabled, TC16H * 256 + TC16L is loaded, and T16_OUT is switched
to its initial value (CTR1 d0). When T16 counts down to 0, T16_OUT is toggled (in
normal or ping-pong mode), an interrupt is generated if enabled (CTR2 D1), and a
status bit (CTR2 D5) is set. If it is in modulo-N mode, it is loaded with TC16H * 256
+ TC16L, and the counting continues.
The user can modify the values in TC16H and TC16L at any time. The new values
take effect when they are loaded. Do not load these registers at the time the val-
ues are to be loaded into the counter/timer. An initial count of 1 is not allowed. An
initial count of 0 causes T16 to count from 0 to FFFFhto FFFEh. Transition from 0
to FFFFhis not a time-out condition.
T16 Demodulation Mode
Program TC16L and TC16H to FFh. After T16 is enabled, when the first edge (ris-
ing, falling, or both, depending on CTR1 D5, D4) is detected, T16 captures HI16
and LO16, reloads, and begins counting.
Ping-Pong Mode
This operation mode is only valid in transmit mode. T8 and T16 must be pro-
grammed in single-pass mode (CTR0 D6, CTR2 D6), and ping-pong mode must
be programmed in CTR1 D3, D2. The user can begin the operation by enabling
either T8 or T16 (CTR0 D7 or CTR2 D7). For example, if T8 is enabled, T8_OUT
is set to this initial value (CTR1 D1). According to T8_OUT’s level, TC8H or TC8L
is loaded into T8. After the terminal count is reached, T8 is disabled, and T16 is
enabled. T16_OUT switches to its initial value (CTR1 D0), data from TC16H and
TC16L is loaded, and T16 starts to count. After T16 reaches the terminal count, it
stops. T8 is enabled again, and the whole cycle repeats. Interrupts can be allowed
when T8 or T16 reaches terminal control (CTR0 D1, CTR2 D1). To stop the ping-
pong operation, write 00 to bits D3 and D2 or CTR1.
Note:
Enabling ping-pong operation while the counters/timers are
running can cause intermittent counter/timer function. Disable
the counters/timers, then reset the status flags before starting
the ping-pong mode.
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Control and Status Registers
The Z86D99/Z86L99 family has 4 I/O port registers, 33 status and control regis-
ters, and 233 general-purpose RAM registers. The I/O port and control registers
are included in the general-purpose register memory to allow any Z8 instruction to
process I/O or control information directly, thus eliminating the requirement for
special I/O or control instructions. The Z8 instruction set permits direct access to
any of these 37 registers. In addition, each of the 233 general-purpose registers
can also function as an accumulator, an address pointer, or an index register.
Registers identified as “Reserved” do not exist or have not been implemented in
this design.
Register Summary
Table 10 through Table 13 summarize the name and location of all registers. The
register-by-register descriptions follow this section.
Table 10.I/O Port Registers (Group 0, Bank 0, Registers 0–F)
Grp/Bnk Reg
(00h) rF
(00h) rE
(00h) rD
(00h) rC
(00h) rB
(00h) rA
(00h) r9
(00h) r8
(00h) r7
(00h) r6
(00h) r5
(00h) r4
(00h) r3
(00h) r2
(00h) r1
(00h) r0
Register Function
Identifier
GPR
GPR
GPR
GPR
GPR
GPR
GPR
GPR
ADCDATA
P6
General-Purpose RAM Register
General-Purpose RAM Register
General-Purpose RAM Register
General-Purpose RAM Register
General-Purpose RAM Register
General-Purpose RAM Register
General-Purpose RAM Register
General-Purpose RAM Register
Analog/Digital Converted Data
Port 6 Control Register
Port 5 Control Register
Port 4 Control Register
Reserved
P5
P4
Port 2 Control Register
Reserved
P2
Reserved
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Table 11. Control and Status Registers (Group F, Bank 0, Registers 0–F)
Grp/Bnk Reg
(F0h) rF
(F0h) rE
(F0h) rD
(F0h) rC
(F0h) rB
(F0h) rA
(F0h) r9
(F0h) r8
(F0h) r7
(F0h) r6
(F0h) r5
(F0h) r4
(F0h) r3
(F0h) r2
(F0h) r1
(F0h) r0
Register Function
Stack Pointer
Identifier
SP
General-purpose RAM Register
Register Pointer
GPR
RP
Program Control Flag Register
Interrupt Mask Register
Interrupt Request Register
Interrupt Priority Register
Reserved
Flags
IMR
IRQ
IPR
Port 3 Mode Register
Port 2 Mode Register
Reserved
P3M
P2M
Reserved
T1 Prescale Register
T1 Data Register
PRE1
T1
T1 Mode Register
Reserved
TMR
Table 12.Timer Control Registers (Group 0, Bank D, Registers 0–F)
Grp/Bnk Reg
(0Dh) rF
(0Dh) rE
(0Dh) rD
(0Dh) rC
(0Dh) rB
(0Dh) rA
(0Dh) r9
(0Dh) r8
(0Dh) r7
(0Dh) r6
(0Dh) r5
(0Dh) r4
(0Dh) r3
(0Dh) r2
(0Dh) r1
(0Dh) r0
Register Function
Identifier
Reserved
Reserved
Reserved
Low-Battery Detect Flag
T16 MS-Byte Capture Register
T16 LS-Byte Capture Register
T8 High Capture Register
T8 Low Capture Register
T16 MS-Byte Hold Register
T16 LS-Byte Hold Register
T8 High Hold Register
T8 Low Hold Register
T8/T16 Control Register B
T16 Control Register
T8/T16 Control Register A
T8 Control Register
LB
HI8
LO8
HI16
LO16
TC16H
TC16L
TC8H
TC8L
CTR3
CTR2
CTR1
CTR0
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Table 13.SMR and Port Mode Registers (Group 0, Bank F, Registers 0–F)
Grp/Bnk Reg
(0Fh) rF
(0Fh) rE
(0Fh) rD
(0Fh) rC
(0Fh) rB
(0Fh) rA
(0Fh) r9
(0Fh) r8
(0Fh) r7
(0Fh) r6
(0Fh) r5
(0Fh) r4
(0Fh) r3
(0Fh) r2
(0Fh) r1
(0Fh) r0
Register Function
Reserved
Identifier
Reserved
Reserved
Reserved
Stop Mode Recovery Register
Reserved
SMR
Reserved
ADC Control Register
Reserved
ADCCTRL
Port 6 Mode
P6M
Port 5 Stop Mode Recovery
Port 5 Mode Register
Reserved
P5SMR
P5M
Port 4 Mode Register
Port 2 Stop Mode Recovery
Port Configuration Register
P4M
P2SMR
P456CON
Register Error Conditions
Registers in the Z8 Standard Register File must be used correctly because certain
conditions produce inconsistent results and must be avoided.
•
•
Registers F5h–F9hare write-only registers. If an attempt is made to read these
registers, FFhis returned. Reading any write-only register returns FFh.
When the Register Pointer (register FDH) is read, the least significant four bits
(lower nibble) indicate the current Expanded Register File Bank. (For
example, 0000 indicates the Standard Register File, while 1010 indicates
Expanded Register File Bank A.)
•
•
•
Writing to bits that are selected as timer outputs changes the I/O register but
has no effect on the pin signal.
The Z8 instruction DJNZ uses any general-purpose working register as a
counter.
Logical instructions such as OR and AND require that the current contents of
the operand be read. They do not function properly on write-only registers.
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Registers (Grouped by Function)
The following is a summary of the 37 special-purpose registers of the Z86D99/
Z86L99 family grouped by function. The following are the functional groups:
•
•
•
•
•
•
•
Flags and Pointers
Analog-to-Digital Converter Control
Interrupt Control
I/O Port Control
Timer Control—General-Purpose Timer (T1)
Timer Control—T8 and T16 Timers
Stop-Mode Recovery Control
For any of the registers described in this section (see Table 14), bits identified as
“Reserved” either do not exist (meaning they have not been implemented in this
design) or have a special purpose in a ZiLOG engineering or test environment.
Caution:
Do not attempt to use these bits as the results are
unpredictable and meaningless.
Table 14.Register Description Locations
Address
Grp/Bnk Register
Register Function
Port 2 Data
Symbol
P2
Location
page 68
page 69
page 70
page 71
page 62
page 77
page 74
page 80
page 76
page 79
page 79
page 82
page 82
page 81
page 81
page 78
00h
00h
00h
00h
00h
0Dh
0Dh
0Dh
0Dh
0Dh
0Dh
0Dh
0Dh
0Dh
0Dh
0Dh
r2 (R2)
r4 (R4)
Port 4 Data
P4
r5 (R5)
Port 5 Data
P5
r6 (R6)
Port 6 Data
P6
r7 (R7)
ADC Data
ADCDATA
CTR0
CTR1
CTR2
CTR3
TC8L†
TC8H†
TC16L†
TC16H†
LO16†
HI16†
LO8†
r0
r1
r2
r3
r4
r5
r6
r7
r8
r9
r10
T8 Timer Control
T8/T16 Control (A)
T16 Timer Control
T8/T16 Control (B)
T8 Low Load
T8 High Load
T16 Low Load
T16 High Load
T16 Low Capture
T16 High Capture
T8 Low Capture
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Table 14.Register Description Locations (Continued)
Address
Grp/Bnk Register
Register Function
T8 High Capture
Symbol
HI8†
Location
page 78
page 60
page 67
page 84
page 69
page 70
page 84
page 71
0Dh
0Dh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
0Fh
F0h
F0h
F0h
F0h
F0h
F0h
F0h
F0h
F0h
F0h
F0h
r11
r12
Low Battery Detect
LB
r0
Port Configuration (A) P456CON
r1
Port 2 SMR Source
Port 4 Mode
P2SMR
P4M
r2
r4
Port 5 Mode
P5M
r5
Port 5 SMR Source
Port 6 Mode
P5SMR
P6M
r6
r8
ADC Control
ADCCTRL page 61
r11
Stop Mode Recovery
T1 Timer Mode
T1 Timer Data
T1 Timer Prescale
Port 2 Mode
SMR
TMR
T1
page 83
page 72
page 72
page 73
page 68
page 67
page 64
page 65
page 63
page 57
page 58
page 59
r1 (R241)
r2 (R242)
r3 (R243)
r6 (R246)
r7 (R247)
r9 (R249)
r10 (R250)
r11 (R251)
r12 (R252)
r13 (R253)
r15 (R255)
PRE1
P2M
Port Configuration (B) P3M
Interrupt Priority
Interrupt Request
Interrupt Mask
IPR
IRQ
IMR
Program Control Flags Flags
Register Pointer
Stack Pointer
RP
SP
Note: †This register is not reset following Stop Mode Recovery
(SMR).
Flags and Pointer Registers
In addition to the three standard Z8 flag and pointer registers (Program Control
Register Pointer, and Stack Pointer), the Z86D99/Z86L99 family includes a Low-
Battery Detect Flag register.
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Program Control Flag Register (Flags)
The Program Control Flag register (see Table 15) reflects the current status of the
Z8 as shown in Table 15. The FLAGS register contains six bits of status informa-
tion that are set or cleared by CPU operations. Four of the bits (C, V, Z, and S) can
be tested for use with conditional jump instructions. Two flags (H and D) cannot be
tested and are used for BCD arithmetic. The two remaining flags in the register
(F1 and F2) are available to the user, but they must be set or cleared by instruc-
tions and are not usable with conditional jumps.
Table 15.FLAGS Register [Group/Bank F0h, Register C (R252)]
Bit
7
6
5
4
3
2
1
0
Bit/Field
R/W
C
Z
S
V
D
H
F2
R/W
X
F1
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
Reset
R = Read, W = Write, X = Indeterminate
Bit
Position
Bit/Field
R/W
Value
Description
7_______
Carry Flag (C)
R/W
1
Indicates the “carry out” of bit 7
position of a register being used as
an accumulator; on Rotate and Shift
instructions this bit contains the most
recent value shifted out of the
specified register
_6______
__5_____
Zero Flag (Z)
Sign Flag (S)
R/W
R/W
1
Indicates that the contents of an
accumulator register is zero following
an arithmetic or logical operation
X
Stores the value of the most
significant bit of a result following an
arithmetic, logical, Rotate, or Shift
operation; in arithmetic operations on
signed numbers, a positive number is
identified by a 0, and a negative
number is identified by a 1
___4____
Overflow
Flag (V)
R/W
1
For signed arithmetic, Rotate, and
Shift operations, the flag is set to 1
when the result is greater than the
maximum possible number (>127) or
less than the minimum possible
number (<-128) that can be
represented in two’s complement
form; following logical operations, this
flag is set to 0
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Table 15.FLAGS Register [Group/Bank F0h, Register C (R252)] (Continued)
____3___
Decimal Adjust
Flag (D)
R/W
1
0
Used for BCD arithmetic—after a
subtraction, the flag is set to 1;
following an addition, it is cleared to 0
_____2__
Half Carry
Flag (H)
R/W
1
0
Set to 1, whenever an addition
generates a “carry out” of bit position
3 (overflow) of an accumulator; or
subtraction generates a “borrow into”
bit 3
______1_
_______0
User Flag (F2)
User Flag (F1)
R/W
R/W
1
0
User definable
1
0
User definable
Register Pointer (RP)
Z8 instructions can access registers directly or indirectly using either a 4-bit or 8-
bit address field. The upper nibble of the Register Pointer, as described in
Table 16, contains the base address of the active Working Register GROUP. The
lower nibble contains the base address of the Expanded Register File BANK.
When using 4-bit addressing, the 4-bit address of the working register (r0 to rF) is
combined with the upper nibble of the Register Pointer (identifying the WR
GROUP), thus forming the 8-bit actual address.
Table 16.RP Register [Group/Bank F0h, Register D (R253)]
Bit
7
6
5
4
3
2
1
0
Bit/Field
R/W
Working Register Group
Expanded Register File Bank
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Reset
R = Read, W = Write, X = Indeterminate
Bit
Position
Bit/Field
R/W
Value
Description
7654_____ Working Register R/W
Group Pointer
X
Identifies 1 of 16 possible WR
Groups, each containing 16 Working
Registers
_____3210 Expanded
Register File
R/W
X
Identifies 1 of 16 possible ERF
Banks; only Banks 0, D, and F are
valid for the Z86D99/Z86L99 family
Bank Pointer
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Stack Pointer (SP)
The Z86D99/Z86L99 family of products is configured for an internal stack. The
size of the stack is limited only by the available memory space or general-purpose
RAM registers dedicated to this task. An 8-bit stack pointer, as described in
Table 17, is used for all stack operations.
Table 17.SP Register [Group/Bank F0h, Register F (R255)]
Bit
7
6
5
4
3
2
1
0
Bit/Field
R/W
Stack Pointer
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
Reset
R = Read, W = Write, X = Indeterminate
Bit
Position
Bit/Field
R/W
Value
Description
76543210
Stack Pointer
R/W
X
Points to the data stored on the top of
the stack; an overflow or underflow
can occur if the stack address is
incremented or decremented during
normal stack operations
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Low-Battery Detect Flag (LB)
When the Z86D99/Z86L99 is used in a battery-operated application, one of the
on-chip comparators can be used to check that the V is at the required level for
CC
correct operation of the device. When voltage begins to approach the V point,
BO
an on-chip low-battery detection circuit is tripped, which in turn sets a user-read-
able flag. The LB register, as described in Table 18, is used to set and reset the
LB flag.
Table 18.LB Register (Group/Bank 0Dh, Register C)
Bit
7
6
5
4
3
2
1
0
Pad
LVD
LVD_
Flag
LVD_
Enable
Bit/Field
R/W
Reserved
W
1
W
W
1
W
1
W
1
R/W
X
R/W
0
R/W
0
Reset
1
R = Read, W = Write, X = Indeterminate
Bit
Position
Bit/Field
R/W
Value
Description
76543___
Reserved
R
1
Always reads 11111
W
X
No Effect
_____2__
Pad LVD
R
1
0
X
Pad is not regulated when P43=0
(Vpad<Vmin; see page 33)
Pad is regulating the current when
P43=0 (Vpad>Vmin; see page 33)
Reset Pad LB flag
R
W
______1_
_______0
LVD_Flag
R
R
W
1
0
X
LB Flag Set if V <V
DD LV
LB Flag Reset
No Effect
LVD_Enable
R/W
1
0
Enable LB *
Disable LB
Note: * When LVD is enabled, IRQ5 is set only for low-voltage detection. Timer 1 will not generate
an interrupt request.
Note:
The LB flag will be valid after enabling the detection for 20 µS
(design estimation, not tested in production). LB does not work
at STOP mode. It must be disabled during STOP mode in order
to reduce current.
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Analog-to-Digital Converter Control Registers
The Z86D99/Z86L99 family features an 8-bit analog-to-digital converter with
external voltage references. The output of the ADC is stored in the ADC Data
Register, as shown in Table 20. The ADC is configured using the ADC Control
Register, as shown in Table 19.
Table 19.ADCCTRL Register (Group/Bank 0Fh, Register 8)
Bit
7
6
5
4
3
2
1
0
ADC
P47_
A/D
P46_
A/D
P45_
A/D
P44_
A/D
Channel
Selection
A/D Pwr Clock
Bit/Field
R/W
On
R/W
0
Select
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
Reset
0
R = Read, W = Write, X = Indeterminate
Bit
Position
Bit/Field
R/W
Value
Description
P47 configured as A/D Input
P47 configured as digital input
7_______
P47_A/D
R/W
1
0
_6______
__5_____
___4____
____32__
P46_A/D
P45_A/D
P44_A/D
R/W
R/W
R/W
R/W
1
0
P46 configured as A/D Input
P46 configured as digital input
1
0
P45 configured as A/D Input
P45 configured as digital input
1
0
P44 configured as A/D Input
P44 configured as digital input
Channel
Selection
11
10
01
00
Channel 3 (P47)
Channel 2 (P46)
Channel 1 (P45)
Channel 0 (P44)
______1_
_______0
A/D_PowerON
R/W
1
0
ON
OFF
ADC Clock Select R/W
1
0
SCLK/2
SCLK
ADC Control Register (ADCCTRL)
The ADCCTRL register controls the operation of the analog-to-digital converter.
Bits 2 and 3 of the ADCCTRL register determine which of the four analog input
channels feeds into the ADC at any given time. Bits 4 through 7 enable or disable
the digital input buffer. When configured as an ADC input channel, the port has to
be configured in Input Mode and with the digital input buffer disabled.
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62
ADC Data Register (ADCDATA)
The ADCDATA register is a read-only register that contains the digital output of
the analog-to-digital converter. See Table 20.
)
Table 20.ADCDATA Register (Group/Bank 00h, Register 7)
Bit
7
6
5
4
3
2
1
0
Bit/Field
R/W
ADC Data
R
0
R
R
0
R
0
R
0
R
0
R
0
R
0
Reset
0
R = Read, W = Write, X = Indeterminate
Bit
Position
Bit/Field
R/W
Value
Description
76543210
ADC Data
R
W
Data
X
Output of the ADC
No Effect
Interrupt Control Registers
The Z8 allows up to six different interrupts from a variety of sources. These inter-
rupts can be masked and their priorities set by using the Interrupt Mask Register
and Interrupt Priority Register. The Interrupt Request Register stores the interrupt
requests for both vectored and polled interrupts.
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Interrupt Mask Register
The IMR, as described in Table 21, individually or globally enables the six interrupt
requests. Bit 7 of the IMR is the master enable and must be set before any of the
individual interrupt requests can be recognized. Bit 7 must be set and reset by the
enable interrupts and disable interrupts instructions only. The IMR is automatically
reset during an interrupt service routine and set following the execution of an
Interrupt Return (IRET) instruction.
Table 21.IMR (Group/Bank 0Fh, Register B)
Bit
7
6
5
4
3
2
1
0
Re-
Bit/Field
R/W
Master served IRQ5
IRQ4
R/W
0
IRQ3
R/W
0
IRQ2
R/W
0
IRQ1
R/W
0
IRQ0
R/W
0
R/W
0
R/W
0
R/W
0
Reset
R = Read, W = Write, X = Indeterminate
Bit
Position
Bit/Field
R/W
Value
Description
7_______
Master
R/W
1
0
Enable Master Interrupt
Disable Master Interrupt
_6______
__5_____
___4____
____3___
_____2__
______1_
_______0
Reserved
IRQ5
R
W
1
X
Always reads 1
No Effect
R/W
R/W
R/W
R/W
R/W
R/W
1
0
Enable IRQ5
Disable IRQ5
IRQ4
1
0
Enable IRQ4
Disable IRQ4
IRQ3
1
0
Enable IRQ3
Disable IRQ3
IRQ2
1
0
Enable IRQ2
Disable IRQ2
IRQ1
1
0
Enable IRQ1
Disable IRQ1
IRQ0
1
0
Enable IRQ0
Disable IRQ0
Note:
Bit 7 must be reset by the DI instruction before the contents of
the Interrupt Mask Register or the Interrupt Priority Register are
changed except in the following situations:
–
–
Immediately after a hardware reset
Immediately after executing an interrupt service routine and before IMR bit
7 has been set by any instruction
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64
Interrupt Priority Register (IPR)
The IPR, as described in Table 22, is a write-only register that sets priorities for
the vectored interrupts in order to resolve simultaneous interrupt requests. There
are 48 sequence possibilities for interrupts. The six interrupts, IRQ to IRQ , are
0
5
divided into three groups of two interrupt requests each, as follows:
•
•
Group A consists of IRQ and IRQ
3
5
2
Group B consists of IRQ and IRQ
0
•
Group C consists of IRQ and IRQ
1 4
)
Table 22.IPR (Group/Bank 0Fh, Register 9)
Bit
7
6
5
4
3
2
1
0
Grp A
Grp B
Grp C
Int_
Bit/Field
R/W
Reserved
IRQ3_5 Int_Group
IRQ0_2 IRQ1_4 Group
W
0
W
W
0
W
0
W
0
W
0
W
0
W
0
Reset
0
R = Read, W = Write, X = Indeterminate
Bit
Position
76______
__5_____
Bit/Field
R/W
W
Value
Description
Reserved
X
No Effect
Grp A Priority:
IRQ3 and IRQ5
W
1
0
IRQ3>IRQ5 (Group A)
IRQ5>IRQ3
___43__0
Interrupt Group
Priority
W
111
110
101
100
011
010
001
000
Reserved
B>A>C
C>B>A
B>C>A
A>C>B
A>B>C
C>A>B
Reserved
_____2__
______1_
Grp B Priority:
IRQ0 and IRQ2
W
W
1
0
IRQ0>IRQ2 (Group B)
IRQ2>IRQ0
Grp C Priority:
IRQ1 and IRQ4
1
0
IRQ4>IRQ1 (Group C)
IRQ1>IRQ4
Priorities can be set both within and between groups using the IPR. Bits 1, 2, and
5 of the IPR define the priority of individual members within the groups. Bits 0, 3,
and 4 are encoded to define six priority orders between the three groups. Bits 6
and 7 are reserved.
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Interrupt Request Register
The IRQ, as described in Table 23, is a read/write register that stores the interrupt
requests for both vectored and polled interrupts. When an interrupt request is
made by any of the six interrupts, the corresponding bit in the IRQ is set to 1.
Table 23.IRQ (Group/Bank 0Fh, Register A)
Bit
7
6
5
4
3
2
1
0
Set
Set
Set
Set
Set
Set
Bit/Field
R/W
Interrupt Edge
IRQ5
IRQ4
IRQ3
IRQ2
IRQ1
IRQ0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Reset
R = Read, W = Write, X = Indeterminate
Bit
Position
Bit/Field
R/W
Value
Description
76______
Interrupt Edge
Trigger
R/W
11
10
01
00
P51 Rise/FallingP52 Rise/Falling
P51 Rising P52 Falling
P51 FallingP52 Rising
P51 FallingP52 Falling
__5_____
___4____
____3___
_____2__
______1_
_______0
Set IRQ5
Set IRQ4
Set IRQ3
Set IRQ2
Set IRQ1
Set IRQ0
R
R
W
W
1
0
1
0
IRQ5 Inactive
IRQ5 Active
Set IRQ5
Reset IRQ5
R
R
W
W
1
0
1
0
IRQ4 Inactive
IRQ4 Active
Set IRQ4
Reset IRQ4
R
R
W
W
1
0
1
0
IRQ3 Inactive
IRQ3 Active
Set IRQ3
Reset IRQ3
R
R
W
W
1
0
1
0
IRQ2 Inactive
IRQ2 Active
Set IRQ2
Reset IRQ2
R
R
W
W
1
0
1
0
IRQ1 Inactive
IRQ1 Active
Set IRQ1
Reset IRQ1
R
R
W
W
1
0
1
0
IRQ0 Inactive
IRQ0 Active
Set IRQ0
Reset IRQ0
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Whenever a power-on reset is executed, the IRQ is reset to 00hand disabled.
Before the IRQ accepts requests, it must be enabled by executing an enable inter-
rupts instruction.
Note:
IRQ is always cleared to 00hand is in read-only mode until the
first EI instruction that enables the IRQ to be read/write. Setting
the Global Interrupt Enable bit in the Interrupt Mask Register
(IMR bit 7) does not enable the IRQ. Execution of an EI
instruction is required.
For polled processing, IRQ must be initialized by an EI instruction. To properly ini-
tialize the IRQ, the following code is provided:
CLR
EI
IMR
; make sure vectored interrupts are disabled
; enable IRQ, otherwise it is read only
; not necessary, if interrupts were previously
; enabled
DI
; disable interrupt handling
IMR is cleared before the IRQ enabling sequence to ensure no unexpected inter-
rupts occur when EI is executed. This code sequence must be executed before
programming the application required values for IPR and IMR.
I/O Port Control Registers
Each of the four ports (Ports 2, 4, 5, and 6) has an input register, an output regis-
ter, and an associated buffer and control logic. Because there are separate input
and output registers associated with each port, writing bits defined as inputs
stores the data in the output register. This data cannot be read as long as the bits
are defined as inputs. However, if the bits are reconfigured as output, the data
stored in the output register is reflected on the output pins and can then be read.
This mechanism allows the user to initialize the outputs before driving their loads.
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Port Configuration Registers (P456CON and P3M)
The port configuration register (described in Table 24) switches the comparator
inputs from digital to analog and allows Ports 4, 5, and/or 6 to be switched from
push/pull active outputs to open drain outputs. In ZiLOG Test Mode, bit 3 of this
register is used to enable the Address Strobe/Data Strobe. Bit 3 is not available in
User Mode.
Table 24.P456CON Register (Group/Bank 0Fh, Register 0)
Bit
7
6
5
4
3
2
1
0
P51_ P52_
P6_
P5_
P4_
Bit/Field
R/W
Not Used
Mode Mode Reserved Output Output Output
R/W
0
R/W
R/W
0
R/W
0
R/W
0
W
1
W
W
1†
0
1
Reset
R = Read, W = Write, X = Indeterminate
Bit
Position
Bit/Field
R/W
Value Description
76______
Not Used
R/W
These bits exist but do not have any
function assigned to them; they are
reserved for future extensions and must
not be used.
__5_____
___4____
Comparator 1
Mode
R/W
R/W
1
0
Analog (P50, P51 as Inputs)
Digital inputs
Comparator 2
Mode
1
0
Analog comparator inputs (P52, P53
configured as Inputs)
Digital inputs
____3___
_____2__
Reserved
Port 6 Output
Configuration
W
W
W
1
0
Push-Pull Active
Open Drain Outputs
Always reads back 1*
______1_
_______0
Port 5 Output
Configuration
1
0
Push-Pull Active
Open Drain Outputs
Always reads back 1*
Port 4 Output
Configuration
1
0
Push-Pull Active
Open Drain Outputs
Always reads back 1*†
Note: *Do not use the read-modify-write instructions (for example, OR and AND) with this register.
Bits 0, 1, and 2 always read back 1.
Note: †For Z86L990/L991, P43 can never be configured as push-pull. After any reset, P43 is
configured as tristate high impedance.
Port 2 outputs are configured using the P3M Register, shown in Table 25. Bit 0 of
the P3M Register switches Port 2 from push/pull active to open drain outputs. No
other bits in this register are implemented.
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Table 25.P3M Register [Group/Bank F0h, Register 7 (R247)]
Bit
7
6
5
4
3
2
1
0
P2_
Bit/Field
R/W
Reserved
Output
W
1
W
W
1
W
1
W
1
W
1
W
1
W
1
Reset
1
R = Read, W = Write, X = Indeterminate
Bit
Position
Bit/Field
R/W
Value
Description
7654321_
Reserved
R
1
Always reads 1111111
W
X
No Effect
_________0 Port 2 Output
Configuration
W
1
0
Push-Pull Active
Open Drain Outputs
Port 2 Control and Mode Registers (P2 and P2M)
Port 2 is a general-purpose 8-bit, bidirectional I/O port, as shown in Table 26.
Each of the eight Port 2 I/O lines can be independently programmed as either
input or output using the Port 2 Mode Register (see Table 27.)
Table 26.P2 Register [Group/Bank 00h, Register 2 (R2)]
Bit
7
6
5
4
3
2
1
0
Bit/Field
R/W
Port 2 Data
R/W
X
R/W
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
Reset
X
R = Read, W = Write, X = Indeterminate
Bit
Position
Bit/Field
R/W
Value
Description
Port 2 Input/Output Register
76543210
Port 2 Data
R/W
Data
Table 27.P2M Register [Group/Bank F0h, Register 6 (R246)]
Bit
7
6
5
4
3
2
1
0
Bit/Field
R/W
P27M
P26M
P25M
P24M
P23M
P22M
P21M
P20M
W
1
W
1
W
1
W
1
W
1
W
1
W
1
W
1
Reset
R = Read, W = Write, X = Indeterminate
Bit
Position
Bit/Field
R/W
Value
Description
76543210
(by bit)
Port 2 Mode
Select
R
W
W
1
1
0
Always reads 11111111
Input
Output
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A bit set to 1 in the P2M Register configures the corresponding bit in Port 2 as an
input, while a bit set to 0 configures an output line.
Port 4 Control and Mode Registers (P4 and P4M)
Port 4 is a general-purpose 8-bit, bidirectional I/O port, as shown in Table 28.
Each of the eight Port 4 I/O lines can be independently programmed as either
input or output using the Port 4 Mode Register (see Table 29.)
Table 28.P4 Register [Group/Bank 00h, Register 4 (R4)]
Bit
7
6
5
4
3
2
1
0
Bit/Field
R/W
Port 4 Data
R/W
X
R/W
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
Reset
X
R = Read, W = Write, X = Indeterminate
Bit
Position
Bit/Field
R/W
Value
Description
Port 4 Input/Output Register
76543210
Port 4 Data
R/W
Data
.
Table 29.P4M Register (Group/Bank 0Fh, Register 2)
Bit
7
6
5
4
3
2
1
0
Bit/Field
R/W
P47M
R/W
1
P46M
R/W
1
P45M
R/W
1
P44M
R/W
1
P43M
R/W
1
P42M
R/W
1
P41M
R/W
1
P40M
R/W
1
Reset
R = Read, W = Write, X = Indeterminate
Bit
Position
Bit/Field
R/W
Value
Description
7654_210
(by bit)
Port 4 Mode
Select
R/W
1
0
Input
Output
____3___
P43
Mode Select
R/W
0
1
Output
Tristate High Impedance (available
on Z86L990/L991 only)
A bit set to 1 in the P4M Register configures the corresponding bit in Port 4 as an
input, while a bit set to 0 configures an output line.
Note:
P43, the controlled current output pad, cannot be configured as
an input. (P43 read = P43 out)
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Port 5 Control and Mode Registers (P5 and P5M)
Port 5 is a general-purpose 8-bit, bidirectional I/O port, as shown in Table 30.
Each of the eight Port 5 I/O lines can be independently programmed as either
input or output using the Port 5 Mode Register (see Table 31.)
Table 30.P5 Register [Group/Bank 00h, Register 5 (R5)]
Bit
7
6
5
4
3
2
1
0
Bit/Field
R/W
Port 5 Data
R/W
X
R/W
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
Reset
X
R = Read, W = Write, X = Indeterminate
Bit
Position
Bit/Field
R/W
Value
Description
Port 5 Input/Output Register
76543210
Port 5 Data
R/W
Data
Table 31.P5M Register (Group/Bank 0Fh, Register 4)
Bit
7
6
5
4
3
2
1
0
Bit/Field
R/W
P57M
R/W
1
P56M
R/W
1
P55M
R/W
1
P54M
R/W
1
P53M
R/W
1
P52M
R/W
1
P51M
R/W
1
P50M
R/W
1
Reset
R = Read, W = Write, X = Indeterminate
Bit
Position
Bit/Field
R/W
Value
Description
7654__10
(by bit)
Port 5 Mode
Select
R/W
1
0
Input
Output
____32__
P53, P52
R/W
1
Input
Mode Select
Regardless of what is written to this
pin, P53 and P52 are always in input
mode.
A bit set to a 1 in the P5M Register configures the corresponding bit in Port 5 as
an input, while a bit set to 0 configures an output line.
Note:
Regardless of how P5M bits 2 and 3 are set, P52 and P53 are
always in input mode.
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Port 6 Control and Mode Registers (P6 and P6M)
Port 6 is a general-purpose 8-bit, bidirectional I/O port, as shown in Table 32.
Each of the eight Port 6 I/O lines can be independently programmed as either
input or output using the Port 6 Mode Register (see Table 33.)
Table 32.P6 Register [Group/Bank 00h, Register 6 (R6)]
Bit
7
6
5
4
3
2
1
0
Bit/Field
R/W
Port 6 Data
R/W
X
R/W
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
R/W
X
Reset
X
R = Read, W = Write, X = Indeterminate
Bit
Position
Bit/Field
R/W
Value
Description
Port 6 Input/Output Register
76543210
Port 6 Data
R/W
Data
Table 33.P6M Register (Group/Bank 0Fh, Register 6)
Bit
7
6
5
4
3
2
1
0
Bit/Field
R/W
P67M
R/W
1
P66M
R/W
1
P65M
R/W
1
P64M
R/W
1
P63M
R/W
1
P62M
R/W
1
P61M
R/W
1
P60M
R/W
1
Reset
R = Read, W = Write, X = Indeterminate
Bit
Position
Bit/Field
R/W
Value
Description
76543210
(by bit)
Port 6 Mode
Select
R/W
1
0
Input
Output
A bit set to 1 in the P6M Register configures the corresponding bit in Port 6 as an
input, while a bit set to 0 configures an output line.
Timer Control Registers—General-Purpose Timer (T1)
The Z86D99/Z86L99 family provides one standard 8-bit Z8 counter/timer, T1,
driven by its own 6-bit prescaler, PRE1. T1 is independent of the processor
instruction sequence, relieving software from time-critical operations such as
interval timing or event counting. There are three registers that control the opera-
tion of T1: T1 Data Register (T1), T1 Mode Register (TMR), and T1 Prescale Reg-
ister (PRE1). Because the timer, prescaler, and mode register are mapped into
the standard Z8 register file, the software can treat the counter/timer as a general-
purpose register, thus eliminating the requirement for special instructions.
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T1 Data Register (T1)
The counter/timer register (T1) consists of an 8-bit down counter, a write-only reg-
ister that holds the initial count value, and a read-only register that holds the cur-
rent count value. The initial value of T1 can range from 1 to 255 (0 represents
256) (see Table 34.)
Table 34.T1 Register [Group/Bank F0h, Register 2 (R242)]
Bit
7
6
5
4
3
2
1
0
Bit/Field
R/W
T1_Value
R/W
0
R/W
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Reset
0
R = Read, W = Write, X = Indeterminate
Bit
Position
Bit/Field
R/W
Value
Description
76543210
T1 Value
R
W
Data
Data
Current Value
Initial Value (Range 1 to 256 Decimal)
T1 Mode Register (TMR)
Under software control, T1 counter/timer is started and stopped using the T1
Mode Register as shown in Table 35.
Table 35.TMR Register [Group/Bank F0h, Register 1 (R241)]
Bit
7
6
5
4
3
2
1
0
T1_
T1_
Bit/Field
R/W
TOUT_Mode
TIN_Mode
Count Load
Reserved
R/W
0
R/W
0
R/W
0
R/W
R/W
0
R/W
0
R/W
R/W
Reset
0
1
1
R = Read, W = Write, X = Indeterminate
Bit
Position
Bit/Field
R/W
Value
Description
76______
TOUT Mode
R/W
11
10
01
00
Internal Clock OUT on P56
T1OUT on P56
Reserved
Not used (P56 configured as I/O)
__54____
____3___
T
IN Mode
R/W
R/W
11
10
01
00
Trigger Input (Retriggerable)
Trigger Input (Not-retriggerable)
Gate Input
External Clock Input (TIN on P52)
T1 Count
1
0
Enable T1 Count
Disable T1 Count
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Table 35.TMR Register [Group/Bank F0h, Register 1 (R241)] (Continued)
_____2__
______10
T1 Load
R/W
1
0
Load T1
No effect
Reserved
R
1
Always reads 11
W
X
No effect
T1 Prescale Register (PRE1)
The T1 prescaler consists of an 8-bit register and a 6-bit down-counter. The six
most significant bits (D2–D7) of PRE1 hold the prescaler’s count modulo, a value
from 1 to 64 decimal, as shown in Table 36. The prescale register also contains
control bits that specify the counting mode and clock source for T1.
Table 36.PRE1 Register [Group/Bank F0h, Register 3 (R243)]
Bit
7
6
5
4
3
2
1
0
Clock_ Count_
Source Mode
Bit/Field
R/W
Prescaler_Modulo
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
R/W
Reset
0
0
R = Read, W = Write, X = Indeterminate
Bit
Position
Bit/Field
R/W
Value
Description
765432__
Prescaler Modulo R/W
Data
Range: 1 to 64 Decimal
_______1_ Clock Source
R/W
R/W
1
0
T1 Internal
T1 External (TIN on P52)
________0 Count Mode
1
0
T1 Modulo-n
T1 Single Pass
Timer Control Registers—T8 and T16 Timers
One of the unique features of the Z86D99/Z86L99 family is a special timer archi-
tecture to automate the generation and reception of complex pulses or signals.
This timer architecture consists of one programmable 8-bit counter timer with two
capture registers and two load registers and a programmable 16-bit counter/timer
with one 16-bit capture register pair and one 16-bit load register pair and their
associated control registers. These counter/timers can work independently or can
be combined together using a number of user-selectable modes governed by the
T8/T16 control registers.
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Low-Voltage Microcontrollers with ADC
74
T8/T16 Control Register A (CTR1)
The T8/T16 Control Register A controls the functions in common with both the T
8
and T counter/timers. The T and T counter/timers have two primary modes of
16
8
16
operation: Transmit Mode and Demodulation Mode. Transmit Mode is used for
generating complex waveforms. The Transmit Mode has two submodes: Normal
Mode and Ping-Pong Mode. The settings for CTR1 in Transmit Mode are given in
Table 37.
Table 37.CTR1 Register (In Transmit Mode) (Group/Bank 0Dh, Register 1)
Bit
7
6
5
4
3
2
1
0
Initial_
P43
Out
Transmit_
Submode
Initial_ T16_
T8_Out Out
Bit/Field
R/W
Mode
R/W
0
T8/T16_Logic
R/W
0
R/W
0
R/W
0
R/W
0
R/W
R/W
R/W
Reset
0
0
0
R = Read, W = Write, X = Indeterminate
Bit
Position
Bit/Field
R/W
Value
Description
7_______
Mode
R/W
1
0
Demodulation
Transmit
_6______
__54____
P43_Out
R/W
R/W
1
0
P43 configured as T8/T16 Output
P43 configured as I/O
T8/T16 Logic
11
10
01
00
NAND
NOR
OR
AND
____32__
Transmit_
Submode
R/W
11
10
01
00
T16_Out = 1
T16_Out = 0
Ping-Pong Mode
Normal Operation
______1_
_______0
Initial_T8_Out
Initial_T16_Out
R/W
R/W
1
0
T8_Out set to 1 initially
T8_Out set to 0 initially
1
0
T16_Out set to 1 initially
T16_Out set to 0 initially
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Z86D990/Z86D991 OTP and Z86L99X ROM
Low-Voltage Microcontrollers with ADC
75
In Demodulation Mode, the T8 and T16 counter/timers are used to capture and
demodulate complex waveforms. The settings for CTR1 in Demodulation Mode
are given in Table 38.
Table 38.CTR1 Register (in Demodulation Mode) (Group/Bank 0Dh, Register 1)
Bit
7
6
5
4
3
2
1
0
Demod
Rising Falling
Bit/Field
R/W
Mode
R/W
0
_Input Edge_Detect
Glitch_Filter
Edge
R/W
0
Edge
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Reset
R = Read, W = Write, X = Indeterminate
Bit
Position
Bit/Field
R/W
Value
Description
7_______
Mode
R/W
1
0
Demodulation
Transmit
_6______
__54____
Demodulator_
Input
R/W
R/W
1
0
P20 as Demodulator Input
P51 as Demodulator Input
Edge_Detect
Glitch_Filter
Rising_Edge
Falling_Edge
11
10
01
00
Reserved
Both Edges
Rising Edge
Falling Edge
____32__
______1_
_______0
R/W
11
10
01
00
16 SCLK Cycles
8 SCLK Cycles
4 SCLK Cycles
No Filter
R
R
W
W
1
0
1
0
Rising Edge Detected
No Rising Edge
Reset Flag to 0
No Effect
R
R
W
W
1
0
1
0
Falling Edge Detected
No Falling Edge
Reset Flag to 0
No Effect
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Low-Voltage Microcontrollers with ADC
76
T8/T16 Control Register B (CTR3)
The T8/T16 Control Register B, known as CTR3, is a new register to the Z86D99/
Z86L99 family. This register allows the T and T counters to be synchronized.
8
16
The settings of CTR3 are described in Table 39.
Table 39.CTR3 Register (Group/Bank 0Dh, Register 3)
Bit
7
6
5
4
3
2
1
0
T16_
T8_
Sync
Bit/Field
R/W
Enable Enable Mode
Reserved
R/W
0
R/W
0
R/W
0
R/W
X
R/W
R/W
X
R/W
R/W
Reset
X
X
X
R = Read, W = Write, X = Indeterminate
Bit
Position
Bit/Field
16 Enable
R/W
Value
Description
7_______
T
R
R
W
W
1
0
1
0
Counter Enabled
Counter Disabled
Enable Counter
Stop Counter
_6______
T8 Enable
R
R
W
W
1
0
1
0
Counter Enabled
Counter Disabled
Enable Counter
Stop Counter
__5_____
___43210
Sync Mode
Reserved
R/W
1
0
Enable Sync Mode
Diable Sync Mode
R
1
Always reads 11111
W
X
No Effect
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Low-Voltage Microcontrollers with ADC
77
T8 Control Register (CTR0)
As shown in Table 40, the T8 Control Register, known as CTR0, controls the oper-
ation of the 8-bit T timer.
8
Table 40.CTR0 Register (Group/Bank 0Dh, Register 0)
Bit
7
6
5
4
3
2
1
0
Single/
Mod-
Enable ulo-n
Capture Counter
T8_
Time_
Out
INT_
INT_
P40_
Out
Bit/Field
R/W
T8_Clock
Mask
Mask
R/W
0
R/W
0
R/W
0
R/W
0
R/W
R/W
0
R/W
R/W
Reset
0
0
0
R = Read, W = Write, X = Indeterminate
Bit
Position
Bit/Field
R/W
Value
Description
7_______
T8 Enable
R
R
W
W
1
0
1
0
Counter Enabled
Counter Disabled
Enable Counter
Stop Counter
_6______
__5_____
Single/
Modulo-n
R/W
1
0
Single Pass
Modulo-n
Time_Out
R
R
W
W
1
0
1
0
Counter Timeout Occurred
No Counter Timeout
Reset Flag to 0
No Effect
___43___
T8 Clock
R/W
11
10
01
00
SCLK/8
SCLK/4
SCLK/2
SCLK
_____2__
______1_
_______0
Capture Interrupt R/W
Mask
1
0
Enable Data Capture Interrupt
Disable Data Capture Interrupt
Counter Interrupt R/W
Mask
1
0
Enable Time_Out Interrupt
Disable Time_Out Interrupt
P40_Out
R/W
1
0
P40 configured as T8 Output
P40 configured as I/O
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Low-Voltage Microcontrollers with ADC
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T8 High Capture Register (HI8)
The T8 High Capture Register, as described in Table 41, holds the captured data
from the output of the T counter/timer. This register is typically used to hold the
8
number of counts when the input signal is high (or 1).
Table 41.HI8 Register (Group/Bank 0Dh, Register B)
Bit
7
6
5
4
3
2
1
0
Bit/Field
R/W
T8_Capture_HI
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Reset
R = Read, W = Write, X = Indeterminate
Bit
Position
Bit/Field
R/W
Value
Description
76543210
T8 Capture
High Value
R
W
Data
Captured Data
No Effect
T8 Low Capture Register (LO8)
The T8 Low Capture Register, as described in Table 42, holds the captured data
from the output of the T counter/timer. This register is typically used to hold the
8
number of counts when the input signal is low (or 0).
Table 42.LO8 Register (Group/Bank 0Dh, Register A)
Bit
7
6
5
4
3
2
1
0
Bit/Field
R/W
T8_Capture_LO
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Reset
R = Read, W = Write, X = Indeterminate
Bit
Position
Bit/Field
R/W
Value
Description
76543210
T8 Capture
Low Value
R
W
Data
Captured Data
No Effect
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Low-Voltage Microcontrollers with ADC
79
T8 High Load Register (TC8H)
The T8 High Load Register, as described in Table 43, is loaded with the counter
value necessary to keep the T8_Out signal in the high state for the required time.
Table 43.TC8H Register (Group/Bank 0Dh, Register 5)
Bit
7
6
5
4
3
2
1
0
Bit/Field
R/W
T8_Level_HI
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Reset
R = Read, W = Write, X = Indeterminate
Bit
Position
Bit/Field
R/W
Value
Description
Duration that T8_Out remains High
76543210
T8 Level
R/W
Data
High Value
T8 Low Load Register (TC8L)
The T8 Low Load Register, as described in Table 44, is loaded with the counter
value necessary to keep the T8_Out signal in the low state for the required time.
Table 44.TC8L Register (Group/Bank 0Dh, Register 4)
Bit
7
6
5
4
3
2
1
0
Bit/Field
R/W
T8_Level_LO
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Reset
R = Read, W = Write, X = Indeterminate
Bit
Position
Bit/Field
R/W
Value
Description
Duration that T8_Out remains Low
76543210
T8 Level
R/W
Data
Low Value
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Low-Voltage Microcontrollers with ADC
80
T16 Control Register (CTR2)
The T16 Control Register, known as CTR2, controls the operation of the 16-bit T
timer (see Table 45).
16
Table 45.CTR2 Register (Group/Bank 0Dh, Register 2)
Bit
7
6
5
4
3
2
1
0
Single/
Mod-
Enable ulo-n
Capture Counter
T16_
Time_
Out
INT_
INT_
P41_
Out
Bit/Field
R/W
T16_Clock
Mask
Mask
R/W
0
R/W
0
R/W
0
R/W
0
R/W
R/W
0
R/W
R/W
Reset
0
0
0
R = Read, W = Write, X = Indeterminate
Bit
Position
Bit/Field
16 Enable
R/W
Value
Description
7_______
T
R
R
W
W
1
0
1
0
Counter Enabled
Counter Disabled
Enable Counter
Stop Counter
_6______
Single/
Modulo-n
R/W
In Transmit Mode:
Single Pass
Modulo-n
1
0
In Demodulation Mode:
1
0
T
T
16 Does Not Recognize Edge
16 Recognizes Edge
__5_____
___43___
Time_Out
R
R
W
W
1
0
1
0
Counter Timeout Occurred
No Counter Timeout
Reset Flag to 0
No Effect
T
16 Clock
R/W
11
10
01
00
SCLK/8
SCLK/4
SCLK/2
SCLK
_____2__
______1_
_______0
Capture Interrupt R/W
Mask
1
0
Enable Data Capture Interrupt
Disable Data Capture Interrupt
Counter Interrupt R/W
Mask
1
0
Enable Time_Out Interrupt
Disable Time_Out Interrupt
P41_Out
R/W
1
0
P41 configured as T16 Output
P41 configured as I/O
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T16 MS-Byte Capture Register (HI16)
The T16 MS-Byte Capture Register, as described in Table 46, holds the captured
data from the output of the T counter/timer. This register holds the most signifi-
16
cant byte of the data.
Table 46.HI16 Register (Group/Bank 0Dh, Register 9)
Bit
7
6
5
4
3
2
1
0
Bit/Field
R/W
T16_Capture_HI
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Reset
R = Read, W = Write, X = Indeterminate
Bit
Position
Bit/Field
16 Capture HI
R/W
Value
Description
76543210
T
R
W
Data
MS-Byte of Captured Data
No Effect
T16 LS-Byte Capture Register (LO16)
The T16 LS-Byte Capture Register, as described in Table 47, holds the captured
data from the output of the T counter/timer. This register holds the least signifi-
16
cant byte of the data.
Table 47.LO16 Register (Group/Bank 0Dh, Register 8)
Bit
7
6
5
4
3
2
1
0
Bit/Field
R/W
T16_Capture_LO
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Reset
R = Read, W = Write, X = Indeterminate
Bit
Position
Bit/Field
16 Capture LO
R/W
Value
Description
76543210
T
R
W
Data
LS-Byte of Captured Data
No Effect
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Low-Voltage Microcontrollers with ADC
82
T16 MS-Byte Load Register (TC16H)
The T16 MS-Byte Load Register, as described in Table 48, is loaded with the most
significant byte of the T counter value.
16
Table 48.TC16H Register (Group/Bank 0Dh, Register 7)
Bit
7
6
5
4
3
2
1
0
Bit/Field
R/W
T16_Data_HI
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Reset
R = Read, W = Write, X = Indeterminate
Bit
Position
Bit/Field
16 Data HI
R/W
Value
Description
MS-Byte of the T16 Counter
76543210
T
R/W
Data
T16 LS-Byte Load Register (TC16L)
The T16 LS-Byte Load Register, as described in Table 49, is loaded with the least
significant byte of the T counter value.
16
Table 49.TC16L Register (Group/Bank 0Dh, Register 6)
Bit
7
6
5
4
3
2
1
0
Bit/Field
R/W
T16_Data_LO
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Reset
R = Read, W = Write, X = Indeterminate
Bit
Position
Bit/Field
16 Data LO
R/W
Value
Description
LS-Byte of the T16 Counter
76543210
T
R/W
Data
Stop-Mode Recovery Control Registers
The Z86D99/Z86L99 family of products allows 16 individual I/O pins (Ports 2 and
5) to be used as a stop-mode recovery sources. The STOP mode is exited when
one of these SMR sources is toggled.
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Low-Voltage Microcontrollers with ADC
83
Stop-Mode Recovery Register
The SMR register serves two functions. Bit D7 of the SMR register, as shown in
Table 50, is the Stop Mode Flag that is set upon entering stop mode. A 0 in this bit
indicates that the device has been reset by a POR or WDT Reset. A POR or WDT
Reset is sometimes referred to as a “cold” start. A 1 in bit D7 indicates that the
device was awakened by a SMR source. Waking a device with a SMR source is
sometimes referred to as a “warm” start.
The Stop Mode Recovery source can be selected by any combination of P2 and
P5 by P2SMR and P5SMR, respectively. If the pin is selected as the SMR source,
its logic level is latched into a register. A wait up signal is generated if its logic level
changes. This applies to all selected pins for the SMR source.
The comparators of P5 cannot be used as an SMR source. The comparator is
turned off in STOP mode.
Table 50.SMR Register (Group/Bank 0Fh, Register B)
Bit
7
6
5
4
3
2
1
0
Stop
Flag
Re-
Stop
Bit/Field
R/W
served Delay
Reserved
SCLK Select
R
0
R/W
0
W
1
R/W
0
R/W
R/W
0
W
0
W
0
Reset
0
R = Read, W = Write, X = Indeterminate
Bit
Position
Bit/Field
R/W
Value
Description
7_______
Stop Mode Flag
R
R
W
1
0
X
Stop Recovery (warm start)
POR/WDT Reset (cold start)
No Effect
_6______
__5_____
Reserved
R
W
1
X
Always reads 1
No Effect
Stop Delay
R
W
W
1
1
0
Always reads 1
Enable 5ms /Reset delay
Disable /Reset delay after SMR
___432__
Reserved
R
1
Always reads 111
W
X
No Effect
_______10 System Clock
Select
R
11
11
10
01
00
Always reads 11
W
W
W
W
SCLK, TCLK = XTAL/16
SCLK, TCLK = XTAL
SCLK, TCLK = XTAL/32
SCLK, TCLK = XTAL/2
The second function of the SMR register is the selection of the external clock
divide value. The purpose of this control is to selectively reduce device power
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Low-Voltage Microcontrollers with ADC
84
consumption during normal processor execution (SCLK control) and/or HALT
mode (where TCLK sources counter/timers and interrupt logic).
Port 2 Stop Mode Recovery (P2SMR)
The P2SMR register, as described in Table 51, defines which I/O lines in Port 2
are to be used as stop mode recovery sources.
Table 51.P2SMR Register (Group/Bank 0Fh, Register 1)
Bit
7
6
5
4
3
2
1
0
Bit/Field
R/W
P27RS P26RS P25RS P24RS P23RS P22RS P21RS P20RS
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Reset
R = Read, W = Write, X = Indeterminate
Bit
Position
Bit/Field
R/W
Value
Description
76543210
(by bit)
Port 2 Stop Mode R/W
Recovery
1
0
Recovery Source
Not
Port 5 Stop-Mode Recovery (P5SMR)
The P5SMR register, as described in Table 52, defines which I/O lines in Port 5
are to be used as stop-mode recovery sources.
Table 52.P5SMR Register (Group/Bank 0Fh, Register 5)
Bit
7
6
5
4
3
2
1
0
Bit/Field
R/W
P57RS P56RS P55RS P54RS P53RS P52RS P51RS P50RS
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Reset
R = Read, W = Write, X = Indeterminate
Bit
Position
Bit/Field
R/W
Value
Description
76543210
(by bit)
Port 5 Stop Mode R/W
Recovery
1
0
Recovery Source
Not
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Z86D990/Z86D991 OTP and Z86L99X ROM
Low-Voltage Microcontrollers with ADC
85
Electrical Characteristics
This section covers the absolute maximum ratings, standard test conditions, DC
characteristics, and AC characteristics.
Absolute Maximum Ratings
Table 53 lists the absolute maximum ratings.
Table 53.Absolute Maximum Ratings
Symbol
Description
Min
Max
+7.0
+150°
†
Units
V
Supply Voltage (*)
Storage Temp.
–0.3
–65°
V
C
C
MAX
T
STG
T
Oper. Ambient Temp.
Minimum RAM Voltage
A
V
1.0 V**
RAM
Note:
*Voltage on all pins with respect to GND.
†See “Ordering Information” on page 95.
** Estimated value, not tested.
Stresses greater than those listed in the preceding table can cause permanent
damage to the device. This rating is a stress rating only. Functional operation of
the device at any condition above those indicated in the operational sections of
these specifications is not implied. Exposure to absolute maximum rating condi-
tions for an extended period can affect device reliability.
Standard Test Conditions
The characteristics listed below apply for standard test conditions as noted. All
voltages are referenced to GND. Positive current flows into the referenced pin
(see Figure 36).
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Z86D990/Z86D991 OTP and Z86L99X ROM
Low-Voltage Microcontrollers with ADC
86
From Output
Under Test
150pF
I
Figure 36. Test Load Diagram
DC Characteristics
Table 54 lists the DC characteristics for the Z86D99X (OTP only). Table 55 lists
the DC characteristics for the Z86L99X (mask only).
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Z86D990/Z86D991 OTP and Z86L99X ROM
Low-Voltage Microcontrollers with ADC
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Table 54.DC Characteristics for the Z86D99X (OTP Only)
Symbol Parameter
VDD
Min
Max
Units
Comments
VDD
VCH
Power Supply Voltage
3
5.5
Clock Input High Voltage
Clock Input Low Voltage
Input High Voltage
3.0 V
5.5 V
0.8Vdd
0.8Vdd
Vdd+0.3
Vdd+0.3
V
V
Driven by Ext. clock
generator
VCL
VIH
3.0 V
5.5 V
Vss–0.3
Vss–0.3
0.2Vdd
0.2Vdd
Driven by Ext. clock
generator
3.0 V
5.5 V
0.7Vdd
0.7Vdd
Vdd+0.3
Vdd+0.3
V
V
VIL
Input Low Voltage
3.0 V
5.5 V
Vss–0.3
Vss–0.3
0.2Vdd
0.2Vdd
V
V
VOH1
VOH2
VOL1
VOL2
ICCO
IIL
Output High Voltage
Regular I/O
3.0 V
5.5 V
VDD–0.8
VDD–0.8
V
V
–1.2 mA
–5.0 mA
High Drive Pins (P54, P55, P56,
P57)
3.0 V
5.5 V
VDD–0.8
VDD–0.8
V
V
Regular I/O
Output low voltage
3.0 V
5.5 V
0.4
0.8
V
V
2 mA
4.0 mA
High Drive Pins (P54, P55, P56,
P57)
3.0 V
5.5 V
0.4
0.8
V
V
4 mA
7.0 mA
Controlled Current Output (P43)
3.0 V
5.5 V
70
70
120
120
mA
mA
Vout = 1.2 V to VDD
(see Figure 17)
Input Leakage
3.0 V
5.5 V
–1
–1
1 µA
1 µA
µA
µA
Vin=0 V, Vdd
Vin=0 V, Vdd
ICC
Supply Current
3.0 V
5.5 V
3.0 V
5.5 V
10
15
250
850
mA
mA
µA
µA
at 8 MHz
at 8 MHz
at 32 KHz
at 32 KHz
ADC is off.
ICC1
Standby Current (Halt Mode)
Standby Current (STOP Mode)
3.0 V
5.5 V
3.0 V
5.5 V
3
5
2
4
mA
mA
mA
mA
Vin=0 V, Vdd
at 8 MHz
Clock divided by 16
XTAL running
ADC is off.
Vin=0 V, Vdd; ADC is off.
P43=1 or high impedance
WDT, Comparators, Low
Voltage Detection, and ADC (if
applicable) are disabled. The
IC might draw more current if
any of the above peripherals is
enabled.
ICC2
3.0 V
5.5 V
20
30
µA
µA
IADC
VLV
Current with A/D Running
Vdd Low-Voltage Protection
3.0 V
5.5 V
500
900
µA
µA
2.90
V
Low voltage protection
is also known as
brownout.
Typical is 2.6 V.
VLB
Low-Battery Detection
VLV+
0.5
V
V
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Low-Voltage Microcontrollers with ADC
88
Table 55.DC Characteristics for the Z86L99X (Mask Only)
Symbol
Parameter
V
Min
Max
Units Comments
DD
V
V
Power Supply Voltage
Clock Input High Voltage
2.3
5.5
DD
CH
2.3 V 0.8Vdd
5.5 V 0.8Vdd
Vdd+0.3
Vdd+0.3
V
V
Driven by Ext. clock generator
V
V
V
V
Clock Input Low Voltage
Input High Voltage
Input Low Voltage
2.3 V Vss–0.3 0.2Vdd
5.5 V Vss–0.3 0.2Vdd
Driven by Ext. clock generator
CL
IH
2.3 V 0.7Vdd
5.5 V 0.7Vdd
Vdd+0.3
Vdd+0.3
V
V
2.3 V Vss–0.3 0.2Vdd
5.5 V Vss–0.3 0.2Vdd
V
V
IL
Output High Voltage
Regular I/O
2.3 V 2.0
5.5 V 5.0
V
V
–0.5 mA
–1.2 mA
–3 mA
–5 mA
2 mA
OH1
2.3 V 1.9
5.5 V 5.0
V
V
V
V
V
High Drive Pins (P54, P55, P56, P57) 2.3 V 1.9
5.5 V 5.1
V
V
OH2
OL1
OL2
2.3 V 1.7
5.5 V 4.7
V
V
Regular I/O
Output low voltage
2.3 V
5.5 V
0.4 V
0.4 V
V
V
2.3 V
5.5 V
0.8 V
0.8 V
V
V
4 mA
High Drive Pins (P54, P55, P56, P57) 2.3 V
5.5 V
0.4 V
0.4 V
V
V
4 mA
2.3 V
5.5 V
0.8 V
0.8 V
V
V
7 mA
I
I
I
Controlled Current Output (P43)
Input Leakage
2.3 V 70
5.5 V 70
120
120
mA
mA
Vout = 1.2 V to VDD at room
temperature (see Figure 17)
CCO
2.3 V –1
5.5 V –1
1 µA
1 µA
µA
µA
Vin=0 V, Vdd
Vin=0 V, Vdd
IL
Supply Current
2.3 V
5.5 V
2.3 V
5.5 V
3
8
250
850
mA
mA
µA
µA
at 8 MHz
at 8 MHz
at 32 KHz
at 32 KHz
ADC is off.
CC
I
I
Standby Current (Halt Mode)
Standby Current (STOP Mode)
2.3 V
5.5 V
2
5
mA
mA
Vin=0 V, Vdd
at 8 MHz
CC1
Vin=0 V, Vdd;ADC is off.
2.3 V
5.5 V
8
25.0
µA
µA
CC2
WDT, Comparators, Low Voltage Detection,
and ADC (if applicable) are disabled. The IC
might draw more current if any of the above
peripherals is enabled.
at 30 °C
I
I
I
Standby Current (STOP Mode)
Standby Current (Low Voltage)
Current with A/D Running
5.5 V
15
20
µA
µA
CC2
Measured at V =V –0.2 V.
LV
DD
LV
2.3 V
5.5 V
500
900
µA
µA
ADC
Low voltage protection is also known as
brownout.
Typical is around 1.7 V at room temperature.
V
Vdd Low-Voltage Protection
Low-Battery Detection
2.2
V
LV
LB
V
3.0
V
Typical is around 2.4 V at room temperature.
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Low-Voltage Microcontrollers with ADC
89
Analog-to-Digital Converter Characteristics
Table 56 lists the analog-to-digital converter characteristics.
Table 56.Analog-to-Digital Converter Characteristics
Parameter
Minimum Typical
Maximum
Units
bits
LSB
LSB
mV
V
Resolution
8
Integral Nonlinearity
Differential Nonlinearity
Zero Error at 25 °C
0.5
0.5
1
1
7.8
5.5
5.5
1.2
4
Supply Voltage Range (OTP) 3.0
Supply Voltage Range (ROM) 2.3
Power Dissipation (No Load)
Clock Frequency (f ADC)
V
mW
MHz
V
Input Voltage Range
Step Response
VRef–
VRef+
2/(0.0021 X f ADC) s
ADC Input Capacitance
Vref Input Capacitance
25
40
pF
25
40
pF
V
V
Ref+ Range
Ref– Range
VRef–+2.0
AGND
AVDD
VRef+–2.0
V
V
(VRef+)–(VRef–
)
2.0
0
AVDD
70
V
Temperature Range
3-db Frequency
°C
Hz
db
(0.0021 X f ADC)
Dout
Signal to Noise
47
ADC Output Code
Vref Input Source Impedance
ADC Input Source Impedance
1.0
1.0
kOhms
kOhms
Notes: Dout= [(Vin–V
)/(V
–V
)] X 256
Ref–
Ref+ Ref–
f ADC = set in ADCCTRL configuration register
Step Response is the time to track the input if a step from V
to V
is applied.
Ref–
Ref+
The ADC input is a switching capacitor that charges up to the applied input volt-
age whenever it is configured as an ADC input. If you switch it from digital mode to
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Low-Voltage Microcontrollers with ADC
90
the ADC input mode, the switching capacitor starts to charge up from 0 V. For the
maximum swing (Dout = 0 to FF), it takes 2/(0.0021x f ADC). For an 8-MHz MCU
crystal (with clock divide-by-two mode), the internal system clock is 4 MHz. In
ADCCTRL, if you select the ADC frequency = system clock divided by 1 option,
f ADC = 4 MHz. The step response = 238 uS.
AC Characteristics
Table 57 lists the AC characteristics.
Table 57.AC Characteristics
No. Symbol
Parameter
VDD
Min
Max
Units
1
2
3
4
5
6
7
8
9
TpC
Input Clock Period
2.3 V
5.5 V
120
120
DC
DC
ns
TrC, TfC
TwC
Clock Input Rise and Fall Times
Input Clock Width
2.3 V
5.5 V
25 ns
25 ns
2.3 V
5.5 V
5.0
5.0
ns
ns
TwTinL
TwTinH
TpT1in
Timer Input Low Width
Timer Input High Width
Timer 1 Input Period
2.3 V
5.5 V
2TPC
2TPC
ns
2.3 V
5.5 V
2
2
TpC
TpC
2.3 V
5.5 V
8
8
TpC
TpC
TrTin, TfTin Timer Input Rise and Fall Time
2.3 V
5.5 V
100
100
ns
ns
TwIL
TwIH
Interrupt Request Low Time
2.3 V
5.5 V
100
70
ns
ns
Interrupt Request Input High Time 2.3 V
5.5 V
5
5
TpC
TpC
10 Twsm
12 Twdt
Stop-Mode Recovery Width Spec 2.3 V
5.5 V
12
12
ns
ns
Watch-Dog Timer Time Out
2.3 V
5.5 V
25
10
ms
ms
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Z86D990/Z86D991 OTP and Z86L99X ROM
Low-Voltage Microcontrollers with ADC
91
Packaging
Figure 37 through Figure 40 show the available packages.
c
D
48
25
E
H
1
24
Detail
A
A2
A
CONTROLLING DIMENSIONS
: MM
LEADS ARE COPLANAR WITHIN .004 INCH
A1
SEATING PLANE
e
b
L
0-8˚
Detail
A
Figure 37. 48-Pin SSOP
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Low-Voltage Microcontrollers with ADC
92
Figure 38. 40-Pin PDIP
Figure 39. 28-Pin PDIP
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Low-Voltage Microcontrollers with ADC
93
Figure 40. 28-Pin SOIC
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Z86D990/Z86D991 OTP and Z86L99X ROM
Low-Voltage Microcontrollers with ADC
94
Design Considerations
The Z8 uses a Pierce oscillator with an internal feedback circuit. The advantages
of this circuit are low cost, large output signal, low-power level in the crystal, stabil-
ity with respect to V and temperature, and low impedances (not disturbed by
CC
stray effects.)
One drawback is the requirement for high gain in the amplifier to compensate for
feedback path losses. Traces connecting crystal, capacitors, and the Z8 oscillator
pins must be as short and wide as possible. Short and wide traces reduce para-
sitic inductance and resistance. The components (capacitors, crystal, and resis-
tors) must be placed as close as possible to the oscillator pins of the Z8.
The traces from the oscillator pins of the integrated circuit (IC) and the ground
side of the lead capacitors must be guarded from all other traces (clock, V , and
CC
system ground) to reduce cross-talk and noise injection. Guarding the traces is
usually accomplished by keeping other traces and system ground trace planes
away from the oscillator circuit and by placing a Z8 device V ground ring around
SS
the traces/components. The ground side of the oscillator lead capacitors must be
connected to a single trace to the Z8 V (GND) pin. It must not be shared with
SS
any other system ground trace or components except at the Z8 device V pin.
SS
Not sharing the ground side of the oscillator lead capacitors is to prevent differen-
tial system ground noise injection into the oscillator.
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Z86D990/Z86D991 OTP and Z86L99X ROM
Low-Voltage Microcontrollers with ADC
95
Ordering Information
Part
PSI
Description
Z86D99 (OTP)
Z86D990PZ008SC
Z86D990HZ008SC
Z86D991PZ008SC
Z86D991SZ008SC
40-pin PDIP
48-pin SSOP
28-pin PDIP
28-pin SOIC
Z86L99 (Mask ROM)
Z86L990PZ008SC
Z86L990HZ008SC
Z86L991PZ008SC
Z86L991SZ008SC
Z86L996PZ008SC
Z86L996SZ008SC
Z86L997PZ008SC
Z86L997SZ008SC
40-pin PDIP
48-pin SSOP
28-pin PDIP
28-pin SOIC
28-pin PDIP
28-pin SOIC
28-pin PDIP
28-pin SOIC
Emulator
Z86L9900100ZEM
Z86D9900100ZDH
Z86L9900100ZCO
Emulator/Programmer
48 SSOP Adapter
Evaluation Board
Adapter
Evaluation Board
For fast results, contact your local ZiLOG sale offices for assistance in ordering
part(s). Updated information can be found on the ZiLOG website:
HTTP://WWW.ZILOG.COM
Precharacterization Product
The product represented by this document is newly introduced and ZiLOG has not
completed the full characterization of the product. The document states what
ZiLOG knows about this product at this time, but additional features or nonconfor-
mance with some aspects of the document might be found, either by ZiLOG or its
customers in the course of further application and characterization work. In addi-
tion, ZiLOG cautions that delivery might be uncertain at times, due to start-up yield
issues.
ZiLOG, Inc.
532 Race Street
San Jose, CA 95126-3432
Telephone: (408) 558-8500
FAX: 408 558-8300
Internet: HTTP://WWW.ZILOG.COM
PS003807-1002
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相关型号：
Z86D991PZ008SG
IC 8-BIT, OTPROM, 8 MHz, MICROCONTROLLER, PDIP28, PLASTIC, DIP-28, Microcontroller
ZILOG
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