Z86E09 [ZILOG]
Z8 CMOS OTP Microcontrollers; Z8 CMOS OTP微控制器
| 型号： | Z86E09 |
| 厂家： | 
ZILOG, INC. |
| 描述： | Z8 CMOS OTP Microcontrollers |
| 文件： | 总38页 (文件大小：286K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Z86E02/E04/E08/E09 SL1995
Z8 CMOS OTP
Microcontrollers
Programming Specification
PS009201-0301
ZiLOG Worldwide Headquarters • 910 E. Hamilton Avenue • Campbell, CA 95008
Telephone: 408.558.8500 • Fax: 408.558.8300 • www.ZiLOG.com
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Telephone: 408.558.8500
Fax: 408.558.8300
www.ZiLOG.com
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Document Disclaimer
© 2001 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices,
applications, or technology described is intended to suggest possible uses and may be superseded.
ZiLOG, INC. DOES NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF
ACCURACY OF THE INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS
DOCUMENT. ZiLOG ALSO DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY
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under any intellectual property rights.
PS009201-0301
Z86E02/E04/E08/E09 SL1995
Z8 CMOS OTP Microcontrollers
iii
Table of Contents
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iv
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Top-Level Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Parallel Programming Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pin Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
OTP Memory Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Device Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Unlock Sequence into EPROM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
EPROM Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Top Level Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
EPROM Array Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Option Bit Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Power-Down Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
EPROM I/O Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Programming Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Recommendations to Third-Party Programmers . . . . . . . . . . . . . . . . . . . . . 31
Precharacterization Product . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Third Party Developer Feedback Form . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
PS009201-0301
Z86E02/E04/E08/E09 SL1995
Z8 CMOS OTP Microcontrollers
iv
List of Figures
Figure 1. Top-Level Programming Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Figure 2. 18-Pin DIP/SOIC Pin Configuration, STANDARD Mode . . . . . . . . . . 3
Figure 3. 18-Pin DIP/SOIC Pin Configuration, EPROM Mode . . . . . . . . . . . . . 3
Figure 4. 20-Pin SSOP Pin Configuration, STANDARD Mode . . . . . . . . . . . . . 4
Figure 5. 20-Pin SSOP Pin Configuration, EPROM Mode . . . . . . . . . . . . . . . . 4
Figure 6. Unlock Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 7. Top Level Operations Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Figure 8. EPROM ARRAY READ/WRITE Mode Entry Functional Timing . . . 11
Figure 9. EPROM ARRAY READ Mode Functional Timing . . . . . . . . . . . . . . 13
Figure 10. EPROM ARRAY PROGRAM AND VERIFY Functional Timing . . . . 15
Figure 11. OPTION BIT PROGRAM AND VERIFY Mode Entry
Functional Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure 12. OPTION BIT PROGRAM AND VERIFY Functional Timing . . . . . . . 19
Figure 13. OPTION BIT READ Mode Functional Timing . . . . . . . . . . . . . . . . . 21
Figure 14. Power-Down Functional Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 15. Z86E0x EPROM ARRAY and OPTION BIT PROGRAM
AND VERIFY Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 16. Z86E0x Additional Timing Waveform . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 17. EPROM ARRAY PROGRAM, VERIFY, and READ Algorithm . . . . 27
Figure 18. EPROM ARRAY READ Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 19. OPTION BIT PROGRAM, VERIFY, and READ Algorithm . . . . . . . . 29
Figure 20. OPTION BIT READ Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 21. Third-Party Top-Level Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
PS009201-0301
Z86E02/E04/E08/E09 SL1995
Z8 CMOS OTP Microcontrollers
v
List of Tables
Table 1. Output Parallel Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 2. Input Parallel Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Table 3. EPROM Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Table 4. Power-On Reset Pin Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 5. Unlock Sequence Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 6. Mode Selections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table 7. EPROM ARRAY READ/WRITE Mode Entry Conditions . . . . . . . . . 11
Table 8. EPROM ARRAY READ Mode Conditions . . . . . . . . . . . . . . . . . . . . 13
Table 9. EPROM ARRAY PROGRAM AND VERIFY Mode Conditions . . . . 15
Table 10. Option Bit Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 11. OPTION BIT PROGRAM AND VERIFY Mode Entry Conditions . . . 17
Table 12. OPTION BIT PROGRAM AND VERIFY Mode Conditions . . . . . . . 20
Table 13. Power-Down Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 14. Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 15. Voltage Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table 16. Z86E0x Additional Timing Specifications . . . . . . . . . . . . . . . . . . . . 25
PS009201-0301
Z86E02/E04/E08/E09 SL1995
Z8 CMOS OTP Microcontrollers
1
General Description
The EPROM Programming interface is a byte-wide data interface with 7 control
inputs and a 17-wire connection. This document describes the EPROM interface
pertinent to the following parts:
Z86E02 SL1995
Z86E04 SL1995
Z86E08 SL1995
Z86E09 SL1995
Top-Level Programming
After powering up, the programming sequence begins by sending the unlock code
sequence, followed by the mode selection. The program address must be reset to
0000hafter entering EPROM mode. The first data byte to be programmed is then
loaded on Port 2. When the programming control sequence is applied, the pro-
gramming pulse commences. Data is then verified for correct programming. If the
data is incorrect, a count begins to record the number of programming pulse
cycles before success is finally achieved. If the data is not programmed after
N
attempts, it is a failed part. If data is verified, then it must be overpro-
MAX
grammed for a minimum of 3 times the cumulative programming time. The
address counter is then incremented to the next address. The next data byte is
sent, and programming continues using the same basic algorithm. See Figure 1.
PS009201-0301
Programming Specification
Z86E02/E04/E08/E09 SL1995
Z8 CMOS OTP Microcontrollers
2
Figure 1. Top-Level Programming Sequence
Start
Power-On Reset
Send Unlock
and Mode Codes
Program Data
at Set Address
Up to NMAX times
Verify Data
at Set Address
Next Address
Fail
Pass
Overprogram
at Set Address
Last Address
Fail
Verify Data
at All Addresses
Last Address
Stop
PS009201-0301
Programming Specification
Z86E02/E04/E08/E09 SL1995
Z8 CMOS OTP Microcontrollers
3
Parallel Programming Interface
The EPROM interface is a 17-wire connection. Review the part-specific pin dia-
grams in Figures 2 through 5 for part pin-out.
Pin Diagrams
Device pin-out diagrams for the 18-pin DIP/SOIC and 20-pin SSOP are shown in
Figures 2 through 5. There are two configurations for the 20-pin SSOP device—
the corresponding parts are identified in the diagrams.
Figure 2. 18-Pin DIP/SOIC Pin Configuration, STANDARD Mode
18
17
16
15
14
13
12
11
10
P24
P25
P26
P27
P23
P22
P21
P20
GND
P02
P01
P00
P33
1
2
3
4
5
6
7
8
9
V
CC
X
OUT
X
IN
P31
P32
Figure 3. 18-Pin DIP/SOIC Pin Configuration, EPROM Mode
18
17
16
15
14
13
12
11
10
D4
D5
D6
D7
D3
1
2
3
4
5
6
7
8
9
D2
D1
D0
GND
PGM
CLOCK
CLEAR
V
CC
NC
CE
OE
EPM
V
PP
PS009201-0301
Programming Specification
Z86E02/E04/E08/E09 SL1995
Z8 CMOS OTP Microcontrollers
4
Figure 4. 20-Pin SSOP Pin Configuration, STANDARD Mode
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
P24
P25
P26
P27
P23
P22
P21
P20
GND
GND
P02
P01
P00
P33
V
V
CC
CC
X
OUT
X
IN
P31
P32
Figure 5. 20-Pin SSOP Pin Configuration, EPROM Mode
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
D4
D5
D6
D7
D3
D2
D1
D0
GND
GND
PGM
CLOCK
CLEAR
V
CC
V
CC
NC
CE
OE
V
EPM
PP
Tables 1 and 2 indicate the device’s Port 2 input and output EPROM data.
Table 1. Output Parallel Byte
Bit Number
Port 2
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
Output EPROM data
Table 2. Input Parallel Byte
Bit Number
Port 2
7
7
6
6
5
5
4
4
3
3
2
2
1
1
0
0
Input EPROM data
PS009201-0301
Programming Specification
Z86E02/E04/E08/E09 SL1995
Z8 CMOS OTP Microcontrollers
5
OTP Memory Size
The device is offered in 4 memory configurations. Table 3 lists the available sizes
of EPROM memory.
Table 3. EPROM Size
Devices
Z86E02
Z86E04
Z86E08
Z86E09
Memory Size
0.5 KB
Last Address
01FFh
1.0 KB
03FFh
2.0 KB
07FFh
4.0 KB
0FFFh
Device Operation
The device must first be unlocked before it can enter EPROM mode. Otherwise,
the device remains in STANDARD mode. The device cannot be programmed in
STANDARD mode. It can only be programmed in EPROM mode. The following
sequence details the unlock procedure.
Unlock Sequence into EPROM Mode
The following unlock sequence is valid for all parts.
Note: Unlock clock cycles are the X clock cycle entered by the programmer,
IN
not the internal Z8 SCLK cycles.
1. A POR must be completed before unlock operations begin. The X pin must
IN
be in a V state. Allow 50 ms minimum for the device to completely exit POR
IL
to allow the internal signal IRESET to go Low. See Table 5 for POR
conditions.
2. Any time after POR, when the internal signal IRESET is Low. The unlock
sequence can be sent. See Figure 6 and Table 4.
3. While the X pin is in a V state, force Port 2 pins with A5h.
IN
IL
4. Apply one clock pulse to X . The clock pulses should be a minimum of 1µsec
IN
in duration.
5. Force the Port 2 pins with 5Ah.
6. Apply one clock pulse to the X pin.
IN
7. Force the Port 2 pins with A5h.
PS009201-0301
Programming Specification
Z86E02/E04/E08/E09 SL1995
Z8 CMOS OTP Microcontrollers
6
8. Apply one clock pulse to X .
IN
9. Force the Port 2 pins with F0h.
10. Apply one clock pulse to X .
IN
11. Force the Port 2 pins with 0Fh.
12. Apply one clock pulse to X .
IN
13. Force the Port 2 pins with 00h.
14. Apply one clock pulse to X .
IN
15. Force the Port 2 pins with F1h.
16. Apply one clock pulse to X .
IN
17. Force the Port 2 pins with 00h.
18. Apply one clock pulse to X .
IN
19. The part is now in EPROM mode. The only way to exit EPROM mode is to
perform a POR.
Note: All signals must be stable before the X (CE) pin is pulsed High and can-
IN
not change until X (CE) pin is in a V state. The signal should be stable
IN
IL
for a minimum of 1µsec.
PS009201-0301
Programming Specification
Z86E02/E04/E08/E09 SL1995
Z8 CMOS OTP Microcontrollers
7
Figure 6. Unlock Sequence
IRESET
5V
V
CC
0V
VIH
CLEAR
EPM
VIL
VIH
VIL
VIH
VIL
XIN (CE)
VIH
VIL
VPP
VIH
VIL
CLOCK
VIH
VIL
OE
PGM
VIH
VIL
1
VIH
VIL
Port 27
Port 26
VIH
VIL
VIH
VIL
Port 25
Port 24
Port 23
Port 22
Port 21
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
Port 20
XOUT
No Connection
Note:
1. The device enters EPROM mode at this point when X goes Low.
IN
PS009201-0301
Programming Specification
Z86E02/E04/E08/E09 SL1995
Z8 CMOS OTP Microcontrollers
8
Table 4. Unlock Sequence Conditions
EPROM Signal
D0–D3
18-Pin DIP/SOIC
Pins 15, 16, 17, 18
Pins 1, 2, 3, 4
Pin 14
20-Pin SSOP
Forced State
See Figure 6
See Figure 6
GND
Pins 17, 18, 19, 20
Pins 1, 2, 3, 4
Pins 15, 16
Pins 5, 6
Pin 8
D4–D7
GND
V
Pin 5
5V
CC
CE (X )
Pin 7
See Figure 6
No Connection
IN
NC (X
OE
)
Pin 6
Pin 7
OUT
Pin 8
Pin 9
V
V
V
V
V
V
IH
IH
IL
IL
IL
IH
EPM
Pin 9
Pin 10
V
Pin 10
Pin 11
PP
CLEAR
CLOCK
PGM
Pin 11
Pin 12
Pin 12
Pin 13
Pin 13
Pin 14
Table 5. Power-On Reset Pin Conditions
EPROM Signal
D0–D3
18-Pin DIP/SOIC
Pins 15, 16, 17, 18
Pins 1, 2, 3, 4
Pin 14
20-Pin SSOP
Pins 17, 18, 19, 20
Pins 1, 2, 3, 4
Pins 15, 16
Pins 5, 6
Pin 8
State
GND
D4–D7
GND
GND
GND
V
Pin 5
Ramp to 5V
GND
CC
CE (X )
Pin 7
IN
NC (X
OE
)
Pin 6
Pin 7
No Connection
GND
OUT
Pin 8
Pin 9
EPM
Pin 9
Pin 10
GND
V
Pin 10
Pin 11
GND
PP
CLEAR
CLOCK
PGM
Pin 11
Pin 12
GND
Pin 12
Pin 13
GND
Pin 13
Pin 14
GND
PS009201-0301
Programming Specification
Z86E02/E04/E08/E09 SL1995
Z8 CMOS OTP Microcontrollers
9
EPROM Modes
The device offers two modes of operation. Table 6 lists the available mode
options.
Table 6. Mode Selections
Value Description
A
B
EPROM Array Read and Write modes
Option Bit Program and Verify modes
Top Level Operations
Figure 7 illustrates the operations available to the user after the device is
unlocked and enters EPROM mode.
Figure 7. Top Level Operations Flow
Start
Power-On Reset
to 5.0V
Unlock Sequence
into EPROM Mode
EPROM Mode Selection
Exit
EPROM ARRAY
READ/WRITE
Mode
OPTION BIT
PROGRAM/VERIFY
Mode
Execute Power
Down Sequence
Program/Verify/
Overprogram
Operation
Program/Verify/
Overprogram
Operation
READ
Operation
READ
Operation
End
PS009201-0301
Programming Specification
Z86E02/E04/E08/E09 SL1995
Z8 CMOS OTP Microcontrollers
10
EPROM Array Modes
EPROM ARRAY READ/WRITE Mode Entry
1. To enter EPROM ARRAY READ/WRITE mode, all pins must be set as per
Table 7.
2. EPM is lowered to V .
IL
3. OE is lowered to V .
IL
4. The V is raised to V .
PP
IH
5. The CLEAR is pulsed High to V and back down to V .
IH
IL
6. The V is lowered to V .
PP
IL
7. After a delay of at least 1µsec minimum, the V is raised to V .
PP
IH
8. OE is raised to V .
IH
9. EPM is raised to V .
IH
10. The device now operates in EPROM ARRAY READ/WRITE mode. See
Figure 8.
Note: The delay between edges should be 1µsec minimum unless specified in
the timing specification in Table 14.
PS009201-0301
Programming Specification
Z86E02/E04/E08/E09 SL1995
Z8 CMOS OTP Microcontrollers
11
Figure 8. EPROM ARRAY READ/WRITE Mode Entry Functional Timing
5V
0V
VCC
VIH
VIL
CLEAR
VIH
VIL
EPM
VIH
VIL
CE
VIH
VIL
VPP
VIH
VIL
CLOCK
VIH
VIL
OE
VIH
VIL
PGM
Data
Not connected
Not connected
(Port 2)
XOUT
Table 7. EPROM ARRAY READ/WRITE Mode Entry Conditions
EPROM Signal
D0–D3
18-Pin DIP/SOIC
Pins 15, 16, 17, 18
Pins 1, 2, 3, 4
Pin 14
20-Pin SSOP
Pins 17, 18, 19, 20
Pins 1, 2, 3, 4
Pins 15, 16
Pins 5, 6
Pin 8
Forced State
NC
D4–D7
NC
GND
GND
5V
V
Pin 5
CC
CE
Pin 7
V
IL
NC
Pin 6
Pin 7
No Connection
See Figure 8
See Figure 8
See Figure 8
OE
Pin 8
Pin 9
EPM
Pin 9
Pin 10
V
Pin 10
Pin 11
PP
PS009201-0301
Programming Specification
Z86E02/E04/E08/E09 SL1995
Z8 CMOS OTP Microcontrollers
12
Table 7. EPROM ARRAY READ/WRITE Mode Entry Conditions (Continued)
EPROM Signal
CLEAR
18-Pin DIP/SOIC
Pin 11
20-Pin SSOP
Pin 12
Forced State
See Figure 8
CLOCK
Pin 12
Pin 13
V
V
IL
PGM
Pin 13
Pin 14
IH
EPROM ARRAY READ Mode Operation
1. Perform Steps 1 through 6 of the EPROM ARRAY READ/WRITE mode entry
(see the EPROM ARRAY READ/WRITE Mode Entry operation, previous
page) before proceeding to Step 2.
2. Reset the address counter by pulsing the CLEAR pin. See Figure 9 and
Table 8. Please refer to Table 14 for minimum and maximum widths of the
CLOCK and CLEAR signals.
3. The address counter is incremented on the rising edge of the CLOCK signal.
4. After resetting the address counter using the CLEAR pin, the address counter
points to address 0000h.
5. The READ operation is performed by lowering OE to V and reading the data
IL
on Port2. Pins P20 to P27 represent the EPROM data D0 to D7, respectively.
See Figure 9 and Table 8.
6. A V -level READ on Port2 corresponds to a 1 state, while a V level
OH
OL
corresponds to a 0 level stored in the EPROM array.
Note: Please refer to Table 14 for the minimum and maximum width of OE dur-
ing EPROM READ mode and data access time.
7. The next address is read by pulsing the clock pin High, then forcing OE to V
and bringing it back High after the data is read.
IL
8. Repeat Step 7 until the final address is read.
9. Because the address is sequentially accessed, a previously-accessed
address can only be read by resetting the address counter to 0000hand
clocking the address counter to increment to the appropriate address.
PS009201-0301
Programming Specification
Z86E02/E04/E08/E09 SL1995
Z8 CMOS OTP Microcontrollers
13
Figure 9. EPROM ARRAY READ Mode Functional Timing
5V
0V
V
CC
VIH
VIL
CLEAR
EPM
CE
VIH
VIL
VIH
VIL
VIH
VIL
VPP
VIH
VIL
CLOCK
OE
VIH
VIL
VIH
VIL
PGM
Data
Invalid
Data Out
0000h
Invalid
Data Out
0001h
Invalid
(Port 2)
Internal
Address
0002h
X
Not connected
OUT
Table 8. EPROM ARRAY READ Mode Conditions
EPROM Signal
D0–D3
18-Pin DIP/SOIC
Pins 15, 16, 17, 18
Pins 1, 2, 3, 4
Pin 14
20-Pin SSOP
Forced State
See Figure 9
See Figure 9
GND
Pins 17, 18, 19, 20
Pins 1, 2, 3, 4
Pins 15, 16
Pins 5, 6
Pin 8
D4–D7
GND
V
Pin 5
5V
CC
CE
Pin 7
V
IL
NC
Pin 6
Pin 7
No Connection
See Figure 9
OE
Pin 8
Pin 9
EPM
Pin 9
Pin 10
V
V
IH
IH
V
Pin 10
Pin 11
PP
PS009201-0301
Programming Specification
Z86E02/E04/E08/E09 SL1995
Z8 CMOS OTP Microcontrollers
14
Table 8. EPROM ARRAY READ Mode Conditions (Continued)
CLEAR
CLOCK
PGM
Pin 11
Pin 12
Pin 13
Pin 12
Pin 13
Pin 14
See Figure 9
See Figure 9
V
IH
EPROM ARRAY PROGRAM AND VERIFY Mode Operation
1. Perform the EPROM ARRAY READ/WRITE mode entry (see the EPROM
ARRAY READ/WRITE Mode Entry operation on page 10) before proceeding
to Step 2.
2. Reset the address counter by pulsing the CLEAR pin. See Figure 10 and
Table 9. Please refer to Table 14 for minimum and maximum widths of the
CLOCK signal.
3. The address counter is incremented on the rising edge of the CLOCK signal.
4. After resetting the address counter using the CLEAR pin, the address counter
points to address 0000h.
5. The PROGRAM operation is performed by lowering PGM to V . See
IL
Figure 10. Please refer to Table 14 for minimum and maximum widths of the
PGM signal.
6. The PROGRAM operation is complete when PGM is raised back to V .
IH
7. The VERIFY operation is performed by lowering OE to V and reading the
IL
data on Port2. Pins P20 to P27 represent the EPROM data D0 to D7,
respectively.
8. A V -level READ on Port2 corresponds to a 1 state, while a V level
OH
OL
corresponds to a 0 level stored in the EPROM array.
9. Please refer to Table 14 for the minimum and maximum width of OE during
EPROM Read mode and data access time.
10. If the data read shows that the address location is not yet programmed, then
repeat Steps 5 to 7 until the data read shows that the address location is
programmed.
11. If the address location is not programmed after the 25th try, then the device is
considered failed.
12. If the address location is programmed, then the address location is
overprogrammed with three times the total accumulated program time.
13. The next address is accessed by pulsing the CLOCK High to V , then Low to
IH
V .
IL
PS009201-0301
Programming Specification
Z86E02/E04/E08/E09 SL1995
Z8 CMOS OTP Microcontrollers
15
14. Repeat Steps 5 to 12 until the last address is read.
15. Because the address is sequentially accessed, a previously-accessed
address can only be programmed or read by resetting the address counter to
0000hand clocking the address counter to increment to the appropriate
address.
Figure 10. EPROM ARRAY PROGRAM AND VERIFY Functional Timing
5V
VCC
0V
V
IH
CLEAR
V
IL
V
IH
EPM
V
IL
V
IH
CE
V
IL
V
IH
VPP
V
IL
V
IH
CLOCK
V
IL
V
IH
OE
V
IL
V
IH
PGM
3 x N x 1ms
Data In
V
IL
Data
(Port 2)
Data
Out
Data In
0000h
Internal
Address
0001h
Table 9. EPROM ARRAY PROGRAM AND VERIFY Mode Conditions
EPROM Signal
D0–D3
18-Pin DIP/SOIC
Pins 15, 16, 17, 18
Pins 1, 2, 3, 4
Pin 14
20-Pin SSOP
Pins 17, 18, 19, 20
Pins 1, 2, 3, 4
Pins 15, 16
Pins 5, 6
Forced State
See Figure 10
See Figure 10
GND
D4–D7
GND
V
Pin 5
5V
CC
CE
Pin 7
Pin 8
V
IL
PS009201-0301
Programming Specification
Z86E02/E04/E08/E09 SL1995
Z8 CMOS OTP Microcontrollers
16
Table 9. EPROM ARRAY PROGRAM AND VERIFY Mode Conditions (Continued)
NC
Pin 6
Pin 7
No Connection
See Figure 10
OE
Pin 8
Pin 9
EPM
Pin 9
Pin 10
Pin 11
Pin 12
Pin 13
Pin 14
V
V
IH
IH
V
Pin 10
Pin 11
Pin 12
Pin 13
PP
CLEAR
CLOCK
PGM
See Figure 10
See Figure 10
See Figure 10
Option Bit Modes
Table 10 lists the device’s available option bits and their default states.
Table 10.Option Bit Values*
Bit
D0
D1
D2
D3
D4
D5
D6
D7
Option
Unprogrammed Default Value
Disabled
ROM Protect
Low-EMI Mode
Autolatches
Reserved
Disabled
Enabled
Must be 1
Permanent WDT
Reserved
Disabled
Must be 1
RC Oscillator
32-kHz Oscillator
Disabled
Disabled
Note: Option bits are 0 when programmed and 1 when unprogrammed.
OPTION BIT PROGRAM AND VERIFY Mode Entry
1. To enter OPTION BIT PROGRAM AND VERIFY mode, all pins must be set as
per Table 11. The initial state for V and CLEAR is V while OE is at V .
PP
IL
IH
2. V is raised to V .
PP
IH
3. CLEAR is pulsed High to V , then Low to V . See Table 14 for specifications
IH
IL
regarding the CLEAR signal.
4. V is lowered to V .
PP
IL
5. After a delay of at least 1µs minimum, V is raised to V .
PP
IH
PS009201-0301
Programming Specification
Z86E02/E04/E08/E09 SL1995
Z8 CMOS OTP Microcontrollers
17
6. After a delay of at least 1µs minimum from V rising, OE is raised to V .
PP
IH
7. The CLOCK is raised to V .
IH
8. OE is pulsed Low to V , then High to V .
IL
IH
9. The CLOCK is lowered to V .
IL
10. Repeat steps 7 to 9 six more times.
11. After a delay of at least 1µs minimum, EPM is raised to V .
IH
12. The device is now in OPTION BIT READ/WRITE mode. See Figure 11.
Figure 11. OPTION BIT PROGRAM AND VERIFY Mode Entry Functional Timing
5V
0V
V
CC
V
VIL
IH
CLEAR
EPM
VIH
VIL
VIH
VIL
CE
VPP
VIH
VIL
VIH
VIL
CLOCK
VIH
VIL
OE
VIH
VIL
PGM
Data
Not connected
Not connected
(Port 2)
X
OUT
Table 11. OPTION BIT PROGRAM AND VERIFY Mode Entry Conditions
EPROM Signal
D0–D3
18-Pin DIP/SOIC
Pins 15, 16, 17, 18
Pins 1, 2, 3, 4
Pin 14
20-Pin SSOP
Pins 17, 18, 19, 20
Pins 1, 2, 3, 4
Pins 15, 16
Forced State
NC
D4–D7
NC
GND
GND
5V
V
Pin 5
Pins 5, 6
CC
PS009201-0301
Programming Specification
Z86E02/E04/E08/E09 SL1995
Z8 CMOS OTP Microcontrollers
18
Table 11. OPTION BIT PROGRAM AND VERIFY Mode Entry Conditions (Continued)
CE
Pin 7
Pin 8
V
IL
NC
Pin 6
Pin 7
No Connection
See Figure 11
See Figure 11
See Figure 11
See Figure 11
See Figure 11
OE
Pin 8
Pin 9
EPM
Pin 9
Pin 10
Pin 11
Pin 12
Pin 13
Pin 14
V
Pin 10
Pin 11
Pin 12
Pin 13
PP
CLEAR
CLOCK
PGM
V
IH
OPTION BIT PROGRAM AND VERIFY Mode Operation
1. Perform the Option Bit READ/WRITE Mode Entry operation (see OPTION BIT
PROGRAM AND VERIFY Mode Entry on page 16) before proceeding to Step 2.
2. The CLOCK is pulsed High to V , then Low to V . Please refer to Table 14 for
IH
IL
minimum and maximum widths of the CLOCK signal. See Figure 12 and
Table 12.
3. The 8 option bit values required in Table 10 are forced onto Port2. Option bits
D0 to D7 corresponds to Port2 pins P20 to P27. Please refer to Table 14 for
setup and hold times.
4. The PROGRAM operation is performed by lowering PGM to V . Please refer
IL
to Table 14 for minimum and maximum widths of the PGM signal. See
Figure 12 and Table 12.
5. The PROGRAM operation is complete when the PGM is raised back to V .
IH
6. The VERIFY operation is performed by lowering OE to V , then reading the
IL
data on Port2. Pins P20 to P27 represent the Option Bit data D0 to D7,
respectively.
7. A V -level READ on Port2 corresponds to a 1 state (unprogrammed), while
OH
a V level corresponds to a 0 level stored in the EPROM array.
OL
Note: Please refer to Table 14 for the minimum and maximum width of OE dur-
ing EPROM READ mode and data access time.
8. If the data read shows that the address location is not yet programmed, then
repeat Steps 4 to 7 until the data read shows that the address location is
programmed.
PS009201-0301
Programming Specification
Z86E02/E04/E08/E09 SL1995
Z8 CMOS OTP Microcontrollers
19
9. If the address location is not programmed after the 25th try, then the device is
failed.
10. If the address location shows that it is programmed, then the address location
is then overprogrammed with three times the total accumulated program time.
Figure 12. OPTION BIT PROGRAM AND VERIFY Functional Timing
5V
VCC
0V
V
IH
CLEAR
V
IL
V
IH
EPM
V
IL
V
IH
(CE)
V
IL
V
IH
VPP
V
IL
V
IH
CLOCK
V
IL
V
IH
OE
V
IL
V
IH
PGM
3 x N x 1ms
Data In
V
IL
Data
(Port 2)
Data
Out
Data In
Data Out
Table 12.OPTION BIT PROGRAM AND VERIFY Mode Conditions
EPROM Signal
D0–D3
18-Pin DIP/SOIC
Pins 15, 16, 17, 18
Pins 1, 2, 3, 4
Pin 14
20-Pin SSOP
Pins 17, 18, 19, 20
Pins 1, 2, 3, 4
Pins 15, 16
Pins 5, 6
Forced State
See Figure 12
See Figure 12
GND
D4–D7
GND
V
Pin 5
5V
CC
CE
NC
Pin 7
Pin 8
V
IL
Pin 6
Pin 7
No Connection
PS009201-0301
Programming Specification
Z86E02/E04/E08/E09 SL1995
Z8 CMOS OTP Microcontrollers
20
Table 12.OPTION BIT PROGRAM AND VERIFY Mode Conditions (Continued)
OE
Pin 8
Pin 9
See Figure 12
EPM
Pin 9
Pin 10
Pin 11
Pin 12
Pin 13
Pin 14
V
V
IH
IH
V
Pin 10
Pin 11
Pin 12
Pin 13
PP
CLEAR
CLOCK
PGM
See Figure 12
See Figure 12
See Figure 12
OPTION BIT READ Mode Operation
1. Perform the Option Bit READ/WRITE Mode Entry operation (see OPTION BIT
PROGRAM AND VERIFY Mode Entry on page 16) before proceeding to Step 2.
2. CLOCK is pulsed High to V then Low to V . Please refer to Table 14 for the
IH,
IL
minimum and maximum width values of the CLOCK signal.
3. The 8 option bit values required in Table 10 are read from Port2. Option bits
D0 to D7 correspond to Port2 pins P20 to P27. Please refer to Table 14 for
setup and hold times.
4. The OPTION BIT READ operation is performed by lowering OE to V and
IL
reading the data on Port2. Pins P20 to P27 represent the option bit data D0 to
D7, respectively. See Figure 13.
5. A V -level READ on Port2 corresponds to a 1 state, while a V -level
OH
OL
corresponds to a 0 level stored in the EPROM array.
6. Please refer to Table 14 for the minimum and maximum width of OE during
EPROM READ mode and data access time.
PS009201-0301
Programming Specification
Z86E02/E04/E08/E09 SL1995
Z8 CMOS OTP Microcontrollers
21
Figure 13. OPTION BIT READ Mode Functional Timing
5V
0V
VCC
V
IH
CLEAR
EPM
CE
V
IL
V
IH
V
IL
V
IH
V
IL
V
IH
VPP
V
IL
V
IH
CLOCK
V
IL
V
IH
OE
V
IL
V
IH
PGM
V
IL
Data
(Port 2)
Invalid
Data Out
Invalid
XOUT
Not connected
Power-Down Procedure
The following steps outline the power-down operation of the Z86E0x device.
1. Set up the I/O pins per Figure 14 and Table 13.
2. CE is raised to V .
IH
3. EPM is lowered to GND.
4. V is lowered to GND.
PP
5. V is lowered from 5.0V to 2.0V.
CC
6. PGM is lowered to GND.
7. OE is lowered to GND.
8. CE is lowered to GND.
9. V is lowered to GND.
CC
PS009201-0301
Programming Specification
Z86E02/E04/E08/E09 SL1995
Z8 CMOS OTP Microcontrollers
22
Figure 14. Power-Down Functional Timing
5V
2V
0V
V
CC
V
0V
IH
CLEAR
EPM
VIH
0V
(CE)
VIH
0V
VPP
VIH
0V
CLOCK
OE
VIH
0V
VIH
0V
PGM
Data
Not connected
Not connected
(Port 2)
XOUT
Table 13.Power-Down Conditions
EPROM Signal
D0–D3
18-Pin DIP/SOIC
Pins 15, 16, 17, 18
Pins 1, 2, 3, 4
Pin 14
20-Pin SSOP
Forced State
NC
Pins 17, 18, 19, 20
Pins 1, 2, 3, 4
Pins 15, 16
Pins 5, 6
Pin 8
D4–D7
NC
GND
GND
V
Pin 5
See Figure 14
See Figure 14
No Connection
See Figure 14
See Figure 14
See Figure 14
CC
CE
Pin 7
NC
Pin 6
Pin 7
OE
Pin 8
Pin 9
EPM
Pin 9
Pin 10
V
Pin 10
Pin 11
PP
CLEAR
CLOCK
PGM
Pin 11
Pin 12
V
V
IL
IL
Pin 12
Pin 13
Pin 13
Pin 14
See Figure 14
PS009201-0301
Programming Specification
Z86E02/E04/E08/E09 SL1995
Z8 CMOS OTP Microcontrollers
23
EPROM I/O Timing
The following section details the programming and verification of the OTP. Input
and output timing is illustrated in Figure 15. Timing specifications are provided in
Table 14. Voltage specifications are provided in Table 15.
Figure 15. Z86E0x EPROM ARRAY and OPTION BIT PROGRAM AND VERIFY Waveform*
4
Clock
1
V
IH
Data
Data Stable
Data Out Valid
V
IL
10
12
5
2
3
8
V
IH
OE
V
IL
11
V
IH
PGM
V
IL
9
6
7
Program Cycle
Verify Cycle
Note: *EPROM bits are 0 when programmed, and 1 when unprogrammed.
Table 14.Timing Specifications
Parameters
Name
Min
2
Max
Units
1
2
3
4
5
6
7
Address setup time
Chip Enable setup time
PGM setup time
µs
µs
µs
µs
µs
ms
ms
2
2
Address to OE setup time
Data setup time
2
2
Program pulse width
Overprogram pulse width
0.95
2.85
PS009201-0301
Programming Specification
Z86E02/E04/E08/E09 SL1995
Z8 CMOS OTP Microcontrollers
24
Table 14.Timing Specifications (Continued)
Parameters
Name
Min
2
Max
Units
µs
8
Data hold time
OE setup time
Data access time
OE width
9
2
µs
10
11
12
188
250
ns
ns
Data output float time
100
ns
Table 15.Voltage Specifications
20ºC to 30ºC
Symbol Description
Min
Max
5.25
50
Typical
Unit
V
V
Programming supply voltage
Programming supply current
Input High Voltage
4.75
5.0
PROG
PROG
I
mA
V
V
V
V
V
0.7 x V
V +0.3
PROG
2.6
1.6
4.8
0.8
IH
PROG
Input Low Voltage
GND–0.3 0.2 x V
V
IL
PROG
Output High Voltage
Output Low Voltage
V
–0.4
PROG
V
OH
OL
1.0
V
Figure 16 illustrates additional timing for the device. Table 16 provides the timing
specifications identified in Figure 16.
PS009201-0301
Programming Specification
Z86E02/E04/E08/E09 SL1995
Z8 CMOS OTP Microcontrollers
25
Figure 16. Z86E0x Additional Timing Waveform
T3
CLOCK
T4
T9
T10
T3
T12
T1
T7
CLEAR
T5
OE
Address
Data
T7
T6
T11
T8
0010h
0000h
0001h
0002h
T13
T13
Valid
Valid
Valid
Table 16.Z86E0x Additional Timing Specifications
Timing
Parameter Name
Minimum
1µs
Maximum
T1
T2
T3
T4
T5
T6
T7
T8
T9
T10
CLEAR Width
Input CLOCK High
1µs
Input CLOCK Period
Input CLOCK Low
2µs
1µs
CLOCK to Address Counter Out Delay
OE Setup Time
15ns
1µs
1µs
OE Hold Time
OE Width Low
250ns
2µs
CLOCK Falling to CLEAR Rising
CLEAR Falling to CLOCK Rising
2µs
PS009201-0301
Programming Specification
Z86E02/E04/E08/E09 SL1995
Z8 CMOS OTP Microcontrollers
26
Table 16.Z86E0x Additional Timing Specifications (Continued)
Timing
Parameter Name
Minimum
Maximum
T11
T12
T13
CLEAR to Address Counter Out Delay
15ns
CLOCK Rising to OE Falling
Data Access Time
1µs
188ns
Programming Flow
Figures 17 and 18 illustrate the flow of the EPROM ARRAY PROGRAM, VERIFY,
and READ operations. Figures 19 and 20 illustrate the flow of the OPTION BIT
PROGRAM, VERIFY, and READ operations.
PS009201-0301
Programming Specification
Z86E02/E04/E08/E09 SL1995
Z8 CMOS OTP Microcontrollers
27
Figure 17. EPROM ARRAY PROGRAM, VERIFY, and READ Algorithm
Start
Power-On Reset
VCC= 5.0V
Send Unlock
Sequence and
Mode A Select
Clear Address
Counter to
First Location
N = 0
Program
1 ms Pulse
Increment N
Yes
N = 25?
No
Fail
Fail
Verify
Verify Byte
Pass
One Byte
Pass
Program One Pulse
3xN ms Duration
No
Increment Address
Final Address?
Yes
Clear Address
Counter to
First Location
Fail
EPROM Read
One Byte
Pass
Device Failed
No
Increment Address
Final Address?
Yes
Device Passed
PS009201-0301
Programming Specification
Z86E02/E04/E08/E09 SL1995
Z8 CMOS OTP Microcontrollers
28
Figure 18. EPROM ARRAY READ Algorithm
Start
Power-On Reset
VCC= 5.0V
Send Unlock
Sequence and
Mode A Select
Clear Address
Counter to
First Location
Fail
EPROM Verify
One Byte
Pass
No
Increment Address
Final Address?
Yes
Device Failed
Device Passed
PS009201-0301
Programming Specification
Z86E02/E04/E08/E09 SL1995
Z8 CMOS OTP Microcontrollers
29
Figure 19. OPTION BIT PROGRAM, VERIFY, and READ Algorithm
Start
Power-On Reset
VCC= 5.0V
Send Unlock
Sequence and
Mode B Select
N = 0
Program
1 ms Pulse*
Increment N
Yes
N = 25?
No
Fail
Fail
Verify
Verify Byte
Pass
One Byte
Pass
Program One Pulse
3xN ms Duration
Device Failed
Device Passed
Note: *It is assumed that the user has already selected the option bits prior to this step.
PS009201-0301
Programming Specification
Z86E02/E04/E08/E09 SL1995
Z8 CMOS OTP Microcontrollers
30
Figure 20. OPTION BIT READ Algorithm
Start
Power-On Reset
VCC= 5.0V
Send Unlock
Sequence and
Mode B Select
Option Bit Verify
One Byte*
Fail
Pass
Device Failed
Device Passed
Note: *It is assumed that the user has already selected the option bits prior to this step.
PS009201-0301
Programming Specification
Z86E02/E04/E08/E09 SL1995
Z8 CMOS OTP Microcontrollers
31
Recommendations to Third-Party Programmers
ZiLOG recommends the top-level flow illustrated in Figure 21 for programming
user code and option bits into OTP.
Figure 21. Third-Party Top-Level Algorithm
Start
Download User Code
to Buffer
Select Option Bits
EPROM ARRAY
PROGRAM/VERIFY
User Code
Fail
Fail
Show as Fail
Pass
EPROM READ
User Code
Pass
OPTION BIT
PROGRAM/VERIFY
Fail
Pass
Show as Pass
ZiLOG recommends that third-party programmers offer the following features for
OTP operations.
•
•
•
•
•
Blank check
Examine OTP code
Program/verify code and option bits
Verify code
Checksum of OTP
PS009201-0301
Programming Specification
Z86E02/E04/E08/E09 SL1995
Z8 CMOS OTP Microcontrollers
32
•
•
•
Checksum of buffer/RAM
Program option bits as a sole option
Read option bits as a sole option
Precharacterization Product
The product represented by this document is newly introduced and ZiLOG has not
completed the full characterization of the product. The document states what
ZiLOG knows about this product at this time, but additional features or nonconfor-
mance with some aspects of the document may be found, either by ZiLOG or its
customers in the course of further application and characterization work. In addi-
tion, ZiLOG cautions that delivery may be uncertain at times, due to start-up yield
issues.
ZiLOG, Inc.
910 East Hamilton Avenue, Suite 110
Campbell, CA 95008
Telephone (408) 558-8500
FAX 408 558-8300
Internet: www.zilog.com
PS009201-0301
Programming Specification
Z86E02/E04/E08/E09 SL1995
Z8 CMOS OTP Microcontrollers
33
Third Party Developer Feedback Form
The Z86E02/E04/E08/E09 SL1995 Programming Specification
If you experience any problems while operating this product, or if you note any inaccuracies
while reading this Product Specification, please copy and complete this form, then mail or
fax it to ZiLOG (see Return Information, below). We also welcome your suggestions!
Third Party Developer Information
Name
Country
Phone
Fax
Company
Address
City/State/Zip
E-Mail
Third Party Developer Product Information
Serial # or Board Fab #/Rev. #
Software Version
Document Number
Host Computer Description/Type
Return Information
ZiLOG
Worldwide Customer Support Center
4201 Bee Caves Road, Suite C-100
Austin, TX, USA 78746
Phone: 1-877-945-6427
Fax: (512) 306-4042
Email: customerfeedback@zilog.com
Problem Description or Suggestion
Provide a complete description of the problem or your suggestion. If you are reporting a
specific problem, include all steps leading up to the occurrence of the problem. Attach
additional pages as necessary.
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PS009201-0301
Programming Specification
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