Z86L89_技术文档

PRELIMINARY PRODUCT SPECIFICATION

1

Z86L88/81/86/87/89/73

1

IR/LOW-VOLTAGE MICROCONTROLLER

FEATURES

–

Programmable Input Glitch Filter for Pulse

Reception

ROM

(KB)

RAM*

(Bytes) Lines

I/O

Voltage

Range

Device

Z86L88

Z86L81

Z86L86

Z86L87

Z86L89

Z86L73

16

24

32

16

24

32

237

236

23

31

2.0V to 3.9V

■ Five Priority Interrupts

–

Three External

Two Assigned to Counter/Timers

■ Low Voltage Detection and Standby Mode

■ Programmable Watch-Dog/Power-On Reset Circuits

Note: *General-Purpose

■ Two Independent Comparators with Programmable

Interrupt Polarity

■ Low Power Consumption - 40 mW (Typical)

■ Three Standby Modes

■ On-Chip Oscillator that Accepts a Crystal, Ceramic

Resonator, LC, RC (Mask Option), or External Clock

Drive

–

STOP

HALT

Low Voltage

■ Mask Selectable 200 kOhms Pull-Ups on Ports 0, 2, 3

–

All Eight Port 2 Bits at One Time or Not

■ Special Architecture to Automate Both Generation and

Pull-Ups Automatically Disabled Upon Selecting

Individual Pins as Outputs.

Reception of Complex Pulses or Signals:

–

One Programmable 8-Bit Counter/Timer with Two

Capture Registers

■ Maskable Mouse/Trackball Interface on P00 Through

One Programmable 16-Bit Counter/Timer with

One 16-Bit Capture Register

P03.

■ 32 kHz Oscillator Mask Option

GENERAL DESCRIPTION

™

The Z86LXX family of IR (Infrared) CCP (Consumer Con-

troller Processor) Controllers are ROM/ROMless-based

ternal key-scan pull-up resistors. The Z86LXX product line

offers easy hardware/software system expansion cost-ef-

fective and low power consumption.

®

members of the Z8 single-chip microcontroller family with

256 bytes of internal RAM. The differentiating factor be-

tween these devices is the availability of ROM, and pack-

age options. For the 40 and 44-pin devices the use of ex-

ternal memory enables these Z8 microcontrollers to be

used where code flexibility is required. Zilog’s CMOS mi-

crocontrollers offers fast executing, efficient use of memo-

ry, sophisticated interrupts, input/output bit manipulation

capabilities, automated pulse generation/reception, and in-

The Z86LXX architecture is based on Zilog's 8-bit micro-

controller core with an Expanded Register File to allow ac-

cess to register mapped peripherals, I/O circuits, and pow-

erful counter/timer circuitry. The CCP offers a flexible I/O

scheme, an efficient register and address space structure,

and a number of ancillary features that are useful in many

DS96LV00800

P R E L I M I N A R Y

1

Z86L88/81/86/87/89/73

IR/Low-Voltage Microcontroller

GENERAL DESCRIPTION (Continued)

consumer, automotive, computer peripheral, and battery

operated hand-held applications.

with 8-bit and 16-bit counter/timers (Figure 1). Also includ-

ed are a large number of user-selectable modes, and two

on-board comparators to process analog signals with sep-

arate reference voltages (Figure 2).

There are four basic address spaces available to support

a wide range of configurations: Program Memory, Regis-

ter File, Expanded Register File, and External Memory.

The register file is composed of 256 bytes of RAM. It in-

cludes four I/O port registers, 16 control and status regis-

ters and the rest are General Purpose registers. The Ex-

panded Register File consists of two additional register

groups (F and D). External Memory is not available on 28-

pin versions.

Notes: All Signals with a preceding front slash, "/", are ac-

tive Low, e.g., B//W (WORD is active Low); /B/W (BYTE is

active Low, only).

Power connections follow conventional descriptions be-

low:

Connection

Power

Circuit

Device

To unburden the program from coping with such real-time

problems as generating complex waveforms or receiving

and demodulating complex waveform/pulses, the Z86LXX

family offers a new intelligent counter/timer architecture

V

DD

CC

Ground

GND

V

SS

HI16

8

LO16

8

16-Bit

T16

Timer 16

16

2 4 8

1

8

SCLK

Clock

Divider

TC16H

TC16L

And/Or

Logic

Timer 8/16

HI8

8

LO8

8

Edge

Input

Glitch

Filter

Detect

Circuit

8-Bit

T8

Timer 8

8

TC8H

TC8L

Figure 1. Counter/Timers Diagram

2

P R E L I M I N A R Y

DS96LV00800

Z86L88/81/86/87/89/73

IR/Low-Voltage Microcontroller

P00

P01

P02

P03

Pref1

P31

P32

P33

Register File

256 x 8-bit

4

1

Port 0

Port 1

Port 2

Port 3

P34

P04

P05

P06

P07

Register Bus

P35

P36

P37

Internal

Address Bus

ROM

24K/32K x 8

Z8 Core

P10

P11

P12

P13

P14

P15

P16

P17

Internal Data Bus

XTAL

8

Machine

Timing

Expanded

Register Bus

/AS

/DS

R/W

/RESET

&

Expanded

Register

File

Instruction

Control

P20

P21

P22

P23

P24

P25

P26

P27

R//RL

(44-Pin)

VDD

VSS

Power

I/O Bit

Programmable

Counter/Timer 16

16-Bit

Counter/Timer 8

8-Bit

Figure 2. Functional Block Diagram

DS96LV00800

P R E L I M I N A R Y

3

Z86L88/81/86/87/89/73

IR/Low-Voltage Microcontroller

PIN DESCRIPTION

1

P25

P26

P27

P04

P05

28

P24

P23

P22

P21

P20

P03

VSS

P02

P01

P00

Pref1

P36

P37

P35

P06

P07

Z86L88/86/81

DIP

VDD

XTAL2

XTAL1

P31

P32

P33

P34

14

15

Figure 3. 28-Pin DIP

Pin Assignments

P24

1

P25

28

P23

P22

P21

P20

P03

VSS

P02

P01

P00

Pref1

P36

P37

P35

P26

P27

P04

P05

P06

Z86L88/86/81

SOIC

P07

VDD

XTAL2

XTAL1

P31

P32

P33

P34

14

15

Figure 4. 28-Pin SOIC

Pin Assignments

4

P R E L I M I N A R Y

DS96LV00800

Z86L88/81/86/87/89/73

IR/Low-Voltage Microcontroller

1

R//W

P25

40

/DS

1

P24

P23

P22

P21

P20

P03

P13

P12

VSS

P02

P11

P10

P01

P00

Pref1

P36

P37

P35

/RESET

P26

P27

P04

P05

P06

P14

P15

P07

Z86L73/89/87

DIP

VDD

P16

P17

XTAL2

XTAL1

P31

P32

P33

P34

/AS

20

21

Figure 5. 40-Pin DIP

Pin Assignments

6

1

40

39

7

P21

P22

P23

P24

/DS

R//RL

R//W

P25

P26

P27

P04

Pref1

P36

P37

P35

/RESET

VSS

/AS

P34

P33

P32

P31

Z86L73/89/73

PLCC

17

29

28

18

Figure 6. 44-Pin PLCC

Pin Assignments

DS96LV00800

P R E L I M I N A R Y

5

Z86L88/81/86/87/89/73

IR/Low-Voltage Microcontroller

PIN DESCRIPTION (Continued)

33

23

22

P21

P22

P23

P24

/DS

R//RL

R//W

P25

P26

P27

P04

34

Pref1

P36

P37

P35

/RESET

VSS

/AS

P34

P33

Z86L73/89/87

QFP

P32

P31

12

11

44

1

Figure 7. 44-Pin QFP

Pin Assignments

6

P R E L I M I N A R Y

DS96LV00800

Z86L88/81/86/87/89/73

IR/Low-Voltage Microcontroller

Table 1. Pin Identiﬁcation

40-Pin

DIP #

44-Pin

PLCC #

44-Pin

QFP #

Symbol

Direction

Input/Output

Description

1

26

27

30

34

5

40

41

44

5

23

24

27

32

44

1

P00

P01

P02

P03

P04

P05

P06

P07

P10

P11

P12

P13

P14

P15

P16

P17

P20

P21

P22

P23

P24

P25

P26

P27

P31

P32

P33

P34

P35

P36

P37

/AS

Port 0 is Nibble Programmable.

Port 0 can be conﬁgured as

A15-A8 external program

ROM Address Bus.

Input/Output

Input

17

18

19

22

42

43

3

Port 0 can be conﬁgured as a

mouse/trackball input.

6

7

2

10

28

29

32

33

8

5

25

26

30

31

3

Port 1 is byte programmable.

Port 1 can be conﬁgured as

multiplexed A7-A0/D7-D0

external program ROM

Address/Data Bus.

4

20

21

25

26

6

9

4

12

13

35

36

37

38

39

2

8

9

33

34

35

36

37

41

42

43

12

13

14

15

19

21

20

16

38

40

18

11

10

6,7

Port 2 pins are individually

7

conﬁgurable as input or output.

8

9

10

14

15

16

29

30

31

32

36

38

37

33

11

13

35

28

27

23,24

3

4

16

17

18

19

22

24

23

20

40

1

IRQ2/Modulator input

IRQ0

Input

IRQ1

Output

T8 output

Output

T16 output

T8/T16 output

Output

Address Strobe

Data Strobe

/DS

R//W

Output

Read/Write

21

15

14

11

/RESET Input

Reset

XTAL1

XTAL2

Input

Crystal, Oscillator Clock

Power Supply

Output

V

DD

31

25

1,2, 34

17,28,29

V

Ground

SS

39

12

22

39

Pref1

R//RL

Input

Comparator 1 Reference

ROM/ROMless

DS96LV00800

P R E L I M I N A R Y

7

Z86L88/81/86/87/89/73

IR/Low-Voltage Microcontroller

PIN DESCRIPTION (Continued)

Table 2. Pin Identiﬁcation

Direction

28-Pin

DIP & SOIC

Symbol

Description

19

20

21

23

4

P00

P01

P02

P03

P04

P05

Input/Output

Port 0 is Nibble Programmable

Port 0 can be conﬁgured as

A15-A8 external program

ROM Address Bus.

5

Port 0 can be conﬁgured as a

mouse/trackball input.

6

P06

P07

P20

P21

P22

P23

P24

P25

P26

P27

Pref1

P31

P32

P33

P34

P35

P36

P37

XTAL1

XTAL2

Input/Output

Input

7

24

25

26

27

28

1

Port 2 pins are individually

conﬁgurable as input or output.

2

3

18

11

12

13

14

15

17

16

10

9

Analog Ref Input

IRQ2/Modulator input

IRQ0

Input

IRQ1

Output

T8 output

Output

T16 output

Output

T8/T16 output

Output

Input

Crystal, Oscillator Clock

Power Supply

Output

8

V

DD

22

V

Ground

SS

8

P R E L I M I N A R Y

DS96LV00800

Z86L88/81/86/87/89/73

IR/Low-Voltage Microcontroller

ABSOLUTE MAXIMUM RATINGS

Stresses greater than those listed under Absolute Maxi-

mum Ratings may cause permanent damage to the de-

vice. This is a stress rating only; operation of the device at

any condition above those indicated in the operational sec-

tions of these specifications is not implied. Exposure to ab-

solute maximum rating conditions for an extended period

may affect device reliability.

Symbol

Description

Min

Max

Units

1

V

Supply Voltage

(*)

–0.3

+7.0

V

CC

T

Storage Temp.

–65°

+150°

C

STG

T

Oper. Ambient

Temp.

†

A

Notes: :

* Voltage on all pins with respect to GND.

† See Ordering Information.

STANDARD TEST CONDITIONS

The characteristics listed below apply for standard test

conditions as noted. All voltages are referenced to GND.

Positive current flows into the referenced pin (Figure 8).

From Output

Under Test

I

150 pF

Figure 8. Test Load Diagram

CAPACITANCE

T = 25°C, V = GND = 0V, f = 1.0 MHz, unmeasured pins returned to GND.

A

CC

Parameter

Max

Input capacitance

Output capacitance

I/O capacitance

12 pF

DS96LV00800

P R E L I M I N A R Y

9

Z86L88/81/86/87/89/73

IR/Low-Voltage Microcontroller

DC CHARACTERISTICS

Preliminary

T = 0°C to +70°C

Typ @

A

V

Sym

Parameter

Min

Max

25°C

Units

Conditions

Notes

CC

Max Input Voltage 2.0V

3.9V

7

V

I

<250 µA

IN

V

Clock Input

High Voltage

2.0V

3.9V

0.8 V

V

+ 0.3

V

Driven by External

Clock Generator

Driven by External

Clock Generator

CH

CC

0.8 V

V

CC

Clock Input

Low Voltage

2.0V

3.9V

V

– 0.3

0.2 V

V

Driven by External

Clock Generator

Driven by External

Clock Generator

CL

SS

CC

SS

CC

V

Input High Voltage2.0V

3.9V

0.7 V

V

+ 0.3

0.5V

V

IH

CC

Input Low Voltage 2.0V

3.9V

V

– 0.3

0.2 V

0.5V

V

IL

SS

CC

SS

CC

Output High

Voltage

2.0V

3.9V

V

– 0.4

1.7

3.7

V

I

= –0.5 mA

OH1

OH2

CC

OH

Output High

Voltage (P36,

P37,P00, P01)

2.0V

3.9V

V

- 0.8

V

I

= –7 mA

CC

OH

V

Output Low

Voltage

2.0V

3.9V

0.4

0.1

0.2

V

I

= 1.0 mA

= 4.0 mA

OL1

OL

Output Low

Voltage

2.0V

3.9V

0.8

0.5

0.3

V

I

= 5.0 mA

OL2*

OL

I

= 7.0 mA

OL

V

Output Low

Voltage(P36,

P37,P00,P01)

2.0V

3.9V

0.8

0.3

0.2

V

I

= 10 mA

OL2

OL

V

Reset Input

High Voltage

2.0V

3.9V

0.8 V

V

1.5

2.0

V

RH

CC

0.8 V

V

Reset Input

Low Voltage

2.0V

3.9V

V

– 0.3

0.2 V

0.5

0.9

V

Rl

SS

CC

SS

CC

Comparator Input 2.0V

Offset Voltage

25

10

mV

OFFSET

3.9V

I

Input Leakage

2.0V

3.9V

-1

1

< 1

µA

V

= O , V

V

IL

IN

CC

= O , V

V

CC

Output Leakage 2.0V

3.9V

–1

1

< 1

µA

V

= O , V

V

OL

IR

IN

CC

= O , V

V

CC

Reset Input Pull- 2.0V

Up Current

–230

–400

-90

–220 µA

µA

V

= O

V

IN

3.9V

= O ‘

IN

V

Supply Current

2.0V

3.9V

10

15

4

10

mA

@ 8.0 MHz

1,2

CC

2.0V

3.9V

250

850

100 µA

500 µA

@ 32 kHz

1,2,7

10

P R E L I M I N A R Y

DS96LV00800

Z86L88/81/86/87/89/73

IR/Low-Voltage Microcontroller

T = 0°C to +70°C

A

Typ @

25°C

1

V

Sym

Parameter

Min

Max

Units

mA HALT Mode

= O , V @

CC

Conditions

Notes

1,2

CC

I

Standby Current

(WDT Off)

2.0V

3

CC1

V

IN

V

8.0 MHz

HALT Mode

= O , V

CC

3.9V

5

4

mA

1,2

V

IN

V

@ 8.0 MHz

2.0V

3.9V

2

4

0.8

2.5

mA Clock Divide-by- 1,2

16 @ 8.0 MHz

mA Clock Divide-by- 1,2

16 @ 8.0 MHz

I

Standby Current

2.0V

8

2

µA

STOP Mode

= O , V

CC

3,5

CC2

V

IN

V

WDT is not

Running

3.9V

10

3

µA

3,5

STOP Mode

= O , V

CC

V

IN

V

WDT is not

Running

2.0V

3.9V

500

800

310

600

µA

STOP Mode

= O , V

CC

3,5

V

IN

V

WDT is Running

T

Power-On Reset

2.0V

3.9V

12

5

75

20

18

7

ms

POR

Vram

Static RAM Data

Retention Voltage

Vram

0.8

0.5

V

6

4

V

Low Voltage

2.15

1.7

V

8 MHz max

LV

CC

Ext. CLK Freq.

(Vbo)

Protection

I

Typ

Max

Unit

Frequency

Notes:

CC1

3.0 mA

5

mA

8.0 MHz

Crystal/Resonator

0.3 mA

5

mA

8.0 MHz

External Clock Drive

1. All outputs unloaded, inputs at rail.

2. CL1 = CL2 = 100 pF

3. Same as note [4] except inputs at V

.

CC

4. The V increases as the temperature decreases.

LV

5. Oscillator stopped.

6. Oscillator stops when VCC falls below Vlv limit

7. 32 kHz clock driver input.

* All Outputs excluding P00, P01, P36, and P37.

DS96LV00800

P R E L I M I N A R Y

11

Z86L88/81/86/87/89/73

IR/Low-Voltage Microcontroller

AC CHARACTERISTICS

External I/O or Memory Read and Write Timing Diagram

R//W

13

19

12

Port 0, /DM

16

20

18

3

Port 1

A7 - A0

D7 - D0 IN

1

2

9

/AS

8

11

4

5

6

/DS

(Read)

17

10

Port 1

A7 - A0

D7 - D0 OUT

14

15

7

/DS

(Write)

Figure 9. External I/O or Memory Read/Write Timing

12

P R E L I M I N A R Y

DS96LV00800

Z86L88/81/86/87/89/73

IR/Low-Voltage Microcontroller

AC CHARACTERISTICS

Preliminary

External I/O or Memory Read and Write Timing Table

1

T = 0°C to +70°C

A

8.0MHz

V

No

Symbol

TdA(AS)

Parameter

Min

Max

Units

Notes

CC

1

Address Valid to

/AS Rising Delay

2.0V

3.9V

55

ns

2

3

4

5

6

7

8

9

TdAS(A)

TdAS(DR)

TwAS

/AS Rising to Address

Float Delay

2.0V

3.9V

70

ns

2

/AS Rising to Read

Data Required Valid

2.0V

3.9V

400

ns

1,2

/AS Low Width

2.0V

3.9V

80

ns

2

Td

Address Float to

/DS Falling

2.0V

3.9V

0

ns

TwDSR

TwDSW

TdDSR(DR)

ThDR(DS)

/DS (Read) Low Width

2.0V

3.9V

300

ns

1,2

2

/DS (Write) Low Width

2.0V

3.9V

165

ns

/DS Falling to Read

Data Required Valid

2.0V

3.9V

260

ns

Read Data to /DS Rising

Hold Time

2.0V

3.9V

0

ns

10 TdDS(A)

/DS Rising to Address

Active Delay

2.0V

3.9V

85

95

ns

2

11 TdDS(AS)

12 TdR/W(AS)

13 TdDS(R/W)

/DS Rising to /AS

Falling Delay

2.0V

3.9V

60

70

ns

2

R//W Valid to /AS

Rising Delay

2.0V

3.9V

70

ns

2

/DS Rising to

R//W Not Valid

2.0V

3.9V

70

ns

2

14 TdDW(DSW) Write Data Valid to /DS

Falling (Write) Delay

2.0V

3.9V

80

ns

2

15 TdDS(DW)

16 TdA(DR)

17 TdAS(DS)

18 TdDM(AS)

19 TdDS(DM)

20 ThDS(A)

/DS Rising to Write

Data Not Valid Delay

2.0V

3.9V

70

80

ns

2

Address Valid to Read

Data Required Valid

2.0V

3.9V

475

ns

1,2

2

/AS Rising to

/DS Falling Delay

2.0V

3.9V

100

ns

/DM Valid to /AS

Falling Delay

2.0V

3.9V

55

ns

2

/DS Rise to

/DM Valid Delay

2.0V

3.9V

70

ns

/DS Rise to Address

Valid Hold Time

2.0V

3.9V

70

ns

Notes:

1. When using extended memory timing add 2 TpC.

2. Timing numbers given are for minimum TpC.

Standard Test Load

All timing references use 0.9 V for a logic 1 and 0.1 V for a logic 0.

CC

DS96LV00800

P R E L I M I N A R Y

13

Z86L88/81/86/87/89/73

IR/Low-Voltage Microcontroller

AC CHARACTERISTICS

Additional Timing Diagram

3

1

Clock

2

3

7

T

IN

4

5

6

IRQ

N

8

9

Clock

Setup

11

Stop

Mode

Recovery

Source

10

Figure 10. Additional Timing

14

P R E L I M I N A R Y

DS96LV00800

Z86L88/81/86/87/89/73

IR/Low-Voltage Microcontroller

AC CHARACTERISTICS

Preliminary

Additional Timing Table

1

T = 0°C to +70°C

A

8.0MHz

Min

V

No

Sym

Parameter

Max

Units

Notes

CC

1

TpC

Input Clock Period

2.0V

3.9V

121

DC

ns

1

2

3

TrC,TfC

TwC

Clock Input Rise

and Fall Times

2.0V

3.9V

25

ns

1

Input Clock Width

2.0V

3.9V

37

ns

1

4

TwTinL

TwTinH

TpTin

Timer Input

Low Width

2.0V

3.9V

100

70

ns

1

5

Timer Input

High Width

2.0V

3.9V

3TpC

1

6

Timer Input

Period

2.0V

3.9V

8TpC

1

7

TrTin,TfTin Timer Input Rise

and Fall Timers

2.0V

3.9V

100

ns

1

8A

8B

9

TwIL

TwIH

Twsm

Interrupt Request

Low Time

2.0V

3.9V

100

70

ns

1,2

Interrupt Request

Low Time

2.0V

3.9V

5TpC

1,3

Interrupt Request

Input High Time

2.0V

3.9V

5TpC

1,2

10

Stop-Mode Recovery

Width Spec

2.0V

3.9V

2.0V

3.9V

12

5 TpC

ns

7

6

11

12

Tost

Oscillator

Start-Up Time

2.0V

3.9V

5TpC

4

Twdt

Watch-Dog Timer

Delay Time (5 ms)

(10 ms)

2.0V

3.9V

2.0V

3.9V

2.0V

3.9V

2.0V

3.9V

12

5

75

20

150

40

300

80

1200

320

ms

25

10

50

20

225

80

(20 ms)

(80 ms)

Notes:

1. Timing Reference uses 0.9 V for a logic 1 and 0.1 V for a logic 0.

CC

2. Interrupt request through Port 3 (P33-P31).

3. Interrupt request through Port 3 (P30).

4. SMR – D5 = 0

CC

DS96LV00800

P R E L I M I N A R Y

15

Z86L88/81/86/87/89/73

IR/Low-Voltage Microcontroller

AC CHARACTERISTICS

Handshake Timing Diagrams

Data In

Data In Valid

Next Data In Valid

2

1

3

/DAV

Delayed DAV

(Input)

5

6

4

RDY

Delayed RDY

(Output)

Figure 11. Port Input Handshake Timing

Data Out

Data Out Valid

Next Data Out Valid

7

/DAV

Delayed DAV

(Output)

8

9

11

10

RDY

Delayed RDY

(Input)

Figure 12. Port Output Handshake Timing

16

P R E L I M I N A R Y

DS96LV00800

Z86L88/81/86/87/89/73

IR/Low-Voltage Microcontroller

AC CHARACTERISTICS

Preliminary

Handshake Timing Table

1

T = 0°C to +70°C

Data

A

V

No

Sym

TsDI(DAV)

Parameter

Min

Max

Direction

CC

1

Data In Setup Time

2.0V

3.9V

0

IN

2

3

ThDI(DAV)

Data In Hold Time

2.0V

3.9V

0

IN

TwDAV

Data Available Width

2.0V

3.9V

155

110

IN

4

TdDAVI(RDY)

TdDAVId(RDY)

TdRDYO(DAV)

TdDO(DAV)

TdDAV0(RDY)

TdRDY0(DAV)

TwRDY

DAV Falling to RDY

Falling Delay

2.0V

3.9V

160

115

IN

5

DAV Rising to RDY

Falling Delay

2.0V

3.9V

120

80

IN

6

RDY Rising to DAV

Falling Delay

2.0V

3.9V

0

IN

7

Data Out to DAV

Falling Delay

2.0V

3.9V

63

OUT

8

DAV Falling to RDY

Falling Delay

2.0V

3.9V

0

OUT

9

RDY Falling to DAV

Rising Delay

2.0V

3.9V

160

115

OUT

10

11

RDY Width

2.0V

3.9V

110

80

OUT

TdRDY0d(DAV)

RDY Rising to DAV

Falling Delay

2.0V

3.9V

110

80

OUT

DS96LV00800

P R E L I M I N A R Y

17

Z86L88/81/86/87/89/73

IR/Low-Voltage Microcontroller

PIN FUNCTIONS

/DS (Output, active Low). Data Strobe is activated once for

each external memory transfer. For a READ operation,

data must be available prior to the trailing edge of /DS. For

WRITE operations, the falling edge of /DS indicates that

output data is valid.

Port 0 (P07-P00). Port 0 is an 8-bit, bidirectional, CMOS

compatible port. These eight I/O lines are configured un-

der software control as a nibble I/O port, or as an address

port for interfacing external memory. The output drivers

are push-pull. Port 0 can be placed under handshake con-

trol. In this configuration, Port 3, lines P32 and P35 are

used as the handshake control /DAV0 and RDY0. Hand-

shake signal function is dictated by the I/O direction of the

Port 0 upper nibble P07-P04. The lower nibble must have

the same direction as the upper nibble.

/AS (Output, active Low). Address Strobe is pulsed once

at the beginning of each machine cycle. Address output is

through Port 0/Port 1 for all external programs. Memory

address transfers are valid at the trailing edge of /AS. Un-

der program control, /AS is placed in the high-impedance

state along with Ports 0 and 1, Data Strobe, and

Read/Write.

For external memory references, Port 0 can provide ad-

dress bits A11-A8 (lower nibble) or A15-A8 (lower and up-

per nibble) depending on the required address space. If

the address range requires 12 bits or less, the upper nibble

of Port 0 can be programmed independently as I/O while

the lower nibble is used for addressing. If one or both nib-

bles are needed for I/O operation, they must be configured

by writing to the Port 0 mode register. After a hardware re-

set, Port 0 is configured as an input port.

XTAL1 Crystal 1 (time-based input). This pin connects a

parallel-resonant crystal, ceramic resonator, LC, or RC

network or an external single-phase clock to the on-chip

oscillator input.

XTAL2 Crystal 2 (time-based output). This pin connects a

parallel-resonant, crystal, ceramic resonant, LC, or RC

network to the on-chip oscillator output.

Port 0 is set in the high-impedance mode (if selected as an

address output) along with Port 1 and the control signals

/AS, /DS, and R//W through P3M bits D4 and D3(Figure

13).

R//W Read/Write (output, write Low). The R//W signal is

Low when the CCP is writing to the external program or

data memory.

A ROM mask option is available to program 0.4 V

CMOS trip inputs on P00-P03. This allows direct interface

to mouse/trackball IR sensors.

DD

R//RL (input). This pin, when connected to GND, disables

the internal ROM and forces the device to function as a

ROMless Z8. (Note that, when left unconnected or pulled

high to V , the part functions normally as a Z8 ROM ver-

sion.)

An optional 200 kOhms pull-up is available as a mask op-

tion on all Port 0 bits with nibble select.

CC

Note: Internal pull-ups are disabled on any given pin or

group of port pins when programmed into output mode.

18

P R E L I M I N A R Y

DS96LV00800

Z86L88/81/86/87/89/73

IR/Low-Voltage Microcontroller

1

4

Port 0 (I/O or A15 - A8)

Z86LXX

MCU

Optional

Handshake Controls

/DAV0 and RDY0

(P32 and P35)

Mask

Option

OEN

200 kΩ

PAD

Out

In

* Mask Selectable

0.4 VDD

Trip Point Buffer

Refer to the Z86C17 specification for

application information in utilizing these

inputs in a mouse or trackball application.

Figure 13. Port 0 Conﬁguration

DS96LV00800

P R E L I M I N A R Y

19

Z86L88/81/86/87/89/73

IR/Low-Voltage Microcontroller

PIN FUNCTIONS (Continued)

Port 1 (P17-P10). Port 1 is a multiplexed Address (A7-A0)

port (Figure 14). If more than 256 external locations are re-

quired, Port 0 outputs the additional lines.

and Data (D7-D0), CMOS compatible port. Port 1 is dedi-

®

cated to the Zilog ZBus -compatible memory interface.

Port 1 can be placed in the high-impedance state along

with Port 0, /AS, /DS, and R//W, allowing the Z86LXX to

share common resources in multiprocessor and DMA ap-

plications. Port1 can also be configured for standard port

output mode..

The operations of Port 1 are supported by the Address

Strobe (/AS) and Data Strobe (/DS) lines, and by the

Read/Write (R//W) and Data Memory (/DM) control lines.

Data memory read/write operations are done through this

Port 1

(I/O or AD7 - AD0)

8

Z86LXX

MCU

Optional

Handshake Controls

/DAV1 and RDY1

(P33 and P34)

OEN

PAD

Out

In

Auto Latch

R ≈ 500 KΩ

Figure 14. Port 1 Conﬁguration

P R E L I M I N A R Y

20

DS96LV00800

Z86L88/81/86/87/89/73

IR/Low-Voltage Microcontroller

Port 2 (P27-P20). Port 2 is an 8-bit, bidirectional, CMOS

compatible I/O port. These eight I/O lines can be indepen-

dently configured under software control as inputs or out-

puts. Port 2 is always available for I/O operation. A mask

option is available to connect eight 200 kOhms (±50%)

pull-up resistors on this port. Bits programmed as outputs

are globally programmed as either push-pull or open-

drain. Port 2 may be placed under handshake control. In

this configuration, Port 3 lines, P31 and P36 are used as

the handshake controls lines /DAV2 and RDY2. The hand-

shake signal assignment for Port 3, lines P31 and P36 is

dictated by the direction (input or output) assigned to Bit 7,

Port 2 (Figure 15). The CCP POR resets with the eight bits

of Port 2 configured as inputs with open-drain outputs.

1

Port 2 also has an 8-bit input OR and an AND gate which

can be used to wake up the part (Figure 41). P20 can be

programmed to access the edge selection circuitry (Figure

24).

Port 2 (I/O)

Z86LXX

MCU

Optional

Handshake Controls

/DAV2 and RDY2

(P31 and P36)

VCC

Open-Drain

OEN

200 kΩ

Mask

Option

PAD

Out

In

Figure 15. Port 2 Conﬁguration

DS96LV00800

P R E L I M I N A R Y

21

Z86L88/81/86/87/89/73

IR/Low-Voltage Microcontroller

PIN FUNCTIONS (Continued)

Port 3 (P37-P31). Port 3 is a 7-bit, CMOS compatible three

fixed input and four fixed output port. Port 3 consists of

three fixed input (P33-P31) and four fixed output (P37-

P34), and can be configured under software control for In-

put/Output, Interrupt, Port handshake, Data Memory func-

tions and output from the counter/timers. P31, P32, and

P33 are standard CMOS inputs; outputs are push-pull.

ence voltage inputs. Access to the Counter Timer edge de-

tection circuit is through P31 or P20 (see CTR1

description). Other edge detect and IRQ modes are de-

scribed in Tables (3-6). Handshake lines Ports 0, 1, and 2

are available on P31 through P36.

Port 3 provides the following control functions: handshake

for Ports 0, 1, and 2 (/DAV and RDY); three external inter-

rupt request signals (IRQ2-IRQ0); Data Memory Select

(/DM) (Table 3).

Two on-board comparators process analog signals on P31

and P32 with reference to the voltage on Pref1 and P33.

The analog function is enabled by programming the Port 3

Mode Register (bit 1). P31 and P32 are programmable as

rising, falling, or both edge triggered interrupts (IRQ regis-

ter bits 6 and 7). Pref1 and P33 are the comparator refer-

Port 3 also provides output for each of the counter/timers

and the AND/OR Logic. Control is performed by program-

ming bits D5-D4 of CTR1, bit 0 of CTR0 and bit 0 of CTR2.

Table 3. Pin Assignments

I/O

C/T

Comp.

Int.

P0 HS

P1 HS

P2 HS

Ext

Pref1

P31

P32

P33

P34

P35

P36

P37

P20

IN

RF1

AN1

AN2

RF2

AO1

IN

IRQ2

IRQ0

IRQ1

D/R

IN

D/R

R/D

IN

D/R

R/D

OUT

I/O

T8

T16

DM

T8/16

R/D

AO2

IN

Notes:

D = /DAV

R = RDY

HS = Handshake Signals

Comparator Inputs. In Analog Mode, Port 3 (P31 and

P32) have a comparator front end. The comparator refer-

ence is supplied to P33 and Pref1. In this mode, the P33

internal data latch and its corresponding IRQ1 is diverted

to the SMR sources (excluding P31,P32, and P33) as

shown in figure 41. In digital mode, P33 is used as D3 of

the Port 3 input register which then generates IRQ1 as

shown in Figure 17.

Comparator Outputs. These may be programmed to be

outputted on P34 and P37 through the PCON register (Fig-

ures 16,38).

/RESET (Input, active Low). Initializes the MCU. Reset is

accomplished either through Power-On, Watch-Dog Tim-

er, Stop-Mode Recovery, Low Voltage detection, or exter-

nal reset. During Power-On Reset and Watch-Dog Timer

Reset, the internally generated reset drives the reset pin

Low for the POR time. Any devices driving the external re-

set line should be open-drain in order to avoid damage

from a possible conflict during reset conditions. Pull-up is

provided internally.

When P31 is used for counter timer input (demodulation

mode), input is always taken from the P31 digital input

buffer whether or not analog mode is enabled).

Notes: Comparators are powered down by entering STOP

mode. For P31-P33 to be used in a Stop-Mode Recovery

source, these inputs must be placed into digital mode.

22

P R E L I M I N A R Y

DS96LV00800

Z86L88/81/86/87/89/73

IR/Low-Voltage Microcontroller

P34

PAD

Counter/Timer

1

T8

P34 OUT

Comp1

P31

+

-

CTR0

Pref1

0 Normal Control

1 8-bit Timer output active

D0

P37

PAD

P37 OUT

Comp2

P32

+

-

P33 (Pref2)

PCON

0 = P34, P37 Standard Output *

1 = P34, P37 Comparator Output

D0

Reset condition.

*

Figure 16. Port 3 Conﬁguration

DS96LV00800

P R E L I M I N A R Y

23

Z86L88/81/86/87/89/73

IR/Low-Voltage Microcontroller

PIN FUNCTIONS (Continued)

After the POR time, /RESET is a Schmitt-triggered input.

To avoid asynchronous and noisy reset problems, the

Z86LXX is equipped with a reset filter of four external

clocks (4TpC). If the external reset signal is less than 4TpC

in duration, no reset occurs. On the fifth clock after the re-

set is detected, an internal RST signal is latched and held

for an internal register count of 18 external clocks, or for

the duration of the external reset, whichever is longer.

During the reset cycle, /DS is held active Low while /AS cy-

cles at a rate of TpC/2. Program execution begins at loca-

tion 000CH, 5-10 TpC cycles after the RST is released. For

Power-On Reset, the typical reset output time is 5 ms. The

Z86LXX does not reset WDTMR, SMR, P2M, or P3M reg-

isters on a Stop-Mode Recovery operation. The output

states of Port3 and Port2 are also un-affected by a Stop-

Mode recovery.

Pref1

200 KΩ

P31

P32

Mask

Option

P33

Port 3

(I/O or Handshake)

Z86L7X

MCU

P34

P35

P36

P37

Note:

P31, 32, 33 have a 200 KΩ

mask option

R247 = P3M

1 = Analog

0 = Digital

D1

DIG.

P31 (AN1)

Comp1

IRQ2, P31 Data Latch

+

AN.

Pref

-

P32 (AN2)

IRQ0, P32 Data Latch

IRQ1, P33 Data Latch

Comp2

+

P33 (REF2)

-

From Stop-Mode

Recovery Source of SMR

Figure 17. Port 3 Conﬁguration

P R E L I M I N A R Y

24

DS96LV00800

Z86L88/81/86/87/89/73

IR/Low-Voltage Microcontroller

1

CTR0, D0

MUX

VDD

Out 34

T8_Out

Pad

P34

CTR2, D0

MUX

Out 35

Pad

P35

T16_Out

CTR1, D6

MUX

Out 36

Pad

P36

T8/16_Out

Figure 18. Port 3 Counter Timer Output Conﬁguration

DS96LV00800

P R E L I M I N A R Y

25

Z86L88/81/86/87/89/73

IR/Low-Voltage Microcontroller

FUNCTIONAL DESCRIPTION

The Z86LXX family of IR CCP incorporates special func-

tions to enhance the Z8's functionality in consumer and

battery operated applications.

65535

32,768

0

Program Memory. The Z86LXX family addresses

16/24/32 Kbytes of internal program memory. The first

twelve bytes are reserved for interrupt vectors. These lo-

cations contain the five 16-bit vectors which correspond to

the five available interrupts. In all cases, at addresses 32K

and greater, external program memory fetches will be ex-

ecuted (provided proper A/D port mode register settings).

Refer to external memory timing specifications. In Rom-

less mode, program memory fetches begin at address

000Ch and data memory fetches begin at address 0000h.

External

Data

Memory

RAM. The Z86LXX devices all have 256 bytes of RAM

which make up the Register file.

External ROM

32768

Location of

First Byte of

On-Chip

Instruction

ROM

Executed

After RESET

Not Addressable

Reset Start Address

12

11

10

9

Reserved

IRQ4

8

7

IRQ4

Figure 20. External Memory Map

IRQ3

Interrupt

Vector

(Lower Byte)

External Memory (/DM). The Z86LXX addresses up to 32

Kbytes of external memory beginning at address 32768

(Figure 20). External data memory is included with, or sep-

arated from, the external program memory space. /DM, an

optional I/O function that is programmed to appear on P34,

is used to distinguish between data and program memory

space. The state of the /DM signal is controlled by the type

of instruction being executed. An LDC opcode references

PROGRAM (/DM inactive) memory, and an LDE instruc-

tion references data (/DM active Low) memory.

6

5

IRQ3

IRQ2

4

3

IRQ2

Interrupt

Vector

(Upper Byte)

IRQ1

2

1

IRQ1

IRQ0

0

IRQ0

Figure 19. Program Memory Map(32K ROM)

26

P R E L I M I N A R Y

DS96LV00800

Z86L88/81/86/87/89/73

IR/Low-Voltage Microcontroller

Expanded Register File. The register file has been ex-

panded to allow for additional system control registers,

and for mapping of additional peripheral devices into the

register address area. The Z8 register address space R0

through R15 has been implemented as 16 banks of 16 reg-

isters per bank. These register groups are known as the

ERF (Expanded Register File). Bits 7-4 of register RP se-

lect the working register group. Bits 3-0 of register RP se-

lect the expanded register file bank. Note that expanded

register bank is also referred to as expanded register

group (Figure 21).

For example:

Z86L73: (See Figure 21)

1

R253 RP = 00h

R0 = Port 0

R1 = Port 1

R2 = Port 2

R3 = Port 3

But if:

R253 RP = 0Dh

R0 = CTRL0

R1 = CTRL1

R2 = CTRL2

R3 = Reserved

The upper nibble of the register pointer (Figure 23) selects

which working register group of 16 bytes in the register file,

out of the possible 256, will be accessed. The lower nibble

selects the expanded register file bank and, in the case of

the Z86LXX family, banks 0, F, and D are implemented. A

0h in the lower nibble will allow the normal register file

(bank 0) to be addressed, but any other value from 1h to

Fh will exchange the lower 16 registers to an expanded

register bank.

The counter/timers are mapped into ERF group D. Access

is easily done using the following example:

LD RP, #0Dh Select ERF D for access to bank D ( work-

ing register group 0)

LD R0,#xx

LD 1, #xx

LD R1, 2

load CTRL0

load CTRL1

CTRL2 → CTRL1

LD RP, #7Dh Select expanded register bank D and

working register group 7 of bank 0 for access .

LD 71h, 2

LD R1, 2

CTRL2 → register 71h

DS96LV00800

P R E L I M I N A R Y

27

Z86L88/81/86/87/89/73

IR/Low-Voltage Microcontroller

Z8^®STANDARD CONTROL REGISTERS

RESET CONDITION

D7 D6

D3 D2 D1

D0

D5 D4

REGISTER**

FF

REGISTER POINTER

7

SPL

SPH

RP

U

0

U

0

U

0

U

0

U

0

U

0

6

5

4

3

2

1

0

FE

FD

FC

FB

FA

F9

F8

F7

F6

F5

F4

F3

F2

F1

F0

0

U

0

U

0

Expanded Register

Bank/Group Pointer

Working Register

Group Pointer

U

0

U

0

U

0

U

0

U

0

FLAGS

IMR

U

0

IRQ

0

IPR

U

0

U

1

U

0

U

0

U

1

U

1

U

0

U

1

P01M

P3M

P2M

0

1

0

1

0

1

0

*

1

U

0

U

0

U

0

U

0

U

0

U

0

U

0

U

0

Reserved

Z8 Register File (Bank0) **

FF

FO

Reserved

0

U

0

U

EXPANDED REG. BANK/GROUP (F)

REGISTER**

RESET CONDITION

(F) 0F

1

0

1

U

0

WDTMR

U

0

1

0

*

(F) 0E

(F) 0D

(F) 0C

(F) 0B

(F) 0A

(F) 09

(F) 08

(F) 07

(F) 06

(F) 05

(F) 04

(F) 03

(F) 02

Reserved

7F

Reserved

0

SMR2

U

0

U

Reserved

SMR

0

1

0

†

Reserved

0F

00

Reserved

PCON

(F) 01

(F) 00

U

0

U

*

EXPANDED REG. BANK/GROUP (D)

REGISTER**

RESET CONDITION

EXPANDED REG. GROUP (0)

(D) 0C

(D) 0B

(D) 0A

Reserved

HI8

REGISTER**

RESET CONDITION

U

(0) 03

P3

0

U

0

U

*

L08

U

(0) 02

P2

U

(D) 09

(D) 08

(D) 07

HI16

L016

U

(0) 01

(0) 00

P1

P0

U

TC16H

U

(D) 06

(D) 05

TC16L

TC8H

U

U = Unknown

U

* Will not be reset with a Stop-Mode Recovery

** All addresses are in Hexadecimal

(D) 04

(D) 03

(D) 02

TC8L

Reserved

CTR2

†^{Will not be reset with a Stop-Mode Recovery, except Bit 0.}

0

U

0

U

0

U

(D) 01

(D) 00

CTR1

CTR0

U

0

Figure 21. Expanded Register File Architecture

P R E L I M I N A R Y

28

DS96LV00800

Z86L88/81/86/87/89/73

IR/Low-Voltage Microcontroller

Note: When SPH is used as a general-purpose register

and Port 0 is in address mode, the contents of SPH will be

loaded into Port 0 whenever the internal stack is accessed.

R253 RP

D7 D6 D5 D4 D3 D2 D1 D0

1

Expanded Register

File Pointer

Working Register

Pointer

r

R253

7

6

5

4

3

2

1

0

Default Setting After Reset = 0000 0000

The upper nibble of the register file address

provided by the register pointer specifies

the active working-register group

Figure 22. Register Pointer Register

7F

Register File. The register file (bank 0) consists of four I/O

port registers, 236 general-purpose registers, and 16 con-

trol and status registers (R0-R3, R4-R239, and R240-

R255, respectively), Plus two expanded registers groups

(Banks D and F). Instructions can access registers directly

or indirectly through an 8-bit address field. This allows a

short, 4-bit register address using the Register Pointer

(Figure 23). In the 4-bit mode, the register file is divided

into 16 working register groups, each occupying 16 contin-

uous locations. The Register Pointer addresses the start-

ing location of the active working register group.

70

6F

60

5F

50

4F

The lower nibble

of the register

file address

provided by the

instruction points

to the specified

register

40

3F

Specified Working

Register Group

30

2F

Note: Working register group E0-EF can only be access-

ed through working registers and indirect addressing

modes.

20

1F

Register Group 1

R15 to R0

10

0F

Stack. The Z86LXX external data memory or the internal

register file is used for the stack. An 8-bit Stack Pointer

(R255) is used for the internal stack that resides in the gen-

eral-purpose registers (R4-R239). SPH is used as a gen-

eral-purpose register only when using internal stacks.

Register Group 0

I/O Ports

R15 to R4 *

R3 to R0 *

00

Figure 23. Register Pointer

COUNTER/TIMER REGISTER DESCRIPTION

Table 4. Expanded Register Group D

Register Description

(D)%0C

(D)%0B

(D)%0A

(D)%09

(D)%08

(D)%07

(D)%06

(D)%05

(D)%04

(D)%03

(D)%02

(D)%01

(D)%00

Reserved

HI8

HI8(D)%0B: Holds the captured data from the output of the

8-bit Counter/Timer0. This register is typically used to hold

the number of counts when the input signal is 1.

LO8

HI16

Field

Bit Position

Description

LO16

T8_Capture_HI 76543210

R

W

Captured Data

No Effect

TC16H

TC16L

TC8H

TC8L

L08(D)%0A: Holds the captured data from the output of

the 8-bit Counter/Timer0. This register is typically used to

hold the number of counts when the input signal is 0.

Reserved

CTR2

CTR1

CTR0

Field

Bit Position

Description

T8_Capture_L0

76543210

R

Captured Data

No Effect

W

DS96LV00800

P R E L I M I N A R Y

29

Z86L88/81/86/87/89/73

IR/Low-Voltage Microcontroller

HI16(D)%09: Holds the captured data from the output of

the 16-bit Counter/Timer16. This register holds the MS-

Byte of the data.

TC16L(D)%06: Counter/Timer2 LS-Byte Hold Register.

Field

Bit Position

Description

T16_Data_LO76543210

R/W

Data

Field

Bit Position

Description

T16_Capture_HI 76543210

R

Captured Data

No Effect

TC8H(D)%05: Counter/Timer8 High Hold Register.

W

Field

Bit Position

Description

R/W Data

T8_Level_HI

76543210

L016(D)%08: Holds the captured data from the output of

the 16-bit Counter/Timer16. This register holds the LS-

Byte of the data.

TC8L(D)%04: Counter/Timer8 Low Hold Register.

Field

Bit Position

Description

Field

Bit Position

Description

T8_Level_LO 76543210

R/W

Data

T16_Capture_L 76543210

O

R

W

Captured Data

No Effect

TC16H(D)%07: Counter/Timer2 MS-Byte Hold Register.

Field

Bit Position

Description

T16_Data_HI 76543210

R/W

Data

30

P R E L I M I N A R Y

DS96LV00800

Z86L88/81/86/87/89/73

IR/Low-Voltage Microcontroller

CTR0 (D)00: Counter/Timer8 Control Register.

Field

T8_Enable

Bit Position

7-------

Value

Description

1

R

0*

1

0

Counter Disabled

Counter Enabled

Stop Counter

W

1

Enable Counter

Single/Modulo-N

Time_Out

-6-------

--5------

R/W

0

1

Modulo-N

Single Pass

R

0

1

0

1

No Counter Time-Out

Counter Time-Out Occurred

No Effect

W

Reset Flag to 0

T8 _Clock

---43---

R/W

0 0

0 1

1 0

1 1

SCLK

SCLK/2

SCLK/4

SCLK/8

Capture_INT_MASK

Counter_INT_Mask

P34_Out

-----2--

------1-

-------0

R/W

0

1

Disable Data Capture Int.

Enable Data Capture Int.

0

1

Disable Time-Out Int.

Enable Time-Out Int.

0*

1

P34 as Port Output

T8 Output on P34

Note: * Indicates the value upon Power-On Reset.

CTR0: Counter/Timer8 Control Register Description

T8 Clock. Defines the frequency of the input signal to T8.

T8 Enable. This field enables T8 when set (written) to 1.

Capture_INT_Mask. Set this bit to allow interrupt when

data is captured into either LO8 or HI8 upon a positive or

negative edge detection in demodulation mode.

Single/Modulo-N. When set to 0 (modulo-n), the counter

reloads the initial value when the terminal count is

reached. When set to 1 (single pass), the counter stops

when the terminal count is reached.

Counter_INT_Mask. Set this bit to allow interrupt when T8

has a time out.

Time-Out. This bit is set when T8 times out (terminal count

reached). To reset this bit, a 1 should be written to this lo-

cation. This is the only way to reset this status condi-

tion, therefore, care should be taken to reset this bit

prior to using/enabling the counter/timers.

P34_Out. This bit defines whether P34 is used as a normal

output pin or the T8 output.

Note: Care must be taken when utilizing the OR or AND

commands to manipulate CTR0, bit 5 and CTR1, bits 0

and 1 (Demodulation Mode). These instructions use a

Read-Modify-Write sequence in which the current status

from the CTR0 and CTR1 registers will be ORed or ANDed

with the designated value and then written back into the

registers. Example: When the status of bit 5 is 1, a timer

reset condition will occur.

DS96LV00800

P R E L I M I N A R Y

31

Z86L88/81/86/87/89/73

IR/Low-Voltage Microcontroller

CTR1(D)%01: Controls the functions in common with the T8 and T16.

Field

Bit Position

7-------

Value

Description

Transmit Mode

Demodulation Mode

Mode

R/W

0*

P36_Out/Demodulator

_Input

-6------

--54----

Transmit Mode

Port Output

T8/T16 Output

Demodulation Mode

P31

0*

1

0

1

P20

T8/T16_Logic/

Edge _Detect

R/W

Transmit Mode

AND

OR

NOR

NAND

00

01

10

11

Demodulation Mode

Falling Edge

Rising Edge

Both Edges

Reserved

00

01

10

11

Transmit_Submode/

Glitch_Filter

----32--

R/W

Transmit Mode

Normal Operation

Ping-Pong Mode

T16_Out = 0

00

01

10

11

T16_Out = 1

Demodulation Mode

No Filter

4 SCLK Cycle

8 SCLK Cycle

16 SCLK Cycle

00

01

10

11

Initial_T8_Out/

Rising Edge

------1-

-------0

Transmit Mode

R/W

0

1

T8_OUT is 0 Initially

T8_OUT is 1 Initially

Demodulation Mode

No Rising Edge

Rising Edge Detected

No Effect

R

0

1

0

1

W

Reset Flag to 0

Initial_T16_Out/

Falling_Edge

Transmit Mode

R/W

0

1

T16_OUT is 0 Initially

T16_OUT is 1 Initially

Demodulation Mode

No Falling Edge

Falling Edge Detected

No Effect

R

0

1

0

1

W

Reset Flag to 0

Note: *Default upon Power-On Reset

32

P R E L I M I N A R Y

DS96LV00800

Z86L88/81/86/87/89/73

IR/Low-Voltage Microcontroller

CTR1 Register Description

Initial_T8_Out/Rising_Edge. In Transmit Mode, if 0, the

output of T8 is set to 0 when it starts to count. If 1, the out-

put of T8 is set to 1 when it starts to count. When The

counter is not enabled and this bit is set to 1 or 0, T8_OUT

will be set to the opposite state of this bit. This insures that

when the clock is enabled a transition occurs to the initial

state set by CTR1, D1.

Mode. If it is 0, the Counter/Timers are in the transmit

mode, otherwise they are in the demodulation mode.

1

P36_Out/Demodulator_Input. In Transmit Mode, this bit

defines whether P36 is used as a normal output pin or the

combined output of T8 and T16.

In Demodulation Mode, this bit is set to 1 when a rising

edge is detected in the input signal. In order to reset it, a 1

should be written to this location.

In Demodulation Mode, this bit defines whether the input

signal to the Counter/Timers is from P20 or P31.

T8/T16_Logic/Edge _Detect. In Transmit Mode, this field

defines how the outputs of T8 and T16 are combined

(AND, OR, NOR, NAND).

Initial_T16 Out/Falling _Edge. In Transmit Mode, if it is 0,

the output of T16 is set to 0 when it starts to count. If it is

1, the output of T16 is set to 1 when it starts to count. This

bit is effective only in Normal or Ping-Pong Mode (CTR1,

D3, D2). When the counter is not enabled and this bit is

set, T16_OUT will be set to the opposite state of this bit.

This insures that when the clock is enabled a transition oc-

curs to the initial state set by CTR1, D0.

In Demodulation Mode, this field defines which edge

should be detected by the edge detector.

Transmit_Submode/Glitch Filter. In Transmit Mode, this

field defines whether T8 and T16 are in the "Ping-Pong"

mode or in independent normal operation mode. Setting

this field to "Normal Operation Mode" terminates the "Ping-

Pong Mode" operation. When set to 10, T16 is immediate-

ly forced to a 0; a setting of 11 will force T16 to output a 1.

In Demodulation Mode, this bit is set to 1 when a falling

edge is detected in the input signal. In order to reset it, a 1

should be written to this location.

Note: Modifying CTR1, (D1 or D0) while the counters are

enabled will cause un-predictable output from T8/16_OUT.

In Demodulation Mode, this field defines the width of the

glitch that should be filtered out.

DS96LV00800

P R E L I M I N A R Y

33

Z86L88/81/86/87/89/73

IR/Low-Voltage Microcontroller

CTR2 (D)%02: Counter/Timer16 Control Register.

Field

T16_Enable

Bit Position

7-------

Value

Description

Counter Disabled

Counter Enabled

Stop Counter

R

0*

1

0

W

1

Enable Counter

Single/Modulo-N

-6------

R/W

Transmit Mode

0

1

Modulo-N

Single Pass

Demodulation Mode

T16 Recognizes Edge

T16 Does Not Recognize Edge

0

1

Time_Out

--5-----

---43---

R

0

1

0

1

No Counter Time-Out

Counter Time-Out Occurred

No Effect

W

Reset Flag to 0

T16 _Clock

R/W

00

01

10

11

SCLK

SCLK/2

SCLK/4

SCLK/8

Capture_INT_Mask

Counter_INT_Mask

P35_Out

-----2--

------1-

-------0

R/W

0

1

Disable Data Capture Int.

Enable Data Capture Int.

0

Disable Time-Out Int.

Enable Time-Out Int.

0*

1

P35 as Port Output

T16 Output on P35

Note: * Indicates the value upon Power-On Reset.

CTR2 Description

T16_Clock. Defines the frequency of the input signal to

Counter/Timer16.

T16_Enable. This field enables T16 when set to 1.

Capture_INT_Mask. Set this bit to allow interrupt when

data is captured into LO16 and HI16.

Single/Modulo-N. In Transmit Mode, when set to 0, the

counter reloads the initial value when terminal count is

reached. When set to 1, the counter stops when the termi-

nal count is reached.

Counter_INT_Mask. Set this bit to allow interrupt when

T16 times out.

In Demodulation Mode, when set to 0 , T16 captures and

reloads on detection of all the edges; when set to 1, T16

captures and detects on the first edge, but ignores the sub-

sequent edges. For details, see the description of T16 De-

modulation Mode.

P35_Out. This bit defines whether P35 is used as a normal

output pin or T16 output.

Time_Out. This bit is set when T16 times out (terminal

count reached). In order to reset it, a 1 should be written to

this location.

34

P R E L I M I N A R Y

DS96LV00800

Z86L88/81/86/87/89/73

IR/Low-Voltage Microcontroller

SMR2(F)%0D: Stop-Mode Recovery Register 2.

Field

Bit Position

7-------

Value

Description

1

Reserved

0

Reserved (Must be 0)

Recovery Level

-6------

W

0*

1

Low

High

Reserved

Source

--5-----

---432--

0

Reserved (Must be 0)

000*

001

010

011

100

101

110

111

A. POR Only

B. NAND of P23-P20

C. NAND or P27-P20

D. NOR of P33-P31

E. NAND of P33-P31

F. NOR of P33-P31, P00,P07

G. NAND of P33-P31,P00,P07

H. NAND of P33-P31,P22-P20

Reserved

------10

00

Reserved (Must be 0)

Notes:

* Indicates the value upon Power-On Reset

Port pins configured as outputs are ignored as a SMR recovery source.

DS96LV00800

P R E L I M I N A R Y

35

Z86L88/81/86/87/89/73

IR/Low-Voltage Microcontroller

Counter/Timer Functional Blocks

CTR1 D5,D4

P31

Pos Edge

Neg Edge

Glitch

Filter

Edge

Detector

MUX

P20

CTR1 D6

CTR1 D3,D2

Figure 24. Glitch Filter Circuitry

Z8 Data Bus

CTR0 D2

Pos Edge

Neg Edge

IRQ4

HI8

LO8

CTR0 D4, D3

CTR0 D1

T8_OUT

Clock

8-Bit

Counter T8

Clock

SCLK

Select

TC8H

TC8L

Z8 Data Bus

Figure 25. 8-Bit Counter/Timer Circuits

36

P R E L I M I N A R Y

DS96LV00800

Z86L88/81/86/87/89/73

IR/Low-Voltage Microcontroller

Input Circuit

sets the time-out status bit (CTR0 D5) and generates an

interrupt if enabled (CTR0 D1) (Figure 27). This completes

one cycle. T8 then loads from TC8H or TC8L according to

the T8_OUT level, and repeats the cycle.

The edge detector monitors the input signal on P31 or P20.

Based on CTR1 D5-D4, a pulse is generated at the Pos

Edge or Neg Edge line when an edge is detected. Glitches

in the input signal which have a width less than specified

(CTR1 D3, D2) are filtered out.

1

The user can modify the values in TC8H or TC8L at any

time. The new values take effect when they are loaded.

Care must be taken not to write these registers at the time

the values are to be loaded into the counter/timer, to en-

sure known operation. An initial count of 1 is not al-

lowed (a non-function will occur). An initial count of 0

will cause TC8 to count from 0 to %FF to %FE (Note, % is

used for hexadecimal values). Transition from 0 to %FF is

not a time-out condition.

T8 Transmit Mode

Before T8 is enabled, the output of T8 depends on CTR1,

D1. If it is 0, T8_OUT is 1. If it is 1, T8_OUT is 0.

When T8 is enabled, the output T8_OUT switches to the

initial value (CTR1 D1). If the initial value (CTR1 D1) is 0,

TC8L is loaded, otherwise TC8H is loaded into the

counter. In Single-Pass Mode (CTR0 D6), T8 counts down

to 0 and stops, T8_OUT toggles, the time-out status bit

(CTR0 D5) is set, and a time-out interrupt can be generat-

ed if it is enabled (CTR0 D1) (Figure 26). In Modulo-N

Mode, upon reaching terminal count, T8_OUT is toggled,

but no interrupt is generated. Then T8 loads a new count

(if the T8_OUT level now is 0), TC8L is loaded; if it is 1,

TC8H is loaded. T8 counts down to 0, toggles T8_OUT,

Note: Using the same instructions for stopping the

counter/timers and setting the status bits is not rec-

ommended. Two successive commands, first stopping

the counter/timers, then resetting the status bits is neces-

sary. This is required because it takes one counter/timer

clock interval for the initiated event to actually occur.

TC8H Counts

“Counter Enable” Command,

T8_OUT Switches To Its

Initial Value (CTR1 D1)

T8_OUT Toggles,

Time-Out Interrupt

Figure 26. T8_OUT in Single-Pass Mode

T8_OUT Toggles

T8_OUT

TC8L

TC8H

TC8L

TC8H

TC8L

“Counter Enable” Command,

T8_OUT Switches To Its

Initial Value (CTR1 D1)

Time-Out Interrupt

Figure 27. T8_OUT in Modulo-N Mode

DS96LV00800

P R E L I M I N A R Y

37

Z86L88/81/86/87/89/73

IR/Low-Voltage Microcontroller

T8 Demodulation Mode

put into LO8, if negative edge, HI8. One of the edge detect

status bits (CTR1 D1, D0) is set, and an interrupt can be

generated if enabled (CTR0 D2). Meanwhile, T8 is loaded

with %FF and starts counting again. Should T8 reach 0,

the time-out status bit (CTR0 D5) is set, an interrupt can be

generated if enabled (CTR0 D1), and T8 continues count-

ing from %FF (Figure 28).

The user should program TC8L and TC8H to %FF. After

T8 is enabled, when the first edge (rising, falling, or both

depending on CTR1 D5, D4) is detected, it starts to count

down. When a subsequent edge (rising, falling, or both de-

pending on CTR1 D5, D4) is detected during counting, the

current value of T8 is one's complemented and put into

one of the capture registers. If it is a positive edge, data is

T8 (8-Bit)

Count Capture

T8_Enable

(Set By User)

No

Yes

Edge Present

Yes

No

What Kind Of Edge

Neg

Pos

T8 → L08

T8 → HI8

%FF → T8

Figure 28. Demodulation Mode Count Capture Flowchart

38

P R E L I M I N A R Y

DS96LV00800

Z86L88/81/86/87/89/73

IR/Low-Voltage Microcontroller

T8 (8-Bit)

Transmit Mode

1

No

T8_Enable Bit Set

CTR0, D7

Reset T8_Enable Bit

Yes

0

1

CTR1, D1

Value

Load TC8L

Reset T8_OUT

Load TC8H

Set T8_OUT

Set Time-out Status Bit

(CTR0 D5) and Generate

Timeout_Int If Enabled

Enable T8

No

T8_Timeout

Yes

Single Pass

Single Pass?

Modulo-N

1

0

T8_OUT Value

Load TC8L

Reset T8_OUT

Load TC8H

Set T8_OUT

Enable T8

Set Time-out Status Bit

(CTR0 D5) and Generate

Timeout_Int If Enabled

No

T8_Timeout

Yes

Disable T8

Figure 29. Transmit Mode Flowchart

P R E L I M I N A R Y

DS96LV00800

39

Z86L88/81/86/87/89/73

IR/Low-Voltage Microcontroller

T8 (8-Bit)

Demodulation Mode

T8_Enable

CTR0, D7

No

Yes

%FF → TC8

First

Edge Present

No

Yes

Disable T8

Enable TC8

T8_Enable Bit Set

Yes

No

Edge Present

Yes

No

T8 Time Out

Yes

Set Edge Present Status

Bit And Trigger Data

Capture Int. If Enabled

Set Time-out Status

Bit And Trigger Time

Out Int. If Enabled

Continue Counting

Figure 30. Demodulation Mode Flowchart

P R E L I M I N A R Y

40

DS96LV00800

Z86L88/81/86/87/89/73

IR/Low-Voltage Microcontroller

Z8 Data Bus

CTR2 D2

1

Pos Edge

IRQ3

Neg Edge

HI16

LO16

CTR2 D4, D3

SCLK

CTR2 D1

T16_OUT

16-Bit

Counter

T16

Clock

Select

TC16H

TC16L

Z8 Data Bus

Figure 31. 16-Bit Counter/Timer Circuits

T16 Transmit Mode

The user can modify the values in TC16H and TC16L at

any time. The new values take effect when they are load-

ed. Care must be taken not to load these registers at the

time the values are to be loaded into the counter/timer, to

ensure known operation. An initial count of 1 is not al-

lowed. An initial count of 0 will cause T16 to count from 0

to %FF FF to %FFFE. Transition from 0 to %FFFF is not a

time-out condition.

In Normal or Ping-Pong Mode, the output of T16 when not

enabled is dependent on CTR1, D0. If it is a 0, T16_OUT

is a 1; if it is a 1, T16_OUT is 0. The user can force the out-

put of T16 to either a 0 or 1 whether it is enabled or not by

programming CTR1 D3, D2 to a 10 or 11.

When T16 is enabled, TC16H * 256 + TC16L is loaded,

and T16_OUT is switched to its initial value (CTR1 D0).

When T16 counts down to 0, T16_OUT is toggled (in Nor-

mal or Ping-Pong Mode), an interrupt is generated if en-

abled (CTR2 D1), and a status bit (CTR2 D5) is set. Note

that global interrupts will override this function as de-

scribed in the interrupts section. If T16 is in Single-Pass

Mode, it is stopped at this point. If it is in Modulo-N Mode,

it is loaded with TC16H * 256 + TC16L and the counting

continues.

DS96LV00800

P R E L I M I N A R Y

41

Z86L88/81/86/87/89/73

IR/Low-Voltage Microcontroller

TC16H*256+TC16L Counts

“Counter Enable” Command,

T16_OUT Switches To Its

Initial Value (CTR1 D0)

T16_OUT Toggles,

Time-Out Interrupt

Figure 32. T16_OUT in Single-Pass Mode

TC16H*256+TC16L

T16_OUT

TC16H*256+TC16L

“Counter Enable” Command,

T16_OUT Switches To Its

Initial Value (CTR1 D0)

T16_OUT Toggles,

Time-Out Interrupt

T16_OUT Toggles,

Time-Out Interrupt

Figure 33.T16_OUT in Modulo-N Mode

T16 Demodulation Mode

If D6 of CTR2 is 1: T16 ignores the subsequent edges in

the input signal and continues counting down. A time out

of T8 will cause T16 to capture its current value and gen-

erate an interrupt if enabled (CTR2, D2). In this case, T16

does not reload and continues counting. If D6 bit of CTR2

is toggled (by writing a 0 then a 1 to it), T16 will capture and

reload on the next edge (rising, falling, or both depending

on CTR1 D5, D4) but continue to ignore subsequent edg-

es.

The user should program TC16L and TC16H to %FF. After

T16 is enabled, when the first edge (rising, falling, or both

depending on CTR1 D5, D4) is detected, T16 captures

HI16 and LO16, reloads and begins counting.

If D6 of CTR2 is 0: When a subsequent edge (rising, fall-

ing, or both depending on CTR1 D5, D4) is detected during

counting, the current count in T16 is one's complemented

and put into HI16 and LO16. When data is captured, one

of the edge detect status bits (CTR1 D1, D0) is set and an

interrupt is generated if enabled (CTR2 D2). T16 is loaded

with %FFFF and starts again.

This T16 mode is generally used to measure mark times;

the length of an active carrier signal bursts.

Should T16 reach 0, it continues counting from %FFFF;

meanwhile, a status bit (CTR2 D5) is set and an interrupt

time-out can be generated if enabled (CTR2 D1).

This T16 mode is generally used to measure space time;

the length of time between bursts of carrier signal(marks).

42

P R E L I M I N A R Y

DS96LV00800

Z86L88/81/86/87/89/73

IR/Low-Voltage Microcontroller

Ping-Pong Mode

and TC16L is loaded, and T16 starts to count. After T16

reaches the terminal count it stops, T8 is enabled again,

and the whole cycle repeats. Interrupts can be allowed

when T8 or T16 reaches terminal control (CTR0 D1, CTR2

D1). To stop the Ping-Pong operation, write 00 to bits D3

and D2 of CTR1.

This operation mode is only valid in Transmit Mode. T8

and T16 need to be programmed in Single-Pass Mode

(CTR0 D6, CTR2 D6) and Ping-Pong Mode needs to be

programmed in CTR1 D3, D2. The user can begin the op-

eration by enabling either T8 or T16 (CTR0 D7 or CTR2

D7). For example, if T8 is enabled, T8_OUT is set to this

initial value (CTR1 D1). According to T8_OUT's level,

TC8H or TC8L is loaded into T8. After the terminal count

is reached, T8 is disabled and T16 is enabled. T16_OUT

switches to its initial value (CTR1 D0), data from TC16H

1

Note: Enabling Ping-Pong operation while the

counter/timers are running may cause intermittent

counter/timer function. Disable the counter/timers, then

reset the status flags prior to instituting this operation.

Enable

TC8

Time-Out

Enable

Ping-Pong

CTR1 D3,D2

TC16

Time-Out

Figure 34. Ping-Pong Mode

To Initiate Ping-Pong Mode

During Ping-Pong Mode

First, make sure both counter/timers are not running. Then

set T8 into Single-Pass Mode (CTR0 D6), set T16 into Sin-

gle-Pass Mode (CTR2 D6), and set Ping-Pong Mode

(CTR1 D2, D3). These instructions do not have to be in

any particular order. Finally, start Ping-Pong Mode by en-

abling either T8 (CTR0 D7) or T16 (CTR2 D7).

The enable bits of T8 and T16 (CTR0 D7, CTR2 D7) will

be set and cleared alternately by hardware. The time-out

bits (CTR0 D5, CTR2 D5) will be set every time the

counter/timers reach the terminal count.

DS96LV00800

P R E L I M I N A R Y

43

Z86L88/81/86/87/89/73

IR/Low-Voltage Microcontroller

P34_INTERNAL

P36_INTERNAL

P34_EXT

MUX

CTR0 D0

MUX

T8_OUT

P36_EXT

P35_EXT

AND/OR/NOR/NAND

Logic

T16_OUT

MUX

CTR1, D2

CTR1 D6

MUX

CTR1 D5,D4

CTR1 D3

P35_INTERNAL

CTR2 D0

Figure 35. Output Circuit

44

P R E L I M I N A R Y

DS96LV00800

Z86L88/81/86/87/89/73

IR/Low-Voltage Microcontroller

Interrupts. The Z86LXX has five different interrupts. The

interrupts are maskable and prioritized (Figure 36). The

five sources are divided as follows: three sources are

claimed by Port 3 lines P33-P31, the remaining two by the

counter/timers (Table 5). The Interrupt Mask Register glo-

bally or individually enables or disables the five interrupt

requests.

1

IRQ0

IRQ2

IRQ 1, 3, 4

Interrupt

Edge

IRQ Register (D6, D7)

Select

IRQ

IMR

IPR

5

Global

Interrupt

Enable

Interrupt

Request

Priority

Logic

Vector Select

Figure 36. Interrupt Block Diagram

DS96LV00800

P R E L I M I N A R Y

45

Z86L88/81/86/87/89/73

IR/Low-Voltage Microcontroller

Table 5. Interrupt Types, Sources, and Vectors

Vector

Programming bits for the Interrupt Edge Select are located

in the IRQ Register (R250), bits D7 and D6 . The configu-

ration is shown in Table 6.

Name

Source

Location

Comments

Table 6. IRQ Register

IRQ0

/DAV0,

IRQ0

0, 1

External

(P32), Rising

Falling Edge

Triggered

IRQ

Interrupt Edge

D7

D6

IRQ2(P31)

IRQ0 (P32)

IRQ1,

IRQ2

IRQ1

2, 3

4, 5

External

(P33), Falling

Edge Triggered

0

1

0

1

0

1

F

R

F

/DAV2,

IRQ2,

External

R/F

(P31), Rising

Falling Edge

Triggered

TIN

Notes:

F = Falling Edge

R = Rising Edge

In analog mode, the Stop-Mode Recovery sources selected by

the SMR register are connected to the IRQ1 input. Any of the

Stop-Mode Recovery sources for SMR (except P31, P32, and

P33) can be used to generate IRQ1 (falling edge triggered).

IRQ3

IRQ4

T16

T8

6, 7

8, 9

Internal

When more than one interrupt is pending, priorities are re-

solved by a programmable priority encoder controlled by

the Interrupt Priority register. An interrupt machine cycle is

activated when an interrupt request is granted. This dis-

ables all subsequent interrupts, saves the Program

Counter and Status Flags, and then branches to the pro-

gram memory vector location reserved for that interrupt.

All Z86LXX interrupts are vectored through locations in the

program memory. This memory location and the next byte

contain the 16-bit address of the interrupt service routine

for that particular interrupt request. To accommodate

polled interrupt systems, interrupt inputs are masked and

the Interrupt Request register is polled to determine which

of the interrupt requests need service.

Clock. The Z86LXX on-chip oscillator has a high-gain,

parallel-resonant amplifier for connection to a crystal, LC,

ceramic resonator, or any suitable external clock source

(XTAL1 = Input, XTAL2 = Output). The crystal should be

AT cut, 1 MHz to 8 MHz maximum, with a series resistance

(RS) less than or equal to 100 Ohms. The Z86LXX on-chip

oscillator may be driven with a low cost RC network or oth-

er suitable external clock source.

For 32 kHz crystal operation, an external feedback resistor

(Rf) and a serial resistor (Rd) are required. See Figure 37.

The crystal should be connected across XTAL1 and

XTAL2 using the recommended capacitors (capacitance

greater than or equal to 22 pF) from each pin to ground.

The RC oscillator configuration is an external resistor con-

nected from XTAL1 to XTAL2, with a frequency-setting ca-

pacitor from XTAL1 to ground (Figure 37).

An interrupt resulting from AN1 is mapped into IRQ2, and

an interrupt from AN2 is mapped into IRQ0. Interrupts

IRQ2 and IRQ0 may be rising, falling, or both edge trig-

gered, and are programmable by the user. The software

can poll to identify the state of the pin.

46

P R E L I M I N A R Y

DS96LV00800

Z86L88/81/86/87/89/73

IR/Low-Voltage Microcontroller

Power-On Reset (POR). A timer circuit clocked by a ded-

1. Power Fail to Power OK status including Waking up

icated on-board RC oscillator is used for the Power-On Re-

from (V Standby).

LV

set (POR) timer function. The POR time allows V

the oscillator circuit to stabilize before instruction execu-

tion begins.

and

CC

2. Stop-Mode Recovery (if D5 of SMR = 1).

3. WDT Time-Out.

1

The POR timer circuit is a one-shot timer triggered by one

of three conditions:

The POR time is a nominal 5 ms. Bit 5 of the Stop-Mode

Register determines whether the POR timer is bypassed

after Stop-Mode Recovery (typical for external clock, RC,

LC oscillators).

XTAL1

XTAL2

XTAL1

XTAL2

XTAL1

XTAL2

XTAL1

XTAL2

XTAL1

XTAL2

C1

C2

C1

C2

Rf

R

L

C2

Rd

External Clock

Ceramic Resonator or Crystal

C1, C2 = 47 pF TYP *

f = 8 MHz

LC

RC

32 kHz XTAL

C1 = 20 pF, C = 33

pF

C1, C2 = 22 pF

@ 3V VCC (TYP)

Rd = 56 - 470K

Rf =10 M

L = 130 µH *

f = 3 MHz *

C1 = 33 pF *

R = 1K *

* Preliminary value including pin parasitics

Figure 37. Oscillator Conﬁguration

HALT. HALT turns off the internal CPU clock, but not the

XTAL oscillation. The counter/timers and external inter-

rupts IRQ0, IRQ1, IRQ2, IRQ3, and IRQ4 remain active.

The devices are recovered by interrupts, either externally

or internally generated. An interrupt request must be exe-

cuted (enabled) to exit HALT mode. After the interrupt ser-

vice routine, the program continues from the instruction af-

ter the HALT.

STOP. This instruction turns off the internal clock and ex-

ternal crystal oscillation and reduces the standby current

to 10 µA or less. STOP mode is terminated only by a reset,

such as WDT time-out, POR, SMR, or external reset. This

causes the processor to restart the application program at

address 000CH. In order to enter STOP (or HALT) mode,

it is necessary to first flush the instruction pipeline to avoid

suspending execution in mid-instruction. To do this, the

user must execute a NOP (opcode = FFH) immediately be-

fore the appropriate sleep instruction, i.e.,

FF

6F

NOP

STOP

; clear the pipeline

; enter STOP mode

or

FF

7F

NOP

HALT

; clear the pipeline

; enter HALT mode

DS96LV00800

P R E L I M I N A R Y

47

Z86L88/81/86/87/89/73

IR/Low-Voltage Microcontroller

Port Configuration Register (PCON). The PCON regis-

ter configures the comparator output on Port 3. It is locat-

ed in the expanded register file at Bank F, location 00 (Fig-

ure 38).

SMR (F) 0B

D7 D6 D5 D4 D3 D2 D1 D0

SCLK/TCLK Divide-by-16

0

1

OFF **

ON

PCON (FH) 00H

Reserved (Must be 0)

D7 D6 D5 D4 D3 D2 D1 D0

Stop-Mode Recovery Source

000 POR Only*

001 Reserved

010 P31

Comparator Output Port 3

0 P34, P37 Standard Output*

1 P34, P37 Comparator Output

011 P32

100 P33

101 P27

11 0 P2 NOR 0-3

111 P2 NOR 0-7

Reserved (Must be 1)

* Default Setting After Reset

Stop Delay

0

1

OFF

ON *

Stop Recovery Level

Figure 38. Port Conﬁguration Register (PCON)

(Write Only)

0

1

Low

*

High

Stop Flag

0

1

POR*

Comparator Output Port 3 (D0). Bit 0 controls the comparator

used in Port 3. A 1 in this location brings the comparator

outputs to P34 and P37, and a 0 releases the Port to its

standard I/O configuration.

Stop Recovery

* Default Setting After Reset

** Default Setting After Reset and Stop-Mode Recovery

Stop-Mode Recovery Register (SMR). This register se-

lects the clock divide value and determines the mode of

Stop-Mode Recovery (Figure 39). All bits are write only ex-

cept bit 7, which is read only. Bit 7 is a flag bit that is hard-

ware set on the condition of STOP recovery and reset by

a power-on cycle. Bit 6 controls whether a low level or a

high level is required from the recovery source. Bit 5 con-

trols the reset delay after recovery. Bits D2, D3, and D4, or

the SMR register, specify the source of the Stop-Mode Re-

covery signal. Bits D0 determines determines if

SCLK/TCLK are divided by 16 or not. The SMR is located

in Bank F of the Expanded Register Group at address

0BH.

Figure 39. Stop-Mode Recovery Register

OSC

2

÷

SCLK

16

÷

TCLK

SMR, D0

Figure 40. SCLK Circuit

48

P R E L I M I N A R Y

DS96LV00800

Z86L88/81/86/87/89/73

IR/Low-Voltage Microcontroller

SMR D4 D3 D2

SMR2 D4 D3 D2

0

1

VCC

SMR D4 D3 D2

SMR2 D4 D3 D2

0

1

0

1

P20

P23

P31

P32

P33

S1

SMR D4 D3 D2

SMR2 D4 D3 D2

0

1

0

1

0

P20

P27

S2

SMR D4 D3 D2

SMR2 D4 D3 D2

1

0

1

P31

P32

P33

S3

To IRQ1

SMR2 D4 D3 D2

S4

SMR D4 D3 D2

1

0

P31

P32

P33

1

0

1

P27

SMR D4 D3 D2

SMR2 D4 D3 D2

1

0

1

0

1

P31

P32

P33

P00

P07

P20

P23

SMR D4 D3 D2

SMR2 D4 D3 D2

1

0

P31

P32

P33

P00

P07

P20

P27

SMR D6

SMR2 D4 D3 D2

1

P31

P32

P33

P20

P21

P22

To RESET and WDT

Circuitry (Active Low)

SMR2 D6

Figure 41. Stop-Mode Recovery Source

P R E L I M I N A R Y

DS96LV00800

49

Z86L88/81/86/87/89/73

IR/Low-Voltage Microcontroller

SCLK/TCLK Divide-by-16 Select (D0). D0 of the SMR

controls a Divide-by-16 prescaler of SCLK/TCLK. The pur-

pose of this control is to selectively reduce device power

consumption during normal processor execution (SCLK

control) and/or HALT mode (where TCLK sources interrupt

logic). After Stop-Mode Recovery, this bit is set to a 0.

Note: Any Port 2 bit defined as an output will drive the cor-

responding input to the default state to allow the remaining

inputs to control the AND/OR function. Refer to SMR2 reg-

ister for other recover sources.

Stop-Mode Recovery Delay Select (D5). This bit, if low,

disables the 5 ms /RESET delay after Stop-Mode Recov-

ery. The default configuration of this bit is one. If the "fast"

wake up is selected, the Stop-Mode Recovery source

needs to be kept active for at least 5TpC.

Stop-Mode Recovery Source (D2, D3, and D4). These

three bits of the SMR specify the wake up source of the

STOP recovery (Figure 41 and Table 7).

Table 7. Stop-Mode Recovery Source

Operation

Stop-Mode Recovery Edge Select (D6). A 1 in this bit po-

sition indicates that a High level on any one of the recovery

sources wakes the Z86LXX from STOP mode. A 0 indi-

cates Low level recovery. The default is 0 on POR (Figure

36).

SMR:432

Description of Action

D4

D3

D2

0

POR and/or external reset

recovery

Cold or Warm Start (D7). This bit is set by the device

upon entering STOP mode. It is a Read Only Flag bit. A 1

in D7 (warm) indicates that the device will awaken from a

SMR source or a WDT while in STOP mode. A 0 in this bit

(cold) indicates that the device will be reset by a POR,

WDT while not in STOP, or the device awakened from a

low voltage standby mode.

0

1

0

1

0

1

0

1

0

1

0

Reserved

P31 transition

P32 transition

P33 transition

P27 transition

Logical NOR of P20

through P23

Stop-Mode Recovery Register 2 (SMR2). This register

determines the mode of Stop-Mode Recovery for SMR2

Figure 42).

1

Logical NOR of P20

through P27

If SMR2 is used in conjunction with SMR, either of the

specified events will cause a Stop-Mode Recovery.

Note: Port pins configured as outputs are ignored as a

SMR or SMR2 recovery source. For example, if the NAND

or P23-P20 is selected as the recovery source and P20 is

configured as an output then the remaining SMR pins

(P23-P21) form the NAND equation.

50

P R E L I M I N A R Y

DS96LV00800

Z86L88/81/86/87/89/73

IR/Low-Voltage Microcontroller

SMR2 (0F) DH

1

D7 D6 D5 D4 D3 D2 D1 D0

Reserved (Must be 0)

Stop-Mode Recovery Source 2

000 POR only*

001 NAND P20, P21, P22, P23

010 NAND P20, P21, P22, P23, P24, P25, P26, P27

011 NOR P31, P32, P33

100 NAND P31, P32, P33

101 NOR P31, P32, P33, P00, P07

110 NAND P31, P32, P33, P00, P07

111 NAND P31, P32, P33, P20, P21, P22

Reserved

(Must be 0)

Recovery Level

0 Low*

1 High

Reserved (Must be 0)

Note: If used in conjunction with SMR,

either of the two specified events will

cause a Stop-Mode Recovery.

*Default Setting After Reset

Figure 42. Stop-Mode Recovery Register 2

((0F) DH: D2-D4, D6 Write Only)

DS96LV00800

P R E L I M I N A R Y

51

Z86L88/81/86/87/89/73

IR/Low-Voltage Microcontroller

Watch-Dog Timer Mode Register (WDTMR). The WDT

is a retriggerable one-shot timer that resets the Z8 if it

reaches its terminal count. The WDT must initially be en-

abled by executing the WDT instruction and refreshed on

subsequent executions of the WDT instruction. The WDT

circuit is driven by an on-board RC oscillator or external

oscillator from the XTAL1 pin. The WDT instruction affects

the Zero (Z), Sign (S), and Overflow (V) flags.

time-out period. Bit 2 determines whether the WDT is ac-

tive during HALT and Bit 3 determines WDT activity during

STOP. Bits 5 through 7 are reserved (Figure 42). This reg-

ister is accessible only during the first 61 processor cycles

(122 XTAL clocks) from the execution of the first instruc-

tion after Power-On-Reset, Watch-Dog Reset, or a Stop-

Mode Recovery (Figure 43). After this point, the register

cannot be modified by any means, intentional or other-

wise. The WDTMR cannot be read and is located in Bank

F of the Expanded Register Group at address location

0FH. It is organized as follows:

The POR clock source is selected with bit 4 of the WDT

register. Bit 0 and 1 control a tap circuit that determines the

WDTMR (0F) 0F

D7 D6 D5 D4 D3 D2 D1 D0

WDT TAP INT RC OSC External Clock

00

5 ms

10 ms

20 ms

80 ms

256 TpC

512 TpC

1024 TpC

4096 TpC

01 *

10

11

WDT During HALT

0 OFF

1 ON *

WDT During STOP

0 OFF

1 ON *

XTAL1/INT RC Select for WDT

0 On-Board RC

1 XTAL

*

Reserved (Must be 0)

* Default Setting After Reset

Figure 43. Watch-Dog Timer Mode Register

(Write Only)

52

P R E L I M I N A R Y

DS96LV00800

Z86L88/81/86/87/89/73

IR/Low-Voltage Microcontroller

WDT Time Select (D0, D1). Selects the WDT time period.

It is configured as shown in Table 8.

WDTMR During HALT (D2). This bit determines whether

or not the WDT is active during HALT mode. A 1 indicates

active during HALT. The default is 1.

Table 8. WDT Time Select

1

WDTMR During STOP (D3). This bit determines whether

or not the WDT is active during STOP mode. Since the

XTAL clock is stopped during STOP mode, the on-board

RC has to be selected as the clock source to the

WDT/POR counter. A 1 indicates active during STOP. The

default is 1.

Time-Out of

Internal RC OSC

Time-Out of

XTAL Clock

D1

D0

0

1

0

1

5 ms min

10 ms min

20 ms min

80 ms min

256 TpC

512 TpC

1024 TpC

4096 TpC

0

1

Clock Source for WDT (D4). This bit determines which

oscillator source is used to clock the internal POR and

WDT counter chain. If the bit is a 1, the internal RC oscil-

lator is bypassed and the POR and WDT clock source is

driven from the external pin, XTAL1. The default configu-

ration of this bit is 0, which selects the RC oscillator.

Notes:

TpC = XTAL clock cycle.

The default on reset is 10 ms.

/RESET

5 Clock

Filter

* /CLR 2

CLK

18 Clock RESET

RESET

Generator

Internal

RESET

Active

High

WDT TAP SELECT

CK Source

Select

(WDTMR)

POR

CLK

2

3

4

WDT1

XTAL

M

U

X

WDT/POR Counter Chain

*CLR1

INTERNAL

RC

OSC.

Low Operating

Voltage Det.

+

-

VDD

VBO/VLV

2V REF.

VCC

WDT

From Stop

Mode

Recovery

Source

12 ns Glitch Filter

Stop Delay

Select (SMR)

* /CLR1 and /CLR2 enable the WDT/POR and

18 Clock Reset timers upon a Low to High input translation.

Figure 44. Resets and WDT

DS96LV00800

P R E L I M I N A R Y

53

Z86L88/81/86/87/89/73

IR/Low-Voltage Microcontroller

Mask Selectable Options. There are seven Mask Select-

able Options to choose from based on ROM code require-

ments. These are:

1.8

1.6

RAM Protect

On/Off

RC/XTAL

On/Off

On/Of

1.4

1.2

1

VLV

RC/Other

32 kHz XTAL

Port 04-07 Pull-Ups

Port 00-03 Pull-Ups

Port 20-27 Pull-Ups

Port 30-33 Pull-Ups

1.8

0.6

0.4

0.2

On/Of

Port 3 Mouse Mode 0.4 V On/Off

DD

0

Trip

0

45

35

Temperature

55

25

15

Low Voltage Detection/Standby. An on-chip Voltage

Comparator checks that the V is at the required level for

CC

correct operation of the device. Reset is globally driven

when V

falls below V (Vrf1). A small further drop in

Figure 45. Typical Z86LXX Low Voltage vs

Temperature at 8 MHZ

CC

LV

V

causes the XTAL1 and XTAL2 circuitry to stop the

CC

crystal or resonator clock. Typical Low-Voltage power con-

The minimum operating voltage varies with the tempera-

sumpion in this Low Voltage Standby mode (I ) is about

LV

ture and operating frequency, while V varies with tem-

45 µA (varying with the number of Mask selectable options

LV

perature only.

enabled). If the V

is allowed to stay above Vram, the

CC

RAM content is preserved. When the power level is re-

The Low Voltage trip voltage (V ) is less than 2.1V under

the following conditions:

LV

turned to above V , the device will perform a POR and

LV

function normally (Figure 45).

Maximum (V ) Conditions:

LV

T = 0°C, +55°C Internal clock frequency equal to or less

A

than 4.0 MHz

Note: The internal clock frequency is one-half the external

clock frequency.

54

P R E L I M I N A R Y

DS96LV00800

Z86L88/81/86/87/89/73

IR/Low-Voltage Microcontroller

EXPANDED REGISTER FILE CONTROL REGISTERS (0D)

1

CTR0 (0D) 0H

D7 D6 D5 D4 D3 D2 D1 D0

0 P34 as Port Output*

1 Timer8 Output

0 Disable T8 Time Out Interrupt

1 Enable T8 Time Out Interrupt

0 Disable T8 Data Capture Interrupt

1 Enable T8 Data Capture Interrupt

00 SCLK on T8

01 SCLK/2 on T8

10 SCLK/4 on T8

11 SCLK/8 on T8

R 0 No T8 Counter Time Out

R 1 T8 Counter Time Out Occured

W 0 No Effect

W 1 Reset Flag to 0

0 Modulo-N

1 Single Pass

R 0 T8 Disabled *

R 1 T8 Enabled

W 0 Stop T8

W 1 Enable T8

* Default Setting After Reset

Figure 46. TC8 Control Register

((0D) OH: Read/Write Except Where Noted)

DS96LV00800

P R E L I M I N A R Y

55

Z86L88/81/86/87/89/73

IR/Low-Voltage Microcontroller

CTR1 (0D) 1H

D7 D6 D5 D4 D3 D2 D1 D0

Transmit Mode

R/W 0 T16_OUT is 0 Initially

1 T16_OUT is 1 Initially

Demodulation Mode

R

0 No Falling Edge Detection

1 Falling Edge Detection

W

0 No Effect

1 Reset Flag to 0

Transmit Mode

R/W 0 T8_OUT is 0 Initially

1 T8_OUT is 1 Initially

Demodulation Mode

0 No Rising Edge Detection

1 Rising Edge Detection

R

W

0 No Effect

1 Reset Flag to 0

Transmit Mode

0 0 Normal Operation

0 1 Ping-Pong Mode

1 0 T16_OUT = 0

1 1 T16_OUT = 1

Demodulation Mode

0 0 No Filter

0 1 4 SCLK Cycle Filter

1 0 8 SCLK Cycle Filter

1 1 16 SCLK Cycle Filter

Transmit Mode/T8/T16 Logic

0 0 AND

0 1 OR

1 0 NOR

1 1 NAND

Demodulation Mode

0 0 Falling Edge Detection

0 1 Rising Edge Detection

1 0 Both Edge Detection

1 1 Reserved

Transmit Mode

0 P36 as Port Output *

1 P36 as T8/T16_OUT

Demodulation Mode

0 P31 as Demodulator Input

1 P20 as Demodulator Input

Transmit/Demodulation Modes

*Default setting after Reset

0 Transmit Mode *

1 Demodulation Mode

Note: Care must be taken in differentiating

Transmit Mode from Demodulation Mode.

Depending on which of these two modes is

operating, the CTR1 bit will have different

functions.

Note: Changing from one mode to

another cannot be done without

disabling the counter/timers.

56

P R E L I M I N A R Y

DS96LV00800

Z86L88/81/86/87/89/73

IR/Low-Voltage Microcontroller

CTR2 (0D) 02H

1

D7 D6 D5 D4 D3 D2 D1 D0

0 P35 is Port Output*

1 P35 is TC16 Output

0 Disable T16 Time-Out Interrupt

1 Enable T16 Time-Out Interrupt

0 Disable T16 Data Capture Interrupt

1 Enable T16 Data Capture Interrupt

0 0 SCLK on T16

0 1 SCLK/2 on T16

1 0 SCLK/4 on T16

1 1 SCLK/8 on T16

R 0 No T16 Time Out

R 1 T16 Time Out Occurs

W 0 No Effect

W 1 Reset Flag to 0

Transmit Mode

0 Modulo-N for T16

1 Single Pass for T16

Demodulator Mode

0 T16 Recognizes Edge

1 T16 Does Not Recognize Edge

R 0 T16 Disabled *

R 1 T16 Enabled

W 0 Stop T16

* Default Setting After Reset

W 1 Enable T16

Figure 48. T16 Control Register

((0D) 2H: Read/Write Except Where Noted)

DS96LV00800

P R E L I M I N A R Y

57

Z86L88/81/86/87/89/73

IR/Low-Voltage Microcontroller

EXPANDED REGISTER FILE CONTROL REGISTERS (0F)

SMR (0F) 0B

D7 D6 D5 D4 D3 D2 D1 D0

SCLK/TCLK Divide-by-16

0 OFF **

1 ON

Reserved (Must be 0)

Stop-Mode Recovery Source

000 POR Only*

001 Reserved

010 P31

011 P32

100 P33

101 P27

11 0 P2 NOR 0-3

111 P2 NOR 0-7

Stop Delay

0 OFF

1 ON *

Stop Recovery Level

0 Low

*

1 High

Stop Flag

0 POR*

1 Stop Recovery * *

* Default Setting After Reset

** Default Setting After Reset and Stop-Mode Recovery

Figure 49. Stop-Mode Recovery Register

((0F) 0BH: D6-D0 = Write Only, D7 = Read Only)

58

P R E L I M I N A R Y

DS96LV00800

Z86L88/81/86/87/89/73

IR/Low-Voltage Microcontroller

SMR2 (0F) 0DH

1

D7 D6 D5 D4 D3 D2 D1 D0

Reserved (Must be 0)

Stop-Mode Recovery Source 2

000 POR only*

001 NAND P20, P21, P22, P23

010 NAND P20, P21, P22, P23, P24, P25, P26, P27

011 NOR P31, P32, P33

100 NAND P31, P32, P33

101 NOR P31, P32, P33, P00, P07

110 NAND P31, P32, P33, P00, P07

111 NAND P31, P32, P33, P20, P21, P22

Reserved

(Must be 0)

Recovery Level

0 Low*

1 High

Reserved (Must be 0)

Note: If used in conjunction with SMR,

either of the two specified events will

cause a Stop-Mode Recovery.

*Default Setting After Reset

Figure 50. Stop-Mode Recovery Register 2

((0F) 0DH: D2-D4, D6 Write Only)

DS96LV00800

P R E L I M I N A R Y

59

Z86L88/81/86/87/89/73

IR/Low-Voltage Microcontroller

WDTMR (0F) 0F

D7 D6 D5 D4 D3 D2 D1 D0

WDT TAP INT RC OSC External Clock

00

5 ms

10 ms

20 ms

80 ms

256 TpC

512 TpC

1024 TpC

4096 TpC

01 *

10

11

WDT During HALT

0 OFF

1 ON *

WDT During STOP

0 OFF

1 ON *

XTAL1/INT RC Select for WDT

0 On-Board RC

1 XTAL

*

Reserved (Must be 0)

* Default Setting After Reset

Figure 51. Watch-Dog Timer Register

((0F) 0FH:Write Only)

PCON (FH) 00H

D4

D7 D6 D5

D3 D2 D1 D0

Comparator Output Port 3

0 P34, P37 Standard Output*

1 P34, P37 Comparator Output

Reserved (Must be 1)

* Default Setting After Reset

Figure 52. Port Conﬁguration Register (PCON)

((0F) 0H:Write Only)

60

P R E L I M I N A R Y

DS96LV00800

Z86L88/81/86/87/89/73

IR/Low-Voltage Microcontroller

Z8 STANDARD CONTROL REGISTER DIAGRAMS

R248 P01M

D7 D6 D5 D4 D3 D2 D1 D0

1

R246 P2M

D7 D6 D5 D4 D3 D2 D1 D0

P00-P03 Mode

00 Output

01 Input*

P27-P20 I/O Definition

0

1

Defines Bit as OUTPUT

Defines Bit as INPUT*

1X A11-A8

*Default Setting After Reset

Stack Selection

0

1

External

Internal*

P17-P10 Mode

00 Byte Output

01 Reserved

10 AD7-AD0

Figure 53. Port 2 Mode Register

(F6H:Write Only)

11 High-ImpedanceAD7AD0,

/AS, /DS, /R//W, A11-A8,

A15-A12, If Selected

R247 P3M

D7 D6 D5 D4 D3 D2 D1 D0

External Memory Timing

0

1

Normal*

Extended

P07-P04 Mode

00 Output

01 Input*

0

1

Port 2 Open Drain*

Port 2 Push-pull

1X A15-A12

0 = P31, P32 Digital Mode

1 = P31, P32 Analog Mode

* Default Setting After Reset.

Note: Only P00 and P07 are Available on Z86L71.

0

1

P32 = Input

P35 = Output

P32 = /DAV0/RDY0

P35 = RDY0//DAV0

Figure 55. Port 0 and 1 Mode Register

(F8H:Write Only)

00 P33 = Input

P34 = Output

01 P33 = Input

10 P34 = /DM

P33 = /DAV1/RDY1

P34 = RDY1//DAV1

11

D7 D6 D5 D4 D3 D2 D1 D0

0

1

P31 = Input (TIN)

Interrupt Group Priority

000 Reserved

001 C>A>B

P36 = Output (TOUT)

P31 = /DAV2/RDY2

P36 = RDY2//DAV2

010 A>B>C

011 A>C>B

Reserved (Must be 0)

* Default Setting After Result

100 B>C>A

101 C>B>A

110 B>A>C

111 Reserved

Figure 54. Port 3 Mode Register

(F7H:Write Only)

IRQ1,IRQ4,Priority

(Group C)

0 IRQ1>IRQ4

1 IRQ4>IRQ1

IRQ0,IRQ2

Priority (Group B)

0 IRQ2>IRQ0

1 IRQ0>IRQ2

IRQ3,IRQ5Priority

(Group A)

0 IRQ5>IRQ3

1 IRQ3>IRQ5

Reserved (Must be 0)

Figure 56. Interrupt Priority Registers

((0) F9H:Write Only)

DS96LV00800

P R E L I M I N A R Y

61

Z86L88/81/86/87/89/73

IR/Low-Voltage Microcontroller

R253 RP

R250 IRQ

D7 D6 D5 D4 D3 D2 D1 D0

Expanded Register Bank

Pointer

IRQ0 = P32 Input

IRQ1 = P33 Input

IRQ2 = P31 Input

IRQ3 = T16

Working Register

Pointer

IRQ4 = T8

Default Setting After

Reset = 0000 0000

Inter Edge

P31 ↓ P32 ↓ = 00

P31 ↓ P32 ↑ = 01

P31 ↑ P32 ↓ = 10

P31 ↑↓ P32 ↑↓ = 11

Figure 60. Register Pointer

((0) FDH: Read/Write)

R254 SPH

D7 D6 D5 D4 D3 D2 D1 D0

Figure 57. Interrupt Request Register

((0) FAH: Read/Write)

Stack Pointer Upper

Byte (SP15-SP8)

R251 IMR

D7 D6 D5 D4 D3 D2 D1 D0

Figure 61. Stack Pointer High

((0) FEH: Read/Write)

1

Enables IRQ4-IRQ0

(D0 = IRQ0)

Reserved (Must be 0)

R255 SPL

D7 D6 D5 D4 D3 D2 D1 D0

0

1

Master Interrupt Disable*

Master Interrupt Enable

* Default Setting After Reset

Stack Pointer Lower

Byte (SP7-SP0)

Figure 58. Interrupt Mask Register

((0) FBH: Read/Write)

Figure 62. Stack Pointer Low

((0) FFH: Read/Write)

R252 Flags

D7 D6 D5 D4 D3 D2 D1 D0

User Flag F1

User Flag F2

Half Carry Flag

Decimal Adjust Flag

Overflow Tag

Sign Flag

Zero Flag

Carry Flag

Figure 59. Flag Register

((0) FCH: Read/Write)

62

P R E L I M I N A R Y

DS96LV00800

Z86L88/81/86/87/89/73

IR/Low-Voltage Microcontroller

PACKAGE INFORMATION

1

Figure 63. 28-Pin DIP Package Diagram

Figure 64. 28-Pin SOIC Package Diagram

P R E L I M I N A R Y

DS96LV00800

63

Z86L88/81/86/87/89/73

IR/Low-Voltage Microcontroller

Figure 65. 40-Pin DIP Package Diagram

Figure 66. 44-Pin PLCC Package Diagram

P R E L I M I N A R Y

64

DS96LV00800

Z86L88/81/86/87/89/73

IR/Low-Voltage Microcontroller

1

Figure 67. 44-Pin QFP Package Diagram

DS96LV00800

P R E L I M I N A R Y

65

Z86L88/81/86/87/89/73

IR/Low-Voltage Microcontroller

ORDERING INFORMATION

Z86L88/81/86/87/89/73

Codes

8.0 MHz

28-Pin DIP

Z86L8808PSC

Z86L8108PSC

Z86L8608PSC

Package

40-Pin DIP

P = Plastic DIP

F = Plastic Quad Flat Pack

V = Plastic Chip Carrier

Z86L8708PSC

Z86L8908PSC

Z86L7308PSC

S = SOIC (Small Outline Integrated Circuit)

Temperature

28-Pin SIOC

44-Pin PLCC

Z86L8708VSC

Z86L8908VSC

Z86L7308VSC

44-Pin QFP

Z86L8808SSC

Z86L8108SSC

Z86L8608SSC

Z86L8708FSC

Z86L8908FSC

Z86L7308FSC

S = 0°C to +70°C

Speed

8 = 8.0 MHz

For fast results, contact your local Zilog sales office for as-

sistance in ordering the part desired.

Environmental

C = Plastic Standard

Example:

Z 86LXX 08 P S C

is a Z86LXX, 8 MHz, DIP, 0°C to +70°C, Plastic Standard Flow

Environmental Flow

Temperature

Package

Speed

Product Number

Zilog Prefix

66

P R E L I M I N A R Y

DS96LV00800


型号：	Z86L89
厂家：	ZILOG, INC.
描述：	IR / LOW - VOLTAGE MICROCONTROLLER IR /低 - 电压微控制器微控制器
文件：	总66页 (文件大小：597K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

Z86L89 [ZILOG]

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