Z87010_技术文档

PRELIMINARY PRODUCT SPECIFICATION

2

Z87010/Z87L10

2

AUDIO ENCODER/DECODERS

FEATURES

■ Direct Interface to 8-Bit µ-law Telephone CODEC

■ I/O Bus (16-Bit Tristable Data, 3-Bit Address)

■ Wait State Generator

ROM

(Kbyte)

I/O

Lines

Package

Information

Device

Z87010

4

16

44-Pin PLCC

44-Pin QFP

Z87L10

4

16

44-Pin QFP

■ Two External Interrupts

Hardware

■ Four Separate I/O Pins (2 Input, 2 Output)

■ 16-Bit DSP Processor

Software

■ 3.0V to 3.6V; -20° to +70°C, Z87L10

4.5V to 5.5V, -20° to +70°C, Z87010

■ Full Duplex 32 Kbps ADPCM Encoding/Decoding

■ Single Tone and DTMF Signal Generation

■ Sidetone, Volume Control, Mute Functions

■ Static Architecture

■ 512 Word On-Chip RAM

■ Modified Harvard Architecture

■ Large Phone Number Memory (21 numbers of 23 digits

each)

■ Direct Interface to Z87000 Frequency Hopping

■ Master-Slave Protocol Interface to Z87000 Spreader/-

Spreader/Despreader

Despreader

GENERAL DESCRIPTION

The Z87010/Z87L10 is a second generation CMOS Digital

Signal Processor (DSP) that has been ROM-coded by

Zilog to provide full-duplex 32 Kbps, Adaptive Delta Pulse

Code Modulation (ADPCM) speech coding/decoding (CO-

DEC), and interface to the Z87000/Z87L00 Spread Spec-

trum Cordless Telephone Controller. Together the

Z87000/Z87L00 and Z87010/Z87L10 devices support the

implementation of a 900 MHz frequency-hopping spread

spectrum cordless telephone in conformance with United

States FCC regulations for unlicensed operation.

The Z87010’s single cycle instruction execution and Har-

vard bus structure promote efficient algorithm execution.

The processor contains a 4K word program ROM and 512

word data RAM. Six dual operand fetching. Three vectored

interrupts are complemented by a six level stack. The CO-

DEC interface enables high-speed transfer rate to accom-

modate digital audio and voice data. A dedicated

Counter/Timer provides the necessary timing signals for

the CODEC interface. An additional 13-bit timer is dedicat-

ed for general-purpose use.

The Z87010 and Z87L10 are distinct 5V and 3.3V versions

of the ADPCM Audio Encoder/Decoder. For the sake of

brevity, all subsequent references to the Z87010 in this

document also are applicable to the Z87L10, unless spe-

cifically noted.

The Z87010’s circuitry is optimized to accommodate intri-

cate signal processing algorithms and is used here for

speech compression/decompression, generation of DTMF

tones and other cordless telephone functions. Dedicated

hardware allows direct interface to a variety of CODEC

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Z87010/Z87L10

Audio Encoder/Decoders

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GENERAL DESCRIPTION (Continued)

ICs. As configured by the Zilog-provided embedded soft-

ware for digital cordless phones, the Z87010 supports a

low-cost 8-bit µ-law telephone CODEC. The Z87010 is to

be used with the Z87000 and operates at 16.384 MHz, pro-

viding 16 MIPS of processing power needed for the cord-

less telephone application.

RXD

TXD

SCLK

FS0

Dual

CODEC

256 Word

RAM1

256 Word

RAM0

Interface

EXT 0-15

FS1

/RDYE

16-Bit

I/O

Interface

UO0-1

UI0-1

/RESET

/INT0-2

ER//W

/EI

DSP

Core

EA0-2

VDD

VSS

Power

Wait

State

Generator

4K Words

Program ROM

13-Bit

Timer

Figure 1. Z87010 Functional Block Diagram

Notes: All signals with a preceding front slash, ‘/’, are

active Low, e.g., B//W (WORD is active Low); /B/W (BYTE

is active Low, only).

Power connections follow conventional descriptions be-

low:

Connection

Power

Circuit

Device

V

DD

CC

Ground

GND

V

SS

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P R E L I M I N A R Y

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Z87010/Z87L10

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Zilog

PIN DESCRIPTION

2

6

1

40

39

7

VSS

EXT0

EXT1

EXT2

VSS

EA0

/RESET

WAIT

RD//WR

VDD

Z87010

RXD

SCLK

UI0

UI1

/INT1

/INT2

EXT11

EXT12

EXT13

EXT14

VSS

17

29

28

EXT15

18

Figure 2. 44-Pin PLCC Pin Assignments

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Z87010/Z87L10

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PIN DESCRIPTION (Continued)

Table 1. 44-Pin PLCC Pin Identiﬁcation

Symbol Function

Stop execution

No.

Direction

1

HALT

FS0

Input

2

CODEC0 frame sync

Interrupt

Input/Output*

Input

3

/INT0

UO0-UO1

FS1

4-5

User output

Output

6

CODEC1 frame sync

Ground

Input/Output*

7,11,16,20,27

V

SS

8-10

12

EXT0-EXT2

RXD

External data bus

Serial input from CODECs

External data bus

Serial output to CODECs

External data bus

Interrupt

Input/Output

Input

13-15

17

EXT12-EXT14

EXT15

Input/Output

Output

18-19

21-23

24

EXT3-EXT4

EXT5-EXT7

TXD

25-26

28-29

30

EXT8-EXT9

EXT10-EXT11

/INT2

Input/Output

Input

31

/INT1

Interrupt

Input

32

UI1

User input

Input

33

UI0

User input

Input

34

SCLK

CODEC serial clock

Power supply

Input/Output*

Input

35,42

V

DD

36

37

RD//WR

WAIT

RD /WR strobe for EXT bus

WAIT state

Output

Input

38

/RESET

EA0-EA2

/DS

Reset

Input

39-41

43

External address bus

Data strobe for external bus

Clock

Output

Input

44

CLK

Note: *Defined input or output by interface mode selection

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Z87010/Z87L10

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Zilog

2

33

23

22

VSS

EXT0

EXT1

EXT2

VSS

34

EA0

/RES

/RDYE

ER//W

VDD

RXD

SCLK

UI0

UI1

/INT1

/INT2

EXT11

Z87010

EXT12

EXT13

EXT14

VSS

EXT15

12

11

44

1

Figure 3. 44-Pin QFP Pin Assignments

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Z87010/Z87L10

Audio Encoder/Decoders

Zilog

PIN DESCRIPTION (Continued)

Table 2. 44-Pin QFP Pin Identiﬁcation

Function

No.

Symbol

EXT3-EXT4

Direction

Input/Output

1-2

External data bus

Ground

3,10

V

–

SS

4-6

7

EXT5-EXT7

TXD

External data bus

Serial output to CODECs

External data bus

Interrupt

Input/Output

Output

8-9

11-12

13

EXT8-EXT9

EXT10-EXT11

/INT2

Input/Output

Input

14

/INT1

Interrupt

Input

15

UI1

User input

Input

16

UI0

User input

Input

17

SCLK

CODEC serial clock

Power supply

Input/Output*

Input

18,25

V

DD

19

20

ER//W

/RDYE

/RES

EA0-EA2

/EI

R/W for External Bus

Data Ready

Output

Input

21

Reset

Input

22-24

26

External Address Bus

Data Strobe for External Bus

Clock

Output

Input

27

CK

28

HALT

FS0

Stop Execution

CODEC0 Frame Sync

Interrupt

Input

29

Input/Output*

Input

30

/INT0

U00-U01

FS1

31-32

33

User Output

–

CODEC1 Frame Sync

Ground

Input/Output*

Input

34

V

SS

35-37

38

EXT0-EXT2

External data bus

Ground

Input/Output

Input

V

SS

39

40-42

43

RXD

Serial Input to CODEC

External Data Bus

Ground

Input

EXT12-EXT14

Input/Output

Input

V

SS

44

EXT15

External Data Bus

Input/Output

Note: *Input or output is defined by interface mode selection.

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ABSOLUTE MAXIMUM RATING

Stresses greater than those listed under Absolute Maxi-

mum Ratings may cause permanent damage to the de-

vice. This is a stress rating only; operation of the device at

any condition above those indicated in the operational sec-

tions of these specifications is not implied. Exposure to ab-

solute maximum rating conditions for extended period may

affect device reliability.

Symbol

Description

Supply Voltage

Storage Temp

Min.

Max.

Units

2

V

-0.3

+7.0

V

C

DD

T

-65°C +150°C

-25° +70°

STG

T

Oper. Ambient

Temp

A

Note: *Voltage on all pins with respect to GND.

STANDARD TEST CONDITIONS

The characteristics listed below apply for standard test

conditions as noted. All voltages are referenced to ground.

Positive current flows into the referenced pin (Figure 4).

IoL

Standard test conditions are as follows:

Output

Under

Test

Threshold

Voltage

3.0V ≤ V ≤3.6V (Z87L10)

DD

4.5V ≤ V ≤5.5V (Z87010)

DD

V

= 0V

SS

50pF

T = -20° to +70°C

A

IoH

Figure 4. Test Load Diagram

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DC ELECTRICAL CHARACTERISTICS

V

= 4.5V to 5.5V (Z87010)

DD

T =-20°C to +70°C

A

Symbol

Parameter

Condition

=5.5V

DD

Min

Max

Units

I

Supply Current

V

40

mA

DD

fclock=16.384 MHz

=5.5V

I

DC Power

V

0.2

mA

DC

DD

Consumption

V

Input High Level

Input Low Level

Input Leakage

2.7

V

IH

V

0.8

10

IL

L

I

µA

V

Output High Voltage

Output Low Voltage

I

=-100µA

V

-0.2

OH

DD

V

=2.0 mA

OL

0.5

10

V (1)

µA

OL

FL

I

Output Floating

Leakage Current

Note:

5. The following specifications are pin specific: EA0-2 has I = 5 mA @ 0.5V

OL

6. I = 1 mA @ 3.3V

OH

V

= 3.0V to 3.6V (Z87L10)

DD

T =-20°C to +70°C

A

Symbol

Parameter

Condition

=3.6V

DD

Min

Max

Units

I

Supply Current

V

25

mA

DD

fclock=16.384 MHz

=3.6V

I

DC Power

V

0.2

mA

DC

DD

Consumption

V

Input High Level

Input Low Level

Input Leakage

.7V

V +.3

DD

V

IH

DD

V

Vss-.3

.1V

DD

IL

L

I

10

µA

V

Output High Voltage

Output Low Voltage

I

=-50µA

V

-0.2

OH

DD

V

=1.0 mA

OL

0.5

10

V (1)

µA

OL

FL

I

Output Floating

Leakage Current

Note:

7. The following specifications are pin specific: EA0-2 has I = 5 mA @ 0.5V

OL

8. I = 1 mA @ 3.3V

OH

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P R E L I M I N A R Y

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Z87010/Z87L10

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AC ELECTRICAL CHARACTERISTICS

)

2

T = -20°C to +70°C

A

Symbol

Parameter

Clock Cycle Time

Min (ns)

Max (ns)

TCY

PWW

Tr

50

23

–

Clock Pulse Width

Clock Rise Time

2

Tf

Clock Fall Time

–

2

TEAD

TXVD

TXWH

TXRS

TXRH

TIEDR

TIEDF

RDYS

RDYH

TINS

TINL

THS

EA, ER//W Delay from CK

EXT Data Output Valid from CK

EXT Data Output Hold from CK

EXT Data Input Setup Time

EXT Data Input Hold from CK

/EI Delay Time from CK

5

28

33

25

–

5

3

10

3

25

15

–

0

Ready Setup Time

8

Ready Hold Time

5

–

Int. Setup Time to CLK Fall

Int. Low Pulse Width

3

_

10

3

–

Halt Setup Time to CLK Rise

Halt Hold Time to CLK Rise

–

THH

10

–

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AC TIMING DIAGRAMS

TXWH

TCY

PWW

TXVD

CK

TEAD

TIEDF

TIEDR

/EI

TEAD

EXT Bus:

Output

ER//W

Valid

EXT (15:0)

Data Out

EA (2:0)

/RDYE

Valid Address Out

TEAD

RDYS

RDYH

Figure 5. Write to External Device Timing

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TXRH

TCY

2

PWW

TXRS

CK

/EI

TEAD

TIEDF

TIED

EXT Bus:

Input

ER//W

Valid

EXT (15:0)

Data In

EA (2:0)

/RDYE

Valid Address Out

TEAD

RDYS

RDYH

Figure 6. Read From External Device Timing

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AC TIMING DIAGRAMS (Continued)

TINS

TINL

CK

Interrupt

HALT

THS

THH

Figure 7. Interrupt/HALT Timing

Table 3. CODEC Interface-AC Timing

Min

Internal SCLK

Max

SDCR

SUCR

FDCR

FUCR

TDSR

TUSR

RSU

SCLK down from CLK rise

–

7

15

6

SCLK up from CLK rise

FS0, FS1 down from SCLK rise

FS0, FS1 up from SCLK rise

TXD down from SCLK rise

TXD up from SCLK rise

6

7

RXD Setup time in respect to

SCLK fall

RH

RXD Hold time in respect to

SCLK fall

0

FDCR

FUCR

TDSR

TUSR

RSU

FS0,FS1 down from SCLK rise

FS0, FS1 up from SCLK rise

TXD down from SCLK rise

TXD up from SCLK rise

–

1

13

12

RXD setup time in respect to

SCLK fall

RH

RXD Hold Time in respect to

SCLK fall

6

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SDCR

TCY

2

CLOCK

SUSR

FUCR

SCLK

FS0, 1

TXD

FDCR

TUSR

TDSR

RSV

RXD

RH

Figure 8. CODEC Interface Timing

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PIN FUNCTIONS

CK Clock (input). This pin controls the external clock.

INT1 and INT2 are shared with internal Z87010 peripher-

als. INT1 is dedicated to the CODEC interface if enabled.

INT2 services the 13-bit Timer if enabled. In the Z87010

standard software configuration, INT0 and INT2 are not

used; INT1 is used by the CODEC interface.

EXT15-EXT0 External Data Bus (input/output). Data bus

for user-defined outside registers. The pins are normally

tri-stated, except when the outside registers are specified

as destination registers in the instructions. All the control

signals exist to allow a read or a write through this bus. The

bus is used for Z87000 interface.

/RES Reset (input, active Low). This pin controls the asyn-

chronous reset signal. The /RESET signal must be kept

Low for at least one clock cycle. The CPU pushes the con-

tents of the Program Counter (PC) onto the stack and then

fetches a new PC value from program memory address

0FFCH after the reset signal is released.

ER//W External Bus Direction (output). Data direction sig-

nal for EXT-Bus. Data is available from the CPU on

EXT15-EXT0 when this signal is Low. EXT-Bus is in input

mode (high-impedance) when this signal is High.

/RDYE Data Ready (input). User-supplied Data Ready sig-

nal for data to and from external data bus. This pin stretch-

es the /EI and ER//W lines and maintains data on the ad-

dress bus and data bus. The ready signal is sampled from

the rising clock only if ready is active. A single wait-state

can be generated internally by setting the appropriate bits

in the EXT7-2 register.

EA2-EA0 External Address (output). User-defined register

address output (latched). One of eight user-defined exter-

nal registers is selected by the processor with these ad-

dresses are part of the processor memory map, the pro-

cessor is simply executing internal reads and writes.

External Addresses EXT4-EXT7 are used internally by the

processor if the CODEC interface and 13-bit timer are en-

abled.

UI1-UI0 Two Input Pins (input). General-purpose input

pins. These input pins are directly tested by the conditional

branch instructions: and are reflected in two bits of the sta-

tus register (S10 and S11). These are asynchronous input

signals that have no special clock synchronization require-

ments.

/EI Enable Input (output). Read/Write timing signal for

EXT-Bus. User strobe is for triggering external peripheral.

Data is read by the external peripheral on the rising edge

of /EI. Data is read by the processor on the rising edge of

CK not /EI.

U01-U00 Two Output Pins (push-pull output). General-

purpose output pins. These pins reflect the value of two

bits in the status register (S5 and S6). UO0 is dedicated to

provide an interrupt signal to the Z87000 controller. Note:

the user output pin values are the inverse of the status reg-

ister content.

HALT Halt State (input). Stop Execution Control. The CPU

continuously executes NOPs and the program counter re-

mains at the same value when this pin is held High. This

signal must be synchronized with CK. An interrupt request

must be executed (enabled) to exit HALT mode. After the

interrupt service routine, the program continues from the

instruction after the HALT.

/INT2-/INT0 Three Interrupts (input, active Low). Interrupt

request 2-0. Interrupts are generated on the rising edge of

the input signal. Interrupt vectors for the interrupt service

routine starting address are stored in the program memory

locations 0FFFH for /INT0, 0FFEH for /INT1, and 0FFFDH

for /INT2. Priorities are: INT2=Lowest, INT0=highest.

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FUNCTIONAL DESCRIPTION

General functional partitioning of the Z87010 is shown in

Figure 1. The chip consists of the Z89S00 static DSP core

with 512 words of RAM, 4K words of ROM, a CODEC in-

terface, a general-purpose timer and a wait state genera-

tor.

User Outputs. The status register bits S5 and S6 connect

directly to UO0 and UO1 pins and may be written to by the

appropriate instruction. Note: The user output value is the

opposite of the status register content.

2

I/O Bus. The Z87010 provides a 16-bit, CMOS compatible

I/O bus. I/O Control pins provide convenient communica-

tion capabilities with external peripherals. Single cycle ac-

cess is possible. For slower communications, an on-board

hardware wait-state generator can be used to accommo-

date timing conflicts.

The DSP core is characterized by an efficient hardware ar-

chitecture that allows fast arithmetic operations such as

multiplication, addition, subtraction and multiply-accumu-

late of two 16-bit operands. Most instructions are executed

in one clock cycle.

The DSP core uses a RAM memory of 512 16-bit words di-

vided in two banks.

These latched output address pins (EA0-2) allow a maxi-

mum of eight external peripherals. However up to four of

these addresses (EXT4-7) are used by internal peripherals

if enabled.

Program Memory. The Z87010 has a 4K 16-bit words in-

ternal ROM including 4 words for interrupt and reset vec-

tors. The ROM is mapped at address 0000H to 0FFFH.

The reset vector is located at address 0FFCH, interrupts

INT0 is at 0FFDH, interrupt INT1 is at 0FFEH and interrupt

INT2 is at 0FFFH.

EXT4 13-bit Timer Configuration Register

EXT5 CODEC Interface Channel 0 Data

EXT6 CODEC Interface Channel 1 Data

Interrupts. The Z87010 has three positive edge-triggered

interrupt inputs pins. However, INT1 is dedicated to the

CODEC interface and INT2 is dedicated to the 13-bit timer

if these peripherals are enabled.

EXT7 CODEC Interface Configuration Register and Wait

State Generator.

User Inputs. The Z87010 has two inputs, UI0 and UI1,

which may be used by Jump and Call instructions. The

Jump or Call tests one of these pins and if appropriate,

jumps to a new location. Otherwise, the instruction be-

haves like a NOP. These inputs are also connected to the

status register bits S10 and S11, which may be read by the

appropriate instruction.

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Z87010/Z87L10

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CODEC INTERFACE

The CODEC interface provides direct-connect capabilities

for standard 8-bit PCM CODECs with hardware µ-law

compression. Internal registers EXT5, EXT6 and EXT7 are

used to program the CODEC mode. One serial clock and

two frame sync control signals are provided, allowing for

two bidirectional data channels.

Note: µ-law expansion must be done in software.

Data Bus

16

µ-Law

Compression

EXT5-1

EXT6-1

CLKIN

EXT7-1

CLKIN

16

EXT5-2

EXT6-2

CLKIN

EXT7-2

CLKIN

CONTROL

LOGIC

TXD

RXD

Figure 9. CODEC Interface Block Diagram

CODEC Interface Hardware

CODEC Interface Control Signals

The Hardware for the CODEC Interface uses six 16-bit

registers, µ-law compression logic and general-purpose

logic to control transfers to the appropriate register.

SCLK (Serial Clock)

The Serial Clock provides a clock signal for operating the

external CODEC. A 4-bit prescaler is used to determine

the frequency of the output signal.

SCLK = (0.5* CLK)/PS where: CLK = System Clock

PS = 4-bit Prescaler*

Note: An internal divide-by-two is performed before the

clock signal is passed to the Serial Clock prescaler.

* The Prescaler is an up-counter.

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Assuming an input clock of 16.384 MHz, SCLK is pro-

grammed by the Z87010 embedded software for 2.048

MHz.

FS0, FS1 (Frame Sync)

The Frame Sync is used for enabling data transfer/receive.

The rising and falling edge of the Frame Sync encloses the

serial data transmission. The Z87010 embedded software

programs the Frame Sync signal to 8 kHz.

2

TXD (Serial Output to CODEC)

The TXD line provides 8-bit data transfers. Each bit is

clocked out of the processor by the rising edge of the

SCLK, with the MSB transmitted first.

Interrupt

Once the transmission of serial data is completed an inter-

nal interrupt signal is initiated. A single-cycle Low pulse

provides an interrupt on INT1. When this occurs, the pro-

cessor will jump to the defined Interrupt 1 vector location.

RXD (Serial Input from CODEC)

The RXD line provides 8-bit data transfers. Each bit is

clocked into the processor by the falling edge of the SCLK,

with the MSB received first.

/int1

fs1

fs0

sclk

txd

rxd

Figure 10. CODEC Interface Timing (8-Bit Mode)

The following modes are available for FSYNC and SCLK

signals:

CODEC Interface Timing

Figure 10 depicts a typical 8-bit serial data transfer using

both of the CODEC Interface Channels. The transmitting

data is clocked out on the rising edge of the SCLK signal.

An external CODEC clocks data in on the falling edge of

the SCLK signal. Once the serial data is transmitted, an in-

terrupt is given. The CODEC interface signals are not initi-

ated if the CODEC interface is not enabled.

SCLK

FSYNC

Internal

External

Internal

External

Internal

External

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CODEC INTERFACE (Continued)

The CODEC interface timing is independent of the proces-

sor clock when external mode is chosen. This feature pro-

vides the capability for an external device to control the

transfer of data to the Z87010. The Frame Sync signal en-

velopes the transmitted data (Figure 10), therefore care

must be taken to ensure proper sync signal timing. In the

cordless phone system, the SCLK is externally provided

by the Z87000 controller, while FSYNC is internally gener-

ated.

The FSYNC Signals (FS0, FS1) when programmed for in-

ternal mode, are generated by 9-bit counter with SCLK as

input clock. Together with the SCLK prescaler, this counter

forms a 13-bit counter clocked by the system clock divided

by two. The output of this counter can be used to clock the

general-purpose 13-bit counter/timer, to form a 26-bit

counter.

CODEC Control Registers

The CODEC interface is accessed through addresses

EXT5, EXT6 and EXT7. The data accesses are double-

buffered registers: two registers (EXT5-1 and EXT5-2) are

mapped on address EXT5 and similarly EXT6-1 and

EXT6-2 registers are mapped on address EXT6.

The Transmit and Receive lines are used for transfer of se-

rial data to or from the CODEC interface. The CODEC in-

terface performs both data transmit and receive simulta-

neously.

EXT5-1

D5

D6

D0

D15 D14 D13 D12 D11 D10 D9

D7

D1

D8

D2

D3

D4

Data Bits 15-0

EXT5-2

D15 D14 D13 D12 D11 D10 D9

D0

Figure 11. CODEC Interface Data Registers (Channel 0)

EXT6-1

D5

D6

D0

D15 D14 D13 D12 D11 D10 D9

D7

D1

D8

D2

D3

D4

Data Bits 15-0

EXT6-2

D15 D14 D13 D12 D11 D10 D9

Figure 12. CODEC Interface Data Registers (Channel 1)

2-18

P R E L I M I N A R Y

DS96WRL0601

Z87010/Z87L10

Audio Encoder/Decoders

Zilog

EXT7-1

D15 D14 D13 D12 D11 D10 D9

D8 D7

D6 D5

D4 D3

D2 D1

D0

2

SCLK Prescaler (up-counter)

SCLK/FSYNC Ratio Prescaler (up-counter)

CODEC Mode

01 Reserved

10 Reserved

11 Reserved

FSYNC

0

1

External Source*

Internal Source

CODEC 0 Disable/Enable

0 = Disable*

Note: The timer is an up-counter.

1 = Enable

Example: EXT7-1 = #%x00D

EXT7-1 = #%x80F

OSC = 12.288 MHz, SCLK = 2.048 MHz, FSYNC = 8 kHz

OSC = 12.288 MHz, SCLK = 6.144 MHz, FSYNC = 48 kHz

No interrupt

* Default

EXT7-1 = #%xFFx

EXT7-1 = #%x000

Max interrupt period (667 µs for OSC = 12.288 MHz)

Figure 13. CODEC Interface Control Register

EXT7-2

D15 D14 D13 D12 D11 D10 D9

D8 D7

D6 D5

D4 D3

D2 D1

D0

Wait State EXT0

Wait State EXT1

nws - no wait states

ws - one wait states

Wait State EXT2

Wait State EXT3

00 no wait states (nws)

01 read (nws), write (ws)

10 read (ws), write (nws)

11 read (ws), write (ws)

Wait State EXT4

Wait State EXT5

Wait State EXT6

SCLK

0

1

External Source*

Internal Source

CODEC 1 Disable/Enable

0 = Disable*

1 = Enable

*Default

Figure 14. Wait/State/CODEC Interface Control Register

DS96WRL0601

P R E L I M I N A R Y

2-19

Z87010/Z87L10

Audio Encoder/Decoders

Zilog

CODEC INTERFACE (Continued)

The CODEC Interface Control Register (EXT7-1) is shown

on Figure 13. Setting of the CODEC mode, FSYNC mode

and CODEC 0 enable/disable is done through this register.

A second control register (EXT7-2) also mapped on ad-

dress EXT7 control the CODEC 1, SCLK source and wait

state generator (see Figure 9). The “operation” section de-

scribes how to access the various register.

General-Purpose Counter Timer

A 13-bit counter/timer is available for general-purpose use.

When the counter counts down to the zero state, an inter-

rupt is received on INT2. If the counter is disabled, EXT4

can be used as a general-purpose address. The counting

operation of the counter can be disabled by resetting bit

14. By selecting the clock source to the CODEC counter

output (FSYNC), one can extend the counter to a total of

26 bits.

Wait-State Generator

An internal wait state generator is provided to accommo-

date slow external peripherals. One wait-state can be au-

tomatically inserted by the Z87010 in any EXT bus access.

Read and/or write cycles can be independently lengthened

for each register, by setting register EXT7-2 accordingly.

See Figure 9 for detailed description of EXT7-2.

Note: Placing zeroes into the Count Value register does

not generate an interrupt. Therefore it is possible to have

a single-pass option by loading the counter with zero after

the start of count.

The Counter is defaulted to the Enable state. If the system

designer does not choose to use the timer, the counter can

be disabled. Once disabled, the designer cannot enable

the counter unless a reset of the processor is performed.

The Z87010 software uses one wait state on all external

register accesses.

For additional wait states, a dedicate pin (/RDYE) can be

held high. The /RDYE pin is monitored only during execu-

tion of a Read or Write Instruction to external peripherals.

Example:

LD

EXT, #%C0008 1100 0000 0000 1000

; Enable Counter

; Enable Counting

; Clock Source = OSC/2

; Count Value = 1000=8

; Interrupt will occur every 16 clock

cycles

EXT4

D15 D14 D13 D12 D11 D10 D9

D8 D7

D6 D5

D4 D3

D2 D1

D0

Count Value (Down-Counter)

Clock Source

0 Oscillator/2*

1 CODEC Counter Output

Count Operation

0 = Disable*

1 = Enable

Counter

0 = Disable

1 = Enable*

* Default State

Figure 15. Timer Register

P R E L I M I N A R Y

2-20

DS96WRL0601

Z87010/Z87L10

Audio Encoder/Decoders

Zilog

OPERATION

Disabling Peripherals

written to while the serial CODEC transfer is taking place.

This is achieved by only writing to EXT5 after the CODEC

interrupt. This also transfers the CODEC value to EXT5-1

which can be read in software.

2

Disabling a properly (CODEC Interface, Counter) provides

a general-purpose use of the EXT address pertaining to

the specific peripheral. If the peripheral is not disabled, the

EXT control signals and EXT data are still provided but

transfer of data on the EXT pins is not available (since in-

ternal transfers are being processes on the internal bus).

Care must be taken to ensure that control of the EXT bus

does not provide bus conflicts.

The correct succession of operations is thus

1. Wait for Interrupt

2. Write to EXT5

3. Read from EXT5

Accessing the CODEC Interface Registers

The same discussion applies for EXT6.

EXT5, EXT6 AND EXT7 host double buffered registers.

External serial CODEC data is transferred from pin RxD to

the Z87010 CODEC interface registers EXT5-2. At the

same time, the data present in EXT5-2 is serially trans-

ferred to the external CODEC through pin TxD.

A similar hardware architecture is used for EXT7. Writing

to EXT7 loads the register EXT7-2 and transfers the previ-

ous contents of EXT7-2 to EXT7-1. Reading from EXT7 re-

turns the contents of EXT7-1.

In order to load both registers, two successive load opera-

tions to EXT7 are required: first with the contents of EXT7-

1 then with the contents of EXT7-2. (See Figure 16).

Writing a new data word to EXT5 loads that data word to

EXT5-2 and transfers the current contents of EXT5-2 to

EXT5-1. Reading data from EXT5 reads the contents of

EXT5-1. Core must be taken to ensure that EXT5 is not

Internal 16-Bit Bus

16

EXT7-2

EXT7-1

EXT7-1 CODEC Timer Register

EXT7-2 Wait-State Register

Figure 16. EXT7 Register Conﬁguration

DS96WRL0601

P R E L I M I N A R Y

2-21


型号：	Z87010
厂家：	ZILOG, INC.
描述：	Audio Encoder/Decoders 音频编码器/解码器解码器编码器
文件：	总22页 (文件大小：89K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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