Z89313 [ZILOG]
DIGITAL TELEVISION CONTROLLER; 数字电视控制器
| 型号： | Z89313 |
| 厂家： | 
ZILOG, INC. |
| 描述： | DIGITAL TELEVISION CONTROLLER |
| 文件： | 总8页 (文件大小：52K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
CUSTOMER PROCUREMENT SPECIFICATION
Z89313
DIGITAL TELEVISION CONTROLLER
FEATURES
■
■
■
■
■
Direct Closed Caption Decoding
TV Tuner Serial Interface
■
Part
ROM
RAM
(Word)
1K x 16
Speed
(MHz)
12
Number (Word)
Z89313
32K x 16
Customized Character Set
Character Control Mode
■
■
■
■
52-Pin Shrink DIP Package
4.5- to 5.5-Volt Operating Range
Z89C00 RISC Processor Core
0°C to +70°C Temperature Range
Directly Controlled Receiver Functions
GENERAL DESCRIPTION
Serial interfacing with the television tuner is provided
through the tuner serial port. Digital channel tuning
adjustments may be accessed through the industry-
standard I2C port.
The Z89313 is a member of Zilog's family of Digital
Television Controllers designed to provide complete audio
and video control of television receivers, video recorders,
and advanced on-screen display facilities.
Additional hardware provides the capability to display two
to three times normal size characters. The smoothing logic
contained in the on-screen display circuit improves the
appearance of larger fonts. Special circuitry can be
activated to improve the visibiity of text by adding a right-
sided shadow effect to the characters.
The Z89313 features a powerful Z89C00 RISC processor
core that controls on-board peripheral functions and
registers using the standard processor instruction set.
In closed caption mode, text can be decoded directly from
the composite video signal and displayed on the screen
with assistance from the processor's digital signal
processing capabilities. The character representation in
this mode allows for a simple attribute control through the
insertion of control characters.
Receiver functions such as color and volume can be
directly controlled by six 8-bit pulse width modulated
ports.
Notes:
The character control mode provides access to the full set
ofattribute controls. The modification ofattributes is allowed
on a character-by-character basis. The insertion of control
characters permits direction of other character attributes.
All Signals with a preceding front slash, "/", are active Low, e.g.:
B//W (WORD is active Low); /B/W (BYTE is active Low, only).
Power connections follow conventional descriptions below:
Display attributes, including underlining, italics, blinking,
eight foreground/background colors, character position
offset delay, and background transparency, are made
possible through a fully customized 512 character set,
formatted in two 256 character banks.
Connection
Circuit
Device
Power
Ground
VCC
GND
VDD
VSS
CP95TEL0700 (6/95)
1
Z89313
P R E L I M I N A R Y
CP95TEL0700
GENERAL DESCRIPTION (Continued)
PWM
Capture
IRIN
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
ADC
ADC0
ADC1
ADC2
ADC3
ADC4
ADC5
CVI
Port 17
Port 00
Port 05
Port 04
Port1
Port 0
Port 00
Port 01
Port 02
Port 03
Port 04
Port 05
Port 06
Port 07
Port 08
Port 09
Port 0A
Port 0B
Port 10
Port 11
Port 12
Port 13
Port 14
Port 15
Port 16
Port 17
Port 18
Port 0C
Port 0D
Port 0E
Port 0F
I2C
Port 01/11
Port 02/12
SCL/MSCL2
SCD/MSCD2
Control
XTAL1
XTAL2
LPF
MSCL1
MSCD1
HSYNC
HSYNC2
VSYNC
PWM6
OSD
Register Addr/Data
V1(R)
/Reset
V2(G)
V3(B)
CPU
RAM
1K x 16
Address
ROM
32K x 16
ROM Addr
ROM Data
Data
Functional Block Diagram
2
Z89313
P R E L I M I N A R Y
CPS5TEL0700
PIN DESCRIPTION
Port 16/SCLK
IRIN
1
2
3
4
5
6
7
8
9
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
Port15/B<1>
Port14/B<0>
Port13/G<1>
Port18/G<0>
Port 0C
Port 0B
Port08/R<1>
Port10/R<0>
PWM6/Hsync2
Port 0A
Port 09
Port 0D
Port 07/CSync
Port 06/Counter
Port 03
PWM5
PWM4
PWM3
PWM2
PWM1
ANGNDX
VCC
10
11
Z89313
Port 01/I2SSC
Port 02/I2SSD
CVI/ADC0
LPF
12
13
14
15
16
17
18
19
20
21
22
GND
ANGNDF
XTAL2
XTAL1
/Reset
I2MSC1
I2MSD1
ADC5
Port 04/ADC4
Port 05/ADC3
Port 00/ADC2
Port 17/ADC1
ANGND
Port 0E
31
30
29
28
27
Port11/I2MSC2
Port11/I2MSD2
ANVCC
Port0F/HalfBlank
23
24
VSync
HSync
V3 (B)
V2 (G)
V1 (R)
25
26
Blank
52-Pin Shrink DIP Configuration
3
Z89313
P R E L I M I N A R Y
CP95TEL0700
PIN DESCRIPTION
Z89313
Pin
Name
Z89313
52-Pin
Configuration
Direction Reset
Function
a
VCC , ANV
+5 V
39,22
38,21,15,40
PWR
PWR
–
–
GND, ANCGCND,
ANGNDF, ANGNDX
0 V
b
IRIN
ADC[5:1]
Infrared Remote Capture Input
4-Bit Analog-to-Digital Converter
Input
2
I
AI
I
I
16,17,18,19,20
PWM[6:1]
Port0[F:0]
8-Bit Pulse Width Modulator
Output
Bit Programmable Input/Output Ports
46,45,44,43,42,41
O
B
O
I
23,32,7,3,4,5,6,48,8,9,18,
17,10,12,11,19
Port1[8:0]
Bit Programmable Input/Output Ports
49,20,1,52,51,50,30,
31,47
B
I
SCL
SCD
I2C Clock I/O
I2C Data I/O
11,31,34
12,30,33
BOD
BOD
XTAL1
XTAL2
Crystal Oscillator Input
Crystal Oscillator Output
36
37
AI
AO
I
O
LPF
Loop Filter
14
AB
O
HSYNC
VSYNC
H_Sync
V_Sync
28,46
29
B
B
I
I
/RESET
V[3:1]
Device Reset
35
I
I
OSD Video Output
24,25,26
O
O
(Typically Drive B, G, and R Outputs)
OSD Blank Output
OSD Half Blank Output
Blank
Half Blank
27
23
O
O
O
SCLK
Internal Processor SCLK
–
O
Notes:
Please refer to pin-out diagram for shared pin numbers.
a) ANVCC is for the reference voltage of the ADC input.
b) ANGND is for the reference ground of the ADC input.
ANGNDF is for LPF ground, and ANGNDX is for XTAL circuit ground.
4
Z89313
P R E L I M I N A R Y
CPS5TEL0700
V1, V2, V3 ANALOG OUTPUT
Specifications V = 5.25 V
CC
V = 5.25 V
Condition
Limit
CC
Output Voltage
Setting Time
Bit = 11
Bit = 10
Bit = 01
Bit = 00
4.30 V ± 0.3 V
3.10 V ± 0.25 V
1.90 V ± 0.20 V
0 V ± 0.75 V
70% of DC Level,
10pf Load
< 50 ns
V1, V2, V3 ANALOG OUTPUT
Specifications V = 4.75 V
CC
V = 4.75 V
Condition
Limit
CC
Output Voltage
Setting Time
Bit = 11
Bit = 10
Bit = 01
Bit = 00
3.90 V ± 0.30 V
2.80 V ± 0.25 V
1.70 V ± 0.20 V
0 V ± 0.65 V
70% of DC Level,
10pf Load
< 50 ns
Z893XX
XTAL1
68pF
XTAL2
27k
560pF
32K Oscillator Recommended Circuit
5
Z89313
P R E L I M I N A R Y
CP95TEL0700
ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Min
Max
Units
Conditions
VCC
Power Supply Voltage
Input Voltage
0
–0.3
7
V
V
V
VCC +0.3
Digital Inputs
ID
V
Input Voltage
Output Voltage
Output Current High
Output Current High
Output Current Low
Output Current Low
–0.3
–0.3
V
CC +0.3
V
V
mA
mA
mA
mA
Analog Inputs (A/D0...A/D4)
All Push-Pull Digital Output
One Pin
All Pins
One Pin
All Pins
IA
VO
IOH
IOH
IOL
IOL
VCC +0.3
–10/–1a
–100
20/1b
200
TA
TA
Operating Temperature
Storage Temperature
0
–65
70
150
°C
°C
Notes:
a) 1 mA max. when output pad impedance is 600 Ω.
b) 1 mA max. when output pad impedance is 600 Ω.
DC CHARACTERISTICS
TA = 0°C to + 70°C; V = 4.5 V to + 5.5 V; FOSC = 32.768 KHz
CC
Symbol
Parameter
Min
Max
Typical
Units
Conditions
V
Input Voltage Low
Input Voltage High
0
0.2 VCC
VCC
0.4
3.6
V
V
IL
V
0.6 VCC
IH
VOL
VOH
Output Voltage Low
Output Voltage High
0.4
0.16
4.75
V
V
@ IOL = 1 mA
@ IOL = 0.75 mA
VCC –0.9
VXL
VXH
VHY
IIR
Input Voltage XTAL1 Low
Input Voltage XTAL1 High
Schmitt Hysteresis
0.3 VCC
1.0
3.5
0.5
90
V
V
V
External Clock
Generator Driven
On XTAL1 Input Pin
VCC –2.0
3.0
0.75
150
Reset Input Current
µA
V = 0 V
RL
IIL
ICC
Input Leakage
Supply Current
–3.0
3.0
100
0.01
60
µA
mA
@ 0 V and V
CC
ICC1
ICC2
Supply Current
Supply Current
300
40
100
5
µA
µA
Sleep Mode @ 32 KHz
Stop Mode
6
Z89313
P R E L I M I N A R Y
CPS5TEL0700
AC CHARACTERISTICS
TA = 0°C to + 70°C; V = 4.5 V to 5.5 V; FOSC = 32.768 KHz
CC
Symbol
Parameter
Min
Max
Typical Units
Note
TPC
TRC,TFC
Input Clock Period
Clock Input Rise and Fall
16
100
32
12
µS
µS
TDPOR
Power On Reset Delay
0.8
1.2
s
Depends on Crystal
AC CHARACTERISTICS*
TA = 0°C to + 70°C; V = 4.5 V to 5.5 V; FOSC = 32.768 KHz
CC
Symbol
Parameter
Min
Max
Typical
Units
TWRES
TDHS
Power-On Reset Min. Width
H_Sync Incoming Signal Width
5TPC
12.5
µS
µS
5.5
11
TDV
V_Sync Incoming Signal Width
Time Delay Between Leading Edge
of V_Sync and H_Sync in Even Field
0.15
–12
1.5
+12
1.0
0
mS
µS
TDESS
TDOS
Time Delay Between Leading Edge
of H_Sync in Odd Field
H_Sync/V_Sync Edge Width
20
44
32
µS
µS
TWHV
2.0
0.5
S
Notes:
All timing of the I2C bus interface are defined by related specifications of
the I2C bus interface.
7
Z89313
P R E L I M I N A R Y
CP95TEL0700
Pre-Characterization Product:
The product represented by this CPS is newly introduced
and Zilog has not completed the full characterization of the
product. The CPS states what Zilog knows about this
product at this time, but additional features or non-con-
formance with some aspects of the CPS may be found,
either by Zilog or its customers in the course of further
application and characterization work. In addition, Zilog
cautions that delivery may be uncertain at times, due to
start-up yield issues.
© 1995 by Zilog, Inc. All rights reserved. No part of this document
may be copied or reproduced in any form or by any means
without the prior written consent of Zilog, Inc. The information in
this document is subject to change without notice. Devices sold
by Zilog, Inc. are covered by warranty and patent indemnification
provisions appearing in Zilog, Inc. Terms and Conditions of Sale
only. Zilog, Inc. makes no warranty, express, statutory, implied or
by description, regarding the information set forth herein or
regarding the freedom of the described devices from intellectual
property infringement. Zilog, Inc. makes no warranty of mer-
chantability or fitness for any purpose. Zilog, Inc. shall not be
responsible for any errors that may appear in this document.
Zilog, Inc. makes no commitment to update or keep current the
information contained in this document.
Zilog’s products are not authorized for use as critical compo-
nents in life support devices or systems unless a specific written
agreement pertaining to such intended use is executed between
the customer and Zilog prior to use. Life support devices or
systems are those which are intended for surgical implantation
into the body, or which sustains life whose failure to perform,
when properly used in accordance with instructions for use
provided in the labeling, can be reasonably expected to result in
significant injury to the user.
Zilog, Inc. 210 East Hacienda Ave.
Campbell, CA 95008-6600
Telephone (408) 370-8000
Telex 910-338-7621
FAX 408 370-8056
Internet: http://www.zilog.com
8
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