Z8937116PSC [ZILOG]
16-BIT DIGITAL SIGNAL PROCESSORS; 16位数字信号处理器
| 型号： | Z8937116PSC |
| 厂家： | 
ZILOG, INC. |
| 描述： | 16-BIT DIGITAL SIGNAL PROCESSORS |
| 文件： | 总40页 (文件大小：300K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY PRODUCT SPECIFICATION
1
Z89321/371/391
1
16-BIT DIGITAL SIGNAL PROCESSORS
FEATURES
DSP ROM
OTP
(KW)
DSP RAM
Lines
MIPS
(Max)
40-Pin
DIP
44-Pin
PLCC
44-Pin
QFP
84-Pin
PLCC
Device
(KW)
Device
Z89321
Z89371
Z89391
4
512
512
512
24
16
24
Z89321
Z89371
Z89391
X
X
X
X
X
X
4
64*
X
Note: *External
Note: *General-Purpose
■ 0°C to +70°C Standard Temperature Range
-40°C to +85°C Extended Temperature Range
On-Board Peripherals
■ Dual 8/16-Bit CODEC Interface Capable of up to
■ 4.5- to 5.5-Volt Operating Range
10 Mbps
■
m-Law Compression Option
(Decompression is Performed in Software)
DSP Core
■ 24 MIPS @ 24 MHz Maximum, 16-Bit Fixed Point DSP
■ 41.7 ns Minimum Instruction Cycle Time
■ Six-Level Hardware Stack
■ 16-Bit I/O Bus (Tri-Stated)
■ Three I/O Address Pins (Latched Outputs)
■ Wait-State Generator
■ Six Register Address Pointers
■ Three Vectored Interrupts
■ Optimized Instruction Set (30 Instructions)
■ 13-Bit General-Purpose Timer
GENERAL DESCRIPTION
The Z893XX products are high-performance Digital Signal
Processors (DSPs) with a modified Harvard-type architec-
ture featuring separate program and data memory. The de-
sign has been optimized for processing power while mini-
mizing silicon space.
Three vectored interrupts are complemented by a six-level
stack, and the CODEC interface allows high-speed trans-
fer rates to accommodate digital audio and voice data.
A dedicated Counter/Timer provides the necessary timing
signals for the CODEC interface, and an additional 13-bit
timer is available for general-purpose use.
The single-cycle instruction execution and bus structure
promotes efficient algorithm execution, while the six regis-
ter pointers provide circular buffering capabilities and dual
operand fetching.
DS97DSP0100
P R E L I M I N A R Y
1
Z89321/371/391
16-Bit Digital Signal Processors
Zilog
The Z893XX DSPs are optimized to accommodate ad-
vanced signal processing algorithms. The 24 MIPS (maxi-
mum) operating performance and efficient architecture
provides real-time instruction execution. Compression, fil-
tering, frequency detection, audio, voice detection/synthe-
sis, and other vital algorithms can all be accommodated.
pro-grammable (OTP) device with a 16 MHz maximum op-
erating frequency.
Notes: All signals with a preceding front slash, "/", are
active Low. For example, B//W (WORD is active Low);
/B/W (BYTE is active Low, only).
Power connections follow conventional descriptions be-
low:
The Z89321/371/391 devices feature an on-board CO-
DEC interface, compatible with 8-bit PCM and 16-bit CO-
DECs for digital audio applications. Additionally, an on-
board wait-state generator is provided to accommodate
slow external peripherals.
Connection
Power
Circuit
Device
V
V
DD
CC
Ground
GND
V
SS
For prototypes, as well as production purposes, the
Z89371 member of the DSP product family is a one-time
Program
ROM/OTP
4096x16
Data RAM0
256x16
Data RAM1
256x16
EA0-2
EXT0-15
/DS
WAIT
RD//WR
PA0-15
PD0-15
PDATA
PADDR
DDATA
XDATA
P0
P1
P2
P0
P1
P2
TXD
RXD
SCLK
FS0
8/16-Bit,
Full Duplex,
10 MBPS
X
Y
Multiplier
P
Serial Port
DP0-3 DP4-6
FS1
INT0-2
HALT
ADDR ADDR
GEN0 GEN1
Shifter
13-Bit Timer
User I/O
Program
Control
Unit
/RESET
CLK
UI1-0
UO1-0
Arithmetic
Logic Unit
(ALU)
Accumulator
Figure 1. Z89321/371/391 Functional Block Diagram
2
P R E L I M I N A R Y
DS97DSP0100
Z89321/371/391
16-Bit Digital Signal Processors
Zilog
PIN DESCRIPTION
1
1
EXT12
EXT13
EXT14
VSS
EXT15
EXT3
EXT4
VSS
40
RXD
VSS
EXT2
EXT1
EXT0
VSS
FS1
U01
EXT5
EXT6
EXT7
TXD
U00
/INT0
FS0
DIP 40 - Pin
CLK
EXT8
EXT9
VSS
/DS
VDD
EA2
EXT10
EXT11
UI1
UI0
SCLK
EA1
EA0
/RESET
RD//WR
VDD
20
21
Figure 2. Z89321/371 40-Pin DIP Pin Assignments
Table 1. Z89321/371 40-Pin DIP Pin IdentiÞcation
Table 1. Z89321/371 40-Pin DIP Pin IdentiÞcation
No.
Symbol
Function
Direction
No.
Symbol
Function
Direction
1-3
EXT12-
EXT14
External Data
Bus
Ground
Input/Output
23
/RESET
Reset
Input
24-26 EA0-EA2
External Address Output
Bus
Power Supply
4
5
V
SS
EXT15
External Data
Bus
Input/Output
Input/Output
27
28
V
Input
DD
/DS
Data Strobe for Output
External Bus
Clock
CODEC 0 Frame Input/Output*
Sync
Interrrupt
6-7
EXT3-EXT4 External Data
Bus
29
30
CLK
FS0
Input
8
V
Ground
SS
9-11
EXT5-EXT7 External Data
Bus
Input/Output
31
/INT0
Input
12
TXD
Serial Output to Output
CODECs
32-33 UO0-UO1
User Output
CODEC 1 Frame Input/Output*
Sync
Output
34
FS1
13-14 EXT8-EXT9 External Data
Bus
15
Input/Output
35
V
Ground
SS
V
Ground
SS
36-38 EXT0-EXT2 External Data
Bus
Input/Output
16-17 EXT10-
EXT11
18
19
20
External Data
Bus
Input/Output
39
40
V
Ground
SS
UI1
UI0
SCLK
User Input
User Input
Input
Input
RXD
Serial Input from Input
CODECs
CODEC Serial
Clock
Input/Output*
Notes:
*Input/Output is defined by interface mode selection.
ꢀHALT/WAIT pins not available on 40-pin DIP package.
21
22
V
Power Supply
Input
DD
RD//WR
Strobes for
Output
External Bus
DS97DSP0100
P R E L I M I N A R Y
3
Z89321/371/391
16-Bit Digital Signal Processors
Zilog
PIN DESCRIPTION (Continued)
6
1
40
39
7
VSS
EXT0
EXT1
EXT2
VSS
EA0
/RESET
WAIT
RD//WR
VDD
SCLK
UI0
UI1
INT1
INT2
PLCC 44 -Pin
RXD
EXT12
EXT13
EXT14
VSS
17
29
28
EXT15
EXT11
18
Figure 3. Z89321/371 44-Pin PLCC Pin Assignments
4
P R E L I M I N A R Y
DS97DSP0100
Z89321/371/391
Zilog
No.
16-Bit Digital Signal Processors
Table 2. Z89321/371 44-Pin PLCC Pin IdentiÞcation
Symbol
Function
Direction
1
2
3
4-5
6
HALT
FS0
/INT0
O0-UO1
FS1
Stop Execution
CODEC 0 Frame Sync
Interrupt
User Output
CODEC 1 frame sync
Ground
Input
Input/Output*
Input
Output
Input/Output*
1
7
V
SS
8-10
11
EXT0-EXT2
External data bus
Ground
Input/Output
V
SS
12
13-15
16
RXD
EXT12-EXT14
Serial input from CODECs
External data bus
Ground
Input
Input/Output
V
SS
17
18-19
20
EXT15
EXT3-EXT4
External data bus
External data bus
Ground
Input/Output
Input/Output
V
SS
21-23
24
25-26
27
EXT5-EXT7
TXD
EXT8-EXT9
External data bus
Serial output to CODECs
External data bus
Ground
Input/Output
Output
Input/Output
V
SS
28-29
30
EXT10-EXT11
/INT2
External data bus
Interrupt
Input/Output
Input
31
/INT1
Interrupt
Input
32
UI1
User input
Input
33
UI0
User input
Input
34
35
SCLK
V
DD
CODEC serial clock
Power supply
Input/Output*
Input
36
37
RD//WR
WAIT
RD//WR strobe for EXT bus
WAIT state
Output
Input
38
39-41
42
/RESET
EA0-EA2
Reset
External Address bus
Power Supply
Input
Output
Input
V
DD
43
44
/DS
CLK
Data strobe for external bus
Clock
Output
Input
Note: * Input or output is defined by interface mode selection.
DS97DSP0100
P R E L I M I N A R Y
5
Z89321/371/391
16-Bit Digital Signal Processors
Zilog
PIN DESCRIPTION (Continued)
33
23
22
VSS
EXT0
EXT1
EXT2
VSS
34
EA0
/RESET
WAIT
RD//WR
VDD
SCLK
UI0
UI1
INT1
INT2
Z89321/371
QFP
RXD
EXT12
EXT13
EXT14
VSS
12
11
EXT15
44
EXT11
1
Figure 4. Z89321/371 44-Pin QFP Pin Assignments
6
P R E L I M I N A R Y
DS97DSP0100
Z89321/371/391
Zilog
No.
16-Bit Digital Signal Processors
Table 3. Z89321/371 44-Pin QFP Pin IdentiÞcation
Function
Symbol
Direction
1-2
3
EXT3-EXT4
External data bus
Ground
Input/Output
1
V
SS
4-6
7
8-9
10
EXT5-EXT7
TXD
EXT8-EXT9
External data bus
Serial output to CODECs
External data bus
Ground
Input/Output
Output
Input/Output
V
SS
11-12
13
EXT10-EXT1
/INT2
External data bus
Interrupt
Input/Output
Input
14
/INT1
Interrupt
Input
15
UI1
User input
Input
16
UI0
User input
Input
17
18
SCLK
V
DD
CODEC serial clock
Power supply
Input/Output*
Input
19
20
RD//WR
WAIT
RD//WR strobe EXT bus
WAIT state
Output
Input
21
22-24
25
/RESET
EA0-EA2
Reset
External address bus
Power supply
Input
Output
Input
V
DD
26
27
/DS
CLK
Data strobe for external bus
Clock
Output
Input
28
29
30
31-32
33
HALT
FS0
/INT0
UO0-UO1
FS1
Stop execution
CODEC 0 frame sync
Interrupt
User output
CODEC 1 frame sync
Ground
Input
Input/Output*
Input
Output
Input/Output*
34
V
SS
35-37
38
EXT0-EXT2
External data bus
Ground
Input/Output
V
SS
39
40-42
43
RXD
EXT12-EXT14
Serial input to CODECs
External data bus
Ground
Input
Input/Output
V
SS
44
EXT15
External data bus
Input/Output
Note: *Input or output is defined by interface mode selection.
DS97DSP0100
P R E L I M I N A R Y
7
Z89321/371/391
16-Bit Digital Signal Processors
Zilog
PIN DESCRIPTION (Continued)
75
1
11
/EXTEN
12
EXT3
VSS
PD15
FS1
74
PA8
EXT4
PA9
VSS
PD14
UO1
PD13
UO0
PD12
INTO
FS0
HALT
PD11
CLK
EXT5
PA10
EXT6
PA11
EXT7
TXD
PA12
EXT8
PA13
EXT9
VSS
Z89391
84-Pin PLCC
/DS
PD10
VDD
PD9
PA14
EXT10
PA15
EA2
PD8
EA1
VDD
32
/ROMEN
54
33
53
Figure 5. Z89391 84-Pin PLCC Pin Assignments
8
P R E L I M I N A R Y
DS97DSP0100
Z89321/371/391
16-Bit Digital Signal Processors
Zilog
Table 4. Z89391 84-Pin PLCC Pin IdentiÞcation
No. Symbol Function Direction
Serial Input from CODEC Input
Table 4. Z89391 84-Pin PLCC Pin IdentiÞcation
No. Symbol Function
43 SCLK CODEC Interface Clock
44 Power Supply
45 RD//WR R/W External Bus
Direction
1
2
3
4
5
6
7
8
RXD
In/Output
Input
1
EXT12
PA4
EXT13
PA5
EXT14
PA6
External Data 12
Program Address 4
External Data 13
Program Address 5
External Data 14
Program Address 6
Ground
In/Output
Output
In/Output
Output
In/Output
Output
V
DD
Output
Input
Input
Input
Input
Input
Output
Input
Input
46 PD4
47 WAIT
48 PD5
Program Data 4
Wait State Input
Program Data 5
49 /RESET Reset
V
50 PD6
51 EA0
52 PD7
Program Data 6
SS
9
PA7
Program Address 7
External Data 15
Prog. Mem. Address Enable Input
Output
In/Output
External Address 0
Program Data 7
Power Supply
10 EXT15
11 /PA_EN
53
V
DD
12 /EXTEN Ext. Bus Enable
Input
54 /ROMEN ROM Enable
Input
13 EXT3
14 PA8
15 EXT4
16 PA9
External Data 3
Program Address 8
External Data 4
Program Address 9
Ground
In/Output
Output
In/Output
Output
55 EA1
56 PD8
57 EA2
58 PD9
External Address 1
Output
Input
Output
Input
Program Data 8
External Address 2
Program Data 9
Power Supply
17
V
SS
59
V
Input
DD
18 EXT5
19 PA10
20 EXT6
21 PA11
22 EXT7
23 TXD
24 PA12
25 EXT8
26 PA13
27 EXT9
External Data 5
Program Address 10
External Data 6
Program Address 11
External Data 7
Serial Output to CODEC
Program Address 12
External Data 8
In/Output
Output
In/Output
Output
In/Output
Output
Output
In/Output
Output
In/Output
60 PD10
61 /DS
62 CLK
63 PD11
64 HALT
65 FS0
Program Data 10
External Data Strobe
Clock
Program Data 11
Stop Execution
Frame Synch for CODEC In/Output
Interface 0
User Interrupt 0
Program Data 12
User Output 0
Program Data 13
User Output 1
Program Data 14
Frame Synch for CODEC In/Output
Interface 1
Program Data 15
Ground
Input
Output
Input
Input
Input
66 INT0
67 PD12
68 UO0
69 PD13
70 UO1
71 PD14
72 FS1
Input
Input
Input
Input
Input
Input
Program Address 13
External Data 9
Ground
28
V
SS
29 PA14
30 EXT10
31 PA15
Program Address 14
External Data 10
Program Address 15
Power Supply
Output
In/Output
Output
Input
32
33
V
V
DD
SS
73 PD15
Input
Ground
74
75
V
V
SS
DD
34 PD0
35 EXT11
36 PD1
37 INT2
38 PD2
39 INT1
40 PD3
41 UI1
Program Data 0
External Data 11
Program Data 1
User Interrupt 2
Program Data 2
User Interrupt 1
Program Data 3
User Input 1
Input
In/Output
Input
Input
Input
Input
Input
Input
Input
Power Supply
Input
76 PA0
77
Program Address 0
Ground
Output
V
SS
78 EXT0
79 PA1
80 EXT1
81 PA2
82 EXT2
83 PA3
External Data 0
Program Address 1
External Data 1
Program Address 2
External Data 2
Program Address 3
Ground
In/Output
Output
In/Output
Output
In/Output
Output
42 UI0
User Input 0
84
V
SS
Note: *Input or output is defined by interface mode selection.
DS97DSP0100
P R E L I M I N A R Y
9
Z89321/371/391
16-Bit Digital Signal Processors
Zilog
ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed under Absolute Maxi-
mum Ratings may cause permanent damage to the de-
vice. This is a stress rating only; operation of the device at
any condition above those indicated in the operational sec-
tions of these specifications is not implied. Exposure to ab-
solute maximum rating conditions for extended periods
may affect device reliability.
Symbol Description
Min. Max. Units
V
Supply voltage (*)
Storage Temp.
Ð0.3
+7.0
V
CC
T
Ð65° +150
°C
°C
STG
T
Oper. Ambient Temp.
ꢀ
A
Note:
* Voltage on all pins with respect to GND.
ꢀ See Ordering Information.
STANDARD TEST CONDITIONS
The characteristics listed below apply for standard test
conditions as noted. All voltages are referenced to
Ground. Positive current flows into the referenced pin (Fig-
ure 6).
+5V
2.1 K W
From Output
Under Test
30 pF
9.1 K W
Figure 6. Test Load Diagram
10
P R E L I M I N A R Y
DS97DSP0100
Z89321/371/391
16-Bit Digital Signal Processors
Zilog
DC ELECTRICAL CHARACTERISTICS
(V = 5V ±10%, T = 0°C to +70°C, unless otherwise noted.)
DD
A
1
1
2
3
fclock=20 MHz
fclock=16 MHz
fclock=24 MHz
Sym
Parameter
Condition
Min
Typ Max. Min
Typ Max Min Typ Max Units
I
I
Supply Current
V
= 5.5V
5
70
5
55
5
85
5
mA
mA
V
DD
DC
DD
DC Power Consumption
Input High Level
V
2.7
2.7
.8
2.7
IH
V
Input Low Level
.8
.8
V
IL
L
I
Input Leakage
10
10
10
mA
V
V
Output High Voltage
Input Low Voltage
I
=100 mA V -0.2
V
.5
V
-0.2
V
-0.2
OH
OH
DD
DD
DD
V
I
=2.0 mA
.5
.5
V
OL
FL
OL
I
Output Floating
Leakage Current
10
10
10
mA
Notes:
1. Z89321 and Z89391 only
2. Z89371 only. V = 5V, ± 5% for 16 MHz operation. V = 5V, ± 10% for 10 MHz operation.
DD
DD
3. Z89321 only. Limited availability. Contact Zilog sales office.
DC ELECTRICAL CHARACTERISTICS
(V = 5V 10%, T = Ð40°C to +85°C, unless otherwise specified)
DD
A
1
fclock = 20 MHz
Sym
Parameter
Condition
Min
Typ
70
5
Max
I
I
Supply Current
V
=5.5V
DD
DC
DD
DC Power Consumption
Input High Level
Input Low Level
V
2.7
IH
V
.8
IL
IL
Input Leakage
10
V
Output High Voltage
I
=100 mA
V
-0.2
DD
OH
OH
V
Input Low Voltage
I
=2.0 mA
.5
OL
FL
OL
I
Output Floating
Leakage Current
10
Notes:
1. Z89321 only
DS97DSP0100
P R E L I M I N A R Y
11
Z89321/371/391
16-Bit Digital Signal Processors
Zilog
AC ELECTRICAL CHARACTERISTICS
(V = 5V ±10%, T = 0°C to +70°C, unless otherwise specified.)
DD
A
fclock = 20
fclock = 24
1
2
3
MHz
fclock = 16 MHz
MHz
Symbol
Parameter
Min
Max
Min
Max
Min
Max Units
Clock
ns
ns
ns
ns
ns
TCY
Tr
Tf
Clock Cycle Time
Clock Rise Time
Clock Fall Time
Clock Pulse Width
50
6.25
41.7
2
2
2
2
2
2
CPW
23
29
19
I/O
DSVALID
DSHOLD
EASET
EAHOLD
RDSET
RDHOLD
WRVALID
WRHOLD
/DS Valid Time from CLOCK Fall
/DS Hold Time from CLOCK Rise
EA Setup Time to /DS Fall
0
4
12
4
14
6
15
15
0
4
12
4
14
6
15
15
0
4
12
4
14
6
15
15
ns
ns
ns
ns
ns
ns
ns
ns
EA Hold Time from /DS Rise
Data Read Setup Time to /DS Rise
Data Read Hold Time from /DS Rise
Data Write Valid Time from /DS Fall
Data Write Hold Time from /DS Rise
18
18
18
5
5
5
Interrupt
INTSET
INTWIDTH
CODEC Interface
SSET
Interrupt Setup Time to CLOCK Fall
Interrupt Low Pulse Width
7
7
7
ns
ns
1 TCY
1 TCY
1 TCY
SCLK Setup Time from Clock Rise
FSYNC Setup Time from SCLK Rise
TXD Setup Time from SCLK Rise
RXD Setup Time to SCLK Fall
15
6
7
15
6
7
15
6
7
ns
ns
ns
ns
ns
FSSET
TXSET
RXSET
7
0
7
0
7
0
RXHOLD
Reset
RXD Hold Time from SCLK Fall
RRISE
RSET
Reset Rise Time
Reset Setup Time to CLOCK Rise
Reset Low Pulse Width
1000
20
10000
20
1000
20
ns
ns
ns
15
2 TCY
15
2 TCY
15
2 TCY
RWIDTH
External Program Memory
PAVALID
PDSET
PDHOLD
PA Valid Time from CLOCK Rise
PD Setup Time to CLOCK Rise
PD Hold Time from CLOCK Rise
ns
ns
ns
10
10
10
10
10
10
Wait State
WSET
WHOLD
WAIT Setup Time to CLOCK Rise
WAIT Hold Time from CLOCK Rise
23
1
23
1
23
1
ns
ns
Halt
HSET
HHOLD
Halt Setup Time to CLOCK Rise
Halt Hold Time from CLOCK Rise
3
10
3
10
3
10
ns
ns
Notes:
1. Z89321 and Z89391 only
2. Z89371 only (V = 5V ± 5%)
DD
3. Z89321 only. Limited availability. Contact Zilog sales office.
12
P R E L I M I N A R Y
DS97DSP0100
Z89321/371/391
16-Bit Digital Signal Processors
Zilog
AC ELECTRICAL CHARACTERISTICS
(V = 5V ±10%, T = Ð40°C to +85°C, unless otherwise specified.)
DD
A
1
1
fclock = 20 MHz
Symbol
Parameter
Min
Max
Clock
TCY
Tr
Tf
Clock Cycle Time
Clock Rise Time
Clock Fall Time
Clock Pulse Width
50
5
5
CPW
20
I/O
DSVALID
DSHOLD
EASET
EAHOLD
RDSET
RDHOLD
WRVALID
WRHOLD
/DS Valid Time from CLOCK Fall
/DS Hold Time from CLOCK Rise
EA Setup Time to /DS Fall
0
5
15
5
17
8
18
18
EA Hold Time from /DS Rise
Data Read Setup Time to /DS Rise
Data Read Hold Time from /DS Rise
Data Write Valid Time from /DS Fall
Data Write Hold Time from /DS Rise
20
6
Interrupt
INTSET
INTWIDTH
Interrupt Setup Time to CLOCK Fall
Interrupt Low Pulse Width
9
1 TCY
CODEC Interface
SSET
SCLK Setup Time from Clock Rise
FSYNC Setup Time from SCLK Rise
TXD Setup Time from SCLK Rise
RXD Setup Time to SCLK Fall
18
8
9
FSSET
TXSET
RXSET
9
0
RXHOLD
Reset
RXD Hold Time from SCLK Fall
RRISE
RSET
RWIDTH
Reset Rise Time
Reset Setup Time to CLOCK Rise
Reset Low Pulse Width
1000
25
18
2 TCY
External Program Memory
PAVALID
PDSET
PDHOLD
Wait State
WSET
PA Valid Time from CLOCK Rise
PD Setup Time to CLOCK Rise
PD Hold Time from CLOCK Rise
12
12
WAIT Setup Time to CLOCK Rise
WAIT Hold Time from CLOCK Rise
28
2
WHOLD
Halt
HSET
HHOLD
Halt Setup Time to CLOCK Rise
Halt Hold Time from CLOCK Rise
4
12
Note:
1. Z89321 only
DS97DSP0100
P R E L I M I N A R Y
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TIMING DIAGRAMS
TCY
Tr
Tf
CLOCK
CPW
DSHOLD
DSVALID
/DS
EASET
EAHOLD
Valid Address Out
EA(2:0)
RD//WR
RDHOLD
RDSET
EXT(15:0)
Data In
Figure 7. Read Timing
TCY
CLOCK
WHOLD
WSET
WAIT
/DS
EA(2:0)
Valid Address Out
RD//WR
EXT(15:0)
Data In
Figure 8. External (EXT) Bus Read Timing Using WAIT Pin
14
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TIMING DIAGRAMS (Continued)
TCY
CLOCK
DSHOLD
DSVALID
/DS
EASET
EAHOLD
EA(2:0)
Valid Address Out
EAHOLD
WRHOLD
EASET
RD//WR
WRVALID
EXT(15:0)
Data Out
Figure 9. Write Timing
15
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Zilog
TCY
CLOCK
SSET
SCLK
FSSET
FSSET
FS0, FS1
TXSET
TXD
1
0
1
0
1
RXHOLD
RXSET
RXD
1
0
1
0
1
Figure 10. CODEC Interface Timing
TCY
CLOCK
INTSET
INT 0,1,2
INTWidth
PROGRAM
ADDRESS
Fetch N –1
Fetch N
Fetch N +1
Execute N
Fetch Int_Addr
Fetch I
Fetch I +1
EXECUTE
Execute N –1
CALL Int Routine
Execute Int Routine
Figure 11. Interrupt Timing
16
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TIMING DIAGRAMS (Continued)
TCY
CLOCK
HHOLD
HSET
HALT
Figure 12. HALT Timing
TCY
CLOCK
RSET
RRISE
/RESET
RWIDTH
INTERNAL
RESET
EXECUTE
RD/WR
/DS
Cycle 1
Cycle 2
Cycle 3
Cycle 4
Cycle 5
Code Execution
Cycle 0
UO0-1
EA0-2
EXT0-15
PA0-15
Tri-Stated
Tri-Stated
Access Reset Vector
RAM/
REGISTERS
Intact*
* The RAM and hardware registers are left intact
during a warm reset. A cold reset will produce
random data in these locations. The status
register is set to zeroes in both cases.
Figure 13. RESET Timing
17
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Zilog
TCY
CLOCK
PASET
PROGRAM
ADDRESS
Valid
Valid
Valid
PDSET
PDHOLD
PROGRAM
DATA
Valid
Valid
Valid
Figure 14. External Program Memory Port Timing
ADDRESS SPACE
Program Memory. Programs of up to 4 K words can be
masked into internal ROM (OTP for Z89371). Four loca-
tions are dedicated to the vector address for the three in-
terrupts (0FFDH-0FFFH) and the starting address follow-
ing a Reset (0FFCH). Internal ROM is mapped from 0000H
to 0FFFH, and the highest location for program is 0FFBH.
A 64 K word External Program Memory Space is available
on the Z89391. The vector addresses for the Z89391 re-
side at FFFCH-FFFFH (Figure 15).
lower byte of the internal 16-bit D-Bus and are used to per-
form modulo addressing.
Three addressing modes are available to access the Data
RAM: register indirect, direct addressing, and short form
direct. The contents of the RAM can be read to, or written
from, in one machine cycle per word, without disturbing
any internal registers or status other than the RAM ad-
dress pointer used for each RAM. The contents of each
RAM can be loaded simultaneously into the X and Y inputs
of the multiplier.
Internal Data RAM. The Z89321, 371 and 391 all have in-
ternal 512 x 16-bit word data RAM organized as two banks
of 256 x 16-bit words each: RAM0 and RAM1. Each data
RAM bank is addressed by three pointers: Pn:0 (n = 0-2)
for RAM0 and Pn:1 (n = 0-2) for RAM1. The RAM address-
es for RAM0 and RAM1 are arranged from 0-255 and 256-
511, respectively. The address pointers, which may be
written to, or read from, are 8-bit registers connected to the
Registers. The Z89321 has 19 internal registers and up to
an additional eight external registers. The external regis-
ters are user-definable for peripherals, such as A/D or D/A,
or to DMA, or other addressing peripherals. Both external
and internal registers are accessed in one machine cycle.
Program Memory
Data Memory
FFFF
FFFF
INT0-INT2 Vect. 64 Kwords
FFFC
RESET Vector
Not Used
Not Used
Or
4 Kwords
512 words
01FF
INT0-INT2 Vect.
RESET Vector
0FFF
0FFC
DRAM1
DRAM0
0100
00FF
0000
0000
On-Chip Memory
Off-Chip Memory
Figure 15. Memory Map
P R E L I M I N A R Y
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FUNCTIONAL DESCRIPTION
Instruction Timing. Most instructions are executed in one
machine cycle. Long immediate instructions and Jump or
Call instructions are executed in two machine cycles. A
multiplication or multiplication/accumulate instruction re-
quires a single cycle. Specific instruction cycle times are
described in the Condition Code section.
Note that all inputs to the multiplier should be fractional
twoÕs-complement, 16-bit binary numbers (Figure 16). This
puts them in the range [Ð1 to 0.9999695], and the result is
in 24 bits so that the range is [Ð1 to 0.9999999]. In addition,
if 8000H is loaded into both X and Y registers, the resulting
multiplication is considered an illegal operation as an over-
flow would result. Positive one cannot be represented in
fractional notation, and the multiplier will actually yield the
result 8000H x 8000H = 8000H (Ð1 x Ð1 = Ð1).
1
Multiply/Accumulate. The multiplier can perform a 16-bit
x 16-bit multiply, or multiply accumulate, in one machine
cycle using the Accumulator and/or both the X and Y in-
puts. The multiplier produces a 32-bit result, however, only
the 24 most significant bits are saved for the next instruc-
tion or accumulation. For operations on very small num-
bers where the least significant bits are important, the data
should first be scaled by eight bits (or the multiplier and
multiplicand by four bits each) to avoid truncation errors.
ALU. The ALU has two input ports, one of which is con-
nected to the output of the 24-bit Accumulator. The other
input is connected to the 24-bit P-Bus, the upper 16 bits of
which are connected to the 16-bit D-Bus. A shifter between
the P-Bus and the ALU input port can shift the data by
three bits right, one bit right, one bit left or no shift (Figure
17).
DDATA
XDATA
DDATA
16
X Register (16)
16
Mult. (24)
Shift Unit *
Y Register (16)
* Options:
16 24 24
MUX
24
1 Bit Right
3 Bits Right
No Shift
Multiplier
P Register (24)
1 Bit Left
24
24
24
Arithmetic Logic Unit (ALU)
24
Shift Unit *
24
* Options:
24
1 Bit Right
3 Bits Right
No Shift
MUX
24
Accumulator (24)
1 Bit Left
Figure 17. ALU Block Diagram
Figure 16. Multiplier Block Diagram
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Hardware Stack. A six-level hardware stack is connected
to the D-Bus to hold subroutine return addresses or data.
The Call instruction pushes PC+2 onto the stack, and the
RET instruction pops the contents of the stack to the PC.
I/O Bus. The processor provides a 16-bit, CMOS-compat-
ible bus. I/O Control pins provide convenient communica-
tion capabilities with external peripherals, and single-cycle
access is possible. For slower communications, an on-
board hardware wait-state generator can be used to ac-
commodate timing conflicts. Three latched I/O address
pins are used to access external registers. The EXT 4, 5,
6, 7 pins are used by the internal peripherals. Disabling a
peripheral allows access to these addresses for general-
purpose use.
User Inputs. The Z89321 has two inputs, UI0 and UI1,
which may be used by Jump and Call instructions. The
Jump or Call tests one of these pins and if appropriate,
jumps to a new location. Otherwise, the instruction be-
haves like a NOP. These inputs are also connected to the
status register bits S10 and S11, which may be read by the
appropriate instruction (Figure 8).
CODEC Interface. The multi-compatible, dual CODEC in-
terface provides the necessary control signals for trans-
mission of CODEC information to the DSP processor. The
interface accommodates 8-bit PCM or 16-bit Linear CO-
DECs. Special compatibility with Crystal Semiconductor's
4215/4216 CODECs provides the necessary interface for
audio applications. Many general-purpose 8-, 16-bit A/Ds,
D/As are adaptable. The interface can also be used as a
high-speed serial port.
User Outputs. The status register bits S5 and S6 connect
directly to UO0 and UO1 pins and may be written to by the
appropriate instruction. Note: The user output value is the
opposite of the status register content.
Interrupts. The Z89321 has three positive edge-triggered
interrupt inputs. An interrupt is acknowledged at the end of
an instruction execution. It takes two machine cycles to en-
ter an interrupt instruction sequence. The PC is pushed
onto the stack. A RET instruction transfers the contents of
the stack to the PC and decrements the stack pointer by
one word. The priority of the interrupts is INT0 = highest,
INT2 = lowest. INT1 is dedicated to the CODEC interface
and INT2 is dedicated to the 13-bit timer if both peripherals
are enabled. Note: The SIEF instruction enables the inter-
rupts. The SIEF instruction must be used before exiting an
interrupt routine since the interrupts are automatically dis-
abled when entering the routine.
m-Law Compression. The 8-bit CODEC interface mode
provides m-law compression from 13-bit format to 8-bit for-
mat. Decompression is performed in software by use of a
128-word lookup table.
Timer. Two programmable timers are available. One is
dedicated to the CODEC interface, the other for general-
purpose use. When a time-out event occurs, an interrupt
request is generated. Single pass and/or continuous
modes are available. If the CODEC interface is not used,
both timers can be used for general-purpose.
Registers. The Z89321 has 19 physical internal registers
and up to eight user-defined external registers. The EA2-
EA0 determines the address of the external registers. The
signals are used to read from or write to the external reg-
isters /DS, WAIT, RD//WR.
Note: Wait-State Generator. An internal wait-state
generator is provided to accommodate slow external
peripherals. A single wait-state can be implemented
through control registers EXT7-2. For additional states, a
dedicated pin (WAIT) can be held High. The WAIT pin is
monitored only during execution of a read or write
instruction to external peripherals (EXT bus).
Note: A WAIT pin is not available on the 40-pin DIP
package.
20
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REGISTERS
The internal registers are defined below:
EXTn are external registers (n = 0 to 7). There are eight
16-bit registers provided here for mapping external devic-
es into the address space of the processor. Note that the
actual register RAM does not exist on the chip, but would
exist as part of the external device, such as an ADC result
latch. Use of the CODEC interface and 13-bit timer reduc-
es the number of external registers to four.
1
Register
Register DeÞnition
P
Output of Multiplier, 24-bit
X
X Multiplier Input, 16-bit
Y
Y Multiplier Input, 16-bit
A
SR
Pn:b
PC
EXT4
EXT5-1
EXT5-2
EXT6-1
EXT6-2
EXT7-1
EXT7-2
Accumulator, 24-bit
Status Register, 16-bit
Six Ram Address Pointers, 8-bit each
Program Counter, 16-bit
13-Bit Timer ConÞguration Register
CODEC Interface Channel 0 Data
CODEC Interface Channel 0 Data
CODEC Interface Channel 1 Data
CODEC Interface Channel 1 Data
CODEC Interface ConÞguration Register
BUS is a read-only register which, when accessed, returns
the contents of the D-Bus. Bus is used for emulation only.
Dn:b refers to locations in RAM that can be used as a
pointer to locations in program memory which is efficient
for coefficient addressing. The programmer decides which
location to choose from two bits in the status register and
two bits in the operand. Thus, only the lower 16 possible
locations in RAM can be specified. At any one time, there
are eight usable pointers, four per bank, and the four point-
ers are in consecutive locations in RAM.
Wait-State Generator/CODEC Interface
ConÞguration Register
For example, if S3/S4 = 01 in the status register, then
D0:0/D1:0/D2:0/D3:0 refer to register locations 4/5/6/7 in
RAM Bank 0. Note that when the data pointers are being
written to, a number is actually being loaded to Data RAM,
so they can be used as a limited method for writing to
RAM.
The following are virtual registers as physical RAM does
not exist on the chip.
Register
Register DeÞnition
SR is the status register, which contains the ALU status
and certain control bits (Table 5).
EXTn
BUS
Dn:b
External Registers, 16-bit
D-Bus
Eight Data Pointers*
Table 5. Status Register Bit Functions
Note: * These occupy the first four locations in RAM bank.
Status Register Bit
Function
P holds the result of multiplications and is read-only.
S15 (N)
ALU Negative
S14 (OV)
S13 (Z)
S12 (L)
S11 (UI1)
S10 (UI0)
S9 (SH3)
ALU Overßow
ALU Zero
Carry
User Input 1
X and Y are two 16-bit input registers for the multiplier.
These registers can be utilized as temporary registers
when the multiplier is not being used.
User Input 0
A is a 24-bit Accumulator. The output of the ALU is sent to
this register. When 16-bit data is transferred into this reg-
ister, it is placed into the 16 MSBs and the least significant
eight bits are set to zero. Only the upper 16 bits are trans-
ferred to the destination register when the Accumulator is
selected as a source register in transfer instructions.
MPY Output Arithmetically
Shifted Right by Three Bits
Overßow Protection
Interrupt Enable
User Output 1
User Output 0
ÒShort Form DirectÓ bits
RAM Pointer Loop Size
S8 (OP)
S7 (IE)
S6 (UO1)
S5 (UO0)
S4-S3
Pn:b are the pointer registers for accessing data RAM, (n
= 0,1,2 refer to the pointer number) (b = 0,1 refers to RAM
Bank 0 or 1). They can be directly read from or written to,
and can point to locations in data RAM or Program Mem-
ory.
S2-S0 (RPL)
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The status register can always be read in its entirety. S15-
S10 are set/reset by hardware and can only be read by
software. S9-S0 control hardware looping and can be writ-
ten by software (Table 6).
S15-S12 are set/reset by the ALU after an operation. S11-
S10 are set/reset by the user inputs. S6-S0 are control bits
described in Table 5. S7 enables interrupts. If S8 is set, the
hardware clamps at maximum positive or negative values
instead of overflowing. If S9 is set and a multiple/shift op-
tion is used, then the shifter shifts the result three bits right.
This feature allows the data to be scaled and prevents
overflows.
Table 6. RPL Description
S2
S1
S0
Loop Size
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
256
2
4
PC is the Program Counter. When this register is assigned
as a destination register, one NOP machine cycle is added
automatically to adjust the pipeline timing.
8
16
32
64
128
External Register, EXT4-EXT7, are used by the CODEC
interface and 13-bit timer, the registers are reviewed in the
CODEC interface section.
N
OV
Z
C
UI1 UI0 SH3 OP IE UO1 UO0
RPL
S15 S14 S13 S12 S11 S10 S9 S8
S7 S6 S5 S4 S3
S2 S1 S0
Ram Pointer Loop Size
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
256
2
4
8
16
32
64
128
"Short Form Direct" bits
User Output 0-1*
Interrupt Enable
Overflow protection
MPY output arithmetically shifted
right by three bits
User Input 0-1 (Read Only)
Carry
Zero
Overflow
Negative
* The output value is the opposite of the status register content.
Figure 18. Status Register
22
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PERIPHERAL OPERATION
Disabling Peripherals
Disabling a peripheral (CODEC Interface, Counter) allows
general-purpose use of the EXT address for the disabled
peripheral. If the peripheral is not disabled, the EXT control
signals and EXT data are still provided, but transfer of data
on the EXT pins is not available (because internal transfers
are being processed on the internal bus). Care must be
taken to ensure that control of the EXT bus does not cause
bus conflicts.
EXT5-1 before being transferred along the internal data
bus of the processor. This is accomplished by writing data
to EXT5-2.
1
Writing Data to CODEC Interface
Internal data is transferred from the internal data bus of the
processor to the EXT5-2 register. The CODEC interface
constantly transfers and receives data during normal oper-
ation. Data to be transferred is loaded to EXT5-2 and is au-
tomatically serially transferred.
Reading Data from CODEC Interface*
Note: EXT5-1 and EXT5-2 are used in the example, but
this information applies equally to EXT6-1 and EXT6-2.
(Refer to Figure 20, CODEC Block Diagram.)
External data is serially transferred into the CODEC inter-
face registers from an external CODEC. This serial data is
loaded into EXT5-2 (8- or 16-bit modes). Because the in-
terface is double-buffered, data must be transferred to
Internal 16-Bit Bus
16
16
EXT7-2
EXT7-1
EXT7-1 CODEC Timer Register
EXT7-2 Wait-State Register
Figure 19. EXT7 Register ConÞguration
LOADING EXT7
Because EXT7 is double-buffered, a pair of writes are per-
formed when loading the EXT7 registers (Figure 19).
Interrupts
The Z89321 features three interrupts:
LD EXT7, #%54F4
LD EXT7, #%6CDA
LD @P0:0, EXT7
Loads CODEC Timer Register
Loads Wait-State Register
Reads EXT7-1 and places
data in RAM
INT0
INT1
INT2
General-Purpose
CODEC Interface
13-Bit Timer
If all peripherals are enabled, INT0 (general-purpose) can
be used.
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CODEC Interface
CODEC Interface Control Signals
The CODEC Interface provides direct-connect capabilities
for standard 8-, 16-bit CODECs. The interface also sup-
ports 8-bit PCM, 8-bit PCM with hardware m-law conver-
sion (m-law expansion is done in software), 16-bit Linear
and Crystal's Sigma-Delta Stereo CODEC modes. Regis-
ters are used to accommodate the CODEC Interface
(EXT5, EXT6 and EXT7). The CODEC interface provides
two Frame Sync signals, which allows two channels of
data for transmission/receiving.
SCLK (Serial Clock)
The Serial Clock provides a clock signal for operating the
external CODEC. A 4-bit prescaler is used to determine
the frequency of the output signal.
SCLK = (0.5* CLK)/PS
where: CLK = System Clock
PS = 4-bit Prescaler*
* The Prescaler is an up-counter.
Note: An internal divide-by-two is performed before the
clock signal is passed to the Serial Clock prescaler.
CODEC Interface Hardware
The CODEC Interface hardware uses six 16-bit registers,
m-law compression logic and general-purpose logic to con-
trol transfers to the appropriate register (Figure 20).
Data Bus
16
16
16
m-Law
Compression
EXT5-1
EXT6-1
CLKIN
EXT7-1
CLKIN
16
16
16
16
EXT5-2
EXT6-2
CLKIN
EXT7-2
CLKIN
CLKIN
CONTROL
LOGIC
TXD
RXD
Figure 20. CODEC Interface Block Diagram
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TXD (Serial Output to CODEC)
FS0, FS1 (Frame Sync)
The TXD line provides 8-, 16-, and 64-bit data transfers.
Each bit is clocked out of the processor by the rising edge
of the SCLK, with the MSB transmitted first.
The Frame Sync is used for enabling data transfer/receive.
The rising and falling edge of the Frame Sync encloses the
serial data transmission.
1
RXD (Serial Input from CODEC)
Interrupt
The RXD line provides 8-, 16-, and 64-bit data transfers.
Each bit is clocked into the processor by the falling edge of
the SCLK, with the MSB received first.
Once the transmission of serial data is completed an inter-
nal interrupt signal is initiated. A single-cycle Low pulse al-
lows an interrupt on INT1. When this occurs, the processor
will jump to the defined Interrupt 1 vector location (Figure
21).
int1_
fs1
fs0
sclk
txd
rxd
Figure 21. CODEC Interface Timing (8-Bit Mode)
CODEC INTERFACE TIMING
Figure 21 depicts a typical 8-bit serial data transfer using
both of the CODEC Interface Channels. The transmitting
data is clocked out on the rising edge of the SCLK signal.
An external CODEC clocks data in on the falling edge of
the SCLK signal. Once the serial data is transmitted, an in-
terrupt is given. The CODEC interface signals are not initi-
ated if the CODEC interface is not enabled.
Full Duplex Operation
The Transmit and Receive lines are used for transfer of se-
rial data to or from the CODEC interface. The CODEC in-
terface performs both data transmit and receive simulta-
neously.
Control Registers
The following modes are available for FSYNC and SCLK
signals:
The CODEC interface is double-buffered, therefore, four
registers are provided for CODEC interface data storage.
EXT5-1 and EXT5-2 operate with the Frame Sync 0 while
EXT6-1 and EXT6-2 operate with Frame Sync 1. In 8- or
16-bit mode, the CODEC interface uses EXT5-1 and
EXT6-1. For Stereo mode, all four registers are used (Fig-
ures 22 and 23).
SCLK
FSYNC
Internal
External
External
Internal
Internal
External
Internal
External
The CODEC Interface Control Register (EXT7-1) is shown
in Figure 14. Setting of the CODEC mode, FSYNC, and
Enable/Disable of CODEC 0 is done through this register.
The Wait-State Generator, SCLK, and CODEC 1 are con-
trolled from EXT7-2 (Figure 24).
The CODEC interface timing is independent of the proces-
sor clock when external mode is chosen. This feature pro-
vides the capability for an external device to control the
transfer of data to the Z89321. The Frame Sync signal en-
velopes the transmitted data, therefore care must be taken
to ensure proper sync signal timing (Figure 21).
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5-1
D5
D5
D6
D6
D0
D0
D15 D14 D13 D12 D11 D10 D9
D7
D7
D1
D1
D8
D8
D2
D2
D3
D3
D4
D4
Data Bits 15-0
Data Bits 15-0
5-2
D15 D14 D13 D12 D11 D10 D9
Figure 22. CODEC Interface Data Registers (Channel 0)
6-1
D5
D5
D6
D6
D0
D0
D15 D14 D13 D12 D11 D10 D9
D7
D7
D1
D1
D8
D8
D2
D2
D3
D3
D4
D4
Data Bits 15-0
Data Bits 15-0
6-2
D15 D14 D13 D12 D11 D10 D9
Figure 23. CODEC Interface Data Registers (Channel 1)
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REGISTERS
1
EXT7-1
D15 D14 D13 D12 D11 D10 D9
D8 D7
D6 D5
D4 D3
D2 D1
D0
SCLK Prescaler (up-counter)
SCLK/FSYNC Ratio Prescaler (up-counter)
CODEC Mode
00 8-bit with hardware m-law
01 8-bit without hardware m-law
10 16-bit linear
11 Crystal CS4215 / CS4216
FSYNC
0
1
External Source*
Internal Source
CODEC 0 Disable/Enable
Note: The timer is an up-counter.
0 = Disable*
1 = Enable
Example: EXT7-1 = #%x00D
EXT7-1 = #%x80F
OSC = 12.288 MHz, SCLK = 2.048 MHz, FSYNC = 8 kHz
OSC = 12.288 MHz, SCLK = 6.144 MHz, FSYNC = 48 kHz
No interrupt
EXT7-1 = #%xFFx
* Default
EXT7-1 = #%x000
Max interrupt period (667 ms for OSC = 12.288 MHz)
Figure 24. CODEC Interface Control Register
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EXT7-2
D15 D14 D13 D12 D11 D10 D9
D8 D7
D6 D5
D4 D3
D2 D1
D0
Wait State EXT0
Wait State EXT1
nws - no wait states
ws - one wait states
00 no wait states (nws)
Wait State EXT2
01 read (nws), write (ws)
10 read (ws), write (nws)
11 read (ws), write (ws)
Wait State EXT3
Wait State EXT4
Wait State EXT5
Wait State EXT6
SCLK
0
1
External Source*
Internal Source
CODEC 1 Disable/Enable
0 = Disable*
1 = Enable
*Default
Figure 25. WSG, SCLK and CODEC Interface Control Register
28
P R E L I M I N A R Y
DS97DSP0100
Z89321/371/391
16-Bit Digital Signal Processors
Zilog
A/D Accommodation
High-Speed Serial Port
The CODEC interface can be used for serial A/D or serial
D/A transmission. The interface provides the necessary
control signals to adapt to many standard serial convert-
ers. The low-pass and smoothing filters are necessary for
systems with converters.
The Z89321 CODEC interface can be used as a high-
speed serial port. The necessary control signals are pro-
vided for adaptation to standard processors or external pe-
ripherals. Byte, word, or 64-bit data can be transmitted at
speeds up to 10 Mbps. (Condition includes a 20 MHz os-
cillator. Data can be transferred with single-cycle instruc-
tions to an internal register file.)
1
Z89321/371/391
Serial A/D
SCLK
FSO
CLKIN
Low-Pass
Filter
Analog
In
Communicate
Data
Serial
Data Out
FS1
RXD
TXD
Serial A/D
CLKIN
Smoothing
Filter
Analog
Out
Serial
Data In
Communicate
Data
Figure 26. A/D, D/A Implementation Block Diagram
Table 7. Tabulated Transmission Rates*
8-Bit CODEC Interface
The Z89321 provides an option for a standard 8-bit CO-
DEC interface. Hardware m-law compression is available
(expansion performed by software lookup table). The CO-
DEC interface transmits data consisting of 8-bit or com-
pounded 8-bit information. Figure 27 shows a typical sche-
matic arrangement.
Transmission
Rate
Maximum SCLK
Maximum Frame Sync
8-bit
10 Mbps
769.2 kHz
476.2 kHz
263.2 kHz
16-bit
Stereo (64-bit)
The timing for this type of arrangement is presented in Fig-
ure 28. The flexible design provides adaptation for 16-bit
linear CODEC.
Note: Calculations consider the interrupt access time (typically
four cycles), transfer of data, loading of new data, and latency pe-
riods between CODEC transfers. During the interrupt cycle, de-
velopers often execute additional software, affecting the
maximum transfer rate. Calculations are for single-channel trans-
fers only.
DS97DSP0100
P R E L I M I N A R Y
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Zilog
Z89321
/371
/391
VCC
MC145505p
16
Analog
Out
TXD
RXD
VDD
RDD
RCE
DC
1
2
3
4
5
6
7
8
VAG
Rx0
+Tx
Txl
15
14
13
12
11
10
9
10k
5k
Analog
In
SCLK
FS1
CCI
–Tx
Mu/A
PDI
VSS
VCC
TDD
TDE
VLS
GND
–5V
Figure 27. 8-Bit CODEC Schematic
int1_
fs1
fs0
sclk
txd
rxd
Figure 28. 8-Bit Mode Timing Diagram
30
P R E L I M I N A R Y
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Zilog
For data acquisition systems, designers may opt for a 16-
bit serial A/D. A block diagram of the Z89321 with the
AD1876 16-bit 100 Kbps sampling ADC is shown in Figure
30.
16-Bit Linear CODEC Interface
For higher precision transmissions, a 16-bit linear CODEC
is used, however, data is not compressed in this mode of
transmission. The Z89321 provides accommodation for
two channels of 16-bit transmission (Figure 29).
1
int1_
fs1
fs0
sclk
txd
rxd
Figure 29. 16-Bit Mode Timing Diagram
Z89321/371/391
AD 1876
Anti-Alias
Filtered
Analog
Signal
UO0
Sample
CLK
SCLK
RxD
Dout
Vin
Busy
FS1
16-Bit A/D
Figure 30. 16-Bit Mode Timing Diagram
DS97DSP0100
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Zilog
A key feature of the Z893XX DSP product family is that it
adapts easily to other stereo CODECs, including Crystal
Semiconductor's CS4215 and CS4216 devices (Figure
31).
Stereo CODEC Interface
The Z893XX DSP product family CODEC interface pro-
vides direct connection to other CODECs for master or
slave modes, supporting 64 bits of transmission data (16
bits right channel, 16 bits left channel, and 32 bits of con-
figuration information). This configuration information con-
sists of input gain, input MUX, output attenuation, ADC
clipping, and mute and error functions of the CODECs.
The 64 bits of data transferred from the CODEC are placed
in four registers, EXT5-1, 5-2, 6-1, and 6-2 (Figure 32 ).
Ferrite Bead
2.0
+5V
Supply
+
+
0.1 mF 1 mF
0.1 mF 1 mF
24
VA
4
VD
0.47mF
26
150
Audio
Out
³ 1.0 mF
40k
+
15
16
Channel 2
Input
RIN2
ROUT
(Right)
600
600
0.01mF
NPO
0.0022mF
NPO
0.47mF
28
150
³ 1.0 mF
Audio
Out
(Left)
+
Channel 2
Input
LIN2
LOUT
40k
0.01mF
NPO
0.0022mF
NPO
CS4216
Z89321
/371/391
21
22
REFBYP
+
0.47mF
27
150
10mF
0.1mF
Channel 1
Input
RIN1
REFGND
0.01mF
43
42
44
1
SCLK
NPO
SSYNC
SDIN
0.47mF
27
150
SDOUT
SCLK
FS0
Channel 1
Input
LIN1
32
31
SMODE2
SFS1
TxD
0.01mF
NPO
Mode
Setting
RxD
30
29
SFS2
SMODE1
Figure 31. Z893XX and CS4216 CODEC Interface
32
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16-Bit Digital Signal Processors
Zilog
int1_
1
fs1
fs0
64 bits transferred
sclk
txd
rxd
Figure 32. CODEC Stereo Mode Timing Diagram
The counter is defaulted to the enable state, but if it is not
needed, it can be disabled. However, once disabled, the
counter cannot be enabled unless a reset of the processor
is performed.
16-Bit General-Purpose Timer
The 13-bit counter/timer is available for general-purpose
use. When the counter counts down to the zero state, an
interrupt is received on INT2. If the counter is disabled,
EXT4 can be used as a general-purpose address. The
counting operation of the counter can be disabled by reset-
ting bit 14. Selection of the clock source allows the ability
to extend the counter value past the 13 bits available in the
control register. Use of the CODEC counter output can ex-
tend the counter to 26 bits (see Figure 33).
Example:
LD EXT, #%C008 ;1100 0000 0000 1000
; Enable Counter
; Enable Counting
; Clock Source = OSC/2
; Count Value = 1000 = 8
; Interrupt will occur every
16 clock cycles
Note: Placing zeroes into the count value register does
not generate an interrupt. Therefore, it is possible to have
a single-pass option by loading the counter with zeroes
after the start of count.
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Zilog
ADDRESSING MODES (Continued)
EXT4
D15 D14 D13 D12 D11 D10 D9
D8 D7
D6 D5
D4 D3
D2 D1
D0
Count Value (Down-Counter)
Clock Source
0 Oscillator/2*
1 CODEC Counter Output
Count Operation
0 = Disable*
1 = Enable
Counter
0 = Disable
1 = Enable*
* Default State
Figure 33. CODEC Timer Register
ADDRESSING MODES
This section discusses the syntax of the addressing
modes supported by the DSP assembler.
Table 8. Addressing Modes
Symbolic Name
Syntax
Description
<pregs>
<dregs> (Points to RAM)
<hwregs>
Pn:b
Dn:b
Pointer Register
Data Register
X,Y,PC,SR,P , EXTn, A, BUS Hardware Registers
Accumulator Memory Indirect
<accind> (Points to Program Memory @A
<direct>
<expression>
Direct Address Expression
<limm>
<simm>
<regind> (Points to RAM)
#<const exp>
#<const exp>
@Pn:b
Long (16-bit) Immediate Value
Short (8-bit) Immediate Value
Pointer Register Indirect
@Pn:b+
@Pn:bÐLOOP
@Pn:b+LOOP
Pointer Register Indirect with Increment
Pointer Register Indirect with Loop Decrement
Pointer register Indirect with Loop Increment
Pointer Register Memory Indirect
Data Register Memory Indirect
<memind> (Points to Program Memory) @@Pn:b
@Dn:b
@@Pn:bÐLOOP
Pointer Register Memory Indirect with Loop
Decrement
@@Pn:b+LOOP
@@Pn:b+
Pointer Register Memory Indirect with Loop
Increment
Pointer Register Memory Indirect with Increment
34
P R E L I M I N A R Y
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16-Bit Digital Signal Processors
Zilog
There are eight distinct addressing modes for data trans-
fer.
specified by a value in RAM, and the location of the RAM
is in turn specified by the value in the pointer. Note that the
data pointer can also be used for a memory access in this
manner, but only one Ò@Ó precedes the pointer. In both
cases, the memory address stored in RAM is incremented
by one, each time the addressing mode is used, to allow
easy transfer of sequential data from program memory.
<pregs>, <hwregs> These two modes are used for sim-
ple loads to and from registers within the chip, such as
loading to the Accumulator, or loading from a pointer reg-
ister. The names of the registers need only be specified in
the operand field (destination first, then source).
1
<accind> Similar to the previous mode, the address for
the program memory read is stored in the Accumulator.
@A in the second operand field loads the number in mem-
ory specified by the address in A.
<regind> This mode is used for indirect accesses to the
data RAM. The address of the RAM location is stored in
the pointer. The Ò@Ó symbol indicates ÒindirectÓ and pre-
cedes the pointer, therefore @P1:1 instructs the processor
to read or write to a location in RAM1, which is specified by
the value in the pointer.
<direct> The direct mode allows read or write to data
RAM from the Accumulator by specifying the absolute ad-
dress of the RAM in the operand of the instruction. A num-
ber between 0 and 255 indicates a location in RAM0, and
a number between 256 and 511 indicates a location in
RAM1.
<dregs> This mode is also used for accesses to the data
RAM, but only the lower 16 addresses in either bank. The
4-bit address comes from the status register and the oper-
and field of the data pointer. Note that data registers are
typically used not for addressing RAM, but loading data
from program memory space.
<limm> This address mode indicates a long immediate
load. A 16-bit word can be copied directly from the operand
into the specified register or memory.
<memind> This mode is used for indirect accesses to the
program memory. The address of the memory is located in
a RAM location, which is specified by the value in a point-
er. Therefore, @@P1:1 instructs the processor to read
(write is not possible) from a location in memory, which is
<simm> This address mode can only be used for imme-
diate transfer of 8-bit data in the operand to the specified
RAM pointer.
CONDITION CODES
The following Instruction Description defines the condition
codes supported by the DSP assembler.
If the instruction description refers to the <cc> (condition
code) symbol in one of its addressing modes, the instruc-
tion will only execute if the condition is true.
Code
Description
Code
Description
C
Carry
NU1
NZ
Not User One
Not zero
EQ
F
Equal (same as Z)
False
OV
PL
U0
U1
UGE
Overßow
Plus (Positive)
User Zero
IE
MI
Interrupts Enabled
Minus
No Carry
Not Equal (same as NZ)
Not Interrupts Enabled
Not Overßow
Not User Zero
NC
NE
NIE
NOV
NU0
User One
Unsigned Greater Than or
Equal (Same as NC)
Unsigned Less Than (Same as C)
Zero
ULT
Z
DS97DSP0100
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Zilog
PACKAGE INFORMATION
Figure 34. 40-Pin Package Diagram
Figure 35. 44-Pin PLCC Package Diagram
P R E L I M I N A R Y
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DS97DSP0100
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16-Bit Digital Signal Processors
Zilog
1
Figure 36. 44-Pin QFP Package Diagram
Figure 37. 84-Pin PLCC Package Diagram
P R E L I M I N A R Y
DS97DSP0100
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16-Bit Digital Signal Processors
Zilog
ORDERING INFORMATION
Z89321
Z89371
Z89391
20 MHz
16 MHz
20 MHz
44-Pin PLCC
Z8932120VSC
44-pin PLCC
Z8937116VSC
84-Pin PLCC
Z8939120VSC
20 MHz
16 MHz
40-Pin DIP
Z8932120PSC
40-Pin DIP
Z8937116PSC
20 MHz
16 MHz
44-Pin QFP
Z8932120FSC
44-Pin QFP
Z8937116FSC
For fast results, contact your local Zilog sales office for assistance in ordering the part desired.
CODES
Package
Speed
20 = 20 MHz
16 = 16 MHz
P= Plastic DIP
V = Plastic PLCC
F = Plastic QFP
Environmental
Temperature
C = Plastic Standard
S = 0°C to +70°C
E = -40°C to 85°C
Example:
Z 89321 20 V S C
is a Z89321, 20 MHz, PLCC, 0°C to +70°C, Plastic Standard Flow
Environmental Flow
Temperature
Package
Speed
Product Number
Zilog Prefix
38
P R E L I M I N A R Y
DS97DSP0100
Z89321/371/391
16-Bit Digital Signal Processors
Zilog
1
© 1997 by Zilog, Inc. All rights reserved. No part of this
document may be copied or reproduced in any form or by
any means without the prior written consent of Zilog, Inc.
The information in this document is subject to change
without notice. Devices sold by Zilog, Inc. are covered by
warranty and patent indemnification provisions appearing
in Zilog, Inc. Terms and Conditions of Sale only. Zilog, Inc.
makes no warranty, express, statutory, implied or by
description, regarding the information set forth herein or
regarding the freedom of the described devices from
intellectual property infringement. Zilog, Inc. makes no
warranty of merchantability or fitness for any purpose.
Zilog, Inc. shall not be responsible for any errors that may
appear in this document. Zilog, Inc. makes no commitment
to update or keep current the information contained in this
document.
ZilogÕs products are not authorized for use as critical
components in life support devices or systems unless a
specific written agreement pertaining to such intended use
is executed between the customer and Zilog prior to use.
Life support devices or systems are those which are
intended for surgical implantation into the body, or which
sustains life whose failure to perform, when properly used
in accordance with instructions for use provided in the
labeling, can be reasonably expected to result in
significant injury to the user.
Zilog, Inc. 210 East Hacienda Ave.
Campbell, CA 95008-6600
Telephone (408) 370-8000
FAX 408 370-8056
Internet: http://www.zilog.com
DS97DSP0100
P R E L I M I N A R Y
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Zilog
40
P R E L I M I N A R Y
DS97DSP0100
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