Z8E520SSC_技术文档

PRELIMINARY PRODUCT SPECIFICATION

Z8E520/C520

1

1.5 MBPS USB LOW-POWER

DEVICE CONTROLLER FOR

MULTIPROTOCOL POINTING DEVICES

FEATURES

■ Software Programmable Timers Configurable as:

Part

ROM

(KB)

RAM

Speed

(MHz)

–

Two 8-Bit Standard Timers and One 16-Bit

Number

(Bytes)

Standard Timer or

Z8E520 (OTP)

Z8C520 (ROM)

6

176

12

–

One 16-Bit Standard Timer and One 16-Bit Pulse

Width Modulator (PWM) Timer

■ Six Vectored Interrupts with Fixed Priority

■ Identical Masked ROM Version (Z8C520)

■ Processor Speed Dividable by Firmware Control

■ On-Chip Oscillator that accepts a Ceramic Resonator or

External Clock

■ Operating Current: 5 mA typical in USB Mode; 2.5 mA

typical in Serial Mode (@ 3 MHz); 5 mA typical in PS/2

Mode

■ Hardware Support for PS/2, Serial, USB, and General-

Purpose I/O (GPIO)

■ 16 Total Input/Output Pins (Open-Drain/Push-Pull)

■ Power Reduction Modes:

Configurable

–

STOP Mode (functionality shut down except SMR)

HALT Mode (XTAL still running-peripherals active)

■ 6 inputs with 3 level Programmable Reference

Comparators

■ USB SIE Compliant with USB Spec 1.0

■ 16-Bit Programmable Watch-Dog Timer (WDT) with

■ 4.0 VDC to 6.0 VDC Operating Range @ 0°C to +70°C

Internal RC Oscillator

GENERAL DESCRIPTION

Zilog’s Z8E520 (OTP) and Z8C520 (Masked ROM) micro-

The microcontroller clock frequency is derived from the

system clock by a programmable divider under firmware

control.

Plus

controllers are low-power Z8

MCUs, designed for the

cost-effective implementation of USB and multiprotocol

pointing devices.

The device is capable of functioning in four distinct, select-

able communications modes: PS/2, RS232, GPIO (Gener-

al-purpose I/O), and USB. The communications mode de-

termines the functionality of the two special serial

communications pins (PB6 and PB7). The device is placed

in the required mode when firmware sets the specified

mode bit in the communications control register. The firm-

ware interface is similar in all modes. The same buffer area

in RAM will accept the data to be transmitted. Up to 8 bytes

may be loaded, and the data will actually be transmitted as

soon as the appropriate command is issued (setting In

Packet Ready in USB mode, for example).

For applications demanding powerful I/O capabilities, the

Z8E520's input and output lines are grouped into two ports,

and are configurable under software control to provide tim-

ing, status signals, or parallel I/O.

Both 8-bit and 16-bit timers, with a large number of user se-

lectable modes, off-load the system of administering real-

time tasks such as counting/timing and I/O data communi-

cations.

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GENERAL DESCRIPTION (Continued)

Power connections follow conventional descriptions at

right:

Connection

Power

Circuit

Device

V

CC

DD

V

Ground

GND

SS

Ceramic Resonator

GND

V

CC

Two 8-bit Timers

or

Machine Timing

& Inst. Control

One 16-bit PWM

Timer

Port B

(6–7)

ALU

One 16-bit

Std. Timer

FLAG

6 K Bytes

ZIE

Prg. Memory

Interrupt

Control

Register

Pointer

Program

Counter

6 Analog

Comparators

RAM

Register File

(160 Bytes)

WDT

Port A

I/O

Port B

I/O

INTERNAL

RC OSC

Figure 1. Z8E520 Functional Block Diagram

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COMMUNICATION MODES

The Z8E520/C520 allows its user to function in a variety of

communication modes. Having this freedom within a sin-

gle chip opens up many possibilities when utilizing multiple

protocol applications. The modes incorporated into the

Z8E520/C520 include PS/2, RS232, GPIO, and USB. A

description of each mode is detailed below.

GPIO Mode. In General-Purpose I/O Mode, the serial

communications pins function as standard I/O pins, with

Input, Output P/P (Push/Pull) and OD (Open Drain) Out-

put.

1

USB Mode. The Z8E520 includes two bidirectional end-

points that support communications compliant to the USB

Specification version 1.0. The serial communications pins

function as D– (PB6) and D+ (PB7). The detailed behavior

of the SIE is controllable by the firmware, and three sepa-

rate power states are provided for USB Suspend Mode

support (see section below).

PS/2 Mode. The serial baud rate is fixed at 12.5 K baud.

Received data is automatically checked for parity and

framing errors while HOST abort is supported. The serial

communications pins function as PS/2 compatible DATA

(PB6) and CLOCK (PB7).

RS232 Mode. The data rate is fixed at 1200 baud. The se-

rial communications pins function as RxD (PB6) and TxD

(PB7).

USB SUSPEND/RESUME FUNCTIONALITY

Suspend is dedicated through firmware by timing the Ac-

tivity bit which is set by the SIE.

or Resume from the host can be detected and used to

wake up the microcontroller.

In Stop Mode, with the WDT disabled, power requirements

In Stop Mode, with the WDT enabled, slightly more power

is consumed, but the device can wake up periodically to

perform maintenance and detect a change of state in the

application.

are minimized. No power is consumed by the voltage reg-

Plus

ulator, the Z8

core, nor differential detector. Only the

Stop Mode Recovery (SMR) is enabled, so an input signal

USB FUNCTIONAL BLOCK DESCRIPTION

The USB portion of the chip is divided into two areas, the

transceiver and the Serial Interface Engine (SIE). The

transceiver handles incoming differential signals and “sin-

gle ended zero (SE0)”. It also converts output data in digi-

tal form to differential drive at the proper levels (Figure 2).

the host. Data flow into and out of the MCU portions are

dedicated registers mapped into Expanded Register File

Memory.

The USB SIE handles three endpoints (control at Endpoint

0, data into the host from Endpoint 1 and data out from the

host as Endpoint 2). All communications are at the

1.5 MB/sec data rate. Endpoint 1 and 2 can be combined

as Control EP1.

The SIE performs all other processing on incoming and out

going data, including signal recovery timing, bit stuffing,

validity checking, data sequencing, and handshaking to

Figure 2. Data To/From Z8E520/C520

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PIN IDENTIFICATION

1

PA6

PA7

PB0

PB1

PB2

PB3

PB4

PB5

PA0

PA1

20

PA5

PA4

XTAL (2)

GND

XTAL (1)

VCC

PB7

PB6

PA3

PA2

20-Pin

DIP/SOIC

10

11

Figure 3. 20-Pin DIP/SOIC Pin Assignments

Table 1. 20-Pin DIP/SOIC Pin Identiﬁcation

STANDARD Mode

Pin #

Symbol

Function

Direction

1, 2

PA X(6,7)

PB X(0–5)

PA X(0–3)

PB X (6–7)

Digital I/O + I SINK

Digital I/O +Comparators

Digital I/O

Bidirectional

3–8

9–12

13–14

15

Digital I/O + Communications

Power

V

cc

16

XTAL (1)

GND

Clock

Power

17

18

XTAL (2)

PA X(4,5)

Clock

19, 20

Digital I/O + I SINK

Bidirectional

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1

D0

D1

20

1

D2

D3

D4

D5

CLK (1 MHz)

GND

(CLK OUT)

VCC

20-Pin

DIP/SOIC

D6

D7

TST_CLR

PGM

VPP

ADDRCLK

10

11

Figure 4. 20-Pin DIP/SOIC Pin Assignments:

EPROM Programming Mode

Table 2. 20-Pin DIP/SOIC Pin Identiﬁcation:

EPROM Programming Mode

EPROM PROGRAMMING Mode

Pin #

Symbol

D0–D7

Function

Direction

1–8

9

Data Bus

I/O

In

TST_CLR

PGM

Reset Internal Address Counter

Program Pin

10

11

12

In

ADDRCLK

Clock to Address Counter

High Voltage to Program Device

In

V

Power

PP

13–14

15

Unused

Power

V

Power

CC

16

17

18

19

20

CLKOUT

GND

Output from Clock Inverter

Power Ref

Out

Power

In

CLK

1 MHz to chip

Unused

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ABSOLUTE MAXIMUM RATINGS

Stresses greater than those listed under Absolute Maxi-

mum Ratings may cause permanent damage to the de-

vice. This rating is a stress rating only; functional operation

of the device at any condition above those indicated in the

operational sections of these specifications is not implied.

Exposure to absolute maximum rating conditions for an

extended period may affect device reliability. Total power

dissipation should not exceed 880 mW for the package.

Power dissipation is calculated as follows:

Total Power Dissipation =

V

x [I – (sum of I )]

DD DD OH

+ sum of [(V – V ) x I ]

OH

DD

OH

+ sum of (V x I

)

0L

Parameter

Min

Max

Units

Note

Ambient Temperature under Bias

Storage Temperature

–40

–65

–0.6

+105

+150

+7

C

V

Voltage on any Pin with Respect to V

SS

Voltage on V Pin with Respect to V

–0.3

+7

V

DD

SS

Total Power Dissipation

880

80

mW

mA

Maximum Allowable Current out of V

SS

Maximum Allowable Current into V

80

mA

DD

Maximum Allowable Current into an Input Pin

Maximum Allowable Current into an Open-Drain Pin

–600

+600

25

µA

1

2

Maximum Allowable Sink Output Current by Any I/O Pin

Maximum Allowable Source Output Current by Any I/O Pin

Maximum Allowable Sink Output Current by Port A

Maximum Allowable Source Output Current by Port A

Maximum Allowable Sink Output Current by Port B

Maximum Allowable Source Output Current by Port B

mA

25

40

Notes:

1. Excludes XTAL pins.

2. Device pin is not at an output Low state.

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STANDARD TEST CONDITIONS

The characteristics listed here apply for standard test con-

ditions as noted. All voltages are referenced to GND. Pos-

itive current flows into the referenced pin (Figure 5).

From Output

Under Test

1

150 pF

Figure 5. Test Load Diagram

CAPACITANCE

T_A= 25°C; V_CC= GND = 0V; f = 1.0 MHz; unmeasured pins returned to GND.

Parameter

Max

Input Capacitance

12 pF

Output Capacitance

I/O Capacitance

Note: Frequency tolerance ±10%

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DC CHARACTERISTICS: USB MODE

V = 4.4V – 5.25V

cc

T = 0°C to +70°C

A

V

Sym

Parameter

Min

0.7V

Max

V +0.3

CC

Units Conditions

Notes

CC

V

Clock Input High

Voltage

V

Driven by External

CH

CC

Clock Generator

V

Clock Input Low

Voltage

V

–0.3

0.2V

V

Driven by External

Clock Generator

CL

SS

CC

V

Input High Voltage

Input Low Voltage

0.7V

V +0.3

CC

V

IH

CC

V_SS–0.3

V_CC–0.4

0.2V_CC

IL

Output High Voltage

(Port A, B)

I_OH= –2.0 mA

I_OL= +4.0 mA

I_OL= +6 mA,

OH

V

Output Low Voltage

(Port A, B)

0.6

1.2

V

4

OL1

Output Low Voltage

(Port A, B)

OL2

Comparator Input Offset

Voltage

25.0

mV

OFFSET

I

Input Leakage

–1.0

2.0

µA V_IN= 0V, V_CC

V

IL

Output Leakage

OL

V

Comparator Input

Common Mode

Voltage Range

V

–0.3 V_CC–1.0

ICR

SS

I_CC

Supply Current

6.0V

5.25

6.0

3.5

mA @ 6 MHz (Internal open

drain)

1,2

I_CC1

HALT Mode

mA @ 6 MHz (no CPU; RC/WDT

& Detect; D+/D–; I/O active)

I_CC2

I_CC3

Stop Current

60

40

µA

Stop Current w/o RC/WDT

µA

D+, D– Differential Signaling

D– > D+ D+ > D–

mV @ >200 mV Difference

3

Notes:

1. All outputs unloaded, I/O pins floating, and all inputs are at V or V level.

CC

SS

2. CL1 = CL2 = 22 pF

3. Except for SE0 for EOP and Reset (see 7.1.4 of USB Specification)

4. General-Purpose I/O Mode.

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DC CHARACTERISTICS: PS/2 MODE

V = 4.5V – 5.5V

cc

1

T = 0°C to +70°C

A

V

Sym

Parameter

Min

0.7V

Max

V +0.3

CC

Units Conditions

Notes

CC

V

Clock Input High

Voltage

V

Driven by External

Clock Generator

CH

CC

V

Clock Input Low

Voltage

V

–0.3

0.2V

V

Driven by External

Clock Generator

CL

SS

CC

V

Input High Voltage

Input Low Voltage

Output High Voltage

Output Low Voltage

0.7V

V +0.3

CC

V

IH

CC

V_SS–0.3

V_CC–0.4

0.2V_CC

IL

V

I_OH= –2.0 mA

I_OL= +4.0 mA

I_OL= +6 mA,

OH

0.6

1.2

V

OL1

OL2

OFFSET

V

Comparator Input Offset

Voltage

25.0

mV

I

Input Leakage

–1.0

2.0

µA V_IN= 0V, V_CC

V

IL

Output Leakage

OL

V

Comparator Input

Common Mode

Voltage Range

V

–0.3 V_CC–1.0

ICR

SS

I_CC

Supply Current

5.5V

6.0

3.5

60

mA @ 6 MHz

1,2

I_CC1

I_CC2

I_CC3

Notes:

HALT Current

mA @ 6 MHz (no CPU; no SIE)

Stop Current

µA

Stop Current w/o RC/WDT

40

1. All outputs unloaded, I/O pins floating, and all inputs are at V or V level.

CC

SS

2. CL1 = CL2 = 22 pF.

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DC CHARACTERISTICS: RS232 MODE

V = 4.0V – 6.0V

cc

T = 0°C to +70°C

A

V

Sym

Parameter

Min

0.7V

Max

V +0.3

CC

Units Conditions

Notes

CC

V

Clock Input High

Voltage

V

Driven by External

CH

CC

Clock Generator

V

Clock Input Low

Voltage

V

–0.3 0.2V

V

Driven by External

Clock Generator

CL

SS

CC

V

Input High Voltage

Input Low Voltage

Output High Voltage

Output Low Voltage

0.7V

V +0.3

CC

V

IH

CC

V_SS–0.3 0.2V_CC

IL

V_CC–0.4

0.6

V

I_OH= –2.0 mA

I_OL= +4.0 mA

I_OL= +6 mA,

OH

V

OL1

OL2

OFFSET

1.2

V

Comparator Input Offset

Voltage

25.0

mV

I

Input Leakage

–1.0

2.0

µA V_IN= 0V, V_CC

V

IL

Output Leakage

OL

V

Comparator Input

Common Mode

Voltage Range

V

–0.3 V_CC–1.0

SS

ICR

I_CC

Supply Current

HALT Mode

6.0V

4.0

3.5

60

mA @ 3 MHz (6 MHz/2)

1,2

I_CC1

I_CC2

I_CC3

mA @ 3 MHz

Stop Current

µA

Stop Current w/o

RC/WDT

40

Notes:

1. All outputs unloaded, I/O pins floating, and all inputs are at V or V level.

CC

SS

2. CL1 = CL2 = 22 pF.

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DC CHARACTERISTICS: I/O MODE

V = 4.0V – 6.0V

cc

1

T = 0°C to +70°C

A

V

Sym

Parameter

Min

0.7V

Max

V +0.3

CC

Units Conditions

Notes

CC

V

Clock Input High

Voltage

V

Driven by External

Clock Generator

CH

CC

V

Clock Input Low

Voltage

V

–0.3

0.2V

V

Driven by External

Clock Generator

CL

SS

CC

V

Input High Voltage

Input Low Voltage

Output High Voltage

Output Low Voltage

0.7V

V +0.3

CC

V

IH

CC

V_SS–0.3

V_CC–0.4

0.2V_CC

IL

V

I_OH= –2.0 mA

I_OL= +4.0 mA

I_OL= +6 mA,

OH

0.6

1.2

V

OL1

OL2

OFFSET

V

Comparator Input Offset

Voltage

25.0

mV

I

Input Leakage

–1.0

2.0

µA V_IN= 0V, V_CC

V

IL

Output Leakage

OL

V

Comparator Input

Common Mode

Voltage Range

V

–0.3 V_CC–1.0

ICR

SS

I_CC

Supply Current

6.0V

5.5V

6.0

4.0

60

mA @ 6 MHz

1,2

I_CCA

I_CCB

I_CC1

I_CC2

Notes:

mA @ 5.5V

mA @ 6.0V (6 MHz/2)

HALT w/ RC and WDT

µA

50

1. All outputs unloaded, I/O pins floating, and all inputs are at V or V level.

CC

SS

2. CL1 = CL2 = 22 pF.

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AC ELECTRICAL CHARACTERISTICS

Timing Diagram

1

3

CLOCK

2

3

2

IRQ

N

9

8

Figure 6. AC Electrical Timing Diagram

Timing Table

T = 0°C to +70°C

A

6 MHz

No

Symbol

Parameter

Min

Max

Units

Notes

1

TpC

Input Clock Period

83

DC

5

ns

1

2

TrC,TfC

TwC

Clock Input Rise & Fall Times

Input Clock Width

3

37

70

1

4

TwTinL

TwTinH

TpTin

TrTin

TwIL

Timer Input Low Width

1

5

Timer Input High Width

2.5TpC

4TpC

1

6

Timer Input Period

1

7

Timer Input Rise & Fall Timer

Int. Request Low Time

100

ns

1

8

70

1,2

9

TwIH

Twsm

Tost

Int. Request Input High Time

Stop-Mode Recovery Width Spec

Oscillator Start-Up Time

Watch-Dog Timer

3TpC

10

11

12

13

14

15

Notes:

100TpC

ns

ms

nS

0.5

300

50

Twdt

1000

70

D+, D–

POR

Differential Rise and Fall Times (USB Mode)

Power supply; POR rate/Volt level

RC Clock Period (internal)

3

TrC

12.5

µsec

4

1. Timing Reference uses 0.7 V

for a logic 1 and 0.2 V

for a logic 0.

CC

2. Interrupt request

3. See USB Specification 7.1.1.2

4. Corresponds to frequencies of 80 KHz to 20 KHz

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PIN FUNCTIONS

Port A. Port A (4–7) includes a Sink configuration. Port A

(3–0) has a Switch configuration.

In Switch, the options also include input wakeup, bidirec-

tional, push-pull or open drain configurations (Figure 8).

The only difference between the two is the programmable

Sink option.

1

In Sink, the options include input wakeup, bidirectional,

push-pull or open drain configurations (Figure 7). The Sink

is programmable from 0–15 mA (in 1 mA increments).

Vcc

Typical

100K

± 30%

TBD

Pullup Resistor Enable

Vcc

In

Pad

Wake

0–15 mA/ 1 mAincrements

I SINK (3:0)

Figure 7. Port A (4–7) Sink Conﬁguration

Table 3. Port A (4–7) Programmable Current Sink Table

Symbol Parameter

Min.

Max.

Units Conditions

N

Number of Bits

Bits

LSB

µA

4 bits, 16 settings, 0–15 mA

DNL

Diff Non-Linearity

Zero Code/Disable

LSB Current

0.50

I

Disabled

0

0.65

9.75

1.35

20.25

1600

mA

nS

35%

LSB

F

Full Scale Current

Settling Time

35%, Note 1

Within 10% of final value

T

settle

I

Overshoot Current

Compliance Voltage

1.05*I

1.1

µA

overshoot

set

V

Above V with I

ss FMAX

comp

Notes:

1. Setting all (4) I

cells to full scale is a violation of the Absolute Maximum Rating Spec.

SNK

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PIN FUNCTIONS (Continued)

Vcc

In

Pad

Wake

Pull-down Resistor Enable

100K

(± 35%)

Figure 8. Port A (0–3) Switch Conﬁguration

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Port B. Port B (0–5) includes a Quadrature configuration

(Figure 9), with programmable current sink and an analog

comparator with programmable reference voltages (Ta-

bles 4–8).

1

+V

+ V

Pad

AC

V^R1

VR2

VR3

Decode

AC = Analog Comparator Mode

Figure 9. Port B (0–5) Quadrature Conﬁguration

PORT B (0–5) QUADRATURE CONFIGURATION

Table 4. Programmable Voltage Threshold

Min. Max.

0.21 V 0.29 V

Symbol

Parameter

Units

Conditions

V

Voltage Reference 1

Voltage Reference 2

Voltage Reference 3

Ratio Accuracy

V

R1

R2

R3

CC

0.31 V

0.41 V

0.39 V

0.49 V

5

CC

V

Ratio

%

Note (1)

Note:

1. Greatest delta vs. specified delta.

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PORT B (0–5) QUADRATURE CONFIGURATION (Continued)

Table 5. Programmable Voltage Bit Selections (Register Addresses DA–DF)

V

— Bits D5:4

Comp Enable—Bit D7

Selected

Conditions

REF

0

1

xx

Comparator Off

Note (1)

01

0.25 V

0.35 V

0.45 V

CC

1

10

11

Note:

1. If all comparators are off, V

can be powered off. If in Stop Mode, V

is powered off.

REF

Table 6. Programmable Load Resistor

Symbol

Parameter

Min.

0.13 V

Max.

0.15 V

CC

Units

V

Conditions

V

Midpoint Voltage

Load Resistor 1

Load Resistor 2

Load Resistor 3

Load Resistor 4

Load Resistor 5

Load Resistor 6

Ratio Accuracy

MID

CC

R

5.25

9.00

8.75

15.00

22.50

53.75

92.50

138.75

5

K ohm

%

Pad to V , track R , R

SS L2

L1

L2

L3

L4

L5

L6

L3

L2

Pad to V , track R , R

SS

L1

13.50

32.25

55.50

83.25

Pad to V , track R , R

SS

CC

L1

Pad to V

Note (1)

Ratio

Note:

1. Greatest ratio vs. specified ratio.

Table 7. Programmable Load Resistor Bit Selections (Register Addresses DA–DF

Load Selected to V

CC

Divider Bits D2:0

SS

000

001

010

100

No load Resistors

7 K Selected

No load Resistors

43 K Selected

74 K Selected

111 K Selected

12 K Selected

18 K Selected

Table 8. Comparator

Max.

Symbol

Parameter

Min.

Units

Conditions

Common Mode, Note (1)

VOS

HYS

VCM

Offset Voltage

Hysteresis

25

mV

V

TBD

Voltage Range

V

–0.3

V

–1.0

CC

SS

T

Response Time Fast

1

µs

µA

700 mV/µs with 25 mV overdrive

15 mV/µs with 25 mV overdrive

rf

T

Response Time Slow

Supply Current

1

rs

IDD

100

Note:

1. Zilog will provide specification.

16

P R E L I M I N A R Y

DS97KEY2005

Z8E520/C520

1.5 MBPS USB Device Controller

Zilog

Port B. Port B (6–7) is configured as a serial communica-

Port B (6) has a programmable internal pullup of 7.5 K ±

tion port as follows:

30%. For USB Mode, Port B (7) requires an external pullup

of 7.5 K ± 1% to V (Figure 10).

CC

1

USB

PS/2

RS232

GPIO

Port B (6)

Port B (7)

D–

D+

Data

R x D

T x D

Port B (6)

Port B (7)

Clock

Vcc

7.5 K Pullup

Pull-up Resistor Enable

VUSB

Vcc

In/Wake

Pad

Figure 10. Port B (6–7) Serial Communication Port

DS97KEY2005

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Z8E520/C520

1.5 MBPS USB Device Controller

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FUNCTIONAL DESCRIPTION

Program Memory. The 16-bit program counter addresses

6 KB of program memory space at internal locations

(Figure 11).

The first 14 bytes of program memory are reserved for the

rollover and interrupt vectors. These locations have six

16-bit vectors that correspond to the six available inter-

rupts.

ADDRESS

ON-CHIP EPROM PROGRAM MEMORY

HEX

DECIMAL

6143

17FF

33

32

31

021

020

01F

AVAILABLE TO USER (AREA INTENDED

FOR FUTURE ADDITIONAL INTERRUPTS)

LOCATION OF FIRST

BYTE OF INSTRUCTION

EXECUTED AFTER

RESET

14

13

12

11

10

9

00E

00D

00C

00B

00A

009

008

007

006

005

004

003

002

001

000

IRQ5

IRQ4

IRQ3

8

IRQ3

7

IRQ2 INTERRUPT VECTOR (Lower Byte)

6

IRQ2 INTERRUPT VECTOR (Upper Byte)

5

IRQ1

4

IRQ1

3

2

IRQ0

1

0

PC ROLLOVER VECTOR (Lower Byte)

PC ROLLOVER VECTOR (Upper Byte)

Figure 11. Z8E520 Program Memory Map

18

P R E L I M I N A R Y

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1.5 MBPS USB Device Controller

Zilog

Register File. The register file consists of the following:

160 General-Purpose Registers in group 0–7, SIE Buffers

in group 8–A, SIE Control in group B, Timer/Counters in

group C, Configuration Registers in group D, Virtual Reg-

isters in group E and System Registers in Group F

(Figure 12).

1

System Registers

Virtual Registers

F

E

D

I/O Configuration

Timer/Counter

SIE Control

C

B

A

9

XMIT Buffer

RECEIVE Buffer

SIE Buffers

(for PS/2 or RS232-C Mode)

General Purpose RAM

8

7

6

5

4

3

2

General-Purpose

Registers

1

0

EP0 IN Buffer

A

Depends on

EP Mode

(See Table Below)

EP0 OUT Buffer

9

8

SIE Buffers

(for USB Mode)

EP0 SETUP Buffer

Figure 12. Register Files

Table 9. EP Modes for SIE Buffer (In USB Mode)

EP Mode

Description

Buffer Address

0x98–0x9F

0x88–0x8F

0xA8–0xAF

000

001

010

011

100

101

110

111

EP1 OFF, EP2 OFF

EP1 IN, EP2 OFF

EP1 OUT, EP2 OFF

EP1 CONTROL

GPR

EPI IN Buffer

EP1 OUT Buffer

EP1 IN Buffer

EP1 OUT Buffer

EP1 IN Buffer

EP1 OUT Buffer

EP1 IN Buffer

GPR

EP1 SETUP Buffer

GPR

EP1 OUT Buffer

EP2 OUT Buffer

EP1 OUT Buffer

EP1 IN Buffer

EP2 IN Buffer

EP1 OUT, EP2 OUT

EP1 IN, EP1 OUT

EP1 OUT, EP1 IN

EP1 IN, EP2 IN

GPR

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19

Z8E520/C520

1.5 MBPS USB Device Controller

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FUNCTIONAL DESCRIPTION (Continued)

STACK POINTER

RESERVED

REGPTR

FF

FE

FD

FC

FB

FA

F9

FLAGS

IMASK

IREQ

F8

F7

F6

F5

F4

F3

F2

RESERVED

F1

F0

Figure 13. System Registers

20

P R E L I M I N A R Y

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Z8E520/C520

1.5 MBPS USB Device Controller

Zilog

RESERVED

T1CNT

CF

CE

1

CD

CC

CB

CA

C9

T0CNT

T3CNT

T2CNT

T3AR

T2AR

C8

C7

T1ARHI

T0ARHI

C6

C5

C4

C3

C2

T1ARLO

T0ARLO

WDTHI

READ

ONLY

WDTLO

TCTLHI

C1

C0

TCTLLO

Figure 14. T/C Control Registers

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Z8E520/C520

1.5 MBPS USB Device Controller

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FUNCTIONAL DESCRIPTION (Continued)

ADDR

B0

NAME

D7

D6

D5

D4

D3

D2

D1

D0

PORT A

PORT B

A7

B7

A6

B6

A5

B5

A4

B4

A3

B3

A2

B2

A1

B1

A0

B0

B1

USB ADDRESS 6:0

ADDR

B2

B3

SIE MODE

RS232

PS/2

USB

SIE MODE 7:0

SIE

POWER

FORCE

RESUME

J STATE

ACTIVITY

USB CSR

B4

B5

B6

EP MODE 2:0

LOW

PRIORITY

INTR

LOW

PRIORITY

MASK

DEPENDS ON EP MODE

(SEE TABLE 10)

DEPENDS ON EP MODE

(SEE TABLE 10)

HIGH

PRIORITY RESUME

NAK

SENT

EP1

NAK

SENT

EP0

STALL

SENT

EP2

STALL STALL

SETUP

EP1

SETUP

EP0

B7

B8

B9

BA

BB

SENT

INTR

EP1

EP0

HIGH

PRIORITY

MASK

SAME AS HIGH PROIORITY INTR

OUT

ACK

SETUP

STATUS BUFFER

IN

DATA

EP0

CSR

OUT

SERVICED

FORCE FORCE

DATA

TOGGLE

PACKET

TOGGLE

READY

STALL

NAK

OUT

VOLATILE

EP1/2

CSR

DEPENDS ON EP MODE

(SEE TABLE 11)

EP0

COUNT

EP0 OUT COUNT 3:0

EP0 IN COUNT 3:0

EP1/2

COUNT

DEPENDS ON EP MODE

(SEE TABLE 12)

BC

BD

BE

BF

Figure 15. COMM Registers (USB Mode: B0–BF)

P R E L I M I N A R Y

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DS97KEY2005

Z8E520/C520

1.5 MBPS USB Device Controller

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COMMUNICATION REGISTER DEFINITIONS (USB MODE)

The following definitions on pages 23–26 describe in detail

the specific USB mode registers as illustrated in Figure 15.

available 7.5 K ohm pull-up internal to the chip. An external

7.5 K ohm pull-up should be provided for DATA.

1

PORT A, PORT B: I/O Port data registers. At all times, a

read to this port should indicate the current state at the

pins. Read/Write.

RS232: Port B7 is serial data out (T x D). Port B6 is serial

data in (R x D). These signals are CMOS-level signals,

positive logic. Appropriate transceiver circuitry must be

added externally to comply with RS232-C signal levels at

the device connector.

ADDR: Determines the USB Device Address. Cleared by

USB or POR Reset. Read/Write.

SIE POWER: Powers up the SIE when USB Resume sig-

naling has been received, or shuts down SIE in prepara-

tion for USB Suspend. Read/Write.

SIE MODE: Determines the mode of the SIE communica-

tion pins (Port B7:6). Read/Write. The SIE modes are as

follows:

FORCE RESUME: Forces a K state on the USB pins.

Read/Write.

SIE Mode Description

Port B7 Port B6

00000000 GPIO

00000001 USB

00000010 PS/2

I/O

D+

I/O

D–

ACTIVITY: This bit is set by the SIE when the state of the

USB pins changes. Read/Write.

CLOCK

DATA

J STATE: This bit is set when the USB is in the ‘J’ state

and cleared when in ‘K’ or ‘SE0’. Read only.

00000100 RS232-C 1200 Baud DATA IN DATA OUT

N81 Full Duplex

Other

Reserved

Reserved Reserved

EP MODE: These bits define the operation of the non-zero

endpoints of the SIE. Changing this mode resets the SIE,

while writing the same value does not. Read/Write. The

EP modes are as follows:

GPIO: The SIE is off and the communication lines are

standard I/O pins on Port B.

USB: Port B7 is D+, which connects to pin 3 on a series A,

or series B USB connector and whose conductor is green.

Port B6 is D–, which connects to pin 2 on a series A or se-

ries B USB connector and whose conductor is white. An

external 7.5K pull-up should be provided for D–.

EP Mode

Description

000

001

010

011

100

101

110

111

EP1 OFF, EP2 OFF

EP1 IN, EP2 OFF

EP1 OUT, EP2 OFF

EP1 CONTROL

PS/2: Port B7 is CLOCK, which connects to pin 5 on a

male 6-pin Mini-DIN connector and Port B6 is DATA, which

connects to pin 1 on a male 6-pin Mini-DIN connector.

These signals are open-drain. The CLOCK pin has an

EP1 OUT, EP2 OUT

EP1 IN, EP1 OUT

EP1 OUT, EP1 IN

EP1 IN EP2 IN

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Z8E520/C520

1.5 MBPS USB Device Controller

Zilog

COMMUNICATION REGISTER DEFINITIONS (USB MODE) (Continued)

LOW PRIORITY INTR: This register contains the IRQ

source flags of a low-priority communications interrupt.

The ISR should check these bits to determine the cause of

the interrupt. The definition of these bits depends on the

EP Mode as specified in the USB CSR. Writing a 1 to their

position clears interrupt sources. Read/Write.

LOW PRIORITY MASK: This register contains mask bits

for the IRQ sources specified in the LOW PRIORITY INTR

register. A set bit indicates that the corresponding interrupt

source is unmasked.

Table 10 illustrates both Low Priority MASK and INTR con-

ditions according to EP Mode:

Table 10. Low Priority MASK and INTR Conditions

EP

MODE

Description

EP 2

EP 1

EP 0

OUT

PACKET

READY

000

001

010

011

100

101

110

111

EP1 OFF, EP2 OFF

OUT

NAK

SENT

IN

NAK

SENT

DONE

EP1 IN EP2 OFF

EP1 OUT, EP2 OFF

EP1 CONTROL

IN

DONE

OUT

NAK

SENT

OUT

PACKET

READY

IN

NAK

SENT

NAK

SENT

DONE

OUT

NAK

OUT

NAK

SENT

OUT

PACKET

READY

IN

PACKET

NAK

SENT

DONE

READY READY

OUT

IN

DONE

OUT

NAK

SENT

OUT

PACKET

READY

IN

NAK

SENT

PACKET

READY

NAK

SENT

NAK

SENT

DONE

EP1 OUT, EP2 OUT

EP1 IN, EP1 OUT

EP1 OUT, EP1 IN

EP1 IN EP2 IN

OUT

NAK

SENT

OUT

NAK

SENT

OUT

NAK

SENT

OUT

PACKET

READY

IN

PACKET

READY

PACKET

READY

NAK

SENT

DONE

OUT

NAK

SENT

OUT

IN

DONE

OUT

NACK PACKET

IN

PACKET

READY

NAK

SENT

NAK

SENT

DONE

SENT

READY

IN

DONE

OUT

NAK

SENT

OUT

NAK

SENT

OUT

PACKET

READY

IN

NAK

SENT

PACKET

READY

NAK

SENT

DONE

IN

OUT

IN

NAK

SENT

DONE

NAK

SENT

DONE

NACK PACKET

SENT READY

NAK

SENT

DONE

IN DONE: The SIE received a valid IN token, sent the data

packet and received an ACK from the host. Setting this bit

by the SIE, clears IN PACKET READY and IN NAK SENT.

SIE may never write to the IN buffer.

OUT PACKET READY: The SIE received a valid OUT

packet and placed the received data, if any, in the buffer,

thereby updating the OUT count register and sending an

ACK. Setting this bit by the SIE clears OUT SERVICED

and OUT NAK SENT. Firmware may never write to the

OUT buffer.

IN NAK SENT: The SIE sent a NAK on an IN transmission

because IN PACKET READY was clear.

OUT NAK SENT: The SIE sent a NAK on an OUT trans-

action because OUT SERVICED was clear. If an OUT

packet was NAK’d, OUT DATA TOGGLE and the OUT

buffer must not be affected.

24

P R E L I M I N A R Y

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1.5 MBPS USB Device Controller

Zilog

HIGH PRIORITY INTR: This register contains the IRQ

source flags of a high-priority communications interrupt.

The ISR should check these bits to determine the cause of

the interrupt. Writing a 1 to their position clears interrupt

sources. Read/Write.

■ SETUP EP1: This bit is set after the completion of the

setup stage of a control transfer on EP1. This bit is valid

only in EP mode 011.

1

■ SETUP EP0: This bit is set after the completion of the

setup stage of a control transfer on EP0.

■ RESUME: This bit is set when the ACTIVITY bit is set in

the USB CSR, allowing the device to wake up on any

activity of the USB.

HIGH PRIORITY MASK: This register contains mask bits

for the IRQ sources specified in the HIGH PRIORITY INTR

register. A set bit indicates that the corresponding interrupt

source is unmasked.

■ STALL SENT EP2: This bit is set when a STALL is sent

on EP2. This bit is valid only in EP modes 100, 101, 110

and 111.

EP0 CSR: Control/Status register of Endpoint 0 (Control

pipe).

■ STALL SENT EP1: This bit is set when a STALL is sent

on EP1. This bit is not valid in EP mode 000.

EP1/2 CSR: Control/Status register of additional end-

points. The definition of these bits depends on the EP

Mode as specified in the USB CSR. Read/Write.

■ STALL SENT EP0: This bit is set when a STALL is sent

on EP0.

Table 11 illustrates the EP1/2 CSR registers according to

EP Mode:

Table 11. EP 1/2 CSR Registers (BA)

EP

MODE

Description

EP 1

000 EP1 OFF, EP2 OFF

001 EP1 IN EP2 OFF

010 EP1 OUT, EP2 OFF

011 EP1 CONTROL

FORCE FORCE

STALL NAK

IN

PACKET

READY TOGGLE

IN

DATA

FORCE FORCE

STALL NAK

IN

PACKET

READY TOGGLE

IN

DATA

FORCE FORCE

STALL NAK

OUT

PACKET

READY TOGGLE

OUT

DATA

ACK

SETUP

OUT

DATA

TOGGLE

FORCE FORCE

STALL NAK

IN

PACKET

READY TOGGLE

IN

DATA

STATUS BUFFER SERVICED

OUT VOLATILE

100 EP1 OUT, EP2 OUT FORCE FORCE

STALL NAK

OUT

SERVICED

OUT

DATA

FORCE FORCE

STALL NAK

OUT

PACKET

OUT

DATA

TOGGLE

READY TOGGLE

101 EP1 IN, EP1 OUT

110 EP1 OUT, EP1 IN

111 EP1 IN EP2 IN

FORCE FORCE

STALL NAK

OUT

SERVICED

OUT

DATA

TOGGLE

FORCE FORCE

STALL NAK

IN

PACKET

READY TOGGLE

IN

DATA

FORCE FORCE

STALL NAK

IN

PACKET

READY TOGGLE

IN

DATA

FORCE FORCE

STALL NAK

OUT

PACKET

READY TOGGLE

OUT

DATA

FORCE FORCE

STALL NAK

IN

PACKET

IN

DATA

FORCE FORCE

STALL NAK

IN

PACKET

IN

DATA

READY TOGGLE

FORCE STALL: Forces the SIE to stall all IN and OUT

transactions. The successful receipt of a setup token

clears this bit. STALL takes priority over NAK or ACK.

Read/Write.

IN PACKET READY: When clear, IN transactions are

NAK’d. This bit cannot be cleared by firmware. To clear it,

firmware should be set FORCE NAK. Firmware must not

write to the IN buffer or IN COUNT while this bit is set. It is

cleared when the SIE sets IN DONE or when the SIE re-

DS97KEY2005

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Z8E520/C520

1.5 MBPS USB Device Controller

Zilog

COMMUNICATION REGISTER DEFINITIONS (USB MODE) (Continued)

ceives a valid setup token (via FORCE NAK). Setting IN

PACKET READY clears IN NAK SENT. Read/Set.

ACK STATUS OUT: This bit serves to filter the response

to an OUT transaction. Setting this bit also sets OUT SER-

VICED. This bit cannot be cleared by firmware. To clear it,

firmware should be set FORCE NAK. Read/Set.

FORCE NAK: Setting this bit clears IN PACKET READY if

no IN transaction are in progress, and clears OUT SER-

VICED and ACK STATUS OUT if no OUT transactions are

in progress. This bit is cleared by a setup token or by firm-

ware. Read/Write.

While ACK STATUS OUT is set:

■ If IN NAK SENT is clear, the SIE will ACK an empty OUT

DATA 1 transaction.

IN DATA TOGGLE: Indicates what type of PID to use in

the data phase of the next IN transaction. SIE may never

write to this bit. Read/Write.

■ If IN NAK SENT is set, the SIE will NAK an empty OUT

DATA 1 transaction.

■ Any other kind of OUT transaction will be stalled and set

the STALL SENT interrupt. It is possible to have both

STALL SENT and OUT PACKET READY set on a

single, incorrect OUT transaction.

OUT SERVICED: When cleared, OUT transactions are

NAK’d. It is cleared when the SIE sets OUT PACKET

READY or receives a valid setup token (via FORCE NAK).

This bit cannot be cleared by firmware. To clear it, firm-

ware should be set FORCE NAK. When set, OUT COUNT

and OUT buffer are volatile. Setting OUT SERVICED

clears OUT N AK SENT. Read/Set.

■ Any out transaction will cause the SIE to set FORCE

NAK and OUT PACKET READY. As a result, ACK

STATUS OUT is cleared. ACK STATUS OUT has “one-

shot” behavior. It only handles one OUT transaction.

OUT DATA TOGGLE: Indicates what type of PID was re-

ceived in the data phase of the most recent successful

OUT transaction. Read only.

■ The successful receipt of a setup token sets FORCE

NAK, which clears this bit.

SETUP BUFFER VOLATILE: Indicates that the SIE has

entered the data stage of a control transfer. The successful

receipt of a setup token sets and locks this bit. The bit re-

mains locked as set until the data phase is complete and

error free. If the data phase has an error, this bit will re-

mained locked, but a setup interrupt will still occur to inform

the firmware that a new transfer was attempted. After the

data phase is received without errors, firmware may clear

this bit. Read/Clear (if unlocked).

EP0 COUNT: Contains counts of bytes in the endpoint

buffers.

EP1/2 COUNT: Contains counts of bytes in the endpoint

buffers. Definition of this register depends on the EP Mode

as illustrated in Table 12:

Table 12. EP 1/2 Counts

EP MODE

Description

EP1 OFF, EP2 OFF

EP1/2 COUNT

000

001

010

011

100

101

110

111

GP R

EP1 IN EP2 OFF

EP1 OUT, EP2 OFF

EP1 CONTROL

GPR

EP1 IN COUNT 3:0

GPR

EP1 OUT COUNT 3:0

EP1 IN COUNT 3:0

EP1 OUT COUNT 3:0

EP1 IN COUNT 3:0

EP1 OUT COUNT 3:0

EP1 IN COUNT 3:0

EP1 OUT COUNT 3:0

EP2 OUT COUNT 3:0

EP1 OUT COUNT 3:0

EP1 IN COUNT 3:0

EP2 IN COUNT 3:0

EP1 OUT, EP2 OUT

EP1 IN, EP1 OUT

EP1 OUT, EP1 IN

EP1 IN EP2 IN

EP OUT COUNT: Set by the SIE to indicate the number of

bytes received in the most recent OUT transaction. Invalid

while OUT SERVICED is set.

EP IN COUNT: Set by firmware to indicate the number of

bytes to transfer in the next IN transaction. Invalid while IN

PACKET READY is set.

26

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Z8E520/C520

1.5 MBPS USB Device Controller

Zilog

ADDR

B0

NAME

D7

D6

D5

D4

D3

D2

D1

D0

1

PORT A

PORT B

A7

B7

A6

B6

A5

B5

A4

B4

A3

B3

A2

B2

A1

B1

A0

B0

B1

B2

B3

1200

BAUD

SERIAL

SIE MODE

MODE 3:0

USB

PS/2

B4

B5

B6

LOW

PRIORITY

INTR

LOW

PRIORITY

MASK

PB7

INTR

PB6

INTR

XMIT

DONE

HOST

ABORT ERROR

COMM

BYTE

RCV

PB7

MSK

PB6

MSK

SAME AS LOW PRIORITY INTR

HIGH

PRIORITY

INTR

OVER-

RUN

ERROR ERROR

RCV

COMM

RCV

DONE

B7

B8

B9

BA

BB

HIGH

PRIORITY

MASK

SAME AS HIGH PRIORITY INTR

COMM

CSR

RCV

READY

XMIT

READY

PACKET

SIZE

RCV PACKET SIZE

XMIT PACKET SIZE

BYTE

OFFSETS

LAST BYTE RECEIVED OFFSET

NEXT SEND BYTE OFFSET

BC

BD

BE

BF

Figure 16. COMM Registers (Non-USB Modes: B0–BF)

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1.5 MBPS USB Device Controller

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COMMUNICATION REGISTER DEFINITIONS (NON-USB MODES)

The following definitions describe in detail the specific non-

USB mode registers as illustrated in Figure 16.

■ RCV COMM ERROR: Indicates that a communications

error occurred while receiving a byte, resulting in a

framing or parity error. In PS/2 mode, it may also

indicate that the host aborted its own transmission.

PORT A, PORT B: Same as USB mode. Port B6 and B7

are I/O in the GPIO Mode.

■ RCV DONE: Indicates that RCV PACKET SIZE bytes

SIE MODE: Same as USB mode.

have been received since RCV READY was set.

LOW PRIORITY INTR: This register contains the IRQ

COMM CSR: Controls the SIE in PS/2 and RS232-C

mode.

flags of

a

low-priority communications interrupt.

Read/Write.

■ XMIT READY: Indicates to the SIE that the XMIT buffer

is valid. Cleared by SIE when XMIT DONE is set.

Cannot be cleared by firmware. Read/Write.

LOW PRIORITY MASK: This register contains mask bits

for the IRQ sources specified in the LOW PRIORITY INTR

register. A set bit indicates that the corresponding interrupt

source is unmasked.

■ RCV READY: Indicates to the SIE that the most recent

packet received has been handled. Cleared by the SIE

after RCV DONE is set. Cannot be cleared by firmware.

Read/Write.

■ XMIT COMM ERROR: Indicates that a communications

error occurred while transmitting a byte. Valid only when

the SIE is in PS/2 mode. Indicates that the host aborted

the transfer.

■ RCV PACKET SIZE: Number of bytes to receive before

BYTE RECEIVED interrupt. Value may not exceed the

size specified in RCV BUFFER SIZE. A “0” indicates that

the packet size = the buffer size. Read/Write.

■ XMIT DONE: Indicates that XMIT PACKET SIZE bytes

have been sent since XMIT READY was set.

HIGH PRIORITY INTR: This register contains the IRQ

source flags of a low-priority communications interrupt.

The ISR should check these bits to determine the cause of

the interrupt. Read/Write.

■ XMIT PACKET SIZE: The number of bytes to send

before the XMIT DONE interrupt. A “0” indicates that the

packet size = the buffer size

■ LAST BYTE RECEIVED OFFSET: Indicates the offset

in the RECEIVE buffer of the most recent byte received.

Read only.

HIGH PRIORITY MASK: This register contains mask bits

for the IRQ sources specified in the HIGH PRIORITY INTR

register. A set bit indicates that the corresponding interrupt

source is unmasked.

■ NEXT SEND BYTE OFFSET: Indicates the offset in the

XMIT buffer of the next byte to be sent. If the host has

aborted a PS/2 transmission, it is the offset of the byte

that was aborted. Read only.

■ OVERRUN ERROR: Indicates that RCV READY was

clear when RCV DONE was set.

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1.5 MBPS USB Device Controller

Zilog

INITIAL STATES: COMM REGISTERS, UPON CHANGING MODES:

ADDR

NAME

D7

D6

D5

D4

D3

D2

D1

D0

1

0

1

2

3

4

5

6

7

8

9

A

B

C

D

E

F

PORT A

PORT B

Cleared by POR,or not changed

Same as Port A

SIE

CONTROL

REGS

ALL 0

Uninitialized

INITIAL STATES: PORT CONFIGURATION REGISTERS:

All Registers in this state are cleared to 0 on POR.

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1.5 MBPS USB Device Controller

Zilog

PORT CONFIGURATION REGISTERS

ADDR

D0

NAME

D7

D6

D5

D4

D3

D2

D1

D0

A0

A1

PUSH/ PULLDWN

PORT A

CONFIG

01

PUSH/

PULL

PULLDWN

ON

WAKE

OUTPUT

WAKE

OUTPUT

PULL

ON

A2

A3

PORT A

CONFIG

23

PUSH/

PULL

PULLUP

ON

PUSH/ PULLDWN

PULL

D1

ON

A4

A5

PORT A

CONFIG

45

PUSH/

PULL

PULLUP

ON

PUSH/

PULL

PULLUP

ON

D2

D3

A6

B0

A7

PORT A

CONFIG

67

PUSH/

PULL

PULLUP

ON

PUSH/

PULL

PULLUP

ON

WAKE

OUTPUT

B1

PORT B

CONFIG

01

D4

D5

D6

PUSH/

PULL

PULLUP

ON

PUSH/

PULL

PULLUP

ON

WAKE

B2

B4

B6

B3

B5

B7

PORT B

CONFIG

23

PORT B

CONFIG

45

PORT B

CONFIG

67

PUSH/

PULL

PULLUP

ON

PUSH/

PULL

PULLUP

ON

WAKE

OUTPUT

PUSH/

PULL

PULLUP

ON

PUSH/

PULL

PULLUP

ON

D7

D8

D9

DA

DB

PUSH/

PULL

PULLUP

ON

PUSH/

PULL

PULLUP

ON

OUTPUT

A5

A4

PORT A

SINK

45

SINK 3:0

A7

SINK 3:0

A6

PORT A

SINK

67

SINK 3:0

B0

PORT B0

PORT B1

COMP

ENABLE

VREF 5:4

DIVIDER 2:0

B1

B2

COMP

ENABLE

DIVIDER 2:0

PORT B2

PORT B3

PORT B4

DC

DD

COMP

ENABLE

DIVIDER 2:0

VREF 5:4

B3

B4

COMP

ENABLE

DIVIDER 2:0

DE

DF

COMP

ENABLE

VREF 5:4

B5

PORT B5

COMP

ENABLE

DIVIDER 2:0

Figure 17. Port Conﬁguration Registers ( D0–DF)

P R E L I M I N A R Y

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Zilog

PORT REGISTER DEFINITIONS

The following definitions describe in detail the specific port

registers as illustrated in Figure 17.

SINK: Indicates the level of current drawn by the current

sink on the pin. When SINK ≠ 0, the n-channel output tran-

sistor is disabled. When SINK = 0, the sink is off and the n-

channel output transistor may be enabled according to the

OUTPUT bit.

1

WAKE: When set, this pin is capable of waking the device

on any edge.

PUSH/PULL: When set, this pin is a push-pull output.

When clear, this pin is an open-drain output. Ignored if

OUTPUT is clear.

DIVIDER: Selects one of the three voltage dividers to be

placed on the pin. Divider 0 indicates no divider.

VREF: Indicates the voltage reference level for the com-

parator. Ignored if COMP ENABLED is clear.

PULLUP ON: When set, the pull-up resistor is on.

OUTPUT: When set, the pin’s output drivers are enabled.

However, the pin may be read at any time regardless of the

configuration.

COMP ENABLE: When set, the comparator is powered.

When clear, the comparator and VREF circuitry are pow-

ered down.

FUNCTIONAL DESCRIPTIONS

Counter/Timers. For the Z8E20, 8-bit timers T0 and T1

are available to function as a pair of independent 8-bit

standard timers, or they can be cascaded to function as a

16-bit PWM timer. In addition, 8-bit timers T2 and T3 are

provided but they can only operate in cascade to function

as a 16-bit standard timer (Figure 18).

ue register is being written while the timer is in the process

of being initialized. Whether initialization is done with the

new or old value is a function of the exact timing of the

write operation. In all cases, the Z8E520 will prioritize the

software write above that of a decremented writeback.

However, when hardware clears a control register bit for a

timer that is configured for single-shot operation; the clear-

ing of the control bit will override a software write. Reading

either register can be done at any time, and will have no

effect on the functionality of the timer.

Each 8-bit timer is provided a pair of registers, which are

both readable and writable. One of the registers is defined

to contain the auto-initialization value for the timer, while

the second register contains the current value for the timer.

When a timer is enabled, the timer will decrement whatev-

er value is currently held in its count register, and will then

continue decrementing until it reaches 0, at which time an

interrupt will be generated and the contents of the auto-ini-

tialization register are optionally copied into the count val-

ue register. If auto-initialization is not enabled, the timer

will stop counting upon reaching 0 and control logic will

clear the appropriate control register bit to disable the tim-

er. This occurrence is referred to as “single-shot” opera-

tion. If auto-initialization is enabled, the timer will continue

counting from the initialization value. Software should not

attempt to use registers that are defined as having timer

functionality.

If a timer pair is defined to operate as a single 16-bit entity,

the entire 16-bit value must reach 0 before an interrupt is

generated. In this case, a single interrupt will be generat-

ed, and the interrupt will correspond to the even 8-bit time.

For example, timers T2 and T3 are cascaded to form a sin-

gle 16-bit timer, so the interrupt for the combined timer will

be defined to be that of timer T2 rather than T3. When a

timer pair is specified to act as a single 16-bit timer, the

even timer registers in the pair (timer T0 or T2) will be de-

fined to hold the timer’s least significant byte; while the odd

timer in the pair will hold the timer’s most significant byte.

In parallel with the posting of the interrupt request, the in-

terrupting timer’s count value will be initialized by copying

the contents of the auto-initialization value register to the

count value register.

Software is allowed to write to any register at any time, but

it is not recommended that timer registers be updated

while the timer is enabled. If software updates the count

value while the timer is in operation, the timer will continue

counting based upon the software-updated value. This oc-

currence can produce strange behavior if the software up-

date occurred at exactly the point that the timer was reach-

ing 0 to trigger an interrupt and/or reload.

Note: Any time that a timer pair is defined to act as a

single 16-bit timer, that the auto-reload function will be

performed automatically. All 16-bit timers will continue

counting while their interrupt requests are active, and will

operate in a free-running manner.

If interrupts are disabled for a long period of time, it is pos-

sible for the timer to decrement to 0 again before its initial

interrupt has been responded to. This occurrence is a de-

generate case, and hardware is not required to detect this

Similarly, if software updates the initialization value regis-

ter while the timer is active, the next time that the timer

reaches 0, it will be initialized using the updated value.

Again, strange behavior could result if the initialization val-

DS97KEY2005

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1.5 MBPS USB Device Controller

Zilog

FUNCTIONAL DESCRIPTIONS (Continued)

condition. When the timer control register is written, all tim-

ers that are enabled by the write will begin counting using

the value that is held in their count register. An auto-initial-

ization is not performed. All timers can receive an internal

clock source only, so synchronization of timer updates is

not an issue. Each standard timer that is enabled will be

updated every 8th XTAL clock cycle.

form, and the T0 interrupt will mark the end of the Low por-

tion of the PWM waveform.

To use the cascaded timers as a PWM, one must initialize

the T0/T1 count registers to work in conjunction with the

port pin. The user should initialize the T0 and T1 count reg-

isters to the PWM hi auto-init value to obtain the required

PWM behavior. The PWM is arbitrarily defined to use the

Low auto-reload registers first, implying that it had just

timed out after beginning in the High portion of the PWM

waveform. As such, the PWM is defined to assert the T1

interrupt after the first timeout interval.

If T0 and T1 are defined to work independently, then each

will work as an 8-bit timer with a single auto-initialization

register; T0ARLO for T0, and T1ARLO for T1. Each timer

will assert its predefined interrupt when it times out, and

will optionally perform the auto-initialization function. If T0

and T1 are cascaded to form a single 16-bit timer, then the

single 16-bit timer will be capable of performing as a Pulse-

Width Modulator (PWM). This timer is referred to as T01 to

distinguish it as having special functionality that is not

available when T0 and T1 act independently.

After the auto-initialization has been completed, decre-

menting occurs for the number of counts defined by the

auto-init_lo registers. When decrementing again reaches

0, the T0 interrupt is asserted; and auto-init using the auto-

init_hi registers occurs. Decrementing occurs for the num-

ber of counts defined by the auto-init_hi registers until

reaching 0, at which time the the T1 interrupt is asserted,

and the cycle begins again. The internal timers can be

used to trigger external events by toggling port output

when generating an interrupt. This functionality can only

be achieved in conjunction with the port unit defining the

appropriate pin as an output signal with the timer output

special function enabled. In this mode, the appropriate port

output will be toggled when the timer count reaches 0, and

will continue toggling each time that the timer times out.

When T01 is enabled, it can use a pair of 16-bit auto-initial-

ization registers. In this mode, one 16-bit auto-initialization

value is composed of the concatenation of T1ARLO and

T0ARLO, and the second auto-initialization value is com-

posed of the concatenation of T1ARHI and T0ARHI. When

T01 times out, it will alternately initialize its count value us-

ing the Lo auto-init pair followed by the Hi auto-init pair.

This functionality corresponds to a PWM where the T1 in-

terrupt will define the end of the High section of the wave-

Register Data Bus

÷ 8

XTAL

IRQ0

T0ARHI

T1ARHI

LOAD

OUF

PA1

PWM

OUF

T

T0

T1

REG C0–0

LOAD

XTAL

÷8

T0ARLO

T1ARLO

IRQ1

REG C0–1

= Bidirectional

Figure 18. Z8E520 Timers Block Diagram

P R E L I M I N A R Y

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Z8E520/C520

1.5 MBPS USB Device Controller

Zilog

Watch-Dog Timer. The WDT can be programmed at any-

time in the program operation.

trolled by the Interrupt Priority register. All interrupts are

vectored through locations in the program memory. When

an interrupt machine cycle is activated an interrupt request

is granted. All of the subsequent interrupts are thus dis-

abled, saving the Program Counter and status flags, and

branching to the program memory vector location reserved

for that interrupt. This memory location and the next byte

contain the 16-bit address of the interrupt service routine

for that particular interrupt request.

Default value (Reset) = 98 ms

1

The RC oscillator is under firmware control. If the oscillator

is enabled during USB Suspend/Chip Stop Mode, the de-

vice will be periodically woke up by the WDT timeout. If the

application does not require “motion detect,” the current

that drives the internal oscillator/WDT can be saved.

EMI. Lower EMI on the Z8E520 is achieved through circuit

modifications.

WDT Control Registers. Select time-out values for the

WDT are programmable –0 to +100%.

The Z8E520 also accepts external clock from XTAL IN pin

(Figure 20).

Interrupts. The Z8E520 has six different interrupts. These

interrupts are maskable and prioritized (Figure 19 ). The

six sources are divided as follows:

Priority

IRQ

0

1

2

3

4

5

TCO

TC1

XTAL1 (in)

TC2

COMM HIGH

COMM LOW

Port

XTAL2 (out)

.

Figure 20. Oscillator Conﬁguration

IRQ0–IRQ4

Power-On-Reset (POR). A timer circuit is triggered by the

system oscillator and is used for the Power-On Reset

(POR) timer function. The POR time allows V_CCand the os-

cillator circuit to stabilize before instruction execution be-

gins. POR period is defined as:

6

IRQ

POR (ms) = 98 ms

IMR

The POR timer circuit is a one-shot timer triggered by pow-

er fail to Power OK status. The POR time is a nominal 100

ms at 6 MHz. The POR time is bypassed after Stop-Mode

Recovery.

6

Global

Interrupt

Enable

HALT. HALT turns off the internal CPU clock, but not the

oscillator. The counter/timer and external interrupts

IRQ0–5 remain active. The Z8E520 recovers by interrupts,

either externally or internally.

Interrupt

Request

USB Reset. Detection by the SIE of a reset from the Host

will cause the chip to reset. The reset will be remembered

so that the program can decide the source of the reset.

The USB Reset will act even if the chip is in the STOP

mode.

Vector Select

Figure 19. Interrupt Block Diagram

When more than one interrupt is pending, priorities are re-

solved by a programmable priority encoder that is con-

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1.5 MBPS USB Device Controller

Zilog

FUNCTIONAL DESCRIPTIONS (Continued)

V

Circuit. The Voltage Brown Out circuit will detect

Note: The timer cannot generate an interrupt in STOP

BO

when voltage has dropped below the normal operating

voltage. The chip will maintain full core functionality and

Mode because the clock is stopped.

The interrupt causes the processor to restart the applica-

tion program at the address or the vector of the interrupt

and continue the program at the end of the interrupt ser-

vice routine. In order to enter STOP (or HALT) Mode, it is

necessary to first flush the instruction pipeline to avoid sus-

pending execution in mid-instruction. As a result, the user

must execute a NOP (Opcode=FFH) immediately before

the appropriate sleep instruction, such as:

RAM values will be preserved during the range from V

MIN

(V = 4V) to V ; however, it may not meet worst case

CC

BO

AC and DC limits. At V , the chip will be placed in reset

BO

and maintained in that state until V exceeds V . When

CC

BO

this condition is reached, the chip will resume operation.

is set by design to 2.7 V ± 0.2 V.

V

BO

STOP. This instruction turns off the internal clock and ex-

ternal ceramic resonator oscillation. It reduces the standby

current to less than 60 µA. The STOP Mode is terminated

by an interrupt. An interrupt from any of the active (en-

abled) interrupts will remove the chip from the STOP Mode

(Ports 31–33 including the USB reset.

FF

6F

NOP

; clear the pipeline

; enter STOP Mode

or

STOP

FF

7F

NOP

; clear the pipeline

; enter HALT Mode

HALT

34

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1.5 MBPS USB Device Controller

Zilog

PLUS

Z8

SYSTEM REGISTERS

Plus

The registers displayed in Figures 21–27 represent Zilog’s

new technology, please refer to the Z8

user’s manual

Plus

new Z8

architecture. For a complete overview of this

(UM97Z8X0300) available at your local Zilog sales office.

1

0FA

IRQ

D7

D6

D5

D4

D3

D2

D1

D0

IRQ0 = TIMER0 TIMEOUT

IRQ1 = TIMER1 TIMEOUT

IRQ2 = TIMER2 TIMEOUT

IRQ3 = HIGH PRIORITY COMM

IRQ4 = LOW PRIORITY COMM

IRQ5 = PORTS

RESERVED (MUST BE 0)

FIXED INTERRUPT PRIORITY: IRQ0 > IRQ1 > IRQ2 > IRQ3 > IRQ4 > IRQ5

Figure 21. Interrupt Request Register

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1.5 MBPS USB Device Controller

Zilog

Z8PLUS SYSTEM REGISTERS (Continued)

0FB

IMR

D7

D6

D5

D4

D3

D2

D1

D0

1 = IRQ BIT N ENABLED

0 = IRQ BIT N MASKED

RESERVED (MUST BE 0)

1= GLOBAL INTERRUPTS ENABLED

0 = GLOBAL INTERRUPTS DISABLED

Figure 22. Interrupt Mask Register

0FF

STACK POINTER

D7

D6

D5

D4

D3

D2

D1

D0

NEXT STACK ADDRESSES

Figure 23. Stack Pointer

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1.5 MBPS USB Device Controller

Zilog

0C1

TCTLHI

D3

1

D7

D6

D5

D4

D2

D1

D0

SIE

WDT POR

RESET SOURCE

0 = STOP MODE ENABLED

1 = STOP MODE DISABLED

D6 D5 D4

WDT TIMEOUT VALUE

MIN NOM MAX

COUNTS

UNITS

mS

0

0 0

DISABLED

0

1

0 1

1 0

1 1

0 0

0 1

1 0

1 1

65,536

131,072

262,144

524,288

1,048,576

2,097,152 156 400 1200.0

4,194,304

5

10

19

38 100

78 200

12

25

50

39.3

78.0

156.0

312.0

624.0

mS

300 800 2400.0

(RC CLOCKS TO TIMEOUT†)

1 = RC ENABLED

0 = RC DISABLED

†: RC FREQUENCY = 40 KHz (Range: 20 TO 100 KHz)

Figure 24. TCTLHI Register

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Z8E520/C520

1.5 MBPS USB Device Controller

Zilog

Z8PLUS SYSTEM REGISTERS (Continued)

0C0

TCTLLO

TIMER STATUS

T0 T1

D7

D6

D5

D4

D3

D2

D1

D0

D2 D1 D0

0

1

0 0 DISAB. DISAB.

0 1 ENAB. DISAB.

1 0 DISAB. ENAB.

1 1 ENAB. ENAB.

0 0 T01 (PWM)

0 1 ENAB.(*) DISAB.

1 0 DISAB. ENAB.(*)

1 1 T32 (16 BIT)

(NOTE: (*) INDICATES AUTO-RELOAD

IS ACTIVE.)

D3 0: 6 MHz CR

D3 1: 12 MHz CR

D4 0: CORE CLK = ÷ (XTAL VALUE)

D4 1: CORE CLK = XTAL ÷ 2

1 = T32 16-BIT TIMER ENABLED WITH

AUTO-RELOAD ACTIVE

0 = T2 AND T3 TIMERS DISABLED

D6 1: PWM MODE IN T0 (PA1 IS OUTPUT)

D7 1: CAPTURE MODE IN T0 (PA0 IS INPUT)

NOTE: TIMER T01 IS A 16-BIT PWM TIMER FORMED BY CASCADING 8-BIT TIMERS

T1 (MSB) AND T0 (LSB). TIMER T32 IS A STANDARD 16-BIT TIMER FORMED

BY CASCADING 8-BIT TIMERS T3(MSB) AND T2(LSB).

NOTE: CLOCK “DIVIDE BY” MODE (÷) ALLOWS FOR LOWER POWER FOR RS232 OR FASTER

CPU EXECUTION WITH ZIE AT NORMAL 6 MHZ CLOCK RATE.

Figure 25. TCTLLO Register

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1.5 MBPS USB Device Controller

Zilog

0FD

RP

1

Register Pointer

D7

D6

D5

D4

D3

D2

D1

D0

MUST BE 0. (ONLY PAGE0 IS

IMPLEMENTED ON Z8E520.)

The upper nibble of the register file address

provided by the register pointer specifies

the active working register group.

DF

R15

R0

Register Group D

D0

CF

R15

R0

Register Group C

C0

3F

R15

Register Group 3

30

R0

R15

R0

2F

Register Group 2 * (ACTIVE)

20

1F

R15

R0

Register Group 1

10

0F

R15

R0

Register Group 0

00

* Register Group 2 is active if RP = 20H.

The lower nibble of the register

file address provided by the

instruction points to the

specific register.

Figure 26. Z8E520 Register Pointe

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Z8E520/C520

1.5 MBPS USB Device Controller

Zilog

Z8PLUS SYSTEM REGISTERS (Continued)

0FC

FLAGS

D7

D6

D5

D4

D3

D2

D1

D0

STOP MODE RECOVERY FLAG (SMR)

WDT RESET FLAG (WDT)

HALF-CARRY FLAG (HC)

DECIMAL ADJUST FLAG (DA)

OVERFLOW FLAG (OVF)

SIGN FLAG (S)

ZERO FLAG (Z)

CARRY FLAG (C)

Figure 27. Flags Register

40

P R E L I M I N A R Y

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Z8E520/C520

1.5 MBPS USB Device Controller

Zilog

PACKAGE INFORMATION

1

Figure 28. 20-Pin DIP Package

Figure 29. 20-Pin SOIC Package

DS97KEY2005

P R E L I M I N A R Y

41

Z8E520/C520

1.5 MBPS USB Device Controller

Zilog

ORDERING INFORMATION

6 MHz

20-Pin DIP

20-Pin SOIC

Z8E520PSC

Z8C520PSC

Z8E520SSC

Z8C520SSC

For fast results, contact your Zilog sales office for assistance in ordering the part required.

CODES

Package

Environment

P = Plastic DIP

C = Plastic Standard

V = Plastic Leaded Chip Carrier

F = Quad Flat Pack

Temperature

S = 0°C to +70°C

Speed

06 = 6 MHz

Example:

Z

8E520 06 P S C is a Z8E520, 6 MHz, SOIC, 0°C to +70°C, Plastic Standard Flow

Environmental Flow

Temperature

Package

Speed

Product Number

Zilog Prefix

42

P R E L I M I N A R Y

DS97KEY2005

Z8E520/C520

1.5 MBPS USB Device Controller

Zilog

1

Development Projects:

Customer is cautioned that while reasonable efforts will be

employed to meet performance objectives and milestone

dates, development is subject to unanticipated problems

and delays. No production release is authorized or

committed until the Customer and Zilog have agreed upon

a Customer Procurement Specification for this product.

Pre-Characterization Product:

The product represented by this CPS is newly introduced

and Zilog has not completed the full characterization of the

product. The CPS states what Zilog knows about this

product at this time, but additional features or

nonconformance with some aspects of the CPS may be

found, either by Zilog or its customers in the course of

further application and characterization work. In addition,

Zilog cautions that delivery may be uncertain at times, due

to start-up yield issues.

Low Margin:

Customer is advised that this product does not meet

Zilog's internal guardbanded test policies for the

specification requested and is supplied on an exception

basis. Customer is cautioned that delivery may be

uncertain and that, in addition to all other limitations on

Zilog liability stated on the front and back of the

acknowledgment, Zilog makes no claim as to quality and

reliability under the CPS. The product remains subject to

standard warranty for replacement due to defects in

materials and workmanship.

document may be copied or reproduced in any form or by

any means without the prior written consent of Zilog, Inc.

The information in this document is subject to change

without notice. Devices sold by Zilog, Inc. are covered by

warranty and patent indemnification provisions appearing

in Zilog, Inc. Terms and Conditions of Sale only.

to update or keep current the information contained in this

document.

Zilog’s products are not authorized for use as critical

components in life support devices or systems unless a

specific written agreement pertaining to such intended use

is executed between the customer and Zilog prior to use.

Life support devices or systems are those which are

intended for surgical implantation into the body, or which

sustains life whose failure to perform, when properly used

in accordance with instructions for use provided in the

labeling, can be reasonably expected to result in

significant injury to the user.

ZILOG, INC. MAKES NO WARRANTY, EXPRESS,

STATUTORY, IMPLIED OR BY DESCRIPTION,

REGARDING THE INFORMATION SET FORTH HEREIN

OR REGARDING THE FREEDOM OF THE DESCRIBED

DEVICES

FROM

INTELLECTUAL

PROPERTY

INFRINGEMENT. ZILOG, INC. MAKES NO WARRANTY

OF MERCHANTABILITY OR FITNESS FOR ANY

PURPOSE.

Zilog, Inc. 210 East Hacienda Ave.

Campbell, CA 95008-6600

Telephone (408) 370-8000

FAX 408 370-8056

Zilog, Inc. shall not be responsible for any errors that may

appear in this document. Zilog, Inc. makes no commitment

Internet: http://www.zilog.com

DS97KEY2005

P R E L I M I N A R Y

43


型号：	Z8E520SSC
厂家：	ZILOG, INC.
描述：	Microcontroller, 8-Bit, OTPROM, Z8 CPU, 12MHz, CMOS, PDSO20, PLASTIC, SOIC-20 可编程只读存储器时钟微控制器光电二极管外围集成电路
文件：	总43页 (文件大小：369K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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