Z8F0423PJ005SG [ZILOG]
IC MCU 8BIT 4KB FLASH 28DIP;
| 型号： | Z8F0423PJ005SG |
| 厂家： | 
ZILOG, INC. |
| 描述： | IC MCU 8BIT 4KB FLASH 28DIP |
| 文件： | 总247页 (文件大小：15293K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
High-Performance 8-Bit Microcontrollers
Z8 Encore! XP® F0823
Series
Product Specification
PS024317-0914
Copyright ©2014 Zilog®, Inc. All rights reserved.
www.zilog.com
Z8 Encore! XP® F0823 Series
Product Specification
ii
DO NOT USE THIS PRODUCT IN LIFE SUPPORT SYSTEMS.
Warning:
LIFE SUPPORT POLICY
ZILOG’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE
SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS PRIOR WRITTEN APPROVAL OF
THE PRESIDENT AND GENERAL COUNSEL OF ZILOG CORPORATION.
As used herein
Life support devices or systems are devices which (a) are intended for surgical implant into the body, or (b)
support or sustain life and whose failure to perform when properly used in accordance with instructions for
use provided in the labeling can be reasonably expected to result in a significant injury to the user. A criti-
cal component is any component in a life support device or system whose failure to perform can be reason-
ably expected to cause the failure of the life support device or system or to affect its safety or effectiveness.
Document Disclaimer
©2014 Zilog, Inc. All rights reserved. Information in this publication concerning the devices, applications,
or technology described is intended to suggest possible uses and may be superseded. ZILOG, INC. DOES
NOT ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE
INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZILOG ALSO
DOES NOT ASSUME LIABILITY FOR INTELLECTUAL PROPERTY INFRINGEMENT RELATED
IN ANY MANNER TO USE OF INFORMATION, DEVICES, OR TECHNOLOGY DESCRIBED
HEREIN OR OTHERWISE. The information contained within this document has been verified according
to the general principles of electrical and mechanical engineering.
Z8, Z8 Encore! and Z8 Encore! XP are trademarks or registered trademarks of Zilog, Inc. All other product
or service names are the property of their respective owners.
PS024317-0914
P R E L I M I N A R Y
Disclaimer
Z8 Encore! XP® F0823 Series
Product Specification
iii
Revision History
Each instance in this document’s revision history reflects a change from its previous edi-
tion. For more details, refer to the corresponding page(s) or appropriate links furnished in
the table below.
Revision
Date Level
Page
No.
Chapter/Section
Description
Sep
2014
17
General-Purpose Input/Output Clarified statements relating to the Direct
LED Drive and LED Drive Enable features.
Updated Table 17.
38, 51
Apr
2013
16
15
Timer Pin Signal Operation
Clarified use/availabity of the T0OUT and
T1OUT timer functions by mode.
83
Sep
LED Drive Enable Register
Clarified statement surrounding the Alternate 51,
2011
Function Register as it relates to the LED
function; revised Flash Sector Protect Regis- 212
ter description; revised Packaging chapter.
146,
Mar
2008
14
13
n/a
Changed branding to Z8 Encore! XP F0823 All
Series where appropriate.
Dec
Pin Description, General-Pur- Updated title from Z8 Encore! 8K and 4K
8, 36,
2007
pose Input/Output, Interrupt
Controller, Watchdog Timer,
Series to Z8 Encore! XP Z8F0823 Series.
Updated Figure 3, Table 15, Table 35, Tables 201,
60, 95,
Electrical Characteristics, and 59 through 61, Table 119 and Part Number
Ordering Information Suffix Designations section.
and
222
Aug
12
Part Selection Guide, External Updated Table 1, Table 16, and Program
2, 35,
2007
Clock Setup, and Program
Memory
Memory section.
and 13
Jun
2007
11
10
n/a
Updated to combine Z8 Encore! 8K and Z8 All
Encore! 4K Series.
Dec
Ordering Information
Updated Ordering Information chapter.
213
2006
PS024317-0914
P R E L I M I N A R Y
Revision History
Z8 Encore! XP® F0823 Series
Product Specification
iv
Table of Contents
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .iii
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .iv
List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . x
List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xii
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Part Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
CPU and Peripheral Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
General-Purpose I/O . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Flash Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Internal Precision Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
10-Bit Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Analog Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Universal Asynchronous Receiver/Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Reset Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
On-Chip Debugger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Available Packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Pin Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Flash Information Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Reset and Stop-Mode Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Reset Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
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Voltage Brown-Out Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Watchdog Timer Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
External Reset Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
External Reset Indicator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
On-Chip Debugger Initiated Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Stop-Mode Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Stop-Mode Recovery Using Watchdog Timer Time-Out . . . . . . . . . . . . . . . . . 27
Stop-Mode Recovery Using a GPIO Port Pin Transition . . . . . . . . . . . . . . . . . . 27
Stop-Mode Recovery Using the External RESET Pin . . . . . . . . . . . . . . . . . . . . 28
Reset Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Halt Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Peripheral-Level Power Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Power Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
General-Purpose Input/Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
GPIO Port Availability By Device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
GPIO Alternate Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Direct LED Drive . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
Shared Reset Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Shared Debug Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Crystal Oscillator Override . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5V Tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
External Clock Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
GPIO Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
GPIO Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Port A–C Address Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Port A–C Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Port A–C Data Direction Subregisters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Port A–C Alternate Function Subregisters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Port A–C Input Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Port A–C Output Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
LED Drive Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
LED Drive Level High Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
LED Drive Level Low Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
Interrupt Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Interrupt Vector Listing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
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Z8 Encore! XP® F0823 Series
Product Specification
vi
Master Interrupt Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Interrupt Vectors and Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Interrupt Assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Software Interrupt Assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Watchdog Timer Interrupt Assertion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Interrupt Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Interrupt Request 0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Interrupt Request 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Interrupt Request 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
IRQ0 Enable High and Low Bit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
IRQ1 Enable High and Low Bit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
IRQ2 Enable High and Low Bit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Interrupt Edge Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Shared Interrupt Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Interrupt Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Timer Operating Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Reading the Timer Count Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Timer Pin Signal Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Timer Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Timer 0–1 High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Timer Reload High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Timer 0–1 PWM High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . 86
Timer 0–1 Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Watchdog Timer Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Watchdog Timer Time-Out Response . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Watchdog Timer Reload Unlock Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Watchdog Timer Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Watchdog Timer Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Watchdog Timer Reload Upper, High and Low Byte Registers . . . . . . . . . . . . 94
Universal Asynchronous Receiver/Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Transmitting Data Using the Polled Method . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Transmitting Data Using the Interrupt-Driven Method . . . . . . . . . . . . . . . . . . 100
Receiving Data Using the Polled Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
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Receiving Data Using the Interrupt-Driven Method . . . . . . . . . . . . . . . . . . . . 102
Clear To Send (CTS) Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
MULTIPROCESSOR (9-Bit) Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
External Driver Enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
UART Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
UART Baud Rate Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
UART Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
UART Transmit Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
UART Receive Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
UART Status 0 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
UART Status 1 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
UART Control 0 and Control 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
UART Address Compare Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
UART Baud Rate High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . . 115
Infrared Encoder/Decoder . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Transmitting IrDA Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Receiving IrDA Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Infrared Encoder/Decoder Control Register Definitions . . . . . . . . . . . . . . . . . . . . 121
Analog-to-Digital Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Automatic Powerdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Single-Shot Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Continuous Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Calibration and Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
ADC Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
ADC Control Register 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
ADC Control/Status Register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
ADC Data High Byte Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
ADC Data Low Bits Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
Comparator Control Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Flash Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135
Flash Information Area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
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viii
Flash Operation Timing Using the Flash Frequency Registers . . . . . . . . . . . . 138
Flash Code Protection Against External Access . . . . . . . . . . . . . . . . . . . . . . . 138
Flash Code Protection Against Accidental Program and Erasure . . . . . . . . . . 138
Byte Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
Page Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Mass Erase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Flash Controller Bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Flash Controller Behavior in Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
Flash Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Flash Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
Flash Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Flash Page Select Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Flash Sector Protect Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Flash Frequency High and Low Byte Registers . . . . . . . . . . . . . . . . . . . . . . . . 146
Flash Option Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Option Bit Configuration By Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148
Option Bit Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149
Reading the Flash Information Page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Flash Option Bit Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Trim Bit Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Trim Bit Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Flash Option Bit Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
Trim Bit Address Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Zilog Calibration Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
ADC Calibration Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Serialization Data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Randomized Lot Identifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
On-Chip Debugger . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
OCD Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 159
Debug Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 160
OCD Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
OCD Autobaud Detector/Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
OCD Serial Errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
OCD Unlock Sequence (8-Pin Devices Only) . . . . . . . . . . . . . . . . . . . . . . . . . 163
Breakpoints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
Runtime Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163
On-Chip Debugger Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
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ix
On-Chip Debugger Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . 168
OCD Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 168
OCD Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Oscillator Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
System Clock Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Clock Failure Detection and Recovery . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
Oscillator Control Register Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Internal Precision Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175
eZ8 CPU Instruction Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Assembly Language Programming Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . 176
Assembly Language Syntax . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 177
eZ8 CPU Instruction Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
eZ8 CPU Instruction Classes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
eZ8 CPU Instruction Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
Opcode Maps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
On-Chip Peripheral AC and DC Electrical Characteristics . . . . . . . . . . . . . . . . . . 203
General Purpose I/O Port Input Data Sample Timing . . . . . . . . . . . . . . . . . . . 206
General Purpose I/O Port Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
On-Chip Debugger Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
UART Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 212
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213
Part Number Suffix Designations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223
Customer Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 231
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x
List of Figures
Figure 1. Z8 Encore! XP F0823 Series Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 2. Z8F08x3, Z8F04x3, F02x3 and Z8F01x3 in 8-Pin SOIC, QFN/MLF-S, or
PDIP Package* 8
Figure 3. Z8F08x3, Z8F04x3, F02x3 and Z8F01x3 in 20-Pin SOIC, SSOP or PDIP
Package* 8
Figure 4. Z8F08x3, Z8F04x3, F02x3 and Z8F01x3 in 28-Pin SOIC, SSOP or PDIP
Package* 8
Figure 5. Power-On Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure 6. Voltage Brown-Out Reset Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 7. GPIO Port Pin Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 8. Interrupt Controller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Figure 9. Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 10. UART Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Figure 11. UART Asynchronous Data Format without Parity . . . . . . . . . . . . . . . . . . . 99
Figure 12. UART Asynchronous Data Format with Parity . . . . . . . . . . . . . . . . . . . . . . 99
Figure 13. UART Asynchronous MULTIPROCESSOR Mode Data Format . . . . . . 103
Figure 14. UART Driver Enable Signal Timing (shown with 1 Stop Bit and Parity) 105
Figure 15. UART Receiver Interrupt Service Routine Flow . . . . . . . . . . . . . . . . . . . 107
Figure 16. Infrared Data Communication System Block Diagram . . . . . . . . . . . . . . 118
Figure 17. Infrared Data Transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Figure 18. IrDA Data Reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
Figure 19. Analog-to-Digital Converter Block Diagram . . . . . . . . . . . . . . . . . . . . . . 123
Figure 20. Flash Memory Arrangement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136
Figure 21. Flash Controller Operation Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137
Figure 22. On-Chip Debugger Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 158
Figure 23. Interfacing the On-Chip Debugger’s DBG Pin with an RS-232 Interface, # 1 of
2 159
Figure 24. Interfacing the On-Chip Debugger’s DBG Pin with an RS-232 Interface, # 2 of
2 160
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Z8 Encore! XP® F0823 Series
Product Specification
xi
Figure 25. OCD Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 161
Figure 26. Opcode Map Cell Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 194
Figure 27. First Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 196
Figure 28. Second Opcode Map after 1Fh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197
Figure 29. Port Input Sample Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Figure 30. GPIO Port Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Figure 31. On-Chip Debugger Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Figure 32. UART Timing With CTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Figure 33. UART Timing Without CTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
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Z8 Encore! XP® F0823 Series
Product Specification
xii
List of Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
F0823 Series Family Part Selection Guide . . . . . . . . . . . . . . . . . . . . . . . . . . 2
F0823 Series Package Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Signal Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Pin Characteristics (20- and 28-pin Devices)* . . . . . . . . . . . . . . . . . . . . . . 11
Pin Characteristics (8-Pin Devices) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Z8 Encore! XP F0823 Series Program Memory Maps . . . . . . . . . . . . . . . . 14
F0823 Series Flash Memory Information Area Map . . . . . . . . . . . . . . . . . . 15
Register File Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Reset and Stop-Mode Recovery Characteristics and Latency . . . . . . . . . . . 21
Table 10. Reset Sources and Resulting Reset Type . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table 11. Stop-Mode Recovery Sources and Resulting Action . . . . . . . . . . . . . . . . . 27
Table 12. Reset Status Register (RSTSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 13. POR Indicator Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 14. Power Control Register 0 (PWRCTL0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Table 15. Port Availability by Device and Package Type . . . . . . . . . . . . . . . . . . . . . . 33
Table 16. Port Alternate Function Mapping (8-Pin Parts) . . . . . . . . . . . . . . . . . . . . . . 35
Table 17. Port Alternate Function Mapping (Non 8-Pin Parts) . . . . . . . . . . . . . . . . . . 36
Table 18. GPIO Port Registers and Subregisters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 19. Port A–C GPIO Address Registers (PxADDR) . . . . . . . . . . . . . . . . . . . . . . 41
Table 20. PADDR[7:0] Subregister Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Table 21. Port A–C Control Registers (PxCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 22. Port A–C Data Direction Subregisters (PxDD) . . . . . . . . . . . . . . . . . . . . . . 43
Table 23. Port A–C Alternate Function Subregisters (PxAF) . . . . . . . . . . . . . . . . . . . 44
Table 24. Port A–C Output Control Subregisters (PxOC) . . . . . . . . . . . . . . . . . . . . . . 44
Table 25. Port A–C High Drive Enable Subregisters (PHDEx) . . . . . . . . . . . . . . . . . 45
Table 26. Port A–C Stop-Mode Recovery Source Enable Subregisters (PSMREx) . . 46
Table 27. Port A–C Pull-Up Enable Subregisters (PPUEx) . . . . . . . . . . . . . . . . . . . . 47
Table 28. Port A–C Alternate Function Set 1 Subregisters (PAFS1x) . . . . . . . . . . . . 48
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xiii
Table 29. Port A–C Alternate Function Set 2 Subregisters (PxAFS2) . . . . . . . . . . . . 49
Table 30. Port A–C Input Data Registers (PxIN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table 31. Port A–C Output Data Register (PxOUT) . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 32. LED Drive Enable (LEDEN) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 33. LED Drive Level High Register (LEDLVLH) . . . . . . . . . . . . . . . . . . . . . . 52
Table 34. LED Drive Level Low Register (LEDLVLL) . . . . . . . . . . . . . . . . . . . . . . . 53
Table 35. Trap and Interrupt Vectors in Order of Priority . . . . . . . . . . . . . . . . . . . . . . 55
Table 36. Interrupt Request 0 Register (IRQ0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 37. Interrupt Request 1 Register (IRQ1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 38. Interrupt Request 2 Register (IRQ2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 39. IRQ0 Enable and Priority Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
Table 40. IRQ0 Enable High Bit Register (IRQ0ENH) . . . . . . . . . . . . . . . . . . . . . . . 62
Table 41. IRQ0 Enable Low Bit Register (IRQ0ENL) . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 42. IRQ1 Enable and Priority Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 43. IRQ1 Enable Low Bit Register (IRQ1ENL) . . . . . . . . . . . . . . . . . . . . . . . . 64
Table 44. IRQ1 Enable High Bit Register (IRQ1ENH) . . . . . . . . . . . . . . . . . . . . . . . 64
Table 45. IRQ2 Enable and Priority Encoding . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 46. IRQ2 Enable High Bit Register (IRQ2ENH) . . . . . . . . . . . . . . . . . . . . . . . 65
Table 47. IRQ2 Enable Low Bit Register (IRQ2ENL) . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 48. Interrupt Edge Select Register (IRQES) . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Table 49. Shared Interrupt Select Register (IRQSS) . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 50. Interrupt Control Register (IRQCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 51. Timer 0–1 High Byte Register (TxH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 52. Timer 0–1 Low Byte Register (TxL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Table 53. Timer 0–1 Reload High Byte Register (TxRH) . . . . . . . . . . . . . . . . . . . . . . 85
Table 54. Timer 0–1 Reload Low Byte Register (TxRL) . . . . . . . . . . . . . . . . . . . . . . 85
Table 55. Timer 0–1 PWM High Byte Register (TxPWMH) . . . . . . . . . . . . . . . . . . . 86
Table 56. Timer 0–1 PWM Low Byte Register (TxPWML) . . . . . . . . . . . . . . . . . . . . 86
Table 57. Timer 0–1 Control Register 0 (TxCTL0) . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 58. Timer 0–1 Control Register 1 (TxCTL1) . . . . . . . . . . . . . . . . . . . . . . . . . . 88
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Z8 Encore! XP® F0823 Series
Product Specification
xiv
Table 59. Watchdog Timer Approximate Time-Out Delays . . . . . . . . . . . . . . . . . . . . 92
Table 60. Watchdog Timer Control Register (WDTCTL) . . . . . . . . . . . . . . . . . . . . . 94
Table 61. Watchdog Timer Reload Upper Byte Register (WDTU) . . . . . . . . . . . . . . 95
Table 62. Watchdog Timer Reload High Byte Register (WDTH) . . . . . . . . . . . . . . . 95
Table 63. Watchdog Timer Reload Low Byte Register (WDTL) . . . . . . . . . . . . . . . . 96
Table 64. UART Transmit Data Register (U0TXD) . . . . . . . . . . . . . . . . . . . . . . . . . 109
Table 65. UART Receive Data Register (U0RXD) . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Table 66. UART Status 0 Register (U0STAT0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Table 67. UART Status 1 Register (U0STAT1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Table 68. UART Control 0 Register (U0CTL0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Table 69. UART Control 1 Register (U0CTL1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Table 70. UART Address Compare Register (U0ADDR) . . . . . . . . . . . . . . . . . . . . . 115
Table 71. UART Baud Rate High Byte Register (U0BRH) . . . . . . . . . . . . . . . . . . . 115
Table 72. UART Baud Rate Low Byte Register (U0BRL) . . . . . . . . . . . . . . . . . . . . 115
Table 73. UART Baud Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116
Table 74. ADC Control Register 0 (ADCCTL0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Table 75. ADC Control/Status Register 1 (ADCCTL1) . . . . . . . . . . . . . . . . . . . . . . 130
Table 76. ADC Data High Byte Register (ADCD_H) . . . . . . . . . . . . . . . . . . . . . . . . 131
Table 77. ADC Data Low Bits Register (ADCD_L) . . . . . . . . . . . . . . . . . . . . . . . . . 132
Table 78. Comparator Control Register (CMP0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 134
Table 79. Z8 Encore! XP F0823 Series Flash Memory Configurations . . . . . . . . . . 135
Table 80. Flash Code Protection Using the Flash Option Bits . . . . . . . . . . . . . . . . . 139
Table 81. Flash Control Register (FCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143
Table 82. Flash Status Register (FSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144
Table 83. Flash Page Select Register (FPS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145
Table 84. Flash Sector Protect Register (FPROT) . . . . . . . . . . . . . . . . . . . . . . . . . . . 146
Table 85. Flash Frequency High Byte Register (FFREQH) . . . . . . . . . . . . . . . . . . . 147
Table 86. Flash Frequency Low Byte Register (FFREQL) . . . . . . . . . . . . . . . . . . . . 147
Table 87. Trim Bit Address Register (TRMADR) . . . . . . . . . . . . . . . . . . . . . . . . . . 150
Table 88. Trim Bit Data Register (TRMDR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
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Z8 Encore! XP® F0823 Series
Product Specification
xv
Table 89. Flash Option Bits at Program Memory Address 0000h . . . . . . . . . . . . . . 151
Table 90. Flash Options Bits at Program Memory Address 0001h . . . . . . . . . . . . . 152
Table 91. Trim Options Bits at Address 0000h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 153
Table 92. Trim Option Bits at 0001h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Table 93. Trim Option Bits at 0002h (TIPO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 154
Table 94. ADC Calibration Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Table 95. ADC Calibration Data Location . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
Table 96. Serial Number at 001C–001F (S_NUM) . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Table 97. Serialization Data Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 156
Table 98. Lot Identification Number (RAND_LOT) . . . . . . . . . . . . . . . . . . . . . . . . 156
Table 99. Randomized Lot ID Locations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 157
Table 100. OCD Baud-Rate Limits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 162
Table 101. OCD Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164
Table 102. OCD Control Register (OCDCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 169
Table 103. OCD Status Register (OCDSTAT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 170
Table 104. Oscillator Configuration and Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . 171
Table 105. Oscillator Control Register (OSCCTL) . . . . . . . . . . . . . . . . . . . . . . . . . . . 174
Table 106. Assembly Language Syntax Example 1 . . . . . . . . . . . . . . . . . . . . . . . . . . 177
Table 107. Assembly Language Syntax Example 2 . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Table 108. Notational Shorthand . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 178
Table 109. Additional Symbols . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
Table 110. Arithmetic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 180
Table 111. Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Table 112. Block Transfer Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
Table 113. CPU Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Table 114. Load Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
Table 115. Logical Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Table 116. Program Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Table 117. Rotate and Shift Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Table 118. eZ8 CPU Instruction Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 184
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Z8 Encore! XP® F0823 Series
Product Specification
xvi
Table 119. Opcode Map Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 195
Table 120. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 198
Table 121. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 199
Table 122. Power Consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201
Table 123. AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Table 124. Internal Precision Oscillator Electrical Characteristics . . . . . . . . . . . . . . . 202
Table 125. Power-On Reset and Voltage Brown-Out Electrical Characteristics and Tim-
ing 203
Table 126. Flash Memory Electrical Characteristics and Timing . . . . . . . . . . . . . . . . 204
Table 127. Watchdog Timer Electrical Characteristics and Timing . . . . . . . . . . . . . . 204
Table 128. Analog-to-Digital Converter Electrical Characteristics and Timing . . . . . 205
Table 129. Comparator Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Table 130. GPIO Port Input Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Table 131. GPIO Port Output Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Table 132. On-Chip Debugger Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209
Table 133. UART Timing With CTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 210
Table 134. UART Timing Without CTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 211
Table 135. Z8 Encore! XP F0823 Series Ordering Matrix . . . . . . . . . . . . . . . . . . . . . 213
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List of Tables
Z8 Encore! XP® F0823 Series
Product Specification
1
Overview
Zilog’s Z8 Encore! XP microcontroller unit (MCU) family of products are the first Zilog
microcontroller products based on the 8-bit eZ8 CPU core. Z8 Encore! XP F0823 Series
products expand upon Zilog’s extensive line of 8-bit microcontrollers. The Flash in-circuit
programming capability allows for faster development time and program changes in the
field. The new eZ8 CPU is upward compatible with existing Z8 instructions. The rich
peripheral set of Z8 Encore! XP F0823 Series makes it suitable for a variety of applica-
tions including motor control, security systems, home appliances, personal electronic
devices, and sensors.
Features
The key features of Z8 Encore! XP F0823 Series include:
•
•
•
•
•
•
•
5MHz eZ8 CPU
1KB, 2KB, 4KB, or 8KB Flash memory with in-circuit programming capability
256B, 512B, or 1KB register RAM
6 to 24 I/O pins depending upon package
Internal precision oscillator (IPO)
Full-duplex UART
The universal asynchronous receiver/transmitter (UART) baud rate generator (BRG)
can be configured and used as a basic 16-bit timer
•
Infrared data association (IrDA)-compliant infrared encoder/decoders, integrated with
UART
•
•
•
•
•
•
•
•
•
Two enhanced 16-bit timers with capture, compare, and PWM capability
Watchdog Timer (WDT) with dedicated internal RC oscillator
On-Chip Debugger (OCD)
Optional 8-channel, 10-bit Analog-to-Digital Converter (ADC)
On-Chip analog comparator
Up to 20 vectored interrupts
Direct LED drive with programmable drive strengths
Voltage Brown-Out (VBO) protection
Power-On Reset (POR)
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P R E L I M I N A R Y
Overview
Z8 Encore! XP® F0823 Series
Product Specification
2
•
•
•
•
2.7V to 3.6V operating voltage
Up to thirteen 5V-tolerant input pins
8-, 20-, and 28-pin packages
0°C to +70°C and –40°C to +105°C for operating temperature ranges
Part Selection Guide
Table 1 lists the basic features and package styles available for each device within the Z8
Encore! XP® F0823 Series product line.
Table 1. F0823 Series Family Part Selection Guide
Part
Number
Flash
(KB)
RAM
(B)
ADC
Inputs
I/O
Packages
Z8F0823
Z8F0813
Z8F0423
Z8F0413
Z8F0223
Z8F0213
Z8F0123
Z8F0113
8
8
4
4
2
2
1
1
1024
1024
1024
1024
512
6–22
6–24
6–22
6–24
6–22
6–24
6–22
6–24
4–8
0
8-, 20-, and 28-pins
8-, 20-, and 28-pins
8-, 20-, and 28-pins
8-, 20-, and 28-pins
8-, 20-, and 28-pins
8-, 20-, and 28-pins
8-, 20-, and 28-pins
8-, 20-, and 28-pins
4–8
0
4–8
0
512
256
4–8
0
256
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P R E L I M I N A R Y
Part Selection Guide
Z8 Encore! XP® F0823 Series
Product Specification
3
Block Diagram
Figure 1 displays a block diagram of the F0823 Series architecture.
Internal
Precision
Oscillator
System
Clock
Oscillator
Control
Low Power
RC Oscillator
On-Chip
Debugger
POR/VBO
and Reset
Controller
eZ8
CPU
Interrupt
Controller
WDT
Memory Busses
Register Bus
Flash
RAM
Timers
UART
IrDA
ADC
Comparator
Controller
Controller
Flash
Memory
RAM
GPIO
Figure 1. Z8 Encore! XP F0823 Series Block Diagram
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P R E L I M I N A R Y
Block Diagram
Z8 Encore! XP® F0823 Series
Product Specification
4
CPU and Peripheral Overview
The eZ8 CPU, Zilog’s latest 8-bit central processing unit (CPU), meets the continuing
demand for faster and code-efficient microcontrollers. The eZ8 CPU executes a superset
of the original Z8 instruction set. The eZ8 CPU features include:
•
Direct register-to-register architecture allows each register to function as an
accumulator, improving execution time and decreasing the required program memory
•
Software stack allows much greater depth in subroutine calls and interrupts than
hardware stacks
•
•
•
Compatible with existing Z8 code
Expanded internal Register File allows access of up to 4 KB
New instructions improve execution efficiency for code developed using higher-level
programming languages, including C
•
•
Pipelined instruction fetch and execution
New instructions for improved performance including BIT, BSWAP, BTJ, CPC, LDC,
LDCI, LEA, MULT, and SRL
•
•
•
•
New instructions support 12-bit linear addressing of the Register File
Up to 10 MIPS operation
C-Compiler friendly
2 to 9 clock cycles per instruction
For more information about the eZ8 CPU, refer to the eZ8 CPU Core User Manual
(UM0128) available for download at www.zilog.com.
General-Purpose I/O
F0823 Series features 6 to 24 port pins (Ports A–C) for general-purpose I/O (GPIO). The
number of GPIO pins available is a function of package. Each pin is individually program-
mable. 5V-tolerant input pins are available on all I/Os on 8-pin devices, most I/Os on other
package types.
Flash Controller
The Flash Controller programs and erases Flash memory. The Flash Controller supports
protection against accidental program and erasure, as well as factory serialization and read
protection.
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P R E L I M I N A R Y
CPU and Peripheral Overview
Z8 Encore! XP® F0823 Series
Product Specification
5
Internal Precision Oscillator
The internal precision oscillator (IPO) is a trimmable clock source that requires no exter-
nal components.
10-Bit Analog-to-Digital Converter
The optional analog-to-digital converter (ADC) converts an analog input signal to a 10-bit
binary number. The ADC accepts inputs from eight different analog input pins in both sin-
gle-ended and differential modes.
Analog Comparator
The analog comparator compares the signal at an input pin with either an internal pro-
grammable voltage reference or a second input pin. The comparator output can be used to
drive either an output pin or to generate an interrupt.
Universal Asynchronous Receiver/Transmitter
The UART is full-duplex and capable of handling asynchronous data transfers. The UART
supports 8- and 9-bit data modes and selectable parity. The UART also supports multi-
drop address processing in hardware. The UART baud rate generator can be configured and
used as a basic 16-bit timer.
Timers
Two enhanced 16-bit reloadable timers can be used for timing/counting events or for
motor control operations. These timers provide a 16-bit programmable reload counter and
operate in One-Shot, Continuous, Gated, Capture, Capture Restart, Compare, Capture and
Compare, PWM Single Output, and PWM Dual Output modes.
Interrupt Controller
Z8 Encore! XP® F0823 Series products support up to 20 interrupts. These interrupts con-
sist of eight internal peripheral interrupts and 12 general-purpose I/O pin interrupt sources.
The interrupts have three levels of programmable interrupt priority.
Reset Controller
Z8 Encore! XP® F0823 Series products can be reset using the RESET pin, POR, WDT
time-out, Stop Mode exit, or Voltage Brown-Out warning signal. The RESET pin is bidi-
rectional, that is, it functions as reset source as well as a reset indicator.
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P R E L I M I N A R Y
CPU and Peripheral Overview
Z8 Encore! XP® F0823 Series
Product Specification
6
On-Chip Debugger
F0823 Series products feature an integrated On-Chip Debugger. The OCD provides a rich-
set of debugging capabilities, such as reading and writing registers, programming Flash
memory, setting breakpoints and executing code. A single-pin interface provides commu-
nication to the OCD.
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P R E L I M I N A R Y
CPU and Peripheral Overview
Z8 Encore! XP® F0823 Series
Product Specification
7
Pin Description
Z8 Encore! XP F0823 Series products are available in a variety of package styles and pin
configurations. This chapter describes the signals and pin configurations available for
each of the package styles. For information about physical package specifications, see the
Packaging chapter on page 212.
Available Packages
Table 2 lists the package styles that are available for each device in the F0823 Series prod-
uct line.
Table 2. F0823 Series Package Options
Part
Number
8-pin
PDIP
8-pin 20-pin 20-pin 20-pin 28-pin 28-pin 28-pin 8-pin QFN/
ADC
Yes
No
SOIC
PDIP
SOIC SSOP PDIP
SOIC SSOP
MLF-S
Z8F0823
Z8F0813
Z8F0423
Z8F0413
Z8F0223
Z8F0213
Z8F0123
Z8F0113
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Yes
No
X
X
X
X
Yes
No
X
X
X
X
Yes
No
X
X
X
X
Pin Configurations
Figures 2 through 4 display the pin configurations for all packages available in the F0823
Series. For description of signals, see Table 3. The analog input alternate functions
(ANAx) are not available on the Z8F0x13 devices. The analog supply pins (AVDD and
AVSS) are also not available on these parts, and are replaced by PB6 and PB7.
At reset, all pins of Ports A, B, and C default to an input state. In addition, any alternate
functionality is not enabled, so the pins function as general-purpose input ports until pro-
grammed otherwise.
The pin configurations listed are preliminary and subject to change based on manufactur-
ing limitations.
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P R E L I M I N A R Y
Pin Description
Z8 Encore! XP® F0823 Series
Product Specification
8
VSS
VDD
PA0/T0IN/T0OUT/DBG
1
2
3
4
8
7
6
5
PA5/TXD0/T1OUT/ANA0/CINP
PA4/RXD0/ANA1/CINN
PA1/T0OUT/ANA3/VREF/CLKIN
PA2/RESET/DE0/T1OUT
PA3/CTS0/ANA2/COUT/T1IN
Figure 2. Z8F08x3, Z8F04x3, F02x3 and Z8F01x3 in 8-Pin SOIC, QFN/MLF-S, or PDIP Package*
PB1/ANA1
PB2/ANA2
PB3/CLKIN/ANA3
VDD
PB0/ANA0
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
PC3/COUT/LED
PC2/ANA6/LED/VREF
PC1/ANA5/CINN/LED
PC0/ANA4/CINP/LED
PA0/T0IN/T0OUT
PA1/T0OUT
VSS
DBG
RESET
PA7/T1OUT
PA6/T1IN/T1OUT
PA5/TXD0
PA2/DE0
PA3/CTS0
PA4/RXD0
Figure 3. Z8F08x3, Z8F04x3, F02x3 and Z8F01x3 in 20-Pin SOIC, SSOP or PDIP Package*
PB2/ANA2
PB1/ANA1
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
PB0/ANA0
2
PB4/ANA7
PB5/VREF
3
PC3/COUT/LED
PC2/ANA6/LED
PC1/ANA5/CINN/LED
PC0/ANA4/CINP/LED
DBG
PB3/CLKIN/ANA3
(PB6) AVDD
4
5
6
VDD
PA0/T0IN/T0OUT
PA1/T0OUT
VSS
7
8
RESET
9
PC7/LED
(PB7) AVSS
PA2/DE0
10
11
12
13
14
PC6/LED
PA7/T1OUT
PC5/LED
PA3/CTS0
PA4/RXD0
PA5/TXD0
PC4/LED
PA6/T1IN/T1OUT
Figure 4. Z8F08x3, Z8F04x3, F02x3 and Z8F01x3 in 28-Pin SOIC, SSOP or PDIP Package*
PS024317-0914
P R E L I M I N A R Y
Pin Configurations
Z8 Encore! XP® F0823 Series
Product Specification
9
Note: *Analog input alternate functions (ANA) are not available on Z8F0x13 devices.
Signal Descriptions
Table 3 lists the Z8 Encore! XP F0823 Series signals. To determine the signals available
for the specific package styles, see the Pin Configurations section on page 7.
Table 3. Signal Descriptions
Signal Mnemonic
I/O
Description
General-Purpose I/O Ports A–D
PA[7:0]
PB[7:0]
I/O
I/O
Port A. These pins are used for general-purpose I/O.
1
Port B. These pins are used for general-purpose I/O. PB6 and PB7 are
available only in those devices without an ADC.
PC[7:0]
I/O
Port C. These pins are used for general-purpose I/O.
UART Controllers
TXD0
RXD0
CTS0
DE
O
I
Transmit Data. This signal is the transmit output from the UART and IrDA.
Receive Data. This signal is the receive input for the UART and IrDA.
Clear To Send. This signal is the flow control input for the UART.
I
O
Driver Enable. This signal allows automatic control of external RS-485
drivers. This signal is approximately the inverse of the TXE (Transmit
Empty) bit in the UART Status 0 Register. The DE signal can be used to
ensure the external RS-485 driver is enabled when data is transmitted by
the UART.
Timers
T0OUT/T1OUT
T0OUT/T1OUT
O
O
Timer Output 0–1. These signals are output from the timers.
Timer Complement Output 0–1. These signals are output from the timers
in PWM DUAL OUTPUT Mode.
T0IN/T1IN
I
Timer Input 0–1. These signals are used as the capture, gating and coun-
ter inputs. The T0IN signal is multiplexed T0OUT signals.
Comparator
CINP/CINN
I
Comparator Inputs. These signals are the positive and negative inputs to
the comparator.
Notes:
1. PB6 and PB7 are only available in 28-pin packages without ADC. In 28-pin packages with ADC, they are
replaced by AVDD and AVSS
.
2. The AVDD and AVSS signals are available only in 28-pin packages with ADC. They are replaced by PB6 and
PB7 on 28-pin packages without ADC.
PS024317-0914
P R E L I M I N A R Y
Signal Descriptions
Z8 Encore! XP® F0823 Series
Product Specification
10
Table 3. Signal Descriptions (Continued)
Signal Mnemonic
I/O
Description
COUT
O
Comparator Output. This is the output of the comparator.
Analog
ANA[7:0]
I
Analog port. These signals are used as inputs to the ADC. The ANA0,
ANA1, and ANA2 pins can also access the inputs and output of the inte-
grated transimpedance amplifier.
VREF
I/O
I
Analog-to-Digital Converter reference voltage input.
Clock Input
CLKIN
Clock Input Signal. This pin can be used to input a TTL-level signal to be
used as the system clock.
LED Drivers
LED
O
Direct LED drive capability. All port C pins have the capability to drive an
LED without any other external components. These pins have programma-
ble drive strengths set by the GPIO block.
On-Chip Debugger
DBG
I/O
Debug. This signal is the control and data input and output to and from the
OCD.
Caution: The DBG pin is open-drain and requires an external pull-up
resistor to ensure proper operation.
Reset
RESET
I/O
RESET. Generates a reset when asserted (driven Low). Also serves as a
reset indicator; the Z8 Encore! XP forces this pin Low when in reset. This
pin is open-drain and features an enabled internal pull-up resistor.
Power Supply
V
I
I
I
I
Digital Power Supply.
Analog Power Supply.
Digital Ground.
DD
2
AV
DD
V
SS
AV
Analog Ground.
SS
Notes:
1. PB6 and PB7 are only available in 28-pin packages without ADC. In 28-pin packages with ADC, they are
replaced by AVDD and AVSS
.
2. The AVDD and AVSS signals are available only in 28-pin packages with ADC. They are replaced by PB6 and
PB7 on 28-pin packages without ADC.
PS024317-0914
P R E L I M I N A R Y
Signal Descriptions
Z8 Encore! XP® F0823 Series
Product Specification
11
Pin Characteristics
Table 4 provides detailed information about the characteristics for each pin available on
Z8 Encore! XP F0823 Series 20- and 28-pin devices. Data in Table 4 is sorted alphabeti-
cally by the pin symbol mnemonic.
Note: All six I/O pins on the 8-pin packages are 5V-tolerant (unless the pull-up devices are
enabled). The right-most column in Table 4 describes 5V tolerance for the 20- and 28-pin
packages only.
Table 4. Pin Characteristics (20- and 28-pin Devices)*
Active
Low or
Internal
Pull-up Schmitt-
Symbol
Reset
Active Tristate or Pull- Trigger
Open Drain
Output
5V
Tolerance
Mnemonic Direction Direction High Output
down
N/A
N/A
No
Input
N/A
N/A
Yes
AVDD
AVSS
DBG
N/A
N/A
I/O
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Yes
Yes
N/A
N/A
Yes
N/A
NA
N/A
I
I
Yes
PA[7:0]
I/O
Program-
mable
Yes
Yes,
Programmable
PA[7:2] only
Pull-up
PB[7:0]
PC[7:0]
RESET
I/O
I/O
I/O
I
I
N/A
N/A
Yes
Yes
Program-
mable
Pull-up
Yes
Yes
Yes
Yes,
Programmable
PB[7:6] only
PC[7:3] only
Yes
Program-
mable
Pull-up
Yes,
Programmable
I/O
Low (in
Yes
(PD0
only)
Always
on for
RESET
Always on for
RESET
(defaults Reset
to
Mode)
RESET)
VDD
VSS
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
Note: PB6 and PB7 are available only in the devices without ADC.
PS024317-0914
P R E L I M I N A R Y
Pin Characteristics
Z8 Encore! XP® F0823 Series
Product Specification
12
Table 5 provides detailed information about the characteristics for each pin available on
Z8 Encore! XP F0823 Series 8-pin devices.
Table 5. Pin Characteristics (8-Pin Devices)
Active
Low
or
Internal
Pull-up Schmitt-
Symbol
Reset Active Tristate or Pull- Trigger
Open Drain
Output
5V
Tolerance
Mnemonic Direction Direction High Output
down
Input
PA0/DBG
I/O
I (but can N/A
change
Yes
Program-
mable
Yes
Yes,
Programmable
Yes, unless
pull-ups
during
Pull-up
enabled
reset if
key
sequence
detected)
PA1
I/O
I/O
I
N/A
N/A
Yes
Yes
Program-
mable
Pull-up
Yes
Yes
Yes,
Programmable
Yes, unless
pull-ups
enabled
RESET/PA2
I/O
(defaults
to
Program-
mable for
PA2;
always
on for
Programma- Yes, unless
ble for PA2;
always on for
RESET
pull-ups
enabled
RESET)
RESET
PA[5:3]
I/O
I
N/A
Yes
Program-
mable
Yes
Yes,
Programmable
Yes, unless
pull-ups
Pull-up
enabled
VDD
VSS
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
PS024317-0914
P R E L I M I N A R Y
Pin Characteristics
Z8 Encore! XP® F0823 Series
Product Specification
13
Address Space
The eZ8 CPU can access three distinct address spaces:
•
•
•
The Register File contains addresses for the general-purpose registers and the eZ8
CPU, peripheral, and general-purpose I/O Port Control Registers
The Program Memory contains addresses for all memory locations having executable
code and/or data
The Data Memory contains addresses for all memory locations that contain data only
These three address spaces are covered briefly in the following subsections. For more
detailed information regarding the eZ8 CPU and its address space, refer to the eZ8 CPU
Core User Manual (UM0128), available for download at www.zilog.com.
Register File
The Register File address space in the Z8 Encore! XP™ MCU is 4KB (4096 bytes). The
Register File is composed of two sections: control registers and general-purpose registers.
When instructions are executed, registers defined as sources are read, and registers defined
as destinations are written. The architecture of the eZ8 CPU allows all general-purpose
registers to function as accumulators, address pointers, index registers, stack areas, or
scratch pad memory.
The upper 256 bytes of the 4KB Register File address space are reserved for control of the
eZ8 CPU, the on-chip peripherals, and the I/O ports. These registers are located at
addresses from F00hto FFFh. Some of the addresses within the 256 B control register
section are reserved (unavailable). Reading from a reserved Register File address returns
an undefined value. Writing to reserved Register File addresses is not recommended and
can produce unpredictable results.
The on-chip RAM always begins at address 000hin the Register File address space. Z8
Encore! XP F0823 Series devices contain 256B–1KB of on-chip RAM. Reading from
Register File addresses outside the available RAM addresses (and not within the control
register address space) returns an undefined value. Writing to these Register File addresses
produces no effect.
Program Memory
The eZ8 CPU supports 64KB of Program Memory address space. F0823 Series devices
contain 1KB to 8KB of on-chip Flash memory in the Program Memory address space.
Reading from Program Memory addresses outside the available Flash memory addresses
PS024317-0914
P R E L I M I N A R Y
Address Space
Z8 Encore! XP® F0823 Series
Product Specification
14
returns FFh. Writing to these unimplemented Program Memory addresses produces no
effect. Table 6 describes the Program Memory maps for the Z8 Encore! XP F0823 Series
products.
Table 6. Z8 Encore! XP F0823 Series Program Memory Maps
Program Memory Address (Hex)
Function
Z8F0823 and Z8F0813 Products
0000–0001
Flash Option Bits
Reset Vector
0002–0003
0004–0005
WDT Interrupt Vector
Illegal Instruction Trap
Interrupt Vectors*
Oscillator Fail Traps*
Program Memory
0006–0007
0008–0037
0038–003D
003E–0FFF
Z8F0423 and Z8F0413 Products
0000–0001
Flash Option Bits
Reset Vector
0002–0003
0004–0005
WDT Interrupt Vector
Illegal Instruction Trap
Interrupt Vectors*
Oscillator Fail Traps*
Program Memory
0006–0007
0008–0037
0038–003D
003E–0FFF
Z8F0223 and Z8F0213 Products
0000–0001
Flash Option Bits
Reset Vector
0002–0003
0004–0005
WDT Interrupt Vector
Illegal Instruction Trap
Interrupt Vectors*
Oscillator Fail Traps*
Program Memory
0006–0007
0008–0037
0038–003D
003E–07FF
Note: *See the Trap and Interrupt Vectors in Order of Priority section on page 55
for a list of the interrupt vectors and traps.
PS024317-0914
P R E L I M I N A R Y
Program Memory
Z8 Encore! XP® F0823 Series
Product Specification
15
Table 6. Z8 Encore! XP F0823 Series Program Memory Maps (Continued)
Program Memory Address (Hex)
Function
Z8F0123 and Z8F0113 Products
0000–0001
Flash Option Bits
Reset Vector
0002–0003
0004–0005
WDT Interrupt Vector
Illegal Instruction Trap
Interrupt Vectors*
Oscillator Fail Traps*
Program Memory
0006–0007
0008–0037
0038–003D
003E–03FF
Note: *See the Trap and Interrupt Vectors in Order of Priority section on page 55
for a list of the interrupt vectors and traps.
Data Memory
Z8 Encore! XP F0823 Series does not use the eZ8 CPU’s 64KB Data Memory address
space.
Flash Information Area
Table 7 lists the F0823 Series Flash Information Area. This 128B Information Area is
accessed by setting bit 7 of the Flash Page Select Register to 1. When access is enabled,
the Flash Information Area is mapped into the Program Memory and overlays the 128
bytes at addresses FE00hto FF7Fh. When the Information Area access is enabled, all
reads from these Program Memory addresses return the Information Area data rather than
the Program Memory data. Access to the Flash Information Area is read-only.
Table 7. F0823 Series Flash Memory Information Area Map
Program Memory
Address (Hex)
FE00–FE3F
FE40–FE53
Function
Zilog Option Bits.
Part Number.
20-character ASCII alphanumeric code
Left-justified and filled with Fh.
FE54–FE5F
FE60–FE7F
FE80–FFFF
Reserved.
Zilog Calibration Data.
Reserved.
PS024317-0914
P R E L I M I N A R Y
Data Memory
Z8 Encore! XP® F0823 Series
Product Specification
16
Register Map
Table 8 lists an address map of the Z8 Encore! XP F0823 Series Register File. Not all
devices and package styles in the Z8 Encore! XP F0823 Series support the ADC, nor all
GPIO ports. Consider registers for unimplemented peripherals to be reserved.
Table 8. Register File Address Map
Page
Address (Hex)
Register Description
Mnemonic
Reset (Hex)
No.
General-Purpose RAM
Z8F0823/Z8F0813 Devices
000–3FF
400–EFF
General-Purpose Register File RAM
Reserved
—
—
XX
XX
Z8F0423/Z8F0413 Devices
000–3FF
400–EFF
General-Purpose Register File RAM
Reserved
—
—
XX
XX
Z8F0223/Z8F0213 Devices
000–1FF
200–EFF
General-Purpose Register File RAM
Reserved
—
—
XX
XX
Z8F0123/Z8F0113 Devices
000–0FF
100–EFF
General-Purpose Register File RAM
—
—
XX
XX
Reserved
Timer 0
F00
Timer 0 High Byte
T0H
T0L
00
01
FF
FF
00
00
00
00
84
84
85
85
86
86
87
88
F01
Timer 0 Low Byte
F02
Timer 0 Reload High Byte
Timer 0 Reload Low Byte
Timer 0 PWM High Byte
Timer 0 PWM Low Byte
Timer 0 Control 0
T0RH
F03
T0RL
F04
T0PWMH
T0PWML
T0CTL0
T0CTL1
F05
F06
F07
Timer 0 Control 1
Timer 1
F08
Timer 1 High Byte
Timer 1 Low Byte
T1H
T1L
00
01
84
84
F09
Note: XX=Undefined.
PS024317-0914
P R E L I M I N A R Y
Register Map
Z8 Encore! XP® F0823 Series
Product Specification
17
Table 8. Register File Address Map (Continued)
Page
No.
Address (Hex)
Register Description
Mnemonic
Reset (Hex)
Timer 1 (cont’d)
F0A
Timer 1 Reload High Byte
Timer 1 Reload Low Byte
Timer 1 PWM High Byte
Timer 1 PWM Low Byte
Timer 1 Control 0
T1RH
T1RL
FF
FF
00
00
00
00
XX
85
85
86
86
87
84
F0B
F0C
T1PWMH
T1PWML
T1CTL0
T1CTL1
—
F0D
F0E
F0F
Timer 1 Control 1
F10–F3F
Reserved
UART
F40
UART0 Transmit Data
UART0 Receive Data
UART0 Status 0
U0TXD
U0RXD
U0STAT0
U0CTL0
U0CTL1
U0STAT1
U0ADDR
U0BRH
U0BRL
—
XX
109
109
110
112
112
111
115
115
115
XX
F41
0000011Xb
F42
UART0 Control 0
00
00
00
00
FF
FF
XX
F43
UART0 Control 1
F44
UART0 Status 1
F45
UART0 Address Compare
UART0 Baud Rate High Byte
UART0 Baud Rate Low Byte
Reserved
F46
F47
F48–F6F
Analog-to-Digital Converter (ADC)
F70
ADC Control 0
ADC Control 1
ADC Data High Byte
ADC Data Low Bits
Reserved
ADCCTL0
ADCCTL1
ADCD_H
ADCD_L
—
00
80
128
128
131
131
F71
F72
XX
XX
XX
F73
F74–F7F
Low Power Control
F80
F81
Power Control 0
PWRCTL0
—
80
32
Reserved
XX
LED Controller
F82
F83
LED Drive Enable
LEDEN
00
00
51
52
LED Drive Level High Byte
LEDLVLH
Note: XX=Undefined.
PS024317-0914
P R E L I M I N A R Y
Register Map
Z8 Encore! XP® F0823 Series
Product Specification
18
Table 8. Register File Address Map (Continued)
Page
No.
Address (Hex)
Register Description
Mnemonic
Reset (Hex)
LED Controller (cont’d)
F84
F85
LED Drive Level Low Byte
LEDLVLL
—
00
53
Reserved
XX
Oscillator Control
F86
Oscillator Control
Reserved
OSCCTL
—
A0
XX
174
134
F87–F8F
Comparator 0
F90
Comparator 0 Control
Reserved
CMP0
—
14
F91–FBF
XX
Interrupt Controller
FC0
Interrupt Request 0
IRQ0
IRQ0ENH
IRQ0ENL
IRQ1
00
00
00
00
00
00
00
00
00
XX
00
00
00
59
62
62
60
64
64
61
65
66
FC1
IRQ0 Enable High Bit
IRQ0 Enable Low Bit
Interrupt Request 1
IRQ1 Enable High Bit
IRQ1 Enable Low Bit
Interrupt Request 2
IRQ2 Enable High Bit
IRQ2 Enable Low Bit
Reserved
FC2
FC3
FC4
IRQ1ENH
IRQ1ENL
IRQ2
FC5
FC6
FC7
IRQ2ENH
IRQ2ENL
—
FC8
FC9–FCC
FCD
FCE
FCF
Interrupt Edge Select
Shared Interrupt Select
Interrupt Control
IRQES
67
67
68
IRQSS
IRQCTL
GPIO Port A
FD0
Port A Address
Port A Control
PAADDR
PACTL
PAIN
00
00
XX
00
40
42
43
43
FD1
FD2
Port A Input Data
Port A Output Data
FD3
PAOUT
GPIO Port B
FD4
Port B Address
Port B Control
PBADDR
PBCTL
00
00
40
42
FD5
Note: XX=Undefined.
PS024317-0914
P R E L I M I N A R Y
Register Map
Z8 Encore! XP® F0823 Series
Product Specification
19
Table 8. Register File Address Map (Continued)
Page
No.
Address (Hex)
Register Description
Mnemonic
Reset (Hex)
GPIO Port B (cont’d)
FD6
FD7
Port B Input Data
PBIN
XX
00
43
43
Port B Output Data
PBOUT
GPIO Port C
FD8
Port C Address
Port C Control
Port C Input Data
Port C Output Data
Reserved
PCADDR
PCCTL
PCIN
00
00
40
42
43
43
FD9
FDA
XX
00
XX
FDB
PCOUT
—
FDC–FEF
Watchdog Timer (WDT)
FF0
Reset Status
RSTSTAT
WDTCTL
WDTU
WDTH
WDTL
—
XX
XX
FF
FF
FF
XX
94
94
95
95
96
Watchdog Timer Control
FF1
Watchdog Timer Reload Upper Byte
Watchdog Timer Reload High Byte
Watchdog Timer Reload Low Byte
Reserved
FF2
FF3
FF4–FF5
Trim Bit Control
FF6
FF7
Trim Bit Address
Trim Data
TRMADR
TRMDR
00
150
151
XX
Flash Memory Controller
FF8
FF8
FF9
Flash Control
FCTL
FSTAT
FPS
00
00
00
00
00
00
143
144
145
146
147
147
Flash Status
Flash Page Select
Flash Sector Protect
FPROT
FFREQH
FFREQL
FFA
FFB
Flash Programming Frequency High Byte
Flash Programming Frequency Low Byte
Note: XX=Undefined.
PS024317-0914
P R E L I M I N A R Y
Register Map
Z8 Encore! XP® F0823 Series
Product Specification
20
Table 8. Register File Address Map (Continued)
Page
No.
Address (Hex)
Register Description
Mnemonic
Reset (Hex)
eZ8 CPU
FFC
Flags
—
XX
XX
XX
XX
Refer
to the
eZ8
CPU
Core
User
Man-
ual
FFD
Register Pointer
Stack Pointer High Byte
Stack Pointer Low Byte
RP
FFE
SPH
SPL
FFF
(UM01
28)
Note: XX=Undefined.
PS024317-0914
P R E L I M I N A R Y
Register Map
Z8 Encore! XP® F0823 Series
Product Specification
21
Reset and Stop-Mode Recovery
The Reset Controller within the Z8 Encore! XP F0823 Series controls Reset and Stop-
Mode Recovery operation and provides indication of low supply voltage conditions. In
typical operation, the following events cause a Reset:
•
•
•
Power-On Reset (POR)
Voltage Brown-Out (VBO)
Watchdog Timer time-out (when configured by the WDT_RES Flash Option Bit to
initiate a reset)
•
•
External RESET pin assertion (when the alternate RESET function is enabled by the
GPIO register)
On-chip Debugger initiated Reset (OCDCTL[0] set to 1)
When the device is in Stop Mode, a Stop-Mode Recovery is initiated by either of the fol-
lowing:
•
•
Watchdog Timer time-out
GPIO port input pin transition on an enabled Stop-Mode Recovery source
The VBO circuitry on the device performs the following function:
Generates the VBO reset when the supply voltage drops below a minimum safe level
•
Reset Types
F0823 Series MCUs provide several different types of Reset operations. Stop-Mode
Recovery is considered a form of Reset. Table 9 lists the types of Reset and their operating
characteristics. The duration of a System Reset is longer if the external crystal oscillator is
enabled by the Flash option bits; this configuration allows additional time for oscillator
startup.
Table 9. Reset and Stop-Mode Recovery Characteristics and Latency
Reset Characteristics and Latency
Reset Type
Control Registers
eZ8 CPU Reset Latency (Delay)
System Reset Reset (as applicable)
Reset
Reset
66 Internal Precision Oscillator Cycles
Stop-Mode
Recovery
Unaffected, except WDT_CTL
and OSC_CTL registers
66 Internal Precision Oscillator Cycles
+ IPO startup time
PS024317-0914
P R E L I M I N A R Y
Reset and Stop-Mode Recovery
Z8 Encore! XP® F0823 Series
Product Specification
22
During a System Reset or Stop-Mode Recovery, the IPO requires 4 µs to start up. Then the
Z8 Encore! XP F0823 Series device is held in Reset for 66 cycles of the Internal Precision
Oscillator. If the crystal oscillator is enabled in the Flash option bits, this reset period is
increased to 5000 IPO cycles. When a reset occurs because of a low voltage condition or
Power-On Reset, this delay is measured from the time that the supply voltage first exceeds
the POR level. If the external pin reset remains asserted at the end of the reset period, the
device remains in reset until the pin is deasserted.
At the beginning of Reset, all GPIO pins are configured as inputs with pull-up resistor dis-
abled.
During Reset, the eZ8 CPU and on-chip peripherals are idle; however, the on-chip crystal
oscillator and Watchdog Timer oscillator continue to run.
Upon Reset, control registers within the Register File that have a defined Reset value are
loaded with their reset values. Other control registers (including the Stack Pointer, Regis-
ter Pointer, and Flags) and general-purpose RAM are undefined following Reset. The eZ8
CPU fetches the Reset vector at Program Memory addresses 0002hand 0003hand loads
that value into the Program Counter. Program execution begins at the Reset vector
address.
When the control registers are re-initialized by a system reset, the system clock after reset
is always the IPO. The software must reconfigure the oscillator control block, such that the
correct system clock source is enabled and selected.
PS024317-0914
P R E L I M I N A R Y
Reset Types
Z8 Encore! XP® F0823 Series
Product Specification
23
Reset Sources
Table 10 lists the possible sources of a System Reset.
Table 10. Reset Sources and Resulting Reset Type
Operating Mode Reset Source
Special Conditions
Normal or Halt
modes
Power-On Reset/Voltage Brown- Reset delay begins after supply voltage exceeds
Out.
POR level.
Watchdog Timer time-out when
configured for Reset.
None.
RESET pin assertion.
All reset pulses less than three system clocks in
width are ignored.
OCD initiated Reset (OCDCTL[0] System Reset, except the OCD is unaffected by
set to 1). the reset.
Power-On Reset/Voltage Brown- Reset delay begins after supply voltage exceeds
Stop Mode
Out.
POR level.
RESET pin assertion.
All reset pulses less than the specified analog
delay are ignored. See the Electrical Characteris-
tics chapter on page 198.
DBG pin driven Low.
None.
Power-On Reset
Each device in the Z8 Encore! XP F0823 Series contains an internal POR circuit. The
POR circuit monitors the supply voltage and holds the device in the Reset state until the
supply voltage reaches a safe operating level. After the supply voltage exceeds the POR
voltage threshold (VPOR), the device is held in the Reset state until the POR Counter has
timed out. If the crystal oscillator is enabled by the option bits, this time-out is longer.
After the Z8 Encore! XP F0823 Series device exits the POR state, the eZ8 CPU fetches the
Reset vector. Following the POR, the POR status bit in Watchdog Timer Control
(WDTCTL) Register is set to 1.
Figure 5 displays POR operation. For the POR threshold voltage (VPOR), see the Electri-
cal Characteristics chapter on page 198.
PS024317-0914
P R E L I M I N A R Y
Reset Sources
Z8 Encore! XP® F0823 Series
Product Specification
24
VCC = 3.3 V
VPOR
VVBO
Program
Execution
VCC = 0.0V
Internal Precision
Oscillator
Internal RESET
signal
POR
counter delay
Note: Not to Scale
Figure 5. Power-On Reset Operation
Voltage Brown-Out Reset
The devices in the Z8 Encore! XP F0823 Series provide low VBO protection. The VBO
circuit senses when the supply voltage drops to an unsafe level (below the VBO threshold
voltage) and forces the device into the Reset state. While the supply voltage remains
below the POR voltage threshold (VPOR), the VBO block holds the device in the Reset.
After the supply voltage again exceeds the Power-On Reset voltage threshold, the device
progresses through a full System Reset sequence, as described in the Power-On Reset sec-
tion on page 23. Following POR, the POR status bit in the Reset Status (RSTSTAT) Regis-
ter is set to 1. Figure 6 displays Voltage Brown-Out operation. For the VBO and POR
threshold voltages (VVBO and VPOR), see the Electrical Characteristics chapter on
page 198.
The VBO circuit can be either enabled or disabled during Stop Mode. Operation during
Stop Mode is set by the VBO_AO Flash Option bit. For information about configuring
VBO_AO, see the Flash Option Bits chapter on page 148.
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Product Specification
25
VCC = 3.3 V
VCC = 3.3 V
VPOR
VVBO
Program
Voltage
Program
Execution
Brown-Out
Execution
WDT Clock
System Clock
Internal RESET
signal
POR
counter delay
Note: Not to Scale
Figure 6. Voltage Brown-Out Reset Operation
The POR level is greater than the VBO level by the specified hysteresis value. This
ensures that the device undergoes a POR after recovering from a VBO condition.
Watchdog Timer Reset
If the device is in Normal or Stop Mode, the Watchdog Timer can initiate a System Reset
at time-out if the WDT_RES Flash Option Bit is programmed to 1. This is the unpro-
grammed state of the WDT_RES Flash Option Bit. If the bit is programmed to 0, it config-
ures the Watchdog Timer to cause an interrupt, not a System Reset, at time-out.
The WDT status bit in the WDT Control Register is set to signify that the reset was initi-
ated by the Watchdog Timer.
External Reset Input
The RESET pin has a Schmitt-Triggered input and an internal pull-up resistor. Once the
RESET pin is asserted for a minimum of four system clock cycles, the device progresses
through the System Reset sequence. Because of the possible asynchronicity of the system
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Product Specification
26
clock and reset signals, the required reset duration can be as short as three clock periods
and as long as four. A reset pulse three clock cycles in duration might trigger a reset; a
pulse four cycles in duration always triggers a reset.
While the RESET input pin is asserted Low, the Z8 Encore! XP F0823 Series devices
remain in the Reset state. If the RESET pin is held Low beyond the System Reset time-
out, the device exits the Reset state on the system clock rising edge following RESET pin
deassertion. Following a System Reset initiated by the external RESET pin, the EXT sta-
tus bit in the WDT Control (WDTCTL) register is set to 1.
External Reset Indicator
During System Reset or when enabled by the GPIO logic (see the Port A–C Control Reg-
isters section on page 42), the RESET pin functions as an open-drain (active Low) reset
mode indicator in addition to the input functionality. This reset output feature allows an Z8
Encore! XP F0823 Series device to reset other components to which it is connected, even
if that reset is caused by internal sources such as POR, VBO, or WDT events.
After an internal reset event occurs, the internal circuitry begins driving the RESET pin
Low. The RESET pin is held Low by the internal circuitry until the appropriate delay
listed in Table 9 has elapsed.
On-Chip Debugger Initiated Reset
A POR is initiated using the On-Chip Debugger by setting the RST bit in the OCD Control
Register. The OCD block is not reset but the rest of the chip goes through a normal system
reset. The RST bit automatically clears during the System Reset. Following the System
Reset, the POR bit in the Reset Status (RSTSTAT) Register is set.
Stop-Mode Recovery
The device enters into Stop Mode when eZ8 CPU executes a stop instruction. For more
details about Stop Mode, see the Low-Power Modes section on page 30. During Stop-
Mode Recovery, the CPU is held in reset for 66 IPO cycles if the crystal oscillator is dis-
abled or 5000 cycles if it is enabled. The SMR delay also included the time required to
start up the IPO.
Stop-Mode Recovery does not affect on-chip registers other than the Watchdog Timer
Control Register (WDTCTL) and the Oscillator Control Register (OSCCTL). After any
Stop-Mode Recovery, the IPO is enabled and selected as the system clock. If another sys-
tem clock source is required or IPO disabling is required, the Stop-Mode Recovery code
must reconfigure the oscillator control block such that the correct system clock source is
enabled and selected.
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Stop-Mode Recovery
Z8 Encore! XP® F0823 Series
Product Specification
27
The eZ8 CPU fetches the Reset vector at Program Memory addresses 0002hand 0003h
and loads that value into the Program Counter. Program execution begins at the Reset vec-
tor address. Following Stop-Mode Recovery, the Stop bit in the Watchdog Timer Control
Register is set to 1. Table 11 lists the Stop-Mode Recovery sources and resulting actions.
The section following the table provides more detailed information about each of the Stop-
Mode Recovery sources.
Table 11. Stop-Mode Recovery Sources and Resulting Action
Operating Mode Stop-Mode Recovery Source
Action
Stop Mode
Watchdog Timer time-out when configured Stop-Mode Recovery
for Reset
Watchdog Timer time-out when configured Stop-Mode Recovery followed by interrupt
for interrupt
(if interrupts are enabled)
Data transition on any GPIO port pin
Stop-Mode Recovery
enabled as a Stop-Mode Recovery source
Assertion of external RESET Pin
Debug Pin driven Low
System Reset
System Reset
Stop-Mode Recovery Using Watchdog Timer Time-Out
If the Watchdog Timer times out during Stop Mode, the device undergoes a Stop-Mode
Recovery sequence. In the Watchdog Timer Control Register, the WDT and Stop bits are set
to 1. If the Watchdog Timer is configured to generate an interrupt upon time-out and Z8
Encore! XP F0823 Series device is configured to respond to interrupts, the eZ8 CPU services
the Watchdog Timer interrupt request following the normal Stop-Mode Recovery sequence.
Stop-Mode Recovery Using a GPIO Port Pin Transition
Each of the GPIO port pins can be configured as a Stop-Mode Recovery input source. On
any GPIO pin enabled as a Stop-Mode Recovery source, a change in the input pin value
(from High to Low or from Low to High) initiates Stop-Mode Recovery.
The SMR pulses shorter than specified does not trigger a recovery. When this happens, the
Stop bit in the Reset Status (RSTSTAT) Register is set to 1.
Note:
In Stop Mode, the GPIO Port Input Data registers (PxIN) are disabled. The Port Input
Data registers record the port transition only if the signal stays on the port pin through the
end of the Stop-Mode Recovery delay. As a result, short pulses on the port pin can initiate
Stop-Mode Recovery without being written to the Port Input Data Register or without ini-
tiating an interrupt (if enabled for that pin).
Caution:
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Stop-Mode Recovery
Z8 Encore! XP® F0823 Series
Product Specification
28
Stop-Mode Recovery Using the External RESET Pin
When a Z8 Encore! XP F0823 Series device is in Stop Mode and the external RESET pin
is driven Low, a system reset occurs. Because of a glitch filter operating on the RESET
pin, the Low pulse must be greater than the minimum width specified, or it is ignored. For
more details, see the Electrical Characteristics chapter on page 198.
Reset Register Definitions
The following sections define the Reset registers.
Reset Status Register
The Reset Status (RSTSTAT) Register is a read-only register that indicates the source of
the most recent Reset event, indicates a Stop-Mode Recovery event, and indicates a
Watchdog Timer time-out. Reading this register resets the upper four bits to 0.
This register shares its address with the Watchdog Timer Control Register, which is write-
only; see Table 12.
Table 12. Reset Status Register (RSTSTAT)
Bit
7
6
5
4
3
2
1
0
POR
STOP
WDT
EXT
Reserved
Field
See descriptions in Table 13
0
0
0
0
0
RESET
R/W
R
R
R
R
R
R
R
R
FF0h
Address
Bit
Description
[7]
POR
Power-On Reset Indicator
If this bit is set to 1, a Power-On Reset event has occurred. This bit is reset to 0 if a WDT time-
out or Stop-Mode Recovery occurs. This bit is also reset to 0 when the register is read. For
POR/Stop Mode Recover event values, please see Table 13.
[6]
STOP
Stop-Mode Recovery Indicator
If this bit is set to 1, a Stop-Mode Recovery is occurred. If the Stop and WDT bits are both set
to 1, the Stop-Mode Recovery occurred because of a WDT time-out. If the Stop bit is 1 and the
WDT bit is 0, the Stop-Mode Recovery was not caused by a WDT time-out. This bit is reset by
a POR or a WDT time-out that occurred while not in Stop Mode. Reading this register also
resets this bit. For POR/Stop Mode Recover event values, please see Table 13.
[5]
WDT
Watchdog Timer Time-Out Indicator
If this bit is set to 1, a WDT time-out has occurred. A POR resets this pin. A Stop-Mode Recov-
ery from a change in an input pin also resets this bit. Reading this register resets this bit; this
read must occur before clearing the WDT interrupt. For POR/Stop Mode Recover event values,
please see Table 13.
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Reset Register Definitions
Z8 Encore! XP® F0823 Series
Product Specification
29
Bit
Description (Continued)
External Reset Indicator
[4]
EXT
If this bit is set to 1, a Reset initiated by the external RESET pin occurred. A Power-On Reset
or a Stop-Mode Recovery from a change in an input pin resets this bit. Reading this register
resets this bit. For POR/Stop Mode Recover event values, please see Table 13.
[3:0]
Reserved
These bits are reserved and must be programmed to 0000 when read.
Table 13. POR Indicator Values
Reset or Stop-Mode Recovery Event
Power-On Reset
POR
STOP
WDT
EXT
0
1
0
0
1
1
0
0
0
0
0
0
0
1
1
0
0
1
0
0
0
1
Reset using RESET pin assertion
1
Reset using WDT time-out
0
Reset using the OCD (OCTCTL[1] set to 1)
Reset from Stop Mode using DBG Pin driven Low
Stop-Mode Recovery using GPIO pin transition
Stop-Mode Recovery using WDT time-out
0
0
0
0
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Reset Register Definitions
Z8 Encore! XP® F0823 Series
Product Specification
30
Low-Power Modes
Z8 Encore! XP F0823 Series products contain power-saving features. The highest level of
power reduction is provided by the Stop Mode, in which nearly all device functions are
powered down. The next lower level of power reduction is provided by the Halt Mode, in
which the CPU is powered down.
Further power savings can be implemented by disabling individual peripheral blocks
while in Active Mode (defined as being in neither Stop nor Halt Mode).
Stop Mode
Executing the eZ8 CPU’s Stop instruction places the device into Stop Mode, powering
down all peripherals except the Voltage Brown-Out detector, and the Watchdog Timer.
These two blocks may also be disabled for additional power savings. In Stop Mode, the
operating characteristics are:
•
Primary crystal oscillator and internal precision oscillator are stopped; XIN and XOUT
(if previously enabled) are disabled, and PA0/PA1 revert to the states programmed by
the GPIO registers
•
•
•
•
System clock is stopped
eZ8 CPU is stopped
Program counter (PC) stops incrementing
Watchdog Timer’s internal RC oscillator continues to operate if enabled by the Oscil-
lator Control Register
•
•
If enabled, the Watchdog Timer logic continues to operate
If enabled for operation in Stop Mode by the associated Flash Option Bit, the Voltage
Brown-Out protection circuit continues to operate
•
All other on-chip peripherals are idle
To minimize current in Stop Mode, all GPIO pins that are configured as digital inputs must
be driven to one of the supply rails (VCC or GND). Additionally, any GPIOs configured as
outputs must also be driven to one of the supply rails. The device can be brought out of
Stop Mode using Stop-Mode Recovery. For more information about Stop-Mode Recovery,
see the Reset and Stop-Mode Recovery chapter on page 21.
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31
Halt Mode
Executing the eZ8 CPU’s Halt instruction places the device into Halt Mode, which powers
down the CPU but leaves all other peripherals active. In Halt Mode, the operating charac-
teristics are:
•
•
•
•
•
•
•
Primary oscillator is enabled and continues to operate
System clock is enabled and continues to operate
eZ8 CPU is stopped
Program counter stops incrementing
Watchdog Timer’s internal RC oscillator continues to operate
If enabled, the Watchdog Timer continues to operate
All other on-chip peripherals continue to operate
The eZ8 CPU can be brought out of Halt Mode by any of the following operations:
•
•
•
•
•
Interrupt
Watchdog Timer time-out (interrupt or reset)
Power-On Reset
Voltage Brown-Out reset
External RESET pin assertion
To minimize current in Halt Mode, all GPIO pins that are configured as inputs must be
driven to one of the supply rails (VCC or GND).
Peripheral-Level Power Control
In addition to the Stop and Halt modes, it is possible to disable each peripheral on each of
the Z8 Encore! XP F0823 Series devices. Disabling a given peripheral minimizes its
power consumption.
Power Control Register Definitions
The following sections describe the power control registers.
Power Control Register 0
Each bit of the following registers disables a peripheral block, either by gating its system
clock input or by removing power from the block.
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Note: This register is only reset during a Power-On Reset sequence. Other System Reset events
do not affect it.
Table 14. Power Control Register 0 (PWRCTL0)
Bit
7
6
5
4
3
2
1
0
Reserved
Reserved
VBO
Reserved
ADC
COMP
Reserved
Field
1
0
0
0
0
0
0
0
RESET
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
F80h
Address
Bit
Description
Reserved
[7]
This bit is reserved and must be programmed to 1.
[6:5]
Reserved
These bits are reserved and must be programmed to 00.
[4]
VBO
Voltage Brown-Out Detector Disable
This bit and the VBO_AO Flash option bit must both enable the VBO for the VBO to be active.
0 = VBO enabled.
1 = VBO disabled.
[3]
Reserved
This bit is reserved and must be programmed to 0.
[2]
ADC
Analog-to-Digital Converter Disable
0 = Analog-to-Digital Converter enabled.
1 = Analog-to-Digital Converter disabled.
[1]
COMP
Comparator Disable
0 = Comparator is enabled.
1 = Comparator is disabled.
[0]
Reserved
This bit is reserved and must be programmed to 0.
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Z8 Encore! XP® F0823 Series
Product Specification
33
General-Purpose Input/Output
Z8 Encore! XP F0823 Series products support a maximum of 24 port pins (Ports A–C) for
general-purpose input/output (GPIO) operations. Each port contains control and data reg-
isters. The GPIO control registers determine data direction, open-drain, output drive cur-
rent, programmable pull-ups, Stop-Mode Recovery functionality, and alternate pin
functions. Each port pin is individually programmable. In addition, the Port C pins are
capable of direct LED drive at programmable drive strengths.
GPIO Port Availability By Device
Table 15 lists the port pins available with each device and package type.
Table 15. Port Availability by Device and Package Type
Devices
Package 10-Bit ADC Port A
Port B
Port C
Total I/O
Z8F0823SB, Z8F0823PB
Z8F0423SB, Z8F0423PB
Z8F0223SB, Z8F0223PB
Z8F0123SB, Z8F0123PB
8-pin
Yes
[5:0]
[5:0]
[7:0]
[7:0]
[7:0]
[7:0]
No
No
6
Z8F0813SB, Z8F0813PB
Z8F0413SB, Z8F0413PB
Z8F0213SB, Z8F0213PB
Z8F0113SB, Z8F011vPB
8-pin
No
No
No
6
Z8F0823PH, Z8F0823HH
Z8F0423PH, Z8F0423HH
Z8F0223PH, Z8F0223HH
Z8F0123PH, Z8F0123HH
20-pin
20-pin
28-pin
28-pin
Yes
No
[3:0]
[3:0]
[5:0]
[7:0]
[3:0]
[3:0]
[7:0]
[7:0]
16
16
22
24
Z8F0813PH, Z8F0813HH
Z8F0413PH, Z8F0413HH
Z8F0213PH, Z8F0213HH
Z8F0113PH, Z8F0113HH
Z8F0823PJ, Z8F0823SJ
Z8F0423PJ, Z8F0423SJ
Z8F0223PJ, Z8F0223SJ
Z8F0123PJ, Z8F0123SJ
Yes
No
Z8F0813PJ, Z8F0813SJ
Z8F0413PJ, Z8F0413SJ
Z8F0213PJ, Z8F0213SJ
Z8F0113PJ, Z8F0113SJ
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Product Specification
34
Architecture
Figure 7 displays a simplified block diagram of a GPIO port pin. In this figure, the ability
to accommodate alternate functions and variable port current drive strength is not dis-
played.
Port Input
Data Register
Schmitt-Trigger
Q
D
Q
D
System
Clock
VDD
Port Output Control
Port Output
Data Register
DATA
Bus
D
Q
Port
Pin
System
Clock
Port Data Direction
GND
Figure 7. GPIO Port Pin Block Diagram
GPIO Alternate Functions
Many of the GPIO port pins are used for general-purpose I/O and access to on-chip
peripheral functions such as the timers and serial communication devices. The port A–D
Alternate Function subregisters configure these pins for either GPIO or alternate function
operation. When a pin is configured for alternate function, control of the port pin direction
(input/output) is passed from the Port A–D Data Direction registers to the alternate func-
tion assigned to this pin. Tables 16 and 17 list the alternate functions possible with each
port pin for 8-pin and non-8-pin parts, respectively. The alternate function associated at a
pin is defined through Alternate Function Sets subregisters AFS1 and AFS2.
The crystal oscillator functionality is not controlled by the GPIO block. When the crystal
oscillator is enabled in the oscillator control block, the GPIO functionality of PA0 and PA1
is overridden. In that case, those pins function as input and output for the crystal oscillator.
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PA0 and PA6 contain two different timer functions, a timer input and a complementary timer
output. Both of these functions require the same GPIO configuration, the selection between
the two is based on the timer mode. For more details, see the Timers chapter on page 69
.
For pins with multiple alternate functions, Zilog recommends writing to the AFS1 and
AFS2 subregisters before enabling the alternate function via the AF Subregister. This
prevents spurious transitions through unwanted alternate function modes.
Caution:
Table 16. Port Alternate Function Mapping (8-Pin Parts)
Alternate
Function
Alternate
Select
Alternate Function
Description
Function Select Register
Register AFS1 AFS2
Port
Pin
Mnemonic
T0IN
Port A
PA0
Timer 0 Input
AFS1[0]: 0
AFS1[0]: 0
AFS1[0]: 1
AFS1[0]: 1
AFS1[1]: 0
AFS1[1]: 0
AFS1[1]: 1
AFS1[1]: 1
AFS1[2]: 0
AFS1[2]: 0
AFS1[2]: 1
AFS1[2]: 1
AFS1[3]: 0
AFS1[3]: 0
AFS1[3]: 1
AFS1[3]: 1
AFS1[4]: 0
AFS1[4]: 0
AFS1[4]: 1
AFS1[4]: 1
AFS1[5]: 0
AFS1[5]: 0
AFS1[5]: 1
AFS1[5]: 1
AFS2[0]: 0
AFS2[0]: 1
AFS2[0]: 0
AFS2[0]: 1
AFS2[1]: 0
AFS2[1]: 1
AFS2[1]: 0
AFS2[1]: 1
AFS2[2]: 0
AFS2[2]: 1
AFS2[2]: 0
AFS2[2]: 1
AFS2[3]: 0
AFS2[3]: 1
AFS2[3]: 0
AFS2[3]: 1
AFS2[4]: 0
AFS2[4]: 1
AFS2[4]: 0
AFS2[4]: 1
AFS2[5]: 0
AFS2[5]: 1
AFS2[5]: 0
AFS2[5]: 1
Reserved
Reserved
T0OUT
Timer 0 Output Complement
Timer 0 Output
PA1
PA2
PA3
PA4
PA5
T0OUT
Reserved
CLKIN
External Clock Input
Analog Functions* ADC Analog Input/V
REF
DE0
UART 0 Driver Enable
RESET
T1OUT
Reserved
CTS0
External Reset
Timer 1 Output
UART 0 Clear to Send
Comparator Output
Timer 1 Input
COUT
T1IN
Analog Functions* ADC Analog Input
RXD0
UART 0 Receive Data
Reserved
Reserved
Analog Functions* ADC/Comparator Input (N)
TXD0
UART 0 Transmit Data
T1OUT
Reserved
Timer 1 Output Complement
Analog Functions* ADC/Comparator Input (P)
Note: *Analog Functions include ADC inputs, ADC reference and comparator inputs. Also, alternate function selection
as described in the Port A–C Alternate Function Subregisters section on page 43 must be enabled.
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Product Specification
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Table 17. Port Alternate Function Mapping (Non 8-Pin Parts)
Alternate Function
Set Register AFS1
Port
Pin
Mnemonic
Alternate Function Description
1
Port A PA0
T0IN/T0OUT
Timer 0 Input/Timer 0 Output Com- N/A
plement
Reserved
T0OUT
PA1
PA2
PA3
PA4
PA5
PA6
Timer 0 Output
Reserved
DE0
UART 0 Driver Enable
UART 0 Clear to Send
UART 0 / IrDA 0 Receive Data
UART 0 / IrDA 0 Transmit Data
Reserved
CTS0
Reserved
RXD0/IRRX0
Reserved
TXD0/IRTX0
Reserved
2
T1IN/T1OUT
Timer 1 Input/Timer 1 Output Com-
plement
Reserved
T1OUT
PA7
Timer 1 Output
Reserved
Notes:
1. Because there is only a single alternate function for each Port A pin, the Alternate Function Set registers
are not implemented for Port A. Enabling alternate function selections as described in the Port A–C
Alternate Function Subregisters section on page 43 automatically enables the associated alternate func-
tion.
2. Whether PA0/PA6 take on the timer input or timer output complement function depends on the timer con-
figuration as described in the Timer Pin Signal Operation section on page 83.
3. Because there are at most two choices of alternate function for any pin of Port B, the Alternate Function
Set register AFS2 is implemented but not used to select the function. Also, alternate function selection
as described in the Port A–C Alternate Function Subregisters section on page 43 must also be enabled.
4. VREF is available on PB5 in 28-pin products only.
5. Because there are at most two choices of alternate function for any pin of Port C, the Alternate Function
Set register AFS2 is implemented but not used to select the function. Also, Alternate Function selection
as described in the Port A–C Alternate Function Subregisters section on page 43 must also be enabled.
6. VREF is available on PC2 in 20-pin parts only.
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Product Specification
37
Table 17. Port Alternate Function Mapping (Non 8-Pin Parts) (Continued)
Alternate Function
Set Register AFS1
Port
Pin
Mnemonic
Reserved
ANA0
Alternate Function Description
ADC Analog Input
3
Port B PB03
AFS1[0]: 0
AFS1[0]: 1
AFS1[1]: 0
AFS1[1]: 1
AFS1[2]: 0
AFS1[2]: 1
AFS1[3]: 0
AFS1[3]: 1
AFS1[4]: 0
AFS1[4]: 1
AFS1[5]: 0
AFS1[5]: 1
AFS1[6]: 0
AFS1[6]: 1
AFS1[7]: 0
AFS1[7]: 1
PB1
Reserved
ANA1
ADC Analog Input
PB2
Reserved
ANA2
ADC Analog Input
External Clock Input
ADC Analog Input
PB3
CLKIN
ANA3
PB4
Reserved
ANA7
ADC Analog Input
PB5
Reserved
4
V
ADC Voltage Reference
REF
PB6
Reserved
Reserved
Reserved
Reserved
PB7
Notes:
1. Because there is only a single alternate function for each Port A pin, the Alternate Function Set registers
are not implemented for Port A. Enabling alternate function selections as described in the Port A–C
Alternate Function Subregisters section on page 43 automatically enables the associated alternate func-
tion.
2. Whether PA0/PA6 take on the timer input or timer output complement function depends on the timer con-
figuration as described in the Timer Pin Signal Operation section on page 83.
3. Because there are at most two choices of alternate function for any pin of Port B, the Alternate Function
Set register AFS2 is implemented but not used to select the function. Also, alternate function selection
as described in the Port A–C Alternate Function Subregisters section on page 43 must also be enabled.
4. VREF is available on PB5 in 28-pin products only.
5. Because there are at most two choices of alternate function for any pin of Port C, the Alternate Function
Set register AFS2 is implemented but not used to select the function. Also, Alternate Function selection
as described in the Port A–C Alternate Function Subregisters section on page 43 must also be enabled.
6. VREF is available on PC2 in 20-pin parts only.
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Table 17. Port Alternate Function Mapping (Non 8-Pin Parts) (Continued)
Alternate Function
Set Register AFS1
Port
Pin
Mnemonic
Alternate Function Description
4
Port C PC0
Reserved
AFS1[0]: 0
AFS1[0]: 1
ANA4/CINP/LED
Drive
ADC or Comparator Input or LED
Drive
PC1
Reserved
AFS1[1]: 0
AFS1[1]: 1
ANA5/CINN/LED
Drive
ADC or Comparator Input or LED
Drive
PC2
Reserved
AFS1[2]: 0
6
ANA6/LED/V
ADC Analog Input or LED Drive or AFS1[2]: 1
ADC Voltage Reference
REF
PC3
PC4
COUT
LED
Comparator Output
LED Drive
AFS1[3]: 0
AFS1[3]: 1
AFS1[4]: 0
AFS1[4]: 1
AFS1[5]: 0
AFS1[5]: 1
AFS1[6]: 0
AFS1[6]: 1
AFS1[7]: 0
AFS1[7]: 1
Reserved
LED
LED Drive
LED Drive
LED Drive
LED Drive
PC5
Reserved
LED
PC6
Reserved
LED
PC7
Reserved
LED
Notes:
1. Because there is only a single alternate function for each Port A pin, the Alternate Function Set registers
are not implemented for Port A. Enabling alternate function selections as described in the Port A–C
Alternate Function Subregisters section on page 43 automatically enables the associated alternate func-
tion.
2. Whether PA0/PA6 take on the timer input or timer output complement function depends on the timer con-
figuration as described in the Timer Pin Signal Operation section on page 83.
3. Because there are at most two choices of alternate function for any pin of Port B, the Alternate Function
Set register AFS2 is implemented but not used to select the function. Also, alternate function selection
as described in the Port A–C Alternate Function Subregisters section on page 43 must also be enabled.
4. VREF is available on PB5 in 28-pin products only.
5. Because there are at most two choices of alternate function for any pin of Port C, the Alternate Function
Set register AFS2 is implemented but not used to select the function. Also, Alternate Function selection
as described in the Port A–C Alternate Function Subregisters section on page 43 must also be enabled.
6. VREF is available on PC2 in 20-pin parts only.
Direct LED Drive
The Port C pins provide a current sinked output capable of driving an LED without requir-
ing an external resistor. The output sinks current at programmable levels of 3mA, 7mA,
13mA, and 20mA. This mode is enabled through the Alternate Function register and
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Alternate Function sub-register AFS1 and is programmable through the LED control reg-
isters. The LED Drive Enable (LEDEN) register turns on the drivers. The LED Drive
Level (LEDLVLH and LEDLVLL) registers select the sink current.
For correct operation, the LED anode must be connected to VDD and the cathode must be
connected to the GPIO pin. Using all Port C pins in LED Drive Mode with maximum cur-
rent can result in excessive total current. For the maximum total current for the applicable
package, see the Electrical Characteristics chapter on page 198.
Shared Reset Pin
On the 8-pin product versions, the reset pin is shared with PA2, but the pin is not limited to
output-only when in GPIO Mode.
If PA2 on the 8-pin product is reconfigured as an input, ensure that no external stimulus
drives the pin Low during any reset sequence. Because PA2 returns to its RESET
alternate function during system resets, driving it Low holds the chip in a reset state until
the pin is released.
Caution:
Shared Debug Pin
On the 8-pin version of this device only, the Debug pin shares function with the PA0 GPIO
pin. This pin performs as a general purpose input pin on power-up, but the debug logic
monitors this pin during the reset sequence to determine if the unlock sequence occurs. If
the unlock sequence is present, the debug function is unlocked and the pin no longer func-
tions as a GPIO pin. If it is not present, the debug feature is disabled until/unless another
reset event occurs. For more details, see the On-Chip Debugger chapter on page 158.
Crystal Oscillator Override
For systems using a crystal oscillator, PA0 and PA1 are used to connect the crystal. When
the crystal oscillator is enabled (see the Oscillator Control Register Definitions section on
page 173), the GPIO settings are overridden and PA0 and PA1 are disabled.
5V Tolerance
All six I/O pins on the 8-pin devices are 5V-tolerant, unless the programmable pull-ups
are enabled. If the pull-ups are enabled and inputs higher than VDD are applied to these
parts, excessive current flows through those pull-up devices and can damage the chip.
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Note: In the 20- and 28-pin versions of this device, any pin which shares functionality with an
ADC, crystal or comparator port is not 5V-tolerant, including PA[1:0], PB[5:0], and
PC[2:0]. All other signal pins are 5V-tolerant, and can safely handle inputs higher than
VDD even with the pull-ups enabled.
External Clock Setup
For systems using an external TTL drive, PB3 is the clock source for 20- and 28-pin
devices. In this case, configure PB3 for alternate function CLKIN. Write the Oscillator
Control Register (see the Oscillator Control Register Definitions section on page 173)
such that the external oscillator is selected as the system clock. For 8-pin devices, use PA1
instead of PB3.
GPIO Interrupts
Many of the GPIO port pins are used as interrupt sources. Some port pins are configured
to generate an interrupt request on either the rising edge or falling edge of the pin input
signal. Other port pin interrupt sources generate an interrupt when any edge occurs (both
rising and falling). For more information about interrupts using the GPIO pins, see the
Interrupt Controller chapter on page 54.
GPIO Control Register Definitions
Four registers for each port provide access to GPIO control, input data, and output data.
Table 18 lists these port registers. Use the Port A–D Address and Control registers
together to provide access to subregisters for port configuration and control.
Table 18. GPIO Port Registers and Subregisters
Port Register
Mnemonic
PxADDR
PxCTL
Port Register Name
Port A–C Address Register (Selects subregisters).
Port A–C Control Register (Provides access to subregisters).
Port A–C Input Data Register.
PxIN
PxOUT
Port A–C Output Data Register.
Port Subregister
Mnemonic
Port Register Name
PxDD
Data Direction.
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Table 18. GPIO Port Registers and Subregisters (Continued)
Port Register
Mnemonic
Port Register Name
PxAF
Alternate Function.
PxOC
Output Control (Open-Drain).
High Drive Enable.
PxHDE
PxSMRE
PxPUE
PxAFS1
PxAFS2
Stop-Mode Recovery Source Enable.
Pull-up Enable.
Alternate Function Set 1.
Alternate Function Set 2.
Port A–C Address Registers
The Port A–C Address registers select the GPIO port functionality accessible through the
Port A–C Control registers. The Port A–C Address and Control registers combine to pro-
vide access to all GPIO port controls (Table 19).
Table 19. Port A–C GPIO Address Registers (PxADDR)
Bit
7
6
5
4
3
2
1
0
PADDR[7:0]
00h
Field
RESET
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FD0h, FD4h, FD8h
Address
Bit
Description
[7:0]
Port Address
PADDR The Port Address selects one of the subregisters accessible through the Port Control Register.
See Table 20 for each subregister function.
Table 20. PADDR[7:0] Subregister Functions
PADDR[7:0] Port Control Subregister Accessible Using the Port A–C Control Registers
00h
01h
02h
03h
04h
No function. Provides some protection against accidental Port reconfiguration.
Data Direction.
Alternate Function.
Output Control (Open-Drain).
High Drive Enable.
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Table 20. PADDR[7:0] Subregister Functions
PADDR[7:0] Port Control Subregister Accessible Using the Port A–C Control Registers
05h
06h
Stop-Mode Recovery Source Enable.
Pull-up Enable.
07h
Alternate Function Set 1.
Alternate Function Set 2.
No function.
08h
09h–FFh
Port A–C Control Registers
The Port A–C Control registers set the GPIO port operation. The value in the correspond-
ing Port A–C Address Register determines which subregister is read from or written to by
a Port A–C Control Register transaction; see Table 21.
Table 21. Port A–C Control Registers (PxCTL)
Bit
7
6
5
4
3
2
1
0
PCTL
00h
Field
RESET
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FD1h, FD5h, FD9h
Address
Bit
Description
Port Control
[7:0]
PCTL
The Port Control Register provides access to all subregisters that configure the GPIO Port
operation.
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Port A–C Data Direction Subregisters
The Port A–C Data Direction Subregister is accessed through the Port A–C Control Regis-
ter by writing 01hto the Port A–C Address Register; see Table 22.
Table 22. Port A–C Data Direction Subregisters (PxDD)
Bit
7
6
5
4
3
2
1
0
DD7
DD6
DD5
DD4
DD3
DD2
DD1
DD0
Field
1
1
1
1
1
1
1
1
RESET
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
If 01h in Port A–C Address Register, accessible through the Port A–C Control Register.
Address
Bit
Description
[7:0]
DDx
Data Direction
These bits control the direction of the associated port pin. Port Alternate Function operation
overrides the Data Direction register setting.
0 = Output. Data in the Port A–C Output Data Register is driven onto the port pin.
1 = Input. The port pin is sampled and the value written into the Port A–C Input Data Register.
The output driver is tristated.
Note: x indicates the specific GPIO port pin number (7–0).
Port A–C Alternate Function Subregisters
The Port A–C Alternate Function Subregister (Table 23) is accessed through the Port A–C
Control Register by writing 02hto the Port A–C Address Register. The Port A–C Alter-
nate Function subregisters enable the alternate function selection on pins. If disabled, pins
functions as GPIO. If enabled, select one of four alternate functions using alternate func-
tion set subregisters 1 and 2 as described in the the Port A–C Alternate Function Set 1
Subregisters section on page 48 and the Port A–C Alternate Function Set 2 Subregisters
section on page 49. See the GPIO Alternate Functions section on page 34 to determine
the alternate function associated with each port pin.
Do not enable alternate functions for GPIO port pins for which there is no associated al-
ternate function. Failure to follow this guideline can result in unpredictable operation.
Caution:
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Table 23. Port A–C Alternate Function Subregisters (PxAF)
Bit
7
6
5
4
3
2
1
0
AF7
AF6
AF5
AF4
AF3
AF2
AF1
AF0
Field
00h (Ports A–C); 04h (Port A of 8-pin device)
R/W
RESET
R/W
If 02h in Port A–C Address Register, accessible through the Port A–C Control Register
Address
Bit
Description
[7:0]
AFx
Port Alternate Function enabled
0 = The port pin is in Normal Mode and the DDx bit in the Port A–C Data Direction Subregister
determines the direction of the pin.
1 = The alternate function selected through Alternate Function Set subregisters is enabled.
Port pin operation is controlled by the alternate function.
Note: x indicates the specific GPIO port pin number (7–0).
Port A–C Output Control Subregisters
The Port A–C Output Control Subregister (Table 24) is accessed through the Port A–C
Control Register by writing 03hto the Port A–C Address Register. Setting the bits in the
Port A–C Output Control subregisters to 1 configures the specified port pins for open-
drain operation. These subregisters affect the pins directly and, as a result, alternate func-
tions are also affected.
Table 24. Port A–C Output Control Subregisters (PxOC)
Bit
7
6
5
4
3
2
1
0
POC7
POC6
POC5
POC4
POC3
POC2
POC1
POC0
Field
0
0
0
0
0
0
0
0
RESET
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
If 03h in Port A–C Address Register, accessible through the Port A–C Control Register
Address
Bit
Description
[7:0]
POCx
Port Output Control
These bits function independently of the alternate function bit and always disable the drains if
set to 1.
0 = The drains are enabled for any output mode (unless overridden by the alternate function).
1 = The drain of the associated pin is disabled (open-drain mode).
Note: x indicates the specific GPIO port pin number (7–0).
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Port A–C High Drive Enable Subregisters
The Port A–C High Drive Enable Subregister (Table 25) is accessed through the Port A–C
Control Register by writing 04hto the Port A–C Address Register. Setting the bits in the
Port A–C High Drive Enable subregisters to 1 configures the specified port pins for high-
current output drive operation. The Port A–C High Drive Enable Subregister affects the
pins directly and, as a result, alternate functions are also affected.
Table 25. Port A–C High Drive Enable Subregisters (PHDEx)
Bit
7
6
5
4
3
2
1
0
PHDE7
PHDE6
PHDE5
PHDE4
PHDE3
PHDE2
PHDE1
PHDE0
Field
0
0
0
0
0
0
0
0
RESET
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
If 04h in Port A–C Address Register, accessible through the Port A–C Control Register
Address
Bit
Description
[7:0]
PHDEx
Port High Drive Enabled.
0 = The Port pin is configured for standard output current drive.
1 = The Port pin is configured for high output current drive.
Note: x indicates the specific GPIO port pin number (7–0).
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Port A–C Stop-Mode Recovery Source Enable Subregisters
The Port A–C Stop-Mode Recovery Source Enable Subregister (Table 26) is accessed
through the Port A–C Control Register by writing 05hto the Port A–C Address Register.
Setting the bits in the Port A–C Stop-Mode Recovery Source Enable subregisters to 1 con-
figures the specified Port pins as a Stop-Mode Recovery source. During Stop Mode, any
logic transition on a Port pin enabled as a Stop-Mode Recovery source initiates Stop-
Mode Recovery.
Table 26. Port A–C Stop-Mode Recovery Source Enable Subregisters (PSMREx)
Bit
7
6
5
4
3
2
1
0
PSMRE7 PSMRE6 PSMRE5 PSMRE4 PSMRE3 PSMRE2 PSMRE1 PSMRE0
Field
0
0
0
0
0
0
0
0
RESET
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
If 05h in Port A–C Address Register, accessible through the Port A–C Control Register
Address
Bit
Description
Port Stop-Mode Recovery Source Enabled.
[7:0]
PSMREx 0 = The Port pin is not configured as a Stop-Mode Recovery source. Transitions on this pin
during Stop Mode do not initiate Stop-Mode Recovery.
1 = The Port pin is configured as a Stop-Mode Recovery source. Any logic transition on this pin
during Stop Mode initiates Stop-Mode Recovery.
Note: x indicates the specific GPIO port pin number (7–0).
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Port A–C Pull-up Enable Subregisters
The Port A–C Pull-up Enable Subregister (Table 27) is accessed through the Port A–C
Control Register by writing 06hto the Port A–C Address Register. Setting the bits in the
Port A–C Pull-up Enable subregisters enables a weak internal resistive pull-up on the
specified Port pins.
Table 27. Port A–C Pull-Up Enable Subregisters (PPUEx)
Bit
7
6
5
4
3
2
1
0
PPUE7
PPUE6
PPUE5
PPUE4
PPUE3
PPUE2
PPUE1
PPUE0
Field
0
0
0
0
0
0
0
0
RESET
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
If 06h in Port A–C Address Register, accessible through the Port A–C Control Register
Address
Bit
Description
[7:0]
PPUEx
Port Pull-up Enabled
0 = The weak pull-up on the Port pin is disabled.
1 = The weak pull-up on the Port pin is enabled.
Note: x indicates the specific GPIO port pin number (7–0).
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Port A–C Alternate Function Set 1 Subregisters
The Port A–C Alternate Function Set1 Subregister (Table 28) is accessed through the Port
A–C Control Register by writing 07hto the Port A–C Address Register. The Alternate
Function Set 1 subregisters selects the alternate function available at a port pin. Alternate
Functions selected by setting or clearing bits of this register are defined in “GPIO Alter-
nate Functions” on page 34.
Note: Alternate function selection on port pins must also be enabled as described in the Port
A–C Alternate Function Subregisters section on page 43.
Table 28. Port A–C Alternate Function Set 1 Subregisters (PAFS1x)
Bit
7
6
5
4
3
2
1
0
PAFS17
PAFS16
PAFS15
PAFS14
PAFS13
PAFS12
PAFS11
PAFS10
Field
00h (all ports of 20/28 pin devices); 04h (Port A of 8-pin device)
R/W R/W R/W R/W R/W R/W
RESET
R/W
R/W
R/W
If 07h in Port A–C Address Register, accessible through the Port A–C Control Register
Address
Bit
Description
Port Alternate Function Set to 1
[7:0]
PAFS1x 0 = Port Alternate Function selected as defined in Table 15 (see the GPIO Alternate Functions
section on page 34).
1 = Port Alternate Function selected as defined in Table 15 (see the GPIO Alternate Functions
section on page 34).
Note: x indicates the specific GPIO port pin number (7–0).
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Port A–C Alternate Function Set 2 Subregisters
The Port A–C Alternate Function Set 2 Subregister (Table 29) is accessed through the Port
A–C Control Register by writing 08hto the Port A–C Address Register. The Alternate
Function Set 2 subregisters selects the alternate function available at a port pin. Alternate
Functions selected by setting or clearing bits of this register is defined in Table 15 in the
section the GPIO Alternate Functions section on page 34.
Table 29. Port A–C Alternate Function Set 2 Subregisters (PxAFS2)
Bit
7
6
5
4
3
2
1
0
PAFS27
PAFS26
PAFS25
PAFS24
PAFS23
PAFS22
PAFS21
PAFS20
Field
00h (all ports of 20/28 pin devices); 04h (Port A of 8-pin device)
R/W R/W R/W R/W R/W R/W
RESET
R/W
R/W
R/W
If 08h in Port A–C Address Register, accessible through the Port A–C Control Register
Address
Bit
Description
Port Alternate Function Set 2
[7:0]
PAFS2x 0 = Port Alternate Function selected as defined in Table 15 on page 33; also see the GPIO
Alternate Functions section on page 34).
1 = Port Alternate Function selected as defined in Table 15.
Note: x indicates the specific GPIO port pin number (7–0).
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Port A–C Input Data Registers
Reading from the Port A–C Input Data registers (Table 30) returns the sampled values
from the corresponding port pins. The Port A–C Input Data registers are read-only. The
value returned for any unused ports is 0. Unused ports include those missing on the 8- and
28-pin packages, as well as those missing on the ADC-enabled 28-pin packages.
Table 30. Port A–C Input Data Registers (PxIN)
Bit
7
6
5
4
3
2
1
0
PIN7
PIN6
PIN5
PIN4
PIN3
PIN2
PIN1
PIN0
Field
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
RESET
R/W
FD2h, FD6h, FDAh
Address
Bit
Description
[7:0]
PxIN
Port Input Data
Sampled data from the corresponding port pin input.
0 = Input data is logical 0 (Low).
1 = Input data is logical 1 (High).
Note: x indicates the specific GPIO port pin number (7–0).
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Port A–C Output Data Register
The Port A–C Output Data Register (Table 31) controls the output data to the pins.
Table 31. Port A–C Output Data Register (PxOUT)
Bit
7
6
5
4
3
2
1
0
POUT7
POUT6
POUT5
POUT4
POUT3
POUT2
POUT1
POUT0
Field
0
0
0
0
0
0
0
0
RESET
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FD3h, FD7h, FDBh
Address
Bit
Description
[7:0]
PxOUT
Port Output Data
These bits contain the data to be driven to the port pins. The values are only driven if the corre-
sponding pin is configured as an output and the pin is not configured for alternate function
operation.
0 = Drive a logical 0 (Low).
1 = Drive a logical 1 (High). High value is not driven if the drain has been disabled by setting
the corresponding Port Output Control Register bit to 1.
Note: x indicates the specific GPIO port pin number (7–0).
LED Drive Enable Register
The LED Drive Enable Register, shown in Table 32, activates the controlled current drive.
The Port C pin must first be enabled for the LED function by setting the Alternate Func-
tion sub-register AFS1 and Alternate Function register. LEDEN bits [7:0] correspond to
Port C bits [7:0], respectively.
Table 32. LED Drive Enable (LEDEN)
Bit
7
6
5
4
3
2
1
0
LEDEN[7:0]
Field
0
0
0
0
0
0
0
0
RESET
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
F82h
Address
Bit
Description
[7:0]
LED Drive Enable
LEDEN These bits determine which Port C pins are connected to an internal current sink.
0 = Tristate the Port C pin.
1= Connect controlled current sink to the Port C pin.
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LED Drive Level High Register
The LED Drive Level registers contain two control bits for each Port C pin (Table 33).
These two bits select between four programmable drive levels. Each pin is individually
programmable.
Table 33. LED Drive Level High Register (LEDLVLH)
Bit
7
6
5
4
3
2
1
0
LEDLVLH[7:0]
Field
0
0
0
0
0
0
0
0
RESET
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
F83h
Address
Bit
Description
[7:0]
LED Level High Bit
LEDLVLH {LEDLVLH, LEDLVLL} select one of four programmable current drive levels for each Port C
pin.
00 = 3mA.
01= 7mA.
10= 13mA.
11= 20mA.
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LED Drive Level Low Register
The LED Drive Level registers contain two control bits for each Port C pin (Table 34).
These two bits select between four programmable drive levels. Each pin is individually
programmable.
Table 34. LED Drive Level Low Register (LEDLVLL)
Bit
7
6
5
4
3
2
1
0
LEDLVLL[7:0]
Field
0
0
0
0
0
0
0
0
RESET
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
F84h
Address
Bit
Description
[7:0]
LED Level High Bit
LEDLVLL {LEDLVLH, LEDLVLL} select one of four programmable current drive levels for each Port C pin.
00 = 3mA.
01 = 7mA.
10 = 13mA.
11 = 20mA.
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Interrupt Controller
The interrupt controller on the Z8 Encore! XP F0823 Series products prioritizes the inter-
rupt requests from the on-chip peripherals and the GPIO port pins. The features of inter-
rupt controller include:
•
20 unique interrupt vectors
–
–
12 GPIO port pin interrupt sources (two are shared)
8 on-chip peripheral interrupt sources (two are shared)
•
Flexible GPIO interrupts
–
–
Eight selectable rising and falling edge GPIO interrupts
Four dual-edge interrupts
•
•
Three levels of individually programmable interrupt priority
Watchdog Timer can be configured to generate an interrupt
Interrupt requests (IRQs) allow peripheral devices to suspend CPU operation in an orderly
manner and force the CPU to start an interrupt service routine (ISR). Usually this interrupt
service routine is involved with the exchange of data, status information, or control infor-
mation between the CPU and the interrupting peripheral. When the service routine is com-
pleted, the CPU returns to the operation from which it was interrupted.
The eZ8 CPU supports both vectored and polled interrupt handling. For polled interrupts,
the interrupt controller has no effect on operation. For more information about interrupt
servicing by the eZ8 CPU, refer to the eZ8 CPU Core User Manual (UM0128) available
for download at www.zilog.com.
Interrupt Vector Listing
Table 35 lists all of the interrupts available in order of priority. The interrupt vector is
stored with the most-significant byte (MSB) at the even Program Memory address and the
least-significant byte (LSB) at the following odd Program Memory address.
Note: Some port interrupts are not available on the 8- and 20-pin packages. The ADC interrupt is
unavailable on devices not containing an ADC.
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Table 35. Trap and Interrupt Vectors in Order of Priority
Program
Memory
Priority Vector Address Interrupt or Trap Source
Highest 0002h
0004h
003Ah
003Ch
0006h
0008h
000Ah
000Ch
000Eh
0010h
0012h
0014h
0016h
0018h
001Ah
001Ch
001Eh
0020h
0022h
0024h
0026h
0028h
002Ah
002Ch
002Eh
0030h
0032h
0034h
0036h
Reset (not an interrupt)
Watchdog Timer (see the Watchdog Timer section on page 91)
Primary Oscillator Fail Trap (not an interrupt)
Watchdog Timer Oscillator Fail Trap (not an interrupt)
Illegal Instruction Trap (not an interrupt)
Reserved
Timer 1
Timer 0
UART 0 receiver
UART 0 transmitter
Reserved
Reserved
ADC
Port A Pin 7, selectable rising or falling input edge
Port A Pin 6, selectable rising or falling input edge or Comparator Output
Port A Pin 5, selectable rising or falling input edge
Port A Pin 4, selectable rising or falling input edge
Port A Pin 3 or Port D Pin 3, selectable rising or falling input edge
Port A Pin 2 or Port D Pin 2, selectable rising or falling input edge
Port A Pin 1, selectable rising or falling input edge
Port A Pin 0, selectable rising or falling input edge
Reserved
Reserved
Reserved
Reserved
Port C Pin 3, both input edges
Port C Pin 2, both input edges
Port C Pin 1, both input edges
Port C Pin 0, both input edges
Lowest
0038h
Reserved
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Interrupt Vector Listing
Z8 Encore! XP® F0823 Series
Product Specification
56
Architecture
Figure 8 displays the interrupt controller block diagram.
High
Priority
Port Interrupts
Vector
Priority
Mux
IRQ Request
Medium
Priority
Internal Interrupts
Low
Priority
Figure 8. Interrupt Controller Block Diagram
Operation
This section describes the operational aspects of the following functions.
Master Interrupt Enable: see page 56
Interrupt Vectors and Priority: see page 57
Interrupt Assertion: see page 57
Software Interrupt Assertion: see page 58
Watchdog Timer Interrupt Assertion: see page 58
Master Interrupt Enable
The master interrupt enable bit (IRQE) in the Interrupt Control Register globally enables
and disables interrupts.
Interrupts are globally enabled by any of the following actions:
•
Execution of an Enable Interrupt (EI) instruction
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•
•
Execution of an Return from Interrupt (IRET) instruction
Writing a 1 to the IRQE bit in the Interrupt Control Register
Interrupts are globally disabled by any of the following actions:
•
•
•
•
•
•
•
•
Execution of a Disable Interrupt (DI) instruction
eZ8 CPU acknowledgement of an interrupt service request from the interrupt controller
Writing a 0 to the IRQE bit in the Interrupt Control Register
Reset
Execution of a trap instruction
Illegal instruction trap
Primary oscillator fail trap
Watchdog timer oscillator fail trap
Interrupt Vectors and Priority
The interrupt controller supports three levels of interrupt priority. Level 3 is the highest
priority, Level 2 is the second highest priority, and Level 1 is the lowest priority. If all
interrupts are enabled with identical interrupt priority (for example, all as Level 2 inter-
rupts), the interrupt priority is assigned from highest to lowest as specified in Table 35 on
page 55. Level 3 interrupts are always assigned higher priority than Level 2 interrupts
which, in turn, always are assigned higher priority than Level 1 interrupts. Within each
interrupt priority level (Level 1, Level 2 or Level 3), priority is assigned as specified in
Table 35. Reset, Watchdog Timer interrupt (if enabled), Primary Oscillator Fail Trap,
Watchdog Timer Oscillator Fail Trap, and Illegal Instruction Trap always have highest
(Level 3) priority.
Interrupt Assertion
Interrupt sources assert their interrupt requests for only a single system clock period (sin-
gle pulse). When the interrupt request is acknowledged by the eZ8 CPU, the correspond-
ing bit in the Interrupt Request register is cleared until the next interrupt occurs. Writing a
0 to the corresponding bit in the Interrupt Request register likewise clears the interrupt
request.
Zilog recommends not using a coding style that clears bits in the Interrupt Request reg-
isters. All incoming interrupts received between execution of the first LDX command
and the final LDX command are lost. See Example 1, which follows.
Caution:
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Z8 Encore! XP® F0823 Series
Product Specification
58
Example 1. A poor coding style that can result in lost interrupt requests:
LDX r0, IRQ0
AND r0, MASK
LDX IRQ0, r0
To avoid missing interrupts, use the coding style in Example 2 to clear bits in the Interrupt
Request 0 Register:
Example 2. A good coding style that avoids lost interrupt requests:
ANDX IRQ0, MASK
Software Interrupt Assertion
Program code generates interrupts directly. Writing a 1 to the correct bit in the Interrupt
Request register triggers an interrupt (assuming that interrupt is enabled). When the inter-
rupt request is acknowledged by the eZ8 CPU, the bit in the Interrupt Request register is
automatically cleared to 0.
Zilog recommends not using a coding style to generate software interrupts by setting bits
in the Interrupt Request registers. All incoming interrupts received between execution of
the first LDX command and the final LDX command are lost. See Example 3, which fol-
lows.
Caution:
Example 3. A poor coding style that can result in lost interrupt requests:
LDX r0, IRQ0
OR r0, MASK
LDX IRQ0, r0
To avoid missing interrupts, use the coding style in Example 4 to set bits in the Interrupt
Request registers:
Example 4. A good coding style that avoids lost interrupt requests:
ORX IRQ0, MASK
Watchdog Timer Interrupt Assertion
The Watchdog Timer interrupt behavior is different from interrupts generated by other
sources. The Watchdog Timer continues to assert an interrupt as long as the timeout condi-
tion continues. As it operates on a different (and usually slower) clock domain than the
rest of the device, the Watchdog Timer continues to assert this interrupt for many system
clocks until the counter rolls over.
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Z8 Encore! XP® F0823 Series
Product Specification
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To avoid retriggerings of the Watchdog Timer interrupt after exiting the associated inter-
rupt service routine, Zilog recommends that the service routine continues to read from
the RSTSTAT register until the WDT bit is cleared as shown in the following example.
Caution:
CLEARWDT:
LDX r0, RSTSTAT ; read reset status register to clear wdt bit
BTJNZ 5, r0, CLEARWDT
; loop until bit is cleared
Interrupt Control Register Definitions
For all interrupts other than the Watchdog Timer interrupt, the Primary Oscillator Fail
Trap, and the Watchdog Timer Oscillator Fail Trap, the interrupt control registers enable
individual interrupts, set interrupt priorities, and indicate interrupt requests.
Interrupt Request 0 Register
The Interrupt Request 0 (IRQ0) register (Table 36) stores the interrupt requests for both
vectored and polled interrupts. When a request is presented to the interrupt controller, the
corresponding bit in the IRQ0 register becomes 1. If interrupts are globally enabled (vec-
tored interrupts), the interrupt controller passes an interrupt request to the eZ8 CPU. If
interrupts are globally disabled (polled interrupts), the eZ8 CPU reads the Interrupt
Request 0 register to determine if any interrupt requests are pending.
Table 36. Interrupt Request 0 Register (IRQ0)
Bit
7
6
5
4
3
2
1
0
Reserved
T1I
T0I
U0RXI
U0TXI
Reserved
ADCI
Field
0
0
0
0
0
0
0
RESET
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FC0h
Address
Bit
Description
Reserved
[7]
This bit is reserved and must be programmed to 0.
[6]
T1I
Timer 1 Interrupt Request
0 = No interrupt request is pending for Timer 1.
1 = An interrupt request from Timer 1 is awaiting service.
[5]
T0I
Timer 0 Interrupt Request
0 = No interrupt request is pending for Timer 0.
1 = An interrupt request from Timer 0 is awaiting service.
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Z8 Encore! XP® F0823 Series
Product Specification
60
Bit
Description (Continued)
[4]
U0RXI
UART 0 Receiver Interrupt Request
0 = No interrupt request is pending for the UART 0 receiver.
1 = An interrupt request from the UART 0 receiver is awaiting service.
[3]
U0TXI
UART 0 Transmitter Interrupt Request
0 = No interrupt request is pending for the UART 0 transmitter.
1 = An interrupt request from the UART 0 transmitter is awaiting service.
[2:1]
Reserved
These bits are reserved and must be programmed to 00.
[0]
ADCI
ADC Interrupt Request
0 = No interrupt request is pending for the ADC.
1 = An interrupt request from the ADC is awaiting service.
Interrupt Request 1 Register
The Interrupt Request 1 (IRQ1) register (Table 37) stores interrupt requests for both vec-
tored and polled interrupts. When a request is presented to the interrupt controller, the cor-
responding bit in the IRQ1 Register becomes 1. If interrupts are globally enabled
(vectored interrupts), the interrupt controller passes an interrupt request to the eZ8 CPU. If
interrupts are globally disabled (polled interrupts), the eZ8 CPU reads the Interrupt
Request 1 Register to determine if any interrupt requests are pending.
Table 37. Interrupt Request 1 Register (IRQ1)
Bit
7
6
5
4
3
2
1
0
PA7VI
PA6CI
PA5I
PA4I
PA3I
PA2I
PA1I
PA0I
Field
0
0
0
0
0
0
0
0
RESET
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FC3h
Address
Bit
Description
[7]
PA7VI
Port A7 Interrupt Request
0 = No interrupt request is pending for GPIO Port A.
1 = An interrupt request from GPIO Port A.
[6]
PA6CI
Port A6 or Comparator Interrupt Request
0 = No interrupt request is pending for GPIO Port A or Comparator.
1 = An interrupt request from GPIO Port A or Comparator.
[5:0]
PAxI
Port A Pin x Interrupt Request
0 = No interrupt request is pending for GPIO Port A pin x.
1 = An interrupt request from GPIO Port A pin x is awaiting service.
Note: x indicates the specific GPIO Port pin number (0–5).
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Z8 Encore! XP® F0823 Series
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Interrupt Request 2 Register
The Interrupt Request 2 (IRQ2) register (Table 38) stores interrupt requests for both vec-
tored and polled interrupts. When a request is presented to the interrupt controller, the cor-
responding bit in the IRQ2 Register becomes 1. If interrupts are globally enabled
(vectored interrupts), the interrupt controller passes an interrupt request to the eZ8 CPU. If
interrupts are globally disabled (polled interrupts), the eZ8 CPU can read the Interrupt
Request 2 Register to determine if any interrupt requests are pending.
Table 38. Interrupt Request 2 Register (IRQ2)
Bit
7
6
5
4
3
2
1
0
Reserved
PC3I
PC2I
PC1I
PC0I
Field
0
0
0
0
0
0
0
0
RESET
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FC6h
Address
Bit
Description
Reserved
[7:4]
These bits are reserved and must be programmed to 0000.
[3:0]
PCxI
Port C Pin x Interrupt Request
0 = No interrupt request is pending for GPIO Port C pin x.
1 = An interrupt request from GPIO Port C pin x is awaiting service.
Note: x indicates the specific GPIO Port C pin number (3–0).
IRQ0 Enable High and Low Bit Registers
Table 39 describes the priority control for IRQ0. The IRQ0 Enable High and Low Bit reg-
isters (Table 40 and Table 41) form a priority-encoded enabling for interrupts in the Inter-
rupt Request 0 Register. Priority is generated by setting bits in each register.
Table 39. IRQ0 Enable and Priority Encoding
IRQ0ENH[x] IRQ0ENL[x] Priority
Description
Disabled
Low
0
0
1
1
0
1
0
1
Disabled
Level 1
Level 2
Level 3
Nominal
High
Note: where x indicates the register bits from 0–7.
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Table 40. IRQ0 Enable High Bit Register (IRQ0ENH)
Bit
7
6
5
4
3
2
1
0
Reserved T1ENH
T0ENH
U0RENH U0TENH
Reserved
ADCENH
Field
0
0
0
0
0
0
0
RESET
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FC1h
Address
Bit
Description
Reserved
[7]
This bit is reserved and must be programmed to 0.
[6]
Timer 1 Interrupt Request Enable High Bit
T1ENH
[5]
Timer 0 Interrupt Request Enable High Bit
T0ENH
[4]
U0RENH
UART 0 Receive Interrupt Request Enable High Bit
UART 0 Transmit Interrupt Request Enable High Bit
[3]
U0TENH
[2:1]
Reserved
These bits are reserved and must be programmed to 00.
[0]
ADC Interrupt Request Enable High Bit
ADCENH
Table 41. IRQ0 Enable Low Bit Register (IRQ0ENL)
Bit
7
6
5
4
3
2
1
0
Reserved
T1ENL
T0ENL
U0RENL U0TENL
Reserved
ADCENL
Field
0
0
0
0
0
0
0
RESET
R/W
R
R/W
R/W
R/W
R/W
R
R/W
FC2h
Address
Bit
Description
Reserved
[7]
This bit is reserved and must be programmed to 0 when read.
[6]
Timer 1 Interrupt Request Enable Low Bit
T1ENL
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Bit
Description (Continued)
[5]
Timer 0 Interrupt Request Enable Low Bit
T0ENL
[4]
U0RENL
UART 0 Receive Interrupt Request Enable Low Bit
UART 0 Transmit Interrupt Request Enable Low Bit
[3]
U0TENL
[2:1]
Reserved
These bits are reserved and must be programmed to 00.
[0]
ADC Interrupt Request Enable Low Bit
ADCENL
IRQ1 Enable High and Low Bit Registers
Table 42 describes the priority control for IRQ1. The IRQ1 Enable High and Low Bit reg-
isters (Table 43 and Table 44) form a priority-encoded enabling for interrupts in the Inter-
rupt Request 1 Register. Priority is generated by setting bits in each register.
Table 42. IRQ1 Enable and Priority Encoding
IRQ1ENH[x]
IRQ1ENL[x]
Priority
Disabled
Level 1
Level 2
Level 3
Description
Disabled
Low
0
0
1
1
0
1
0
1
Nominal
High
Note: x indicates register bits 0–7.
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Table 43. IRQ1 Enable High Bit Register (IRQ1ENH)
Bit
7
6
5
4
3
2
1
0
PA7VENH PA6CENH PA5ENH PA4ENH PA3ENH PA2ENH PA1ENH PA0ENH
Field
0
0
0
0
0
0
0
0
RESET
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FC4h
Address
Bit
Description
[7]
Port A Bit[7] Interrupt Request Enable High Bit
PA7VENH
[6]
Port A Bit[7] or Comparator Interrupt Request Enable High Bit
PA6CENH
[5:0]
PAxENH
Port A Bit[x] Interrupt Request Enable High Bit
For selection of Port A as the interrupt source, see the Shared Interrupt Select Register sec-
tion on page 67.
Note: x indicates the specific GPIO Port A pin number (5–0).
Table 44. IRQ1 Enable Low Bit Register (IRQ1ENL)
Bit
7
6
5
4
3
2
1
0
PA7VENL PA6CENL PA5ENL PA4ENL PA3ENL PA2ENL PA1ENL PA0ENL
Field
0
0
0
0
0
0
0
0
RESET
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FC5h
Address
Bit
Description
[7]
Port A Bit[7] Interrupt Request Enable Low Bit
PA7VENL
[6]
Port A Bit[7] or Comparator Interrupt Request Enable Low Bit
PA6CENL
[5:0]
Port A Bit[x] Interrupt Request Enable Low Bit
PAxENL
Note: x indicates the specific GPIO Port A pin number (5–0).
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IRQ2 Enable High and Low Bit Registers
Table 45 describes the priority control for IRQ2. The IRQ2 Enable High and Low Bit reg-
isters (Table 46 and Table 47) form a priority encoded enabling for interrupts in the Inter-
rupt Request 2 register. Priority is generated by setting bits in each register.
Table 45. IRQ2 Enable and Priority Encoding
IRQ2ENH[x] IRQ2ENL[x] Priority
Description
Disabled
Low
0
0
1
1
0
1
0
1
Disabled
Level 1
Level 2
Level 3
Nominal
High
Note: where x indicates the register bits from 0–7.
Table 46. IRQ2 Enable High Bit Register (IRQ2ENH)
Bit
7
6
5
4
3
2
1
0
Reserved
C3ENH
C2ENH
C1ENH
C0ENH
Field
0
0
0
0
0
0
0
0
RESET
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FC7h
Address
Bit
Description
Reserved
[7:4]
These bits are reserved and must be programmed to 0000.
[3]
Port C3 Interrupt Request Enable High Bit
C3ENH
[2]
C2ENH
Port C2 Interrupt Request Enable High Bit
Port C1 Interrupt Request Enable High Bit
Port C0 Interrupt Request Enable High Bit
[1]
C1ENH
[0]
C0ENH
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Table 47. IRQ2 Enable Low Bit Register (IRQ2ENL)
Bit
7
6
5
4
3
2
1
0
Reserved
C3ENL
C2ENL
C1ENL
C0ENL
Field
0
0
0
0
0
0
0
0
RESET
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FC8h
Address
Bit
Description
Reserved
[7:4]
These bits are reserved and must be programmed to 0000.
[3]
Port C3 Interrupt Request Enable Low Bit
C3ENL
[2]
C2ENL
Port C2 Interrupt Request Enable Low Bit
Port C1 Interrupt Request Enable Low Bit
Port C0 Interrupt Request Enable High Low
[1]
C1ENL
[0]
C0ENL
Interrupt Edge Select Register
The Interrupt Edge Select (IRQES) Register (Table 48) determines whether an interrupt is
generated for the rising edge or falling edge on the selected GPIO Port A or Port D input
pin.
Table 48. Interrupt Edge Select Register (IRQES)
Bit
7
6
5
4
3
2
1
0
IES7
IES6
IES5
IES4
IES3
IES2
IES1
IES0
Field
0
0
0
0
0
0
0
0
RESET
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FCDh
Address
Bit
Description
[7]
IESx
Interrupt Edge Select x
0 = An interrupt request is generated on the falling edge of the PAx input or PDx.
1 = An interrupt request is generated on the rising edge of the PAx input PDx.
Note: x indicates the specific GPIO port pin number (7–0).
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Shared Interrupt Select Register
The Shared Interrupt Select (IRQSS) register (Table 49) determines the source of the
PADxS interrupts. The Shared Interrupt Select register selects between Port A and
alternate sources for the individual interrupts.
Because these shared interrupts are edge-triggered, it is possible to generate an interrupt
just by switching from one shared source to another. For this reason, an interrupt must be
disabled before switching between sources.
Table 49. Shared Interrupt Select Register (IRQSS)
Bit
7
6
5
4
3
2
1
0
Reserved
PA6CS
Reserved
Field
0
0
0
0
0
0
0
0
RESET
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FCEh
Address
Bit
Description
Reserved
[7]
This bit is reserved and must be programmed to 0.
[6]
PA6CS
PA6/Comparator Selection
0 = PA6 is used for the interrupt for PA6CS interrupt request.
1 = The comparator is used as an interrupt for PA6CS interrupt requests.
[5:0]
Reserved
These bits are reserved and must be programmed to 000000.
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Interrupt Control Register
The Interrupt Control (IRQCTL) Register (Table 50) contains the master enable bit for all
interrupts.
Table 50. Interrupt Control Register (IRQCTL)
Bit
7
6
5
4
3
2
1
0
IRQE
Reserved
Field
0
0
0
0
0
0
0
0
RESET
R/W
R/W
R
R
R
R
R
R
R
FCFh
Address
Bit
Description
[7]
IRQE
Interrupt Request Enable
This bit is set to 1 by executing an Enable Interrupts (EI) or Interrupt Return (IRET) instruction,
or by a direct register write of a 1 to this bit. It is reset to 0 by executing a DI instruction, eZ8
CPU acknowledgement of an interrupt request, reset or by a direct register write of a 0 to this
bit.
0 = Interrupts are disabled.
1 = Interrupts are enabled.
[6:0]
Reserved
These bits are reserved and must be programmed to 0000000 when read.
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Product Specification
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Timers
Z8 Encore! XP F0823 Series products contain up to two 16-bit reloadable timers that are
used for timing, event counting or generation of PWM signals. The timers’ features
include:
•
•
•
•
•
16-bit reload counter
Programmable prescaler with prescale values from 1 to 128
PWM output generation
Capture and compare capability
External input pin for timer input, clock gating, or capture signal; external input pin sig-
nal frequency is limited to a maximum of one-fourth the system clock frequency
•
•
Timer output pin
Timer interrupt
In addition to the timers described in this chapter, the baud rate generator of the UART (if
unused) also provides basic timing functionality. For information about using the baud
rate generator as an additional timer, see the Universal Asynchronous Receiver/Transmit-
ter chapter on page 97.
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Architecture
Figure 9 displays the architecture of the timers.
Timer Block
Timer
Control
Data
Bus
Block
Control
Timer
Interrupt
16-Bit
Reload Register
Interrupt,
PWM,
and
Timer Output
Control
Timer
Output
System
Clock
Timer
Output
16-Bit Counter
with Prescaler
Timer
Input
Complement
Gate
Input
16-Bit
PWM/Compare
Capture
Input
Figure 9. Timer Block Diagram
Operation
The timers are 16-bit up-counters. Minimum time-out delay is set by loading the value
0001hinto the Timer Reload High and Low Byte registers and setting the prescale value
to 1. Maximum time-out delay is set by loading the value 0000hinto the Timer Reload
High and Low Byte registers and setting the prescale value to 128. If the Timer reaches
FFFFh, the timer rolls over to 0000hand continues counting.
Timer Operating Modes
The timers can be configured to operate in the following modes:
One-Shot Mode
In One-Shot Mode, the timer counts up to the 16-bit reload value stored in the Timer
Reload High and Low Byte registers. The timer input is the system clock. Upon reaching
the reload value, the timer generates an interrupt and the count value in the Timer High
and Low Byte registers is reset to 0001h. The timer is automatically disabled and stops
counting.
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Also, if the Timer Output alternate function is enabled, the Timer Output pin changes state
for one system clock cycle (from Low to High or from High to Low) upon timer reload. If
it is appropriate to have the Timer Output make a state change at a One-Shot time-out
(rather than a single cycle pulse), first set the TPOL bit in the Timer Control Register to
the start value before enabling One-Shot Mode. After starting the timer, set TPOL to the
opposite bit value.
Observe the following steps to configure a timer for One-Shot Mode and initiating the
count:
1. Write to the Timer Control Register to:
–
–
–
–
Disable the timer
Configure the timer for One-Shot Mode
Set the prescale value
Set the initial output level (High or Low) if using the Timer Output alternate func-
tion
2. Write to the Timer High and Low Byte registers to set the starting count value.
3. Write to the Timer Reload High and Low Byte registers to set the reload value.
4. If appropriate, enable the timer interrupt and set the timer interrupt priority by writing
to the relevant interrupt registers.
5. If using the Timer Output function, configure the associated GPIO port pin for the
Timer Output alternate function.
6. Write to the Timer Control Register to enable the timer and initiate counting.
In One-Shot Mode, the system clock always provides the timer input. The timer period is
computed via the following equation:
Reload Value – Start Value Prescale
ONE-SHOT Mode Time-Out Period (s) = ----------------------------------------------------------------------------------------------
System Clock Frequency (Hz)
Continuous Mode
In Continuous Mode, the timer counts up to the 16-bit reload value stored in the Timer
Reload High and Low Byte registers. The timer input is the system clock. Upon reaching
the reload value, the timer generates an interrupt, the count value in the Timer High and
Low Byte registers is reset to 0001hand counting resumes. Also, if the Timer Output
alternate function is enabled, the Timer Output pin changes state (from Low to High or
from High to Low) at timer reload.
Observe the following steps to configure a timer for Continuous Mode and to initiate the
count:
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P R E L I M I N A R Y
Operation
Z8 Encore! XP® F0823 Series
Product Specification
72
1. Write to the Timer Control Register to:
–
–
–
–
Disable the timer
Configure the timer for Continuous Mode
Set the prescale value
If using the Timer Output alternate function, set the initial output level (High or
Low)
2. Write to the Timer High and Low Byte registers to set the starting count value (usually
0001h). This action only affects the first pass in Continuous Mode. After the first
timer reload in Continuous Mode, counting always begins at the reset value of 0001h.
3. Write to the Timer Reload High and Low Byte registers to set the reload value.
4. Enable the timer interrupt (if appropriate) and set the timer interrupt priority by writ-
ing to the relevant interrupt registers.
5. Configure the associated GPIO port pin (if using the Timer Output function) for the
Timer Output alternate function.
6. Write to the Timer Control Register to enable the timer and initiate counting.
In Continuous Mode, the system clock always provides the timer input. The timer period
is computed via the following equation:
Reload Value Prescale
CONTINUOUS Mode Time-Out Period (s) = -----------------------------------------------------------------------
System Clock Frequency (Hz)
If an initial starting value other than 0001his loaded into the Timer High and Low Byte
registers, use the One-Shot Mode equation to determine the first time-out period.
Counter Mode
In Counter Mode, the timer counts input transitions from a GPIO port pin. The timer input
is taken from the GPIO port pin Timer Input alternate function. The TPOL bit in the Timer
Control Register selects whether the count occurs on the rising edge or the falling edge of
the timer input signal. In Counter Mode, the prescaler is disabled.
The input frequency of the timer input signal must not exceed one-fourth the system
clock frequency.
Caution:
Upon reaching the reload value stored in the Timer Reload High and Low Byte registers,
the timer generates an interrupt, the count value in the Timer High and Low Byte registers
is reset to 0001hand counting resumes. Also, if the Timer Output alternate function is
enabled, the Timer Output pin changes state (from Low to High or from High to Low) at
timer reload.
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Observe the following steps to configure a timer for Counter Mode and initiating the
count:
1. Write to the Timer Control Register to:
–
–
–
Disable the timer.
Configure the timer for Counter Mode.
Select either the rising edge or falling edge of the Timer Input signal for the count.
This selection also sets the initial logic level (High or Low) for the Timer Output
alternate function. However, the Timer Output function is not required to be
enabled.
2. Write to the Timer High and Low Byte registers to set the starting count value. This
only affects the first pass in Counter Mode. After the first timer reload in Counter
Mode, counting always begins at the reset value of 0001h. In Counter Mode the
Timer High and Low Byte registers must be written with the value 0001h.
3. Write to the Timer Reload High and Low Byte registers to set the reload value.
4. If appropriate, enable the timer interrupt and set the timer interrupt priority by writing
to the relevant interrupt registers.
5. Configure the associated GPIO port pin for the Timer Input alternate function.
6. If using the Timer Output function, configure the associated GPIO port pin for the
Timer Output alternate function.
7. Write to the Timer Control Register to enable the timer.
In Counter Mode, the number of timer input transitions since the timer start is computed
via the following equation:
COUNTER Mode Timer Input Transitions = Current Count Value – Start Value
Comparator Counter Mode
In Comparator Counter Mode, the timer counts input transitions from the analog compara-
tor output. The TPOL bit in the Timer Control Register selects whether the count occurs
on the rising edge or the falling edge of the comparator output signal. In Comparator
Counter Mode, the prescaler is disabled.
The frequency of the comparator output signal must not exceed one-fourth the system
clock frequency.
Caution:
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Z8 Encore! XP® F0823 Series
Product Specification
74
After reaching the reload value stored in the Timer Reload High and Low Byte registers,
the timer generates an interrupt, the count value in the Timer High and Low Byte registers
is reset to 0001hand counting resumes. Also, if the Timer Output alternate function is
enabled, the Timer Output pin changes state (from Low to High or from High to Low) at
timer reload.
Observe the following steps to configure a timer for Comparator Counter Mode and initi-
ating the count:
1. Write to the Timer Control Register to:
–
–
–
Disable the timer.
Configure the timer for Comparator Counter Mode.
Select either the rising edge or falling edge of the comparator output signal for the
count. This also sets the initial logic level (High or Low) for the Timer Output
alternate function. However, the Timer Output function is not required to be
enabled.
2. Write to the Timer High and Low Byte registers to set the starting count value. This
action only affects the first pass in Comparator Counter Mode. After the first timer
reload in Comparator Counter Mode, counting always begins at the reset value of
0001h. Generally, in Comparator Counter Mode the Timer High and Low Byte regis-
ters must be written with the value 0001h.
3. Write to the Timer Reload High and Low Byte registers to set the reload value.
4. If appropriate, enable the timer interrupt and set the timer interrupt priority by writing
to the relevant interrupt registers.
5. If using the Timer Output function, configure the associated GPIO port pin for the
Timer Output alternate function.
6. Write to the Timer Control Register to enable the timer.
In Comparator Counter Mode, the number of comparator output transitions since the timer
start is computed via the following equation:
Comparator Output Transitions = Current Count Value – Start Value
PWM Single Output Mode
In PWM Single Output Mode, the timer outputs a PWM output signal through a GPIO
port pin. The timer input is the system clock. The timer first counts up to the 16-bit PWM
match value stored in the Timer PWM High and Low Byte registers. When the timer count
value matches the PWM value, the Timer Output toggles. The timer continues counting
until it reaches the reload value stored in the Timer Reload High and Low Byte registers.
Upon reaching the reload value, the timer generates an interrupt, the count value in the
Timer High and Low Byte registers is reset to 0001hand counting resumes.
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Z8 Encore! XP® F0823 Series
Product Specification
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If the TPOL bit in the Timer Control Register is set to 1, the Timer Output signal begins as
a High (1) and transitions to a Low (0) when the timer value matches the PWM value. The
Timer Output signal returns to a High (1) after the timer reaches the reload value and is
reset to 0001h.
If the TPOL bit in the Timer Control Register is set to 0, the Timer Output signal begins as
a Low (0) and transitions to a High (1) when the timer value matches the PWM value. The
Timer Output signal returns to a Low (0) after the timer reaches the reload value and is
reset to 0001h.
Observe the following steps to configure a timer for PWM Single Output Mode and initi-
ating the PWM operation:
1. Write to the Timer Control Register to:
–
–
–
–
Disable the timer
Configure the timer for PWM Mode
Set the prescale value
Set the initial logic level (High or Low) and PWM High/Low transition for the
Timer Output alternate function
2. Write to the Timer High and Low Byte registers to set the starting count value (typi-
cally 0001h); this write only affects the first pass in PWM Mode. After the first timer
reset in PWM Mode, counting always begins at the reset value of 0001h.
3. Write to the PWM High and Low Byte registers to set the PWM value.
4. Write to the Timer Reload High and Low Byte registers to set the reload value (PWM
period). The reload value must be greater than the PWM value.
5. If appropriate, enable the timer interrupt and set the timer interrupt priority by writing
to the relevant interrupt registers.
6. Configure the associated GPIO port pin for the Timer Output alternate function.
7. Write to the Timer Control Register to enable the timer and initiate counting.
The PWM period is represented by the following equation:
Reload Value Prescale
PWM Period (s) = -----------------------------------------------------------------------
System Clock Frequency (Hz)
If an initial starting value other than 0001his loaded into the Timer High and Low Byte
registers, use the One-Shot Mode equation to determine the first PWM time-out period. If
TPOL is set to 0, the ratio of the PWM output High time to the total period is represented
by the following equation:
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Z8 Encore! XP® F0823 Series
Product Specification
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Reload Value – PWM Value
PWM Output High Time Ratio (%) =
100
-------------------------------------------------------------------
Reload Value
If TPOL is set to 1, the ratio of the PWM output High time to the total period is repre-
sented by the following equation:
PWM Value
Reload Value
PWM Output High Time Ratio (%) =
100
-----------------------------------
PWM Dual Output Mode
In PWM Dual Output Mode, the timer outputs a PWM output signal pair (basic PWM sig-
nal and its complement) through two GPIO port pins. The timer input is the system clock.
The timer first counts up to the 16-bit PWM match value stored in the Timer PWM High
and Low Byte registers. When the timer count value matches the PWM value, the Timer
Output toggles. The timer continues counting until it reaches the reload value stored in the
Timer Reload High and Low Byte registers. Upon reaching the reload value, the timer
generates an interrupt, the count value in the Timer High and Low Byte registers is reset to
0001hand counting resumes.
If the TPOL bit in the Timer Control Register is set to 1, the Timer Output signal begins as
a High (1) and transitions to a Low (0) when the timer value matches the PWM value. The
Timer Output signal returns to a High (1) after the timer reaches the reload value and is
reset to 0001h.
If the TPOL bit in the Timer Control Register is set to 0, the Timer Output signal begins as
a Low (0) and transitions to a High (1) when the timer value matches the PWM value. The
Timer Output signal returns to a Low (0) after the timer reaches the reload value and is
reset to 0001h.
The timer also generates a second PWM output signal Timer Output Complement. The
Timer Output Complement is the complement of the Timer Output PWM signal. A pro-
grammable deadband delay can be configured to time delay (0 to 128 system clock cycles)
PWM output transitions on these two pins from a low to a high (inactive to active). This
ensures a time gap between the deassertion of one PWM output to the assertion of its com-
plement.
Observe the following steps to configure a timer for PWM DUAL OUTPUT Mode and
initiating the PWM operation:
1. Write to the Timer Control Register to:
–
–
Disable the timer
Configure the timer for PWM DUAL OUTPUT Mode. Setting the mode also
involves writing to the TMODEHI bit in the TxCTL1 Register
–
Set the prescale value
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Z8 Encore! XP® F0823 Series
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–
Set the initial logic level (High or Low) and PWM High/Low transition for the
Timer Output alternate function
2. Write to the Timer High and Low Byte registers to set the starting count value (typi-
cally 0001h); this write only affects the first pass in PWM Mode. After the first timer
reset in PWM Mode, counting always begins at the reset value of 0001h.
3. Write to the PWM High and Low Byte registers to set the PWM value.
4. Write to the PWM Control Register to set the PWM dead band delay value. The dead-
band delay must be less than the duration of the positive phase of the PWM signal (as
defined by the PWM high and low byte registers). It must also be less than the dura-
tion of the negative phase of the PWM signal (as defined by the difference between
the PWM registers and the Timer Reload registers).
5. Write to the Timer Reload High and Low Byte registers to set the reload value (PWM
period). The reload value must be greater than the PWM value.
6. If appropriate, enable the timer interrupt and set the timer interrupt priority by writing
to the relevant interrupt registers.
7. Configure the associated GPIO port pin for the Timer Output and Timer Output Com-
plement alternate functions. The Timer Output Complement function is shared with
the Timer Input function for both timers. Setting the timer mode to Dual PWM auto-
matically switches the function from Timer In to Timer Out Complement.
8. Write to the Timer Control Register to enable the timer and initiate counting.
The PWM period is represented by the following equation:
Reload Value Prescale
PWM Period (s) = -----------------------------------------------------------------------
System Clock Frequency (Hz)
If an initial starting value other than 0001his loaded into the Timer High and Low Byte
registers, the One-Shot Mode equation determines the first PWM time-out period.
If TPOL is set to 0, the ratio of the PWM output High time to the total period is repre-
sented by:
Reload Value – PWM Value
PWM Output High Time Ratio (%) =
100
------------------------------------------------------------------
Reload Value
If TPOL is set to 1, the ratio of the PWM output High time to the total period is repre-
sented by:
PWM Value
Reload Value
PWM Output High Time Ratio (%) =
100
-----------------------------------
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Operation
Z8 Encore! XP® F0823 Series
Product Specification
78
Capture Mode
In Capture Mode, the current timer count value is recorded when the appropriate external
Timer Input transition occurs. The capture count value is written to the Timer PWM High
and Low Byte registers. The timer input is the system clock. The TPOL bit in the Timer
Control Register determines if the capture occurs on a rising edge or a falling edge of the
Timer Input signal. When the capture event occurs, an interrupt is generated and the timer
continues counting. The INPCAP bit in TxCTL1 Register is set to indicate the timer inter-
rupt is because of an input capture event.
The timer continues counting up to the 16-bit reload value stored in the Timer Reload
High and Low Byte registers. Upon reaching the reload value, the timer generates an inter-
rupt and continues counting. The INPCAP bit in TxCTL1 Register clears indicating the
timer interrupt is not because of an input capture event.
Observe the following steps to configure a timer for Capture Mode and initiating the
count:
1. Write to the Timer Control Register to:
–
–
–
–
Disable the timer
Configure the timer for Capture Mode
Set the prescale value
Set the capture edge (rising or falling) for the Timer Input
2. Write to the Timer High and Low Byte registers to set the starting count value (typi-
cally 0001h).
3. Write to the Timer Reload High and Low Byte registers to set the reload value.
4. Clear the Timer PWM High and Low Byte registers to 0000h. Clearing these registers
allows the software to determine if interrupts were generated by either a capture or a
reload event. If the PWM High and Low Byte registers still contain 0000hafter the
interrupt, the interrupt was generated by a reload.
5. Enable the timer interrupt, if appropriate, and set the timer interrupt priority by writing
to the relevant interrupt registers. By default, the timer interrupt is generated for both
input capture and reload events. If appropriate, configure the timer interrupt to be gen-
erated only at the input capture event or the reload event by setting TICONFIG field
of the TxCTL1 Register.
6. Configure the associated GPIO port pin for the Timer Input alternate function.
7. Write to the Timer Control Register to enable the timer and initiate counting.
In Capture Mode, the elapsed time from timer start to capture event can be calculated
using the following equation:
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P R E L I M I N A R Y
Operation
Z8 Encore! XP® F0823 Series
Product Specification
79
Capture Value – Start Value Prescale
Capture Elapsed Time (s) = -------------------------------------------------------------------------------------------------
System Clock Frequency (Hz)
Capture Restart Mode
In Capture Restart Mode, the current timer count value is recorded when the acceptable
external Timer Input transition occurs. The capture count value is written to the Timer
PWM High and Low Byte registers. The timer input is the system clock. The TPOL bit in
the Timer Control Register determines if the capture occurs on a rising edge or a falling
edge of the Timer Input signal. When the capture event occurs, an interrupt is generated
and the count value in the Timer High and Low Byte registers is reset to 0001hand count-
ing resumes. The INPCAP bit in TxCTL1 Register is set to indicate the timer interrupt is
because of an input capture event.
If no capture event occurs, the timer counts up to the 16-bit compare value stored in the
Timer Reload High and Low Byte registers. Upon reaching the reload value, the timer
generates an interrupt, the count value in the Timer High and Low Byte registers is reset to
0001hand counting resumes. The INPCAP bit in TxCTL1 Register is cleared to indicate
the timer interrupt is not caused by an input capture event.
Observe the following steps to configure a timer for Capture Restart Mode and initiating
the count:
1. Write to the Timer Control Register to:
–
–
Disable the timer
Configure the timer for Capture Restart Mode; setting the mode also involves
writing to TMODEHI bit in TxCTL1 Register
–
–
Set the prescale value
Set the capture edge (rising or falling) for the Timer Input
2. Write to the Timer High and Low Byte registers to set the starting count value (typi-
cally 0001h).
3. Write to the Timer Reload High and Low Byte registers to set the reload value.
4. Clear the Timer PWM High and Low Byte registers to 0000h. Clearing these registers
allows the software to determine if interrupts were generated by either a capture or a
reload event. If the PWM High and Low Byte registers still contain 0000hafter the
interrupt, the interrupt was generated by a reload.
5. Enable the timer interrupt, if appropriate, and set the timer interrupt priority by writing
to the relevant interrupt registers. By default, the timer interrupt is generated for both
input capture and reload events. If appropriate, configure the timer interrupt to be gen-
erated only at the input capture event or the reload event by setting TICONFIG field
of the TxCTL1 Register.
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6. Configure the associated GPIO port pin for the Timer Input alternate function.
7. Write to the Timer Control Register to enable the timer and initiate counting.
In Capture Mode, the elapsed time from timer start to capture event can be calculated
using the following equation:
Capture Value – Start Value Prescale
Capture Elapsed Time (s) = -------------------------------------------------------------------------------------------------
System Clock Frequency (Hz)
Compare Mode
In Compare Mode, the timer counts up to the 16-bit maximum compare value stored in the
Timer Reload High and Low Byte registers. The timer input is the system clock. Upon
reaching the compare value, the timer generates an interrupt and counting continues (the
timer value is not reset to 0001h). Also, if the Timer Output alternate function is enabled,
the Timer Output pin changes state (from Low to High or from High to Low) upon com-
pare.
If the Timer reaches FFFFh, the timer rolls over to 0000hand continue counting. Observe
the following steps to configure a timer for Compare Mode and to initiate the count:
1. Write to the Timer Control Register to:
–
–
–
–
Disable the timer
Configure the timer for COMPARE Mode
Set the prescale value
Set the initial logic level (High or Low) for the Timer Output alternate function, if
appropriate
2. Write to the Timer High and Low Byte registers to set the starting count value.
3. Write to the Timer Reload High and Low Byte registers to set the compare value.
4. Enable the timer interrupt, if appropriate, and set the timer interrupt priority by writing
to the relevant interrupt registers.
5. If using the Timer Output function, configure the associated GPIO port pin for the
Timer Output alternate function.
6. Write to the Timer Control Register to enable the timer and initiate counting.
In Compare Mode, the system clock always provides the timer input. The compare time
can be calculated by the following equation:
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Z8 Encore! XP® F0823 Series
Product Specification
81
Compare Value – Start Value Prescale
COMPARE Mode Time (s) = ----------------------------------------------------------------------------------------------------
System Clock Frequency (Hz)
Gated Mode
In Gated Mode, the timer counts only when the Timer Input signal is in its active state
(asserted), as determined by the TPOL bit in the Timer Control Register. When the Timer
Input signal is asserted, counting begins. A timer interrupt is generated when the Timer
Input signal is deasserted or a timer reload occurs. To determine if a Timer Input signal
deassertion generated the interrupt, read the associated GPIO input value and compare to
the value stored in the TPOL bit.
The timer counts up to the 16-bit reload value stored in the Timer Reload High and Low
Byte registers. The timer input is the system clock. When reaching the reload value, the
timer generates an interrupt, the count value in the Timer High and Low Byte registers is
reset to 0001hand counting resumes (assuming the Timer Input signal remains asserted).
Also, if the Timer Output alternate function is enabled, the Timer Output pin changes state
(from Low to High or from High to Low) at timer reset.
Observe the following steps to configure a timer for Gated Mode and to initiate the count:
1. Write to the Timer Control Register to:
–
–
–
Disable the timer
Configure the timer for Gated Mode
Set the prescale value
2. Write to the Timer High and Low Byte registers to set the starting count value. Writing
these registers only affects the first pass in Gated Mode. After the first timer reset in
Gated Mode, counting always begins at the reset value of 0001h.
3. Write to the Timer Reload High and Low Byte registers to set the reload value.
4. Enable the timer interrupt, if appropriate, and set the timer interrupt priority by writing
to the relevant interrupt registers. By default, the timer interrupt is generated for both
input deassertion and reload events. If appropriate, configure the timer interrupt to be
generated only at the input deassertion event or the reload event by setting TICONFIG
field of the TxCTL1 Register.
5. Configure the associated GPIO port pin for the Timer Input alternate function.
6. Write to the Timer Control Register to enable the timer.
7. Assert the Timer Input signal to initiate the counting.
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Z8 Encore! XP® F0823 Series
Product Specification
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Capture/Compare Mode
In Capture/Compare Mode, the timer begins counting on the first external Timer Input
transition. The acceptable transition (rising edge or falling edge) is set by the TPOL bit in
the Timer Control Register. The timer input is the system clock.
Every subsequent acceptable transition (after the first) of the Timer Input signal captures
the current count value. The capture value is written to the Timer PWM High and Low
Byte registers. When the capture event occurs, an interrupt is generated, the count value in
the Timer High and Low Byte registers is reset to 0001h, and counting resumes. The
INPCAP bit in TxCTL1 Register is set to indicate the timer interrupt is caused by an input
capture event.
If no capture event occurs, the timer counts up to the 16-bit compare value stored in the
Timer Reload High and Low Byte registers. Upon reaching the compare value, the timer
generates an interrupt, the count value in the Timer High and Low Byte registers is reset to
0001hand counting resumes. The INPCAP bit in TxCTL1 Register is cleared to indicate
the timer interrupt is not because of an input capture event.
Observe the following steps to configure a timer for Capture/Compare Mode and initiating
the count:
1. Write to the Timer Control Register to:
–
–
–
–
Disable the timer
Configure the timer for Capture/Compare Mode
Set the prescale value
Set the capture edge (rising or falling) for the Timer Input
2. Write to the Timer High and Low Byte registers to set the starting count value (typi-
cally 0001h).
3. Write to the Timer Reload High and Low Byte registers to set the compare value.
4. Enable the timer interrupt, if appropriate, and set the timer interrupt priority by writing
to the relevant interrupt registers.By default, the timer interrupt are generated for both
input capture and reload events. If appropriate, configure the timer interrupt to be gen-
erated only at the input capture event or the reload event by setting TICONFIG field
of the TxCTL1 Register.
5. Configure the associated GPIO port pin for the Timer Input alternate function.
6. Write to the Timer Control Register to enable the timer.
7. Counting begins on the first appropriate transition of the Timer Input signal. No inter-
rupt is generated by this first edge.
In Capture/Compare Mode, the elapsed time from timer start to capture event can be cal-
culated using the following equation:
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Z8 Encore! XP® F0823 Series
Product Specification
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Capture Value – Start Value Prescale
-----------------------------------------------------------------------------------------------------------------------
Capture Elapsed Time (s) =
System Clock Frequency (Hz)
Reading the Timer Count Values
The current count value in the timers can be read while counting (enabled). This capability
has no effect on timer operation. When the timer is enabled and the Timer High Byte Reg-
ister is read, the contents of the Timer Low Byte register are placed in a holding register. A
subsequent read from the Timer Low Byte register returns the value in the holding register.
This operation allows accurate reads of the full 16-bit timer count value while enabled.
When the timers are not enabled, a read from the Timer Low Byte register returns the
actual value in the counter.
Timer Pin Signal Operation
Timer Output is a GPIO port pin alternate function. The Timer Output is toggled every
time the counter is reloaded.
The timer input can be used as a selectable counting source. It shares the same pin as the
complementary timer output (TxOUT). When selected by the GPIO Alternate Function
registers, this pin functions as a timer input in all modes except for Dual PWM Output
Mode. For this mode, there is no timer input available. For the 8-pin device, the T0OUT
function is available for the various timer out functions. The T1OUT function is only
available in Dual PWM Output Mode.
Timer Control Register Definitions
This section defines the features of the following Timer Control registers.
Timer 0–1 High and Low Byte Registers: see page 83
Timer Reload High and Low Byte Registers: see page 84
Timer 0–1 PWM High and Low Byte Registers: see page 86
Timer 0–1 Control Registers: see page 86
Timer 0–1 High and Low Byte Registers
The Timer 0–1 High and Low Byte (TxH and TxL) registers (Table 51 and Table 52) con-
tain the current 16-bit timer count value. When the timer is enabled, a read from TxH
causes the value in TxL to be stored in a temporary holding register. A read from TxL
always returns this temporary register when the timers are enabled. When the timer is dis-
abled, reads from the TxL reads the register directly.
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Writing to the Timer High and Low Byte registers while the timer is enabled is not recom-
mended. There are no temporary holding registers available for write operations, so simul-
taneous 16-bit writes are not possible. If either the Timer High or Low Byte registers are
written during counting, the 8-bit written value is placed in the counter (High or Low
Byte) at the next clock edge. The counter continues counting from the new value.
Table 51. Timer 0–1 High Byte Register (TxH)
Bit
7
6
5
4
3
2
1
0
TH
Field
0
0
0
0
0
0
0
0
RESET
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
F00h, F08h
Address
Table 52. Timer 0–1 Low Byte Register (TxL)
Bit
7
6
5
4
3
2
1
0
TL
Field
0
0
0
0
0
0
0
1
RESET
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
F01h, F09h
Address
Bit
Description
[7:0]
TH, TL
Timer High and Low Bytes
These 2 bytes, {TH[7:0], TL[7:0]}, contain the current 16-bit timer count value.
Timer Reload High and Low Byte Registers
The Timer 0–1 Reload High and Low Byte (TxRH and TxRL) registers (Table 53 and
Table 54) store a 16-bit reload value, {TRH[7:0], TRL[7:0]}. Values written to the Timer
Reload High Byte register are stored in a temporary holding register. When a write to the
Timer Reload Low Byte register occurs, the temporary holding register value is written to
the Timer High Byte register. This operation allows simultaneous updates of the 16-bit
Timer reload value. In Compare Mode, the Timer Reload High and Low Byte registers
store the 16-bit compare value.
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Timer Control Register Definitions
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Product Specification
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Table 53. Timer 0–1 Reload High Byte Register (TxRH)
Bit
7
6
5
4
3
2
1
0
TRH
Field
1
1
1
1
1
1
1
1
RESET
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
F02h, F0Ah
Address
Table 54. Timer 0–1 Reload Low Byte Register (TxRL)
Bit
7
6
5
4
3
2
1
0
TRL
Field
1
1
1
1
1
1
1
1
RESET
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
F03h, F0Bh
Address
Bit
Description
[7]
[6]
[5]
[4]
[3]
[2]
[1]
[0]
TRH and TRL—Timer Reload Register High and Low
These two bytes form the 16-bit reload value, {TRH[7:0], TRL[7:0]}. This value sets the
maximum count value which initiates a timer reload to 0001h. In COMPARE Mode,
these two bytes form the 16-bit compare value.
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Z8 Encore! XP® F0823 Series
Product Specification
86
Timer 0–1 PWM High and Low Byte Registers
The Timer 0–1 PWM High and Low Byte (TxPWMH and TxPWML) registers (Table 55
and Table 56) control pulse-width modulator (PWM) operations. These registers also store
the capture values for the Capture and Capture/Compare modes.
Table 55. Timer 0–1 PWM High Byte Register (TxPWMH)
Bit
7
6
5
4
3
2
1
0
PWMH
Field
0
0
0
0
0
0
0
0
RESET
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
F04h, F0Ch
Address
Table 56. Timer 0–1 PWM Low Byte Register (TxPWML)
Bit
7
6
5
4
3
2
1
0
PWML
Field
0
0
0
0
0
0
0
0
RESET
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
F05h, F0Dh
Address
Bit
Description
[7:0]
Pulse-Width Modulator High and Low Bytes
PWMH, These two bytes, {PWMH[7:0], PWML[7:0]}, form a 16-bit value that is compared to the current
PWML
16-bit timer count. When a match occurs, the PWM output changes state. The PWM output
value is set by the TPOL bit in the Timer Control Register (TxCTL1)
register.
These TxPWMH and TxPWML registers also store the 16-bit captured timer value when oper-
ating in Capture or Capture/Compare modes.
Timer 0–1 Control Registers
The Timer Control registers are 8-bit read/write registers that control the operation of their
associated counter/timers.
Timer 0–1 Control Register 0
The Timer Control Register 0 (TxCTL0) and Timer Control Register 1 (TxCTL1) deter-
mine the timer operating mode. It also includes a programmable PWM deadband delay,
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Timer Control Register Definitions
Z8 Encore! XP® F0823 Series
Product Specification
87
two bits to configure timer interrupt definition, and a status bit to identify if the most
recent timer interrupt is caused by an input capture event.
Table 57. Timer 0–1 Control Register 0 (TxCTL0)
Bit
7
6
5
4
3
2
1
0
TMODEHI
TICONFIG
Reserved
PWMD
INPCAP
Field
0
0
0
0
0
0
0
0
RESET
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
F06h, F0Eh
Address
Bit
Description
[7]
Timer Mode High Bit
TMODEHI This bit along with the TMODE field in TxCTL1 Register determines the operating mode of
the timer. This is the most-significant bit of the Timer mode selection value.
[6:5]
Timer Interrupt Configuration
TICONFIG This field configures timer interrupt definition.
0x = Timer Interrupt occurs on all defined reload, compare and input events.
10 = Timer Interrupt only on defined input capture/deassertion events.
11 = Timer Interrupt only on defined reload/compare events.
[4]
Reserved
This bit is reserved and must be programmed to 0.
[3:1]
PWMD
PWMD—PWM Delay value
This field is a programmable delay to control the number of system clock cycles delay
before the Timer Output and the Timer Output Complement are forced to their active state.
000 = No delay.
001 = 2 cycles delay.
010 = 4 cycles delay.
011 = 8 cycles delay.
100 = 16 cycles delay.
101 = 32 cycles delay.
110 = 64 cycles delay.
111 = 128 cycles delay.
[0]
INPCAP
Input Capture Event
This bit indicates if the most recent timer interrupt is caused by a Timer Input capture event.
0 = Previous timer interrupt is not a result of Timer Input capture event.
1 = Previous timer interrupt is a result of Timer Input capture event.
Timer 0–1 Control Register 1
The Timer 0–1 Control (TxCTL1) registers enable/disable the timers, set the prescaler
value, and determine the timer operating mode.
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Timer Control Register Definitions
Z8 Encore! XP® F0823 Series
Product Specification
88
Table 58. Timer 0–1 Control Register 1 (TxCTL1)
Bit
7
6
5
4
3
2
1
0
TEN
TPOL
PRES
TMODE
Field
0
0
0
0
0
0
0
0
RESET
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
F07h, F0Fh
Address
Bit
Description
[7]
TEN
Timer Enable
0 = Timer is disabled.
1 = Timer enabled to count.
[6]
TPOL
Timer Input/Output Polarity
Operation of this bit is a function of the current operating mode of the timer.
One-Shot Mode
When the timer is disabled, the Timer Output signal is set to the value of this bit. When the
timer is enabled, the Timer Output signal is complemented upon timer reload.
Continuous Mode
When the timer is disabled, the Timer Output signal is set to the value of this bit. When the
timer is enabled, the Timer Output signal is complemented upon timer reload.
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Timer Control Register Definitions
Z8 Encore! XP® F0823 Series
Product Specification
89
Bit
Description (Continued)
Counter Mode
If the timer is enabled the Timer Output signal is complemented after timer reload.
0 = Count occurs on the rising edge of the Timer Input signal.
[6]
TPOL
(cont’d.)
1 = Count occurs on the falling edge of the Timer Input signal.
PWM Single Output Mode
0 = Timer Output is forced Low (0) when the timer is disabled. When enabled, the Timer Output
is forced High (1) upon PWM count match and forced Low (0) upon reload.
1 = Timer Output is forced High (1) when the timer is disabled. When enabled, the Timer Out-
put is forced Low (0) upon PWM count match and forced High (1) upon reload.
Capture Mode
0 = Count is captured on the rising edge of the Timer Input signal.
1 = Count is captured on the falling edge of the Timer Input signal.
Compare Mode
When the timer is disabled, the Timer Output signal is set to the value of this bit. When the
timer is enabled, the Timer Output signal is complemented upon timer reload.
Gated Mode
0 = Timer counts when the Timer Input signal is High (1) and interrupts are generated on the
falling edge of the Timer Input.
1 = Timer counts when the Timer Input signal is Low (0) and interrupts are generated on the
rising edge of the Timer Input.
Capture/Compare Mode
0 = Counting is started on the first rising edge of the Timer Input signal. The current count is
captured on subsequent rising edges of the Timer Input signal.
1 = Counting is started on the first falling edge of the Timer Input signal. The current count is
captured on subsequent falling edges of the Timer Input signal.
PWM Dual Output Mode
0 = Timer Output is forced Low (0) and Timer Output Complement is forced High (1) when the
timer is disabled. When enabled, the Timer Output is forced High (1) upon PWM count
match and forced Low (0) upon reload. When enabled, the Timer Output Complement is
forced Low (0) upon PWM count match and forced High (1) upon reload. The PWMD field
in TxCTL0 register is a programmable delay to control the number of cycles time delay
before the Timer Output and the Timer Output Complement is forced to High (1).
1 = Timer Output is forced High (1) and Timer Output Complement is forced Low (0) when the
timer is disabled. When enabled, the Timer Output is forced Low (0) upon PWM count
match and forced High (1) upon reload.When enabled, the Timer Output Complement is
forced High (1) upon PWM count match and forced Low (0) upon reload. The PWMD field
in TxCTL0 register is a programmable delay to control the number of cycles time delay
before the Timer Output and the Timer Output Complement is forced to Low (0).
Capture Restart Mode
0 = Count is captured on the rising edge of the Timer Input signal.
1 = Count is captured on the falling edge of the Timer Input signal.
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Timer Control Register Definitions
Z8 Encore! XP® F0823 Series
Product Specification
90
Bit
Description (Continued)
[6]
TPOL
(cont’d.)
Comparator Counter Mode
When the timer is disabled, the Timer Output signal is set to the value of this bit. When the
timer is enabled, the Timer Output signal is complemented upon timer reload.
Caution: When the Timer Output alternate function TxOUT on a GPIO port pin is enabled,
TxOUT changes to whatever state the TPOL bit is in. The timer does not need to be enabled
for that to happen. Also, the port data direction sub register is not needed to be set to output on
TxOUT. Changing the TPOL bit with the timer enabled and running does not immediately
change the TxOUT.
[5:3]
PRES
Prescale Value
The timer input clock is divided by 2
PRES
, where PRES can be set from 0 to 7. The prescaler is
reset each time the timer is disabled. This reset ensures proper clock division each time the
timer is restarted.
000 = Divide by 1.
001 = Divide by 2.
010 = Divide by 4.
011 = Divide by 8.
100 = Divide by 16.
101 = Divide by 32.
110 = Divide by 64.
111 = Divide by 128.
[2:0]
Timer Mode
TMODE This field, along with the TMODEHI bit in TxCTL0 Register, determines the operating mode of
the timer. TMODEHI is the most significant bit of the timer mode selection value.
0000 = One-Shot Mode.
0001 = Continuous Mode.
0010 = Counter Mode.
0011 = PWM Single Output Mode.
0100 = Capture Mode.
0101 = Compare Mode.
0110 = Gated Mode.
0111 = Capture/Compare Mode.
1000 = PWM Dual Output Mode.
1001 = Capture Restart Mode.
1010 = Comparator Counter Mode.
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Timer Control Register Definitions
Z8 Encore! XP® F0823 Series
Product Specification
91
Watchdog Timer
The Watchdog Timer (WDT) protects against corrupt or unreliable software, power faults,
and other system-level problems which can place Z8 Encore! XP F0823 Series devices
into unsuitable operating states. The features of Watchdog Timer include:
•
•
•
On-chip RC oscillator
A selectable time-out response: reset or interrupt
24-bit programmable time-out value
Operation
The WDT is a retriggerable one-shot timer that resets or interrupts F0823 Series devices
when the WDT reaches its terminal count. The Watchdog Timer uses a dedicated on-chip
RC oscillator as its clock source. The Watchdog Timer operates in only two modes: ON
and OFF. Once enabled, it always counts and must be refreshed to prevent a time-out. Per-
form an enable by executing the WDT instruction or by setting the WDT_AO Flash
Option Bit. The WDT_AO bit forces the Watchdog Timer to operate immediately upon
reset, even if a WDT instruction has not been executed.
The Watchdog Timer is a 24-bit reloadable down counter that uses three 8-bit registers in
the eZ8 CPU register space to set the reload value. The nominal WDT time-out period is
described by the following equation:
WDT Reload Value
------------------------------------------
WDT Time-out Period (ms) =
10
where the WDT reload value is the decimal value of the 24-bit value given by
{WDTU[7:0], WDTH[7:0], WDTL[7:0]} and the typical Watchdog Timer RC oscillator
frequency is 10kHz. The Watchdog Timer cannot be refreshed after it reaches 000002h.
The WDT Reload Value must not be set to values below 000004h. Table 59 provides
information about approximate time-out delays for the minimum and maximum WDT
reload values.
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Watchdog Timer
Z8 Encore! XP® F0823 Series
Product Specification
92
Table 59. Watchdog Timer Approximate Time-Out Delays
Approximate Time-Out Delay
(with 10kHz typical WDT oscillator frequency)
WDT Reload Value WDT Reload Value
(Hex)
000004
FFFFFF
(Decimal)
Typical
400 s
Description
4
Minimum time-out delay
Maximum time-out delay
16,777,215
28 minutes
Watchdog Timer Refresh
When first enabled, the WDT is loaded with the value in the Watchdog Timer Reload reg-
isters. The Watchdog Timer counts down to 000000hunless a WDT instruction is exe-
cuted by the eZ8 CPU. Execution of the WDT instruction causes the down counter to be
reloaded with the WDT reload value stored in the Watchdog Timer Reload registers.
Counting resumes following the reload operation.
When Z8 Encore! XP F0823 Series devices are operating in Debug Mode (using the
OCD), the Watchdog Timer is continuously refreshed to prevent any Watchdog Timer
time-outs.
Watchdog Timer Time-Out Response
The Watchdog Timer times out when the counter reaches 000000h. A time-out of the
Watchdog Timer generates either an interrupt or a system reset. The WDT_RES Flash
Option Bit determines the time-out response of the Watchdog Timer. For information
about programming of the WDT_RES Flash Option Bit, see the Flash Option Bits chapter
on page 148.
WDT Interrupt in Normal Operation
If configured to generate an interrupt when a time-out occurs, the Watchdog Timer issues
an interrupt request to the interrupt controller and sets the WDT status bit in the Watchdog
Timer Control Register. If interrupts are enabled, the eZ8 CPU responds to the interrupt
request by fetching the Watchdog Timer interrupt vector and executing code from the vec-
tor address. After time-out and interrupt generation, the Watchdog Timer counter rolls
over to its maximum value of FFFFFhand continues counting. The Watchdog Timer
counter is not automatically returned to its Reload Value.
The Reset Status Register (see the Reset Status Register section on page 28) must be read
before clearing the WDT interrupt. This read clears the WDT time-out Flag and prevents
further WDT interrupts for immediately occurring.
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Operation
Z8 Encore! XP® F0823 Series
Product Specification
93
WDT Interrupt in Stop Mode
If configured to generate an interrupt when a time-out occurs and F0823 Series are in Stop
Mode, the Watchdog Timer automatically initiates a Stop-Mode Recovery and generates
an interrupt request. Both the WDT status bit and the stop bit in the Watchdog Timer Con-
trol Register are set to 1 following a WDT time-out in Stop Mode. For more information
about Stop-Mode Recovery, see the Reset and Stop-Mode Recovery chapter on page 21.
If interrupts are enabled, following completion of the Stop-Mode Recovery the eZ8 CPU
responds to the interrupt request by fetching the Watchdog Timer interrupt vector and exe-
cuting code from the vector address.
WDT Reset in Normal Operation
If configured to generate a Reset when a time-out occurs, the Watchdog Timer forces the
device into the System Reset state. The WDT status bit in the Watchdog Timer Control
Register is set to 1. For more information about System Reset, see the Reset and Stop-
Mode Recovery chapter on page 21.
WDT Reset in Stop Mode
If configured to generate a Reset when a time-out occurs and the device is in Stop Mode,
the Watchdog Timer initiates a Stop-Mode Recovery. Both the WDT status bit and the stop
bit in the Watchdog Timer Control Register are set to 1 following WDT time-out in Stop
Mode. For more information, see the Reset and Stop-Mode Recovery chapter on page 21.
Watchdog Timer Reload Unlock Sequence
Writing the unlock sequence to the Watchdog Timer Control Register (WDTCTL) address
unlocks the three Watchdog Timer Reload Byte Registers (WDTU, WDTH, and WDTL)
to allow changes to the time-out period. These write operations to the WDTCTL Register
address produce no effect on the bits in the WDTCTL Register. The locking mechanism
prevents spurious writes to the Reload registers. The following sequence is required to
unlock the Watchdog Timer Reload Byte Registers (WDTU, WDTH, and WDTL) for
write access.
1. Write 55hto the Watchdog Timer Control Register (WDTCTL).
2. Write AAhto the Watchdog Timer Control Register (WDTCTL).
3. Write the Watchdog Timer Reload Upper Byte register (WDTU).
4. Write the Watchdog Timer Reload High Byte register (WDTH).
5. Write the Watchdog Timer Reload Low Byte register (WDTL).
All three Watchdog Timer Reload registers must be written in the order just listed. There
must be no other register writes between each of these operations. If a register write
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Operation
Z8 Encore! XP® F0823 Series
Product Specification
94
occurs, the lock state machine resets and no further writes can occur unless the sequence is
restarted. The value in the Watchdog Timer Reload registers is loaded into the counter
when the Watchdog Timer is first enabled and every time a WDT instruction is executed.
Watchdog Timer Control Register Definitions
This section defines the features of the following Watchdog Timer Control registers.
Watchdog Timer Control Register (WDTCTL): see page 94
Watchdog Timer Reload Upper Byte Register (WDTU): see page 95
Watchdog Timer Reload High Byte Register (WDTH): see page 95
Watchdog Timer Reload Low Byte Register (WDTL): see page 96
Watchdog Timer Control Register
The Watchdog Timer Control (WDTCTL) register is a write-only control register. Writing
the 55h, AAhunlock sequence to the WDTCTL Register address unlocks the three Watch-
dog Timer Reload Byte registers (WDTU, WDTH and WDTL) to allow changes to the
time-out period. These write operations to the WDTCTL Register address produce no
effect on the bits in the WDTCTL Register. The locking mechanism prevents spurious
writes to the Reload registers.
This register address is shared with the read-only Reset Status Register.
Table 60. Watchdog Timer Control Register (WDTCTL)
Bit
7
6
5
4
3
2
1
0
WDTUNLK
Field
X
X
X
X
X
X
X
X
RESET
R/W
W
W
W
W
W
W
W
W
FF0h
Address
Bit
Description
[7:0]
Watchdog Timer Unlock
WDTUNLK The software must write the correct unlocking sequence to this register before it is allowed
to modify the contents of the Watchdog Timer reload registers.
Watchdog Timer Reload Upper, High and Low Byte Registers
The Watchdog Timer Reload Upper, High and Low Byte (WDTU, WDTH, WDTL) regis-
ters, shown in Tables 61 through 63, form the 24-bit reload value that is loaded into the
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Watchdog Timer Control Register
Z8 Encore! XP® F0823 Series
Product Specification
95
Watchdog Timer when a WDT instruction executes. The 24-bit reload value ranges across
bits [23:0] to encompass the three bytes {WDTU[7:0], WDTH[7:0], WDTL[7:0]}. Writ-
ing to these registers sets the appropriate Reload Value. Reading from these registers
returns the current Watchdog Timer count value.
The 24-bit WDT Reload Value must not be set to a value less than 000004h.
Caution:
Table 61. Watchdog Timer Reload Upper Byte Register (WDTU)
Bit
7
6
5
4
3
2
1
0
WDTU
00h
Field
RESET
R/W
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
FF1h
Address
Note: R/W*—Read returns the current WDT count value. Write sets the appropriate Reload Value.
Bit
Description
[7:0]
WDTU
WDT Reload Upper Byte
Most significant byte (MSB), Bits[23:16], of the 24-bit WDT reload value.
Table 62. Watchdog Timer Reload High Byte Register (WDTH)
Bit
7
6
5
4
3
2
1
0
WDTH
04h
Field
RESET
R/W
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
FF2h
Address
Note: R/W*—Read returns the current WDT count value. Write sets the appropriate Reload Value.
Bit
Description
[7:0]
WDTH
WDT Reload High Byte
Middle byte, Bits[15:8], of the 24-bit WDT reload value.
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Z8 Encore! XP® F0823 Series
Product Specification
96
Table 63. Watchdog Timer Reload Low Byte Register (WDTL)
Bit
7
6
5
4
3
2
1
0
WDTL
00h
Field
RESET
R/W
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
R/W*
FF3h
Address
Note: R/W*—Read returns the current WDT count value. Write sets the appropriate Reload Value.
Bit
Description
[7:0]
WDTL
WDT Reload Low
Least significant byte (LSB), Bits[7:0], of the 24-bit WDT reload value.
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Watchdog Timer Control Register
Z8 Encore! XP® F0823 Series
Product Specification
97
Universal Asynchronous Receiver/
Transmitter
The universal asynchronous receiver/transmitter (UART) is a full-duplex communication
channel capable of handling asynchronous data transfers. The UART uses a single 8-bit
data mode with selectable parity. The features of UART include:
•
•
•
•
•
•
•
•
8-bit asynchronous data transfer
Selectable even- and odd-parity generation and checking
Option of one or two Stop bits
Separate transmit and receive interrupts
Framing, parity, overrun, and break detection
Separate transmit and receive enables
16-bit baud rate generator (BRG)
Selectable MULTIPROCESSOR (9-bit) Mode with three configurable interrupt
schemes
•
•
BRG can be configured and used as a basic 16-bit timer
Driver Enable output for external bus transceivers
Architecture
The UART consists of three primary functional blocks: transmitter, receiver, and baud rate
generator. The UART’s transmitter and receiver function independently, but employ the
same baud rate and data format. Figure 10 displays the UART architecture.
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Universal Asynchronous Receiver/
Z8 Encore! XP® F0823 Series
Product Specification
98
Parity Checker
Receive Shifter
Receiver Control
with Address Compare
RXD
Receive Data
Register
Control Registers
System Bus
Transmit Data
Register
Status Register
Baud Rate
Generator
Transmit Shift
Register
TXD
Transmitter Control
Parity Generator
CTS
DE
Figure 10. UART Block Diagram
Operation
The UART always transmits and receives data in an 8-bit data format, least-significant bit
(lsb) first. An even or odd parity bit can be added to the data stream. Each character begins
with an active Low Start bit and ends with either 1 or 2 active High Stop bits. Figure 11
and Figure 12 display the asynchronous data format employed by the UART without par-
ity and with parity, respectively.
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P R E L I M I N A R Y
Operation
Z8 Encore! XP® F0823 Series
Product Specification
99
Data Field
Stop Bit(s)
msb
Idle State
of Line
lsb
1
0
Start
Bit0
Bit1
Bit2
Bit3
Bit4
Bit5
Bit6
Bit7
1
2
Figure 11. UART Asynchronous Data Format without Parity
Data Field
Stop Bit(s)
Idle State
of Line
lsb
msb
Bit7
1
0
Start
Bit0
Bit1
Bit2
Bit3
Bit4
Bit5
Bit6
Parity
1
2
Figure 12. UART Asynchronous Data Format with Parity
Transmitting Data Using the Polled Method
Observe the following steps to transmit data using the polled method of operation:
1. Write to the UART Baud Rate High and Low Byte registers to set the required baud
rate.
2. Enable the UART pin functions by configuring the associated GPIO port pins for
alternate function operation.
3. Write to the UART Control 1 Register, if MULTIPROCESSOR Mode is appropriate,
to enable MULTIPROCESSOR (9-bit) Mode functions.
4. Set the Multiprocessor Mode Select (MPEN) bit to enable MULTIPROCESSOR
Mode.
5. Write to the UART Control 0 Register to:
–
–
Set the transmit enable bit (TEN) to enable the UART for data transmission
Set the parity enable bit (PEN), if parity is appropriate and MULTIPROCESSOR
Mode is not enabled, and select either even or odd parity (PSEL)
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Operation
Z8 Encore! XP® F0823 Series
Product Specification
100
–
Set or clear the CTSE bit to enable or disable control from the remote receiver
using the CTS pin
6. Check the TDRE bit in the UART Status 0 Register to determine if the Transmit Data
Register is empty (indicated by a 1). If empty, continue to Step 7. If the Transmit Data
Register is full (indicated by a 0), continue to monitor the TDRE bit until the Transmit
Data Register becomes available to receive new data.
7. Write the UART Control 1 Register to select the outgoing address bit.
8. Set the Multiprocessor Bit Transmitter (MPBT) if sending an address byte, clear it if
sending a data byte.
9. Write the data byte to the UART Transmit Data Register. The transmitter automati-
cally transfers the data to the Transmit Shift register and transmits the data.
10. Make any changes to the Multiprocessor Bit Transmitter (MPBT) value, if appropriate
and MULTIPROCESSOR Mode is enabled,.
11. To transmit additional bytes, return to Step 5.
Transmitting Data Using the Interrupt-Driven Method
The UART Transmitter interrupt indicates the availability of the Transmit Data Register to
accept new data for transmission. Observe the following steps to configure the UART for
interrupt-driven data transmission:
1. Write to the UART Baud Rate High and Low Byte registers to set the appropriate baud
rate.
2. Enable the UART pin functions by configuring the associated GPIO port pins for
alternate function operation.
3. Execute a DI instruction to disable interrupts.
4. Write to the Interrupt control registers to enable the UART Transmitter interrupt and
set the acceptable priority.
5. Write to the UART Control 1 Register to enable MULTIPROCESSOR (9-bit) Mode
functions, if MULTIPROCESSOR Mode is appropriate.
6. Set the MULTIPROCESSOR Mode Select (MPEN) to Enable MULTIPROCESSOR
Mode.
7. Write to the UART Control 0 Register to:
–
–
Set the transmit enable bit (TEN) to enable the UART for data transmission.
Enable parity, if appropriate and if MULTIPROCESSOR Mode is not enabled,
and select either even or odd parity.
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Operation
Z8 Encore! XP® F0823 Series
Product Specification
101
–
Set or clear CTSE to enable or disable control from the remote receiver using the
CTS pin.
8. Execute an EI instruction to enable interrupts.
The UART is now configured for interrupt-driven data transmission. Because the UART
Transmit Data Register is empty, an interrupt is generated immediately. When the UART
Transmit interrupt is detected, the associated interrupt service routine (ISR) performs the
following:
1. Write the UART Control 1 Register to select the multiprocessor bit for the byte to be
transmitted:
Set the Multiprocessor Bit Transmitter (MPBT) if sending an address byte, clear it if
sending a data byte.
2. Write the data byte to the UART Transmit Data Register. The transmitter automati-
cally transfers the data to the Transmit Shift register and transmits the data.
3. Clear the UART Transmit interrupt bit in the applicable Interrupt Request register.
4. Execute the IRET instruction to return from the interrupt-service routine and wait for
the Transmit Data Register to again become empty.
Receiving Data Using the Polled Method
Observe the following steps to configure the UART for polled data reception:
1. Write to the UART Baud Rate High and Low Byte registers to set an acceptable baud
rate for the incoming data stream.
2. Enable the UART pin functions by configuring the associated GPIO port pins for
alternate function operation.
3. Write to the UART Control 1 Register to enable MULTIPROCESSOR Mode func-
tions, if appropriate.
4. Write to the UART Control 0 Register to:
–
–
Set the receive enable bit (REN) to enable the UART for data reception
Enable parity, if appropriate and if Multiprocessor Mode is not enabled, and select
either even or odd parity
5. Check the RDA bit in the UART Status 0 Register to determine if the Receive Data
Register contains a valid data byte (indicated by a 1). If RDA is set to 1 to indicate
available data, continue to Step 6. If the Receive Data Register is empty (indicated by
a 0), continue to monitor the RDA bit awaiting reception of the valid data.
6. Read data from the UART Receive Data Register. If operating in MULTIPROCES-
SOR (9-bit) Mode, further actions may be required depending on the MULTIPRO-
CESSOR Mode bits MPMD[1:0].
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7. Return to Step 4 to receive additional data.
Receiving Data Using the Interrupt-Driven Method
The UART Receiver interrupt indicates the availability of new data (as well as error condi-
tions). Observe the following steps to configure the UART receiver for interrupt-driven
operation:
1. Write to the UART Baud Rate High and Low Byte registers to set the acceptable baud
rate.
2. Enable the UART pin functions by configuring the associated GPIO port pins for
alternate function operation.
3. Execute a DI instruction to disable interrupts.
4. Write to the Interrupt control registers to enable the UART Receiver interrupt and set
the acceptable priority.
5. Clear the UART Receiver interrupt in the applicable Interrupt Request register.
6. Write to the UART Control 1 Register to enable Multiprocessor (9-bit) Mode func-
tions, if appropriate.
–
–
–
Set the Multiprocessor Mode Select (MPEN) to Enable MULTIPROCESSOR
Mode
Set the Multiprocessor Mode Bits, MPMD[1:0], to select the acceptable address
matching scheme
Configure the UART to interrupt on received data and errors or errors only (inter-
rupt on errors only is unlikely to be useful for Z8 Encore! XP devices without a
DMA block)
7. Write the device address to the Address Compare Register (automatic MULTIPRO-
CESSOR modes only).
8. Write to the UART Control 0 Register to:
–
–
Set the receive enable bit (REN) to enable the UART for data reception
Enable parity, if appropriate and if Multiprocessor Mode is not enabled, and select
either even or odd parity
9. Execute an EI instruction to enable interrupts.
The UART is now configured for interrupt-driven data reception. When the UART
Receiver interrupt is detected, the associated interrupt service routine (ISR) performs the
following:
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1. Checks the UART Status 0 Register to determine the source of the interrupt - error,
break, or received data.
2. Reads the data from the UART Receive Data Register if the interrupt was because of
data available. If operating in MULTIPROCESSOR (9-bit) Mode, further actions may
be required depending on the MULTIPROCESSOR Mode bits MPMD[1:0].
3. Clears the UART Receiver interrupt in the applicable Interrupt Request register.
4. Executes the IRET instruction to return from the interrupt-service routine and await
more data.
Clear To Send (CTS) Operation
The CTS pin, if enabled by the CTSE bit of the UART Control 0 Register, performs flow
control on the outgoing transmit datastream. The Clear To Send (CTS) input pin is sam-
pled one system clock before beginning any new character transmission. To delay trans-
mission of the next data character, an external receiver must deassert CTS at least one
system clock cycle before a new data transmission begins. For multiple character trans-
missions, this action is typically performed during Stop Bit transmission. If CTS deasserts
in the middle of a character transmission, the current character is sent completely.
MULTIPROCESSOR (9-Bit) Mode
The UART has a MULTIPROCESSOR (9-bit) Mode that uses an extra (9th) bit for selec-
tive communication when a number of processors share a common UART bus. In MULTI-
PROCESSOR Mode (also referred to as 9-bit Mode), the multiprocessor bit (MP) is
transmitted immediately following the 8-bits of data and immediately preceding the Stop
bit(s) as displayed in Figure 13. The character format is given below:
Data Field
Stop Bit(s)
Idle State
of Line
lsb
msb
Bit7
1
0
Start
Bit0
Bit1
Bit2
Bit3
Bit4
Bit5
Bit6
MP
1
2
Figure 13. UART Asynchronous MULTIPROCESSOR Mode Data Format
In MULTIPROCESSOR (9-bit) Mode, the parity bit location (9th bit) becomes the Multi-
processor control bit. The UART Control 1 and Status 1 registers provide MULTIPRO-
CESSOR (9-bit) Mode control and status information. If an automatic address matching
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scheme is enabled, the UART Address Compare register holds the network address of the
device.
MULTIPROCESSOR (9-bit) Mode Receive Interrupts
When MULTIPROCESSOR Mode is enabled, the UART only processes frames addressed
to it. The determination of whether a frame of data is addressed to the UART can be made
in hardware, software or some combination of the two, depending on the multiprocessor
configuration bits. In general, the address compare feature reduces the load on the CPU,
because it does not require access to the UART when it receives data directed to other
devices on the multi-node network. The following three MULTIPROCESSOR modes are
available in hardware:
•
•
•
Interrupt on all address bytes
Interrupt on matched address bytes and correctly framed data bytes
Interrupt only on correctly framed data bytes
These modes are selected with MPMD[1:0] in the UART Control 1 Register. For all multi-
processor modes, bit MPEN of the UART Control 1 Register must be set to 1.
The first scheme is enabled by writing 01bto MPMD[1:0]. In this mode, all incoming
address bytes cause an interrupt, while data bytes never cause an interrupt. The interrupt
service routine must manually check the address byte that caused triggered the interrupt. If
it matches the UART address, the software clears MPMD[0]. Each new incoming byte
interrupts the CPU. The software is responsible for determining the end of the frame. It
checks for the end-of-frame by reading the MPRX bit of the UART Status 1 Register for
each incoming byte. If MPRX=1, a new frame has begun. If the address of this new frame
is different from the UART’s address, MPMD[0] must be set to 1 causing the UART inter-
rupts to go inactive until the next address byte. If the new frame’s address matches the
UART’s, the data in the new frame is processed as well.
The second scheme requires the following: set MPMD[1:0] to 10b and write the UART’s
address into the UART Address Compare register. This mode introduces additional hard-
ware control, interrupting only on frames that match the UART’s address. When an
incoming address byte does not match the UART’s address, it is ignored. All successive
data bytes in this frame are also ignored. When a matching address byte occurs, an inter-
rupt is issued and further interrupts now occur on each successive data byte. When the first
data byte in the frame is read, the NEWFRM bit of the UART Status 1 Register is asserted.
All successive data bytes have NEWFRM=0. When the next address byte occurs, the
hardware compares it to the UART’s address. If there is a match, the interrupts continues
and the NEWFRM bit is set for the first byte of the new frame. If there is no match, the
UART ignores all incoming bytes until the next address match.
The third scheme is enabled by setting MPMD[1:0] to 11band by writing the UART’s
address into the UART Address Compare Register. This mode is identical to the second
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scheme, except that there are no interrupts on address bytes. The first data byte of each
frame remains accompanied by a NEWFRM assertion.
External Driver Enable
The UART provides a Driver Enable (DE) signal for off-chip bus transceivers. This fea-
ture reduces the software overhead associated with using a GPIO pin to control the trans-
ceiver when communicating on a multi-transceiver bus, such as RS-485.
Driver Enable is an active High signal that envelopes the entire transmitted data frame
including parity and Stop bits as displayed in Figure 14. The Driver Enable signal asserts
when a byte is written to the UART Transmit Data Register. The Driver Enable signal
asserts at least one UART bit period and no greater than two UART bit periods before the
Start bit is transmitted. This allows a setup time to enable the transceiver. The Driver
Enable signal deasserts one system clock period after the final Stop bit is transmitted. This
one system clock delay allows both time for data to clear the transceiver before disabling
it, as well as the ability to determine if another character follows the current character. In
the event of back to back characters (new data must be written to the Transmit Data Regis-
ter before the previous character is completely transmitted) the DE signal is not deasserted
between characters. The DEPOL bit in the UART Control Register 1 sets the polarity of
the Driver Enable signal.
1
DE
0
Data Field
Stop Bit
Idle State
of Line
lsb
msb
Bit7
1
0
Start
Bit0
Bit1
Bit2
Bit3
Bit4
Bit5
Bit6
Parity
1
Figure 14. UART Driver Enable Signal Timing (shown with 1 Stop Bit and Parity)
The Driver Enable to Start bit setup time is calculated as follows:
UART Interrupts
The UART features separate interrupts for the transmitter and the receiver. In addition,
when the UART primary functionality is disabled, the Baud Rate Generator can also func-
tion as a basic timer with interrupt capability.
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1
2
----------------------------------------
----------------------------------------
DE to Start Bit Setup Time (s)
Baud Rate (Hz)
Baud Rate (Hz)
Transmitter Interrupts
The transmitter generates a single interrupt when the Transmit Data Register Empty bit
(TDRE) is set to 1. This indicates that the transmitter is ready to accept new data for trans-
mission. The TDRE interrupt occurs after the Transmit shift register has shifted the first
bit of data out. The Transmit Data Register can now be written with the next character to
send. This action provides 7 bit periods of latency to load the Transmit Data Register
before the Transmit shift register completes shifting the current character. Writing to the
UART Transmit Data Register clears the TDRE bit to 0.
Receiver Interrupts
The receiver generates an interrupt when any of the following occurs:
•
A data byte is received and is available in the UART Receive Data Register. This inter-
rupt can be disabled independently of the other receiver interrupt sources. The received
data interrupt occurs after the receive character has been received and placed in the Re-
ceive Data Register. To avoid an overrun error, software must respond to this received
data available condition before the next character is completely received.
In MULTIPROCESSOR Mode (MPEN = 1), the receive data interrupts are dependent on
the multiprocessor configuration and the most recent address byte.
Note:
•
•
•
A break is received
An overrun is detected
A data framing error is detected
UART Overrun Errors
When an overrun error condition occurs the UART prevents overwriting of the valid data
currently in the Receive Data Register. The Break Detect and Overrun status bits are not
displayed until after the valid data has been read.
After the valid data has been read, the UART Status 0 Register is updated to indicate the
overrun condition (and Break Detect, if applicable). The RDA bit is set to 1 to indicate that
the Receive Data Register contains a data byte. However, because the overrun error
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occurred, this byte cannot contain valid data and must be ignored. The BRKD bit indicates
if the overrun was caused by a break condition on the line. After reading the status byte
indicating an overrun error, the Receive Data Register must be read again to clear the error
bits is the UART Status 0 Register. Updates to the Receive Data Register occur only when
the next data word is received.
UART Data and Error Handling Procedure
Figure 15 displays the recommended procedure for use in UART receiver interrupt service
routines.
Receiver
Ready
Receiver
Interrupt
Read Status
No
Errors?
Yes
Read Data which
clears RDA bit and
resets error bits
Read Data
Discard Data
Figure 15. UART Receiver Interrupt Service Routine Flow
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Baud Rate Generator Interrupts
If the Baud Rate Generator (BRG) interrupt enable is set, the UART Receiver interrupt
asserts when the UART Baud Rate Generator reloads. This condition allows the Baud
Rate Generator to function as an additional counter if the UART functionality is not
employed.
UART Baud Rate Generator
The UART Baud Rate Generator creates a lower frequency baud rate clock for data trans-
mission. The input to the Baud Rate Generator is the system clock. The UART Baud Rate
High and Low Byte registers combine to create a 16-bit baud rate divisor value
(BRG[15:0]) that sets the data transmission rate (baud rate) of the UART. The UART data
rate is calculated using the following equation:
System Clock Frequency (Hz)
--------------------------------------------------------------------------------
UART Data Rate (bits/s) =
16 UART Baud Rate Divisor Value
When the UART is disabled, the Baud Rate Generator functions as a basic 16-bit timer
with interrupt on time-out. Observe the following steps to configure the Baud Rate Gener-
ator as a timer with interrupt on time-out:
1. Disable the UART by clearing the REN and TEN bits in the UART Control 0 Register
to 0.
2. Load the acceptable 16-bit count value into the UART Baud Rate High and Low Byte
registers.
3. Enable the Baud Rate Generator timer function and associated interrupt by setting the
BIRQ bit in the UART Control 1 Register to 1.
When configured as a general purpose timer, the interrupt interval is calculated using the
following equation:
Interrupt Interval (s) = System Clock Period (s) BRG[15:0]
UART Control Register Definitions
The UART control registers support the UART and the associated infrared encoder/decod-
ers. For more information about the infrared operation, see the Infrared Encoder/Decoder
chapter on page 118.
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UART Transmit Data Register
Data bytes written to the UART Transmit Data Register (Table 64) are shifted out on the
TXDx pin. The Write-only UART Transmit Data Register shares a Register File address
with the read-only UART Receive Data Register.
Table 64. UART Transmit Data Register (U0TXD)
Bit
7
6
5
4
3
2
1
0
TXD
Field
X
X
X
X
X
X
X
X
RESET
R/W
W
W
W
W
W
W
W
W
F40h
Address
Bit
Description
[7:0]
TXD
Transmit Data
UART transmitter data byte to be shifted out through the TXDx pin.
UART Receive Data Register
Data bytes received through the RXDx pin are stored in the UART Receive Data Register
(Table 65). The read-only UART Receive Data Register shares a Register File address
with the Write-only UART Transmit Data Register.
Table 65. UART Receive Data Register (U0RXD)
Bit
7
6
5
4
3
2
1
0
RXD
F40h
Field
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
RESET
R/W
Address
Bit
Description
[7:0]
RXD
Receive Data
UART receiver data byte from the RXDx pin.
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UART Status 0 Register
The UART Status 0 and Status 1 registers (Table 66 and Table 67) identify the current
UART operating configuration and status.
Table 66. UART Status 0 Register (U0STAT0)
Bit
7
6
5
4
3
2
1
0
RDA
PE
OE
FE
BRKD
TDRE
TXE
CTS
Field
0
0
0
0
0
1
1
X
R
RESET
R/W
R
R
R
R
R
R
R
F41h
Address
Bit
Description
[7]
RDA
Receive Data Available
This bit indicates that the UART Receive Data Register has received data. Reading the UART
Receive Data Register clears this bit.
0 = The UART Receive Data Register is empty.
1 = There is a byte in the UART Receive Data Register.
[6]
PE
Parity Error
This bit indicates that a parity error has occurred. Reading the UART Receive Data
register clears this bit.
0 = No parity error has occurred.
1 = A parity error has occurred.
[5]
OE
Overrun Error
This bit indicates that an overrun error has occurred. An overrun occurs when new data is
received and the UART Receive Data Register has not been read. If the RDA bit is reset to 0,
reading the UART Receive Data Register clears this bit.
0 = No overrun error occurred.
1 = An overrun error occurred.
[4]
FE
Framing Error
This bit indicates that a framing error (no Stop bit following data reception) was detected.
Reading the UART Receive Data Register clears this bit.
0 = No framing error occurred.
1 = A framing error occurred.
[3]
BRKD
Break Detect
This bit indicates that a break occurred. If the data bits, parity/multiprocessor bit, and Stop
bit(s) are all 0s this bit is set to 1. Reading the UART Receive Data Register clears this bit.
0 = No break occurred.
1 = A break occurred.
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Bit
Description (Continued)
[2]
TDRE
Transmitter Data Register Empty
This bit indicates that the UART Transmit Data Register is empty and ready for additional data.
Writing to the UART Transmit Data Register resets this bit.
0 = Do not write to the UART Transmit Data Register.
1 = The UART Transmit Data Register is ready to receive an additional byte to be transmitted.
[1]
TXE
Transmitter Empty
This bit indicates that the transmit shift register is empty and character transmission is finished.
0 = Data is currently transmitting.
1 = Transmission is complete.
[0]
CTS
CTS Signal
When this bit is read, it returns the level of the CTS signal. This signal is active Low.
UART Status 1 Register
This register contains multiprocessor control and status bits.
Table 67. UART Status 1 Register (U0STAT1)
Bit
7
6
5
4
3
2
1
0
Reserved
NEWFRM
MPRX
Field
0
0
0
0
0
0
0
0
RESET
R/W
R
R
R
R
R/W
R/W
R
R
F44h
Address
Bit
Description
Reserved
[7:2]
These bits are reserved; R/W bits must be programmed to 000000 during writes and
000000 when read.
[1]
NEWFRM
New Frame
A status bit denoting the start of a new frame. Reading the UART Receive Data Register
resets this bit to 0.
0 = The current byte is not the first data byte of a new frame.
1 = The current byte is the first data byte of a new frame.
[0]
MPRX
Multiprocessor Receive
Returns the value of the most recent multiprocessor bit received. Reading from the UART
Receive Data Register resets this bit to 0.
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UART Control 0 and Control 1 Registers
The UART Control 0 and Control 1 registers (Table 68 and Table 69) configure the
properties of the UART’s transmit and receive operations. The UART Control registers
must not be written while the UART is enabled.
Table 68. UART Control 0 Register (U0CTL0)
Bit
7
6
5
4
3
2
1
0
TEN
REN
CTSE
PEN
PSEL
SBRK
STOP
LBEN
Field
0
0
0
0
0
0
0
0
RESET
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
F42h
Address
Bit
Description
[7]
TEN
Transmit Enable
This bit enables or disables the transmitter. The enable is also controlled by the CTS signal
and the CTSE bit. If the CTS signal is low and the CTSE bit is 1, the transmitter is enabled.
0 = Transmitter disabled.
1 = Transmitter enabled.
[6]
REN
Receive Enable
This bit enables or disables the receiver.
0 = Receiver disabled.
1 = Receiver enabled.
[5]
CTSE
CTSE—CTS Enable
0 = The CTS signal has no effect on the transmitter.
1 = The UART recognizes the CTS signal as an enable control from the transmitter.
[4]
PEN
Parity Enable
This bit enables or disables parity. Even or odd is determined by the PSEL bit.
0 = Parity is disabled.
1 = The transmitter sends data with an additional parity bit and the receiver receives an addi-
tional parity bit .
[3]
PSEL
Parity Select
0 = Even parity is transmitted and expected on all received data.
1 = Odd parity is transmitted and expected on all received data.
[2]
SBRK
Send Break
This bit pauses or breaks data transmission. Sending a break interrupts any transmission in
progress, so ensure that the transmitter has finished sending data before setting this bit.
0 = No break is sent.
1 = Forces a break condition by setting the output of the transmitter to zero.
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Bit
Description (Continued)
[1]
STOP
Stop Bit Select
0 = The transmitter sends one stop bit.
1 = The transmitter sends two stop bits.
[0]
LBEN
Loop Back Enable
0 = Normal operation.
1 = All transmitted data is looped back to the receiver.
Table 69. UART Control 1 Register (U0CTL1)
Bit
7
6
5
4
3
2
1
0
MPMD[1]
MPEN
MPMD[0]
MPBT
DEPOL
BRGCTL RDAIRQ
IREN
Field
0
0
0
0
0
0
0
0
RESET
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
F43h
Address
Bit
Description
MULTIPROCESSOR Mode
[7,5]
MPMD[1:0] If MULTIPROCESSOR (9-bit) Mode is enabled.
00 = The UART generates an interrupt request on all received bytes (data and address).
01 = The UART generates an interrupt request only on received address bytes.
10 = The UART generates an interrupt request when a received address byte matches the
value stored in the Address Compare Register and on all successive data bytes until
an address mismatch occurs.
11 = The UART generates an interrupt request on all received data bytes for which the most
recent address byte matched the value in the Address Compare Register.
[6]
MPEN
MULTIPROCESSOR (9-bit) Enable
This bit is used to enable MULTIPROCESSOR (9-bit) Mode.
0 = Disable MULTIPROCESSOR (9-bit) Mode.
1 = Enable MULTIPROCESSOR (9-bit) Mode.
[4]
MPBT
Multiprocessor Bit Transmit
This bit is applicable only when MULTIPROCESSOR (9-bit) Mode is enabled. The 9th bit is
used by the receiving device to determine if the data byte contains address or data informa-
tion.
0 = Send a 0 in the multiprocessor bit location of the data stream (data byte).
1 = Send a 1 in the multiprocessor bit location of the data stream (address byte).
[3]
DEPOL
Driver Enable Polarity
0 = DE signal is Active High.
1 = DE signal is Active Low.
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Bit
Description (Continued)
Baud Rate Control
[2]
BRGCTL
This bit causes an alternate UART behavior depending on the value of the REN bit in the
UART Control 0 Register.
When the UART receiver is not enabled (REN=0), this bit determines whether the Baud
Rate Generator issues interrupts.
0 = Reads from the Baud Rate High and Low Byte registers return the BRG Reload Value.
1 = The Baud Rate Generator generates a receive interrupt when it counts down to 0.
Reads from the Baud Rate High and Low Byte registers return the current BRG count value.
When the UART receiver is enabled (REN=1), this bit allows reads from the Baud Rate Reg-
isters to return the BRG count value instead of the Reload Value.
0 = Reads from the Baud Rate High and Low Byte registers return the BRG Reload Value.
1 = Reads from the Baud Rate High and Low Byte registers return the current BRG count
value. Unlike the Timers, there is no mechanism to latch the Low Byte when the High
Byte is read.
[1]
RDAIRQ
Receive Data Interrupt Enable
0 = Received data and receiver errors generates an interrupt request to the Interrupt Con-
troller.
1 = Received data does not generate an interrupt request to the Interrupt Controller. Only
receiver errors generate an interrupt request.
[0]
IREN
Infrared Encoder/Decoder Enable
0 = Infrared encoder/decoder is disabled. UART operates normally.
1 = Infrared encoder/decoder is enabled. The UART transmits and receives data through
the infrared encoder/decoder.
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UART Address Compare Register
The UART Address Compare Register stores the multinode network address of the UART.
When the MPMD[1] bit of UART Control Register 0 is set, all incoming address bytes are
compared to the value stored in the Address Compare Register. Receive interrupts and
RDA assertions only occur in the event of a match.
Table 70. UART Address Compare Register (U0ADDR)
Bit
7
6
5
4
3
2
1
0
COMP_ADDR
Field
0
0
0
0
0
0
0
0
RESET
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
F45h
Address
Bit
Description
Compare Address
[7:0]
COMP_ADDR This 8-bit value is compared to incoming address bytes.
UART Baud Rate High and Low Byte Registers
The UART Baud Rate High and Low Byte registers (Table 71 and Table 72) combine to
create a 16-bit baud rate divisor value (BRG[15:0]) that sets the data transmission rate
(baud rate) of the UART.
Table 71. UART Baud Rate High Byte Register (U0BRH)
Bit
7
6
5
4
3
2
1
0
BRH
Field
1
1
1
1
1
1
1
1
RESET
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
F46h
Address
Table 72. UART Baud Rate Low Byte Register (U0BRL)
Bit
7
6
5
4
3
2
1
0
BRL
Field
1
1
1
1
1
1
1
1
RESET
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
F47h
Address
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The UART data rate is calculated using the following equation:
System Clock Frequency (Hz)
--------------------------------------------------------------------------------
UART Baud Rate (bits/s) =
16 UART Baud Rate Divisor Value
For a given UART data rate, calculate the integer baud rate divisor value using the follow-
ing equation:
System Clock Frequency (Hz)
-----------------------------------------------------------------
UART Baud Rate Divisor Value (BRG) = Round
16 UART Data Rate (bits/s)
The baud rate error relative to the acceptable baud rate is calculated using the following
equation:
Actual Data Rate – Desired Data Rate
------------------------------------------------------------------------------------
Desired Data Rate
UART Baud Rate Error (%) = 100
For reliable communication, the UART baud rate error must never exceed five percent.
Table 73 provides information about data rate errors for a 5.5296MHz System Clock.
Table 73. UART Baud Rates
5.5296MHz System Clock
Acceptable Rate
(kHz)
BRG Divisor
(Decimal)
Actual Rate
(kHz)
Error (%)
N/A
1250.0
625.0
250.0
115.2
57.6
N/A
N/A
1
N/A
N/A
N/A
345.6
115.2
57.6
38.4
19.2
9.60
38.24
0.00
3
6
0.00
38.4
9
0.00
19.2
18
36
0.00
9.60
0.00
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Table 73. UART Baud Rates
5.5296MHz System Clock
4.80
2.40
1.20
0.60
0.30
72
144
288
576
1152
4.80
2.40
1.20
0.60
0.30
0.00
0.00
0.00
0.00
0.00
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Infrared Encoder/Decoder
Z8 Encore! XP F0823 Series products contain a fully-functional, high-performance UART
with an infrared encoder/decoder (endec). The infrared endec is integrated with an on-chip
UART to allow easy communication between the Z8 Encore! XP and IrDA Physical Layer
Specification, Version 1.3-compliant infrared transceivers. Infrared communication pro-
vides secure, reliable, low-cost, point-to-point communication between PCs, PDAs, cell
phones, printers and other infrared enabled devices.
Architecture
Figure 16 displays the architecture of the infrared endec.
System
Clock
Infrared
Transceiver
RxD
RXD
TXD
RXD
TXD
Infrared
TxD
Encoder/Decoder
(Endec)
UART
Baud Rate
Clock
Interrupt
I/O
Data
Signal Address
Figure 16. Infrared Data Communication System Block Diagram
Operation
When the infrared endec is enabled, the transmit data from the associated on-chip UART
is encoded as digital signals in accordance with the IrDA standard and output to the infra-
red transceiver through the TXD pin. Similarly, data received from the infrared transceiver
is passed to the infrared endec through the RXD pin, decoded by the infrared endec, and
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Infrared Encoder/Decoder
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Product Specification
119
passed to the UART. Communication is half-duplex, which means simultaneous data
transmission and reception is not allowed.
The baud rate is set by the UART’s baud rate generator and supports IrDA standard baud
rates from 9600 baud to 115.2 kbaud. Higher baud rates are possible, but do not meet IrDA
specifications. The UART must be enabled to use the infrared endec. The infrared endec
data rate is calculated using the following equation:
System Clock Frequency (Hz)
--------------------------------------------------------------------------------
Infrared Data Rate (bits/s) =
16 UART Baud Rate Divisor Value
Transmitting IrDA Data
The data to be transmitted using the infrared transceiver is first sent to the UART. The
UART’s transmit signal (TXD) and baud rate clock are used by the IrDA to generate the
modulation signal (IR_TXD) that drives the infrared transceiver. Each UART/Infrared
data bit is 16 clocks wide. If the data to be transmitted is 1, the IR_TXD signal remains
low for the full 16 clock period. If the data to be transmitted is 0, the transmitter first out-
puts a 7 clock low period, followed by a 3 clock high pulse. Finally, a 6 clock low pulse is
output to complete the full 16 clock data period. Figure 17 displays IrDA data transmis-
sion. When the infrared endec is enabled, the UART’s TXD signal is internal to Z8
Encore! XP F0823 Series products while the IR_TXD signal is output through the TXD
pin.
16 clock
period
Baud Rate
Clock
UART’s
TXD
Start Bit = 0
Data Bit 0 = 1
Data Bit 1 = 0
Data Bit 2 = 1
Data Bit 3 = 1
3 clock
pulse
IR_TXD
7-clock
delay
Figure 17. Infrared Data Transmission
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Receiving IrDA Data
Data received from the infrared transceiver using the IR_RXD signal through the RXD pin
is decoded by the infrared endec and passed to the UART. The UART’s baud rate clock is
used by the infrared endec to generate the demodulated signal (RXD) that drives the
UART. Each UART/Infrared data bit is 16-clocks wide. Figure 18 displays data reception.
When the infrared endec is enabled, the UART’s RXD signal is internal to the Z8 Encore!
XP F0823 Series products while the IR_RXD signal is received through the RXD pin.
16 clock
period
Baud Rate
Clock
Start Bit = 0
Data Bit 0 = 1
Data Bit 1 = 0
Data Bit 2 = 1
Data Bit 3 = 1
IR_RXD
min. 1.4 s
pulse
UART’s
RXD
Start Bit = 0
Data Bit 0 = 1
Data Bit 1 = 0
Data Bit 2 = 1
Data Bit 3 = 1
8 clock
delay
16 clock
period
16 clock
period
16 clock
period
16 clock
period
Figure 18. IrDA Data Reception
Infrared Data Reception
The system clock frequency must be at least 1.0MHz to ensure proper reception of the
1.4µs minimum width pulses allowed by the IrDA standard.
Caution:
Endec Receiver Synchronization
The IrDA receiver uses a local baud rate clock counter (0 to 15 clock periods) to generate
an input stream for the UART and to create a sampling window for detection of incoming
pulses. The generated UART input (UART RXD) is delayed by 8 baud rate clock periods
with respect to the incoming IrDA data stream. When a falling edge in the input data
stream is detected, the endec counter is reset. When the count reaches a value of 8, the
UART RXD value is updated to reflect the value of the decoded data. When the count
reaches 12 baud clock periods, the sampling window for the next incoming pulse opens.
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The window remains open until the count again reaches 8 (that is, 24 baud clock periods
since the previous pulse was detected), giving the endec a sampling window of minus four
baud rate clocks to plus eight baud rate clocks around the expected time of an incoming
pulse. If an incoming pulse is detected inside this window this process is repeated. If the
incoming data is a logical 1 (no pulse), the endec returns to the initial state and waits for
the next falling edge. As each falling edge is detected, the endec clock counter is reset,
resynchronizing the endec to the incoming signal, allowing the endec to tolerate jitter and
baud rate errors in the incoming datastream. Resynchronizing the endec does not alter the
operation of the UART, which ultimately receives the data. The UART is only synchro-
nized to the incoming data stream when a Start bit is received.
Infrared Encoder/Decoder Control Register Definitions
All infrared endec configuration and status information is set by the UART control regis-
ters as defined in the Universal Asynchronous Receiver/Transmitter chapter on page 97.
To prevent spurious signals during IrDA data transmission, set the IREN bit in the UART
Control 1 Register to 1 to enable the endec before enabling the GPIO port alternate func-
tion for the corresponding pin.
Caution:
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Analog-to-Digital Converter
The Analog-to-Digital Converter (ADC) converts an analog input signal to its digital rep-
resentation. The features of this sigma-delta ADC include:
•
•
10-bit resolution
Eight single-ended analog input sources are multiplexed with general-purpose I/O
ports
•
•
•
Interrupt upon conversion complete
Bandgap generated internal voltage reference generator with two selectable levels
Factory offset and gain calibration
Architecture
Figure 19 displays the major functional blocks of the ADC. An analog multiplexer net-
work selects the ADC input from the available analog pins, ANA0 through ANA7.
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2
Internal Voltage
VREFSEL
V
REF
Reference Generator
VREFEXT
Ref Input
11
ADC
Data
Analog Input
Multiplexer
Analog Input
ANA0
ANA1
ANA2
ANA3
ADC
IRQ
ANA4
ANA5
ANA6
ANA7
4
ANAIN
Figure 19. Analog-to-Digital Converter Block Diagram
Operation
The output of the ADC is an 11-bit, signed, two’s-complement digital value. The output
generally ranges from 0 to +1023, but offset errors can cause small negative values.
The ADC registers return 13 bits of data, but the two LSBs are intended for compensation
use only. When the compensation routine is performed on the 13 bit raw ADC value, two
bits of resolution are lost because of a rounding error. As a result, the final value is an 11-
bit number.
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Automatic Powerdown
If the ADC is idle (no conversions in progress) for 160 consecutive system clock cycles,
portions of the ADC are automatically powered down. From this powerdown state, the
ADC requires 40 system clock cycles to powerup. The ADC powers up when a conversion
is requested by the ADC Control Register.
Single-Shot Conversion
When configured for single-shot conversion, the ADC performs a single analog-to-digital
conversion on the selected analog input channel. After completion of the conversion, the
ADC shuts down. Observe the following steps for setting up the ADC and initiating a sin-
gle-shot conversion:
1. Enable the acceptable analog inputs by configuring the general-purpose I/O pins for
alternate function. This configuration disables the digital input and output drivers.
2. Write the ADC Control/Status Register 1 to configure the ADC
–
Write the REFSELH bit of the pair {REFSELH, REFSELL} to select the internal
voltage reference level or to disable the internal reference. The REFSELH bit is
contained in the ADC Control/Status Register 1.
3. Write to the ADC Control Register 0 to configure the ADC and begin the conversion.
The bit fields in the ADC Control Register can be written simultaneously:
–
Write to the ANAIN[3:0] field to select from the available analog input sources
(different input pins available depending on the device).
–
–
Clear CONT to 0 to select a single-shot conversion.
If the internal voltage reference must be output to a pin, set the REFEXT bit to 1.
The internal voltage reference must be enabled in this case.
–
–
Write the REFSELL bit of the pair {REFSELH, REFSELL} to select the internal
voltage reference level or to disable the internal reference. The REFSELL bit is
contained in the ADC Control Register 0.
Set CEN to 1 to start the conversion.
4. CEN remains 1 while the conversion is in progress. A single-shot conversion requires
5129 system clock cycles to complete. If a single-shot conversion is requested from an
ADC powered-down state, the ADC uses 40 additional clock cycles to power-up
before beginning the 5129 cycle conversion.
5. When the conversion is complete, the ADC control logic performs the following oper-
ations:
–
11-bit two’s-complement result written to {ADCD_H[7:0], ADCD_L[7:5]}
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–
CEN resets to 0 to indicate the conversion is complete
6. If the ADC remains idle for 160 consecutive system clock cycles, it is automatically
powered-down.
Continuous Conversion
When configured for continuous conversion, the ADC continuously performs an analog-
to-digital conversion on the selected analog input. Each new data value over-writes the
previous value stored in the ADC Data registers. An interrupt is generated after each con-
version.
In Continuous Mode, ADC updates are limited by the input signal bandwidth of the ADC
and the latency of the ADC and its digital filter. Step changes at the input are not detected
at the next output from the ADC. The response of the ADC (in all modes) is limited by
the input signal bandwidth and the latency.
Caution:
Observe the following steps for setting up the ADC and initiating continuous conversion:
1. Enable the acceptable analog input by configuring the general-purpose I/O pins for
alternate function. This action disables the digital input and output driver.
2. Write the ADC Control/Status Register 1 to configure the ADC:
–
Write the REFSELH bit of the pair {REFSELH, REFSELL} to select the internal
voltage reference level or to disable the internal reference. The REFSELH bit is
contained in the ADC Control/Status Register 1.
3. Write to the ADC Control Register 0 to configure the ADC for continuous conversion.
The bit fields in the ADC Control Register can be written simultaneously:
–
Write to the ANAIN[3:0] field to select from the available analog input sources
(different input pins available depending on the device).
–
–
Set CONT to 1 to select continuous conversion.
If the internal VREF must be output to a pin, set the REFEXT bit to 1. The inter-
nal voltage reference must be enabled in this case.
–
–
Write the REFSELL bit of the pair {REFSELH, REFSELL} to select the internal
voltage reference level or to disable the internal reference. The REFSELL bit is
contained in ADC Control Register 0.
Set CEN to 1 to start the conversions.
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4. When the first conversion in continuous operation is complete (after 5129 system
clock cycles, plus the 40 cycles for power-up, if necessary), the ADC control logic
performs the following operations:
–
CEN resets to 0 to indicate the first conversion is complete. CEN remains 0 for all
subsequent conversions in continuous operation
–
An interrupt request is sent to the Interrupt Controller to indicate the conversion is
complete
5. The ADC writes a new data result every 256 system clock cycles. For each completed
conversion, the ADC control logic performs the following operations:
–
–
Writes the 11-bit two’s complement result to {ADCD_H[7:0], ADCD_L[7:5]}
An interrupt request to the Interrupt Controller denoting conversion complete
6. To disable continuous conversion, clear the CONTbit in the ADC Control Register to 0.
Interrupts
The ADC is able to interrupt the CPU whenever a conversion has been completed and the
ADC is enabled.
When the ADC is disabled, an interrupt is not asserted; however, an interrupt pending
when the ADC is disabled is not cleared.
Calibration and Compensation
Z8 Encore! XP F0823 Series ADC can be factory calibrated for offset error and gain error,
with the compensation data stored in Flash memory. Alternatively, user code can perform
its own calibration, storing the values into Flash themselves.
Factory Calibration
Devices that have been factory calibrated contain nine bytes of calibration data in the
Flash option bit space. This data consists of three bytes for each reference type. For a list
of input modes for which calibration data exists, see the Zilog Calibration Data section on
page 154. There is 1 byte for offset, and there are 2 bytes for gain correction.
User Calibration
If you have precision references available, its own external calibration can be performed,
storing the values into Flash themselves.
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Software Compensation Procedure
The value read from the ADC high and low byte registers are uncompensated. The user
mode software must apply gain and offset correction to this uncompensated value for
maximum accuracy. The following formula yields the compensated value:
1
– OFFCAL GAINCAL 2
ADC
= ADC
– OFFCAL + ADC
comp
uncomp
uncomp
where GAINCAL is the gain calibration byte, OFFCAL is the offset calibration byte and
ADCuncomp is the uncompensated value read from the ADC. The OFFCAL value is in
two’s complement format, as are the compensated and uncompensated ADC values.
The offset compensation is performed first, followed by the gain compensation. One bit of
resolution is lost because of rounding on both the offset and gain computations. As a result
the ADC registers read back 13 bits: 1 sign bit, two calibration bits lost to rounding and 10
data bits. Also note that in the second term, the multiplication must be performed before
the division by 216. Otherwise, the second term evaluates to zero incorrectly.
Note:
Although the ADC can be used without the gain and offset compensation, it does exhibit
non-unity gain. Designing the ADC with sub-unity gain reduces noise across the ADC
range but requires the ADC results to be scaled by a factor of 8/7.
Caution:
ADC Control Register Definitions
The following sections define the ADC Control registers.
ADC Control Register 0
The ADC Control Register selects the analog input channel and initiates the analog-to-dig-
ital conversion.
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Table 74. ADC Control Register 0 (ADCCTL0)
Bit
7
6
5
4
3
2
1
0
CEN
REFSELL REFEXT
CONT
ANAIN[3:0]
Field
0
0
0
0
0
0
0
0
RESET
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
F70h
Address
Bit
Description
[7]
CEN
Conversion Enable
0 = Conversion is complete. Writing a 0 produces no effect. The ADC automatically clears
this bit to 0 when a conversion is complete.
1 = Begin conversion. Writing a 1 to this bit starts a conversion. If a conversion is already in
progress, the conversion restarts. This bit remains 1 until the conversion is complete.
[6]
REFSELL
Voltage Reference Level Select Low Bit
In conjunction with the High bit (REFSELH) in ADC Control/Status Register 1, this deter-
mines the level of the internal voltage reference; the following details the effects of {REF-
SELH, REFSELL}. This reference is independent of the Comparator reference.
00 = Internal Reference Disabled, reference comes from external pin.
01 = Internal Reference set to 1.0V.
10 = Internal Reference set to 2.0V (default).
[5]
REFEXT
External Reference Select
0 = External reference buffer is disabled; V
pin is available for GPIO functions.
REF
1 = The internal ADC reference is buffered and connected to the V
pin.
REF
[4]
CONT
Continuous Conversion
0 = Single-shot conversion. ADC data is output once at completion of the 5129 system clock
cycles.
1 = Continuous conversion. ADC data updated every 256 system clock cycles.
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Z8 Encore! XP® F0823 Series
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129
Bit
Description (Continued)
Analog Input Select
[3:0]
ANAIN
These bits select the analog input for conversion. Not all port pins in this list are available in
all packages for Z8 Encore! XP F0823 Series. For information about the port pins available
with each package style, see the Pin Description section on page 7. Do not enable unavail-
able analog inputs. Usage of these bits changes depending on the buffer mode selected in
ADC Control/Status Register 1.
For the reserved values, all input switches are disabled to avoid leakage or other undesir-
able operation. ADC samples taken with reserved bit settings are undefined.
Single-Ended:
0000 = ANA0.
0001 = ANA1.
0010 = ANA2.
0011 = ANA3.
0100 = ANA4.
0101 = ANA5.
0110 = ANA6.
0111 = ANA7.
1000 = Reserved.
1001 = Reserved.
1010 = Reserved.
1011 = Reserved.
1100 = Reserved.
1101 = Reserved.
1110 = Reserved.
1111 = Reserved.
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ADC Control/Status Register 1
The second ADC Control Register contains the voltage reference level selection bit.
Table 75. ADC Control/Status Register 1 (ADCCTL1)
Bit
7
6
5
4
3
2
1
0
REFSELH
Reserved
Field
1
0
0
0
0
0
0
0
RESET
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
F71h
Address
Bit
Description
[7]
Voltage Reference Level Select High Bit
REFSELH In conjunction with the Low bit (REFSELL) in ADC Control Register 0, this bit determines
the level of the internal voltage reference; the following details the effects of {REFSELH,
REFSELL}; this reference is independent of the Comparator reference.
00 = Internal Reference Disabled, reference comes from external pin.
01 = Internal Reference set to 1.0V.
10 = Internal Reference set to 2.0V (default).
[6:0]
Reserved
These bits are reserved and must be programmed to 0000000.
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ADC Data High Byte Register
The ADC Data High Byte Register contains the upper eight bits of the ADC output. The
output is an 11-bit two’s complement value. During a single-shot conversion, this value is
invalid. Access to the ADC Data High Byte register is read-only. Reading the ADC Data
High Byte Register latches data in the ADC Low Bits Register.
Table 76. ADC Data High Byte Register (ADCD_H)
Bit
7
6
5
4
3
2
1
0
ADCDH
F72h
Field
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
RESET
R/W
Address
Bit
Description
[7:0]
ADC Data High Byte
ADCDH This byte contains the upper eight bits of the ADC output. These bits are not valid during a sin-
gle-shot conversion. During a continuous conversion, the most recent conversion output is
held in this register. These bits are undefined after a Reset.
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Product Specification
132
ADC Data Low Bits Register
The ADC Data Low Byte register contains the lower bits of the ADC output as well as an
overflow status bit. The output is a 11-bit two’s complement value. During a single-shot
conversion, this value is invalid. Access to the ADC Data Low Byte register is read-only.
Reading the ADC Data High Byte register latches data in the ADC Low Bits Register.
Table 77. ADC Data Low Bits Register (ADCD_L)
Bit
7
6
5
4
3
2
1
0
ADCDL
Reserved
OVF
Field
X
R
X
R
X
R
X
R
X
R
X
R
X
R
X
R
RESET
R/W
F73h
Address
Bit
Description
[7:5]
ADC Data Low Bits
ADCDL These bits are the least significant three bits of the 11-bits of the ADC output. These bits are
undefined after a Reset.
[4:1]
Reserved
These bits are reserved and are undefined when read.
[0]
OVF
Overflow Status
0 = An overflow did not occur in the digital filter for the current sample.
1 = An overflow did occur in the digital filter for the current sample.
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Comparator
Z8 Encore! XP F0823 Series devices feature a general purpose comparator that compares
two analog input signals. A GPIO (CINP) pin provides the positive comparator input. The
negative input (CINN) can be taken from either an external GPIO pin or an internal refer-
ence. The output is available as an interrupt source or can be routed to an external pin
using the GPIO multiplex.
The features of the comparator include:
•
•
•
•
Two inputs which can be connected up using the GPIO multiplex (MUX)
One input can be connected to a programmable internal reference
One input can be connected to the on-chip temperature sensor
Output can be either an interrupt source or an output to an external pin
Operation
One of the comparator inputs can be connected to an internal reference which is a user
selectable reference that is user programmable with 200 mV resolution.
The comparator can be powered down to save on supply current. For details, see the Power
Control Register 0 section on page 31.
Because of the propagation delay of the comparator, Zilog does not recommend enabling
or reconfiguring the comparator without first disabling the interrupts and waiting for the
comparator output to settle. Doing so can result in spurious interrupts.
Caution:
The following example shows how to safely enable the comparator:
di
ld cmp0
nop
nop
; wait for output to settle
clr irq0 ; clear any spurious interrupts pending
ei
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Comparator Control Register Definition
The Comparator Control Register (CMPCTL) configures the comparator inputs and sets
the value of the internal voltage reference.
Table 78. Comparator Control Register (CMP0)
Bit
7
6
5
4
3
2
1
0
INPSEL
INNSEL
REFLVL
Reserved
Field
0
0
0
1
0
1
0
0
RESET
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
F90h
Address
Bit
Description
[7]
Signal Select for Positive Input
INPSEL 0 = GPIO pin used as positive comparator input.
1 = temperature sensor used as positive comparator input.
[6]
Signal Select for Negative Input
INNSEL 0 = internal reference disabled, GPIO pin used as negative comparator input.
1 = internal reference enabled as negative comparator input.
[5:2]
Internal Reference Voltage Level
REFLVL 0000 = 0.0V.
0001 = 0.2V.
0010 = 0.4V.
0011 = 0.6V.
0100 = 0.8V.
0101 = 1.0V (Default).
0110 = 1.2V.
0111 = 1.4V.
1000 = 1.6V.
1001 = 1.8V.
1010–1111 = Reserved.
Note: This reference is independent of the ADC voltage reference.
[1:0]
Reserved
These bits are reserved; R/W bits must be programmed to 00 during writes and to 00 when
read.
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Z8 Encore! XP® F0823 Series
Product Specification
135
Flash Memory
The products in Z8 Encore! XP F0823 Series features either 8KB (8192), 4KB (4096),
2KB (2048) or 1KB (1024) of nonvolatile Flash memory with read/write/erase capability.
Flash Memory can be programmed and erased in-circuit by either user code or through the
On-Chip Debugger.
The Flash Memory array is arranged in pages with 512 bytes per page. The 512-byte page
is the minimum Flash block size that can be erased. Each page is divided into 8 rows of 64
bytes.
For program/data protection, the Flash memory is also divided into sectors. In the Z8
Encore! XP F0823 Series, these sectors are either 1024 bytes (in the 8KB devices) or 512
bytes in size (all other memory sizes); each sector maps to a page. Page and sector sizes
are not generally equal.
The first two bytes of the Flash program memory are used as Flash Option bits. For more
information about their operation, see the Flash Option Bits chapter on page 148.
Table 79 describes the Flash memory configuration for each device in the Z8 Encore! XP
F0823 Series. Figure 20 displays the Flash memory arrangement.
Table 79. Z8 Encore! XP F0823 Series Flash Memory Configurations
Program
Flash Size
KB (Bytes)
Memory
Addresses
Flash Sector
Size (bytes)
Part Number
Z8F08x3
Flash Pages
8 (8192)
4 (4096)
2 (2048)
1 (1024)
16
8
0000h–1FFFh
0000h–0FFFh
0000h–07FFh
0000h–03FFh
1024
512
512
512
Z8F04x3
Z8F02x3
4
Z8F01x3
2
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Figure 20. Flash Memory Arrangement
Flash Information Area
The Flash information area is separate from program memory and is mapped to the
address range FE00hto FFFFh. Not all these addresses are accessible. Factory trim values
for the analog peripherals are stored here. Factory calibration data for the ADC is also
stored here.
Operation
The Flash Controller programs and erases Flash memory. The Flash Controller provides
the proper Flash controls and timing for Byte Programming, Page Erase, and Mass Erase
of Flash memory.
The Flash Controller contains several protection mechanisms to prevent accidental program-
ming or erasure. These mechanism operate on the page, sector and full-memory levels.
Figure 21 displays a basic Flash Controller flow. The following subsections provide
details about the various operations (Lock, Unlock, Byte Programming, Page Protect,
Page Unprotect, Page Select Page Erase, and Mass Erase) displayed in Figure 21.
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Reset
Lock State 0
Write Page
Select Register
Write FCTL
No
73h
Yes
Lock State 1
Write FCTL
Writes to Page Select
Register in Lock State 1
result in a return to
Lock State 0
No
8Ch
Yes
Write Page
Select Register
No
Page Select
values match?
Yes
Yes
Page in
Protected Sector?
Byte Program
Write FCTL
No
Page
Yes
Unlocked
95h
No
Page Erase
Program/Erase
Enabled
Figure 21. Flash Controller Operation Flowchart
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Flash Operation Timing Using the Flash Frequency Registers
Before performing either a program or erase operation on Flash memory, you must first
configure the Flash Frequency High and Low Byte registers. The Flash Frequency regis-
ters allow programming and erasing of the Flash with system clock frequencies ranging
from 32kHz (32768Hz) through 20MHz.
The Flash Frequency High and Low Byte registers combine to form a 16-bit value,
FFREQ, to control timing for Flash program and erase operations. The 16-bit binary Flash
Frequency value must contain the system clock frequency (in kHz). This value is calcu-
lated using the following equation:
System Clock Frequency (Hz)
FFREQ[15:0] = -------------------------------------------------------------------------------
1000
Flash programming and erasure are not supported for system clock frequencies below
32kHz (32768 Hz) or above 20MHz. The Flash Frequency High and Low Byte registers
must be loaded with the correct value to ensure operation of Z8 Encore! XP F0823 Series
devices.
Caution:
Flash Code Protection Against External Access
The user code contained within the Flash memory can be protected against external access
with the On-Chip Debugger. Programming the FRP Flash Option Bit prevents reading of
the user code with the On-Chip Debugger. For more information, see the Flash Option Bits
section on page 148 and the On-Chip Debugger chapter on page 158.
Flash Code Protection Against Accidental Program and
Erasure
F0823 Series provides several levels of protection against accidental program and erasure
of the Flash memory contents. This protection is provided by a combination of the Flash
Option bits, the register locking mechanism, the page select redundancy and the sector
level protection control of the Flash Controller.
Flash Code Protection Using the Flash Option Bits
The FRP and FWP Flash Option Bits combine to provide three levels of Flash Program
Memory protection as listed in Table 80. For more information, see the Flash Option Bits
section on page 148.
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.
Table 80. Flash Code Protection Using the Flash Option Bits
FWP Flash Code Protection Description
0
Programming and erasing disabled for all of Flash Program Memory. In user code program-
ming, Page Erase, and Mass Erase are all disabled. Mass Erase is available through the On-
Chip Debugger.
1
Programming, Page Erase, and Mass Erase are enabled for all of Flash Program Memory.
Flash Code Protection Using the Flash Controller
At Reset, the Flash Controller locks to prevent accidental program or erasure of the Flash
memory. To program or erase the Flash memory, first write the Page Select Register with
the target page. Unlock the Flash Controller by making two consecutive writes to the
Flash Control Register with the values 73hand 8Ch, sequentially. The Page Select Regis-
ter must be rewritten with the same page previously stored there. If the two Page Select
writes do not match, the controller reverts to a locked state. If the two writes match, the
selected page becomes active. For more details, see Figure 21.
After unlocking a specific page, you can enable either Page Program or Erase. Writing the
value 95hcauses a Page Erase only if the active page resides in a sector that is not pro-
tected. Any other value written to the Flash Control Register locks the Flash Controller.
Mass Erase is not allowed in the user code but only in through the Debug Port.
After unlocking a specific page, you can also write to any byte on that page. After a byte is
written, the page remains unlocked, allowing for subsequent writes to other bytes on the
same page. Further writes to the Flash Control Register cause the active page to revert to a
locked state.
Sector-Based Flash Protection
The final protection mechanism is implemented on a per-sector basis. The Flash memories
of Z8 Encore! XP devices are divided into maximum number of 8 sectors. A sector is 1/8
of the total Flash memory size unless this value is smaller than the page size – in which
case, the sector and page sizes are equal. On Z8 Encore! F0823 Series devices, the sector
size is varied according to the Flash memory configuration shown in Table 79 on page
135.
The Flash Sector Protect Register can be configured to prevent sectors from being pro-
grammed or erased. After a sector is protected, it cannot be unprotected by user code. The
Flash Sector Protect Register is cleared after reset, and any previously-written protection
values are lost. User code must write this register in their initialization routine if they pre-
fer to enable sector protection.
The Flash Sector Protect Register shares its Register File address with the Page Select
Register. The Flash Sector Protect Register is accessed by writing the Flash Control Regis-
ter with 5Eh. After the Flash Sector Protect Register is selected, it can be accessed at the
Page Select Register address. When user code writes the Flash Sector Protect Register,
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bits can only be set to 1. Thus, sectors can be protected, but not unprotected, via register
write operations. Writing a value other than 5Ehto the Flash Control Register deselects
the Flash Sector Protect Register and reenables access to the Page Select Register.
Observe the following procedure to setup the Flash Sector Protect Register from user
code:
1. Write 00hto the Flash Control Register to reset the Flash Controller.
2. Write 5Ehto the Flash Control Register to select the Flash Sector Protect Register.
3. Read and/or write the Flash Sector Protect Register which is now at Register File
address FF9h.
4. Write 00hto the Flash Control Register to return the Flash Controller to its reset state.
The Sector Protect Register is initialized to 0 on reset, putting each sector into an unpro-
tected state. When a bit in the Sector Protect Register is written to 1, the corresponding
sector can no longer be written or erased by the CPU. External Flash programming
through the OCD or via the Flash Controller Bypass Mode are unaffected. After a bit of
the Sector Protect Register has been set, it cannot be cleared except by powering down the
device.
Byte Programming
The Flash Memory is enabled for byte programming after unlocking the Flash Controller
and successfully enabling either Mass Erase or Page Erase. When the Flash Controller is
unlocked and Mass Erase is successfully completed, all Program Memory locations are
available for byte programming. In contrast, when the Flash Controller is unlocked and
Page Erase is successfully enabled, only the locations of the selected page are available for
byte programming. An erased Flash byte contains all 1’s (FFh). The programming opera-
tion can only be used to change bits from 1 to 0. To change a Flash bit (or multiple bits)
from 0 to 1 requires execution of either the Page Erase or Mass Erase commands.
Byte Programming is accomplished using the On-Chip Debugger's Write Memory com-
mand or eZ8 CPU execution of the LDC or LDCI instructions. For a description of the
LDC and LDCI instructions, refer to the eZ8 CPU Core User Manual (UM0128), available
for download at www.zilog.com. While the Flash Controller programs the Flash memory,
the eZ8 CPU idles but the system clock and on-chip peripherals continue to operate. To
exit programming mode and lock the Flash, write any value to the Flash Control Register,
except the Mass Erase or Page Erase commands.
The byte at each address of the Flash memory cannot be programmed (any bits written
to 0) more than twice before an erase cycle occurs. Doing so may result in corrupted data
at the target byte.
Caution:
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Page Erase
The Flash memory can be erased one page (512 bytes) at a time. Page Erasing the Flash
memory sets all bytes in that page to the value FFh. The Flash Page Select register identi-
fies the page to be erased. Only a page residing in an unprotected sector can be erased.
With the Flash Controller unlocked and the active page set, writing the value 95hto the
Flash Control Register initiates the Page Erase operation. While the Flash Controller exe-
cutes the Page Erase operation, the eZ8 CPU idles but the system clock and on-chip
peripherals continue to operate. The eZ8 CPU resumes operation after the Page Erase
operation completes. If the Page Erase operation is performed using the On-Chip Debug-
ger, poll the Flash Status Register to determine when the Page Erase operation is complete.
When the Page Erase is complete, the Flash Controller returns to its locked state.
Mass Erase
The Flash memory can also be Mass Erased using the Flash Controller, but only by using
the On-Chip Debugger. Mass Erasing the Flash memory sets all bytes to the value FFh.
With the Flash Controller unlocked and the Mass Erase successfully enabled, writing the
value 63hto the Flash Control Register initiates the Mass Erase operation. While the
Flash Controller executes the Mass Erase operation, the eZ8 CPU idles but the system
clock and on-chip peripherals continue to operate. Using the On-Chip Debugger, poll the
Flash Status Register to determine when the Mass Erase operation is complete. When the
Mass Erase is complete, the Flash Controller returns to its locked state.
Flash Controller Bypass
The Flash Controller can be bypassed and the control signals for the Flash memory
brought out to the GPIO pins. Bypassing the Flash Controller allows faster Row Program-
ming algorithms by controlling the Flash programming signals directly.
Row programing is recommended for gang programming applications and large volume
customers who do not require in-circuit initial programming of the Flash memory. Page
Erase operations are also supported when the Flash Controller is bypassed.
For more information about bypassing the Flash Controller, refer to the Zilog application
note titled, Third-Party Flash Programming Support for Z8 Encore! MCUs (AN0117),
available for download at www.zilog.com.
Flash Controller Behavior in Debug Mode
The following changes in behavior of the Flash Controller occur when the Flash Control-
ler is accessed using the On-Chip Debugger:
•
•
The Flash Write Protect option bit is ignored
The Flash Sector Protect register is ignored for programming and erase operations
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•
Programming operations are not limited to the page selected in the Page Select
register
•
•
Bits in the Flash Sector Protect register can be written to one or zero
The second write of the Page Select register to unlock the Flash Controller is not
necessary
•
•
The Page Select register can be written when the Flash Controller is unlocked
The Mass Erase command is enabled through the Flash Control Register
For security reasons, the Flash Controller allows only a single page to be opened for
write/erase. When writing multiple Flash pages, the Flash controller must repeat the un-
lock sequence to select another page.
Caution:
Flash Control Register Definitions
This section defines the features of the following Flash Control registers.
Flash Control Register: see page 142
Flash Status Register: see page 144
Flash Page Select Register: see page 144
Flash Sector Protect Register: see page 146
Flash Frequency High and Low Byte Registers: see page 146
Flash Control Register
The Flash Controller must be unlocked using the Flash Control (FTCTL) Register before
programming or erasing the Flash memory. Writing the sequence 73h8Ch, sequentially,
to the Flash Control Register unlocks the Flash Controller. When the Flash Controller is
unlocked, the Flash memory can be enabled for Mass Erase or Page Erase by writing the
appropriate enable command to the FCTL. Page Erase applies only to the active page
selected in Flash Page Select register. Mass Erase is enabled only through the On-Chip
Debugger. Writing an invalid value or an invalid sequence returns the Flash Controller to
its locked state. The Write-only Flash Control Register shares its Register File address
with the read-only Flash Status Register.
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Table 81. Flash Control Register (FCTL)
Bit
7
6
5
4
3
2
1
0
FCMD
FF8h
Field
0
0
0
0
0
0
0
0
RESET
R/W
W
W
W
W
W
W
W
W
Address
Bit
Description
[7:0]
FCMD
Flash Command
73h = First unlock command.
8Ch = Second unlock command.
95h = Page Erase command (must be third command in sequence to initiate Page Erase).
63h = Mass Erase command (must be third command in sequence to initiate Mass Erase).
5Eh = Enable Flash Sector Protect Register Access.
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Flash Status Register
The Flash Status Register indicates the current state of the Flash Controller. This register
can be read at any time. The read-only Flash Status Register shares its Register File
address with the write-only Flash Control Register.
Table 82. Flash Status Register (FSTAT)
Bit
7
6
5
4
3
2
1
0
Reserved
FSTAT
Field
0
0
0
0
0
0
0
0
RESET
R/W
R
R
R
R
R
R
R
R
FF8h
Address
Bit
Description
Reserved
[7:6]
These bits are reserved and must be programmed to 0 when read.
[5:0]
FSTAT
Flash Controller Status
000000 = Flash Controller locked.
000001 = First unlock command received (73h written).
000010 = Second unlock command received (8Ch written).
000011 = Flash Controller unlocked.
000100 = Sector protect register selected.
001xxx = Program operation in progress.
010xxx = Page erase operation in progress.
100xxx = Mass erase operation in progress.
Flash Page Select Register
The Flash Page Select (FPS) register shares address space with the Flash Sector Protect
Register. Unless the Flash controller is unlocked and written with 5Eh, writes to this
address target the Flash Page Select Register.
The register is used to select one of the eight available Flash memory pages to be pro-
grammed or erased. Each Flash Page contains 512 bytes of Flash memory. During a Page
Erase operation, all Flash memory having addresses with the most significant 7-bits given
by FPS[6:0] are chosen for program/erase operation.
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Table 83. Flash Page Select Register (FPS)
Bit
7
6
5
4
3
2
1
0
INFO_EN
PAGE
Field
0
0
0
0
0
0
0
0
RESET
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FF9h
Address
Bit
Description
[7]
Information Area Enable
INFO_EN 0 = Information Area us not selected.
1 = Information Area is selected. The Information Area is mapped into the Program Memory
address space at addresses FE00h through FFFFh.
[6:0]
PAGE
Page Select
This 7-bit field identifies the Flash memory page for Page Erase and page unlocking.
• Program Memory Address[15:9] = PAGE[6:0].
• For Z8F04x3 devices, the upper 4 bits must always be 0.
• For Z8F02x3 devices, the upper 5 bits must always be 0.
• For Z8F01x3 devices, the upper 6 bits must always be 0.
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Flash Sector Protect Register
The Flash Sector Protect (FPROT) Register is shared with the Flash Page Select Register.
When the Flash Control Register is written with 5Eh, the next write to this address targets
the Flash Sector Protect Register. In all other cases, it targets the Flash Page Select Regis-
ter.
This register selects one of the 8 available Flash memory sectors to be protected. The reset
state of each Sector Protect bit is an unprotected state. After a sector is protected by setting
its corresponding register bit, it cannot be unprotected (the register bit cannot be cleared)
without powering down the device.
Table 84. Flash Sector Protect Register (FPROT)
Bit
7
6
5
4
3
2
1
0
SPROT7 SPROT6 SPROT5 SPROT4 SPROT3 SPROT2 SPROT1 SPROT0
Field
0
0
0
0
0
0
0
0
RESET
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FF9h
Address
Bit
Description
[7]
Sector Protection
SPROTn Each bit corresponds to a 1024-byte Flash sector on devices in the 8K range, while the
remaining devices correspond to a 512-byte Flash sector. To determine the appropriate Flash
memory sector address range and sector number for your Z8F0823 Series product, please
refer to Table 79 on page 135 and to Figure 20, which follows the table.
• For Z8F08x3 and Z8F04x3 devices, all bits are used.
• For Z8F02x3 devices, the upper 4 bits are unused.
• For Z8F01x3 devices, the upper 6 bits are unused.
Note: n indicates the specific Flash sector (7–0).
Flash Frequency High and Low Byte Registers
The Flash Frequency High (FFREQH) and Low Byte (FFREQL) registers combine to
form a 16-bit value, FFREQ, to control timing for Flash program and erase operations.
The 16-bit binary Flash Frequency value must contain the system clock frequency (in
kHz) and is calculated using the following equation:
System Clock Frequency
FFREQ[15:0] = FFREQH[7:0],FFREQL[7:0] = ------------------------------------------------------------------
1000
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The Flash Frequency High and Low Byte registers must be loaded with the correct value
to ensure proper operation of the device. Also, Flash programming and erasure is not sup-
ported for system clock frequencies below 20kHz or above 20MHz.
Caution:
Table 85. Flash Frequency High Byte Register (FFREQH)
Bit
7
6
5
4
3
2
1
0
FFREQH
Field
RESET
R/W
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FFAh
Address
Bit
Description
[7:0]
Flash Frequency High Byte
FFREQH High byte of the 16-bit Flash Frequency value.
Table 86. Flash Frequency Low Byte Register (FFREQL)
Bit
7
6
5
4
3
2
1
0
FFREQL
0
Field
RESET
R/W
R/W
FFBh
Address
Bit
Description
[7:0]
Flash Frequency Low Byte
FFREQL Low byte of the 16-bit Flash Frequency value.
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Flash Option Bits
Programmable Flash option bits allow user configuration of certain aspects of Z8 Encore!
XP F0823 Series operation. The feature configuration data is stored in the Flash program
memory and loaded into holding registers during Reset. The features available for control
through the Flash Option Bits include:
•
•
•
•
Watchdog Timer time-out response selection–interrupt or system reset
Watchdog Timer always on (enabled at Reset)
The ability to prevent unwanted read access to user code in Program Memory
The ability to prevent accidental programming and erasure of all or a portion of the user
code in Program Memory
•
Voltage Brown-Out configuration-always enabled or disabled during Stop Mode to re-
duce Stop Mode power consumption
•
•
•
Factory trimming information for the internal precision oscillator
Factory calibration values for ADC
Factory serialization and randomized lot identifier (optional)
Operation
This section describes the type and configuration of the programmable Flash option bits.
Option Bit Configuration By Reset
Each time the Flash Option Bits are programmed or erased, the device must be Reset for
the change to take effect. During any reset operation (System Reset, Power-On Reset, or
Stop-Mode Recovery), the Flash Option Bits are automatically read from the Flash Pro-
gram Memory and written to Option Configuration registers. The Option Configuration
registers control operation of the devices within the Z8 Encore! XP 8K and 4K Series.
Option bit control is established before the device exits Reset and the eZ8 CPU begins
code execution. The Option Configuration registers are not part of the Register File and
are not accessible for read or write access.
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Option Bit Types
This section describes the five types of Flash option bits offered in the F083A Series.
User Option Bits
The user option bits are contained in the first two bytes of program memory. Access to
these bits has been provided because these locations contain application-specific device
configurations. The information contained here is lost when page 0 in program memory is
erased.
Trim Option Bits
The trim option bits are contained in a Flash memory information page. These bits are fac-
tory programmed values required to optimize the operation of onboard analog circuitry
and cannot be permanently altered. Program memory may be erased without endangering
these values. It is possible to alter working values of these bits by accessing the Trim Bit
Address and Data Registers, but these working values are lost after a power loss or any
other reset event.
There are 32 bytes of trim data. To modify one of these values the user code must first
write a value between 00hand 1Fhinto the Trim Bit Address Register. The next write to
the Trim Bit Data Register changes the working value of the target trim data byte.
Reading the trim data requires the user code to write a value between 00hand 1Fhinto the
Trim Bit Address Register. The next read from the Trim Bit Data Register returns the
working value of the target trim data byte.
Note: The trim address range is from information address 20–3Fonly. The remainder of the
information page is not accessible through the trim bit address and data registers.
Calibration Option Bits
The calibration option bits are also contained in the information page. These bits are fac-
tory programmed values intended for use in software correcting the device’s analog per-
formance. To read these values, the user code must employ the LDC instruction to access
the information area of the address space as defined in the Flash Information Area section
on page 15.
Serialization Bits
As an optional feature, Zilog is able to provide factory-programmed serialization. For seri-
alized products, the individual devices are programmed with unique serial numbers. These
serial numbers are binary values, four bytes in length. The numbers increase in size with
each device, but gaps in the serial sequence may exist.
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These serial numbers are stored in the Flash information page (for more details, see the
Reading the Flash Information Page section on page 150 and the Serialization Data sec-
tion on page 156) and are unaffected by mass erasure of the device’s Flash memory.
Randomized Lot Identification Bits
As an optional feature, Zilog is able to provide a factory-programmed random lot identi-
fier. With this feature, all devices in a given production lot are programmed with the same
random number. This random number is uniquely regenerated for each successive produc-
tion lot and is not likely to be repeated.
The randomized lot identifier is a 32-byte binary value, stored in the flash information
page (for more details, see the Reading the Flash Information Page section on page 150
and the Randomized Lot Identifier section on page 156) and is unaffected by mass erasure
of the device’s flash memory.
Reading the Flash Information Page
The following code example shows how to read data from the Flash Information Area.
; get value at info address 60 (FE60h)
ldx FPS, #%80 ; enable access to flash info page
ld R0, #%FE
ld R1, #%60
ldc R2, @RR0 ; R2 now contains the calibration value
Flash Option Bit Control Register Definitions
This section briefly describes the features of the Trim Bit Address and Data registers.
Trim Bit Address Register
The Trim Bit Address (TRMADR) Register contains the target address for an access to the
trim option bits.
Table 87. Trim Bit Address Register (TRMADR)
Bit
7
6
5
4
3
2
1
0
TRMADR: Trim Bit Address (00h to 1Fh)
Field
0
0
0
0
0
0
0
0
RESET
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FF6h
Address
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Trim Bit Data Register
The Trim Bid Data (TRMDR) register contains the read or write data for access to the trim
option bits.
Table 88. Trim Bit Data Register (TRMDR)
Bit
7
6
5
4
3
2
1
0
TRMDR: Trim Bit Data
Field
0
0
0
0
0
0
0
0
RESET
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
FF7h
Address
Flash Option Bit Address Space
The first two bytes of Flash program memory at addresses 0000hand 0001hare reserved
for the user-programmable Flash option bits.
Table 89. Flash Option Bits at Program Memory Address 0000h
Bit
7
6
5
4
3
2
1
0
WDT_RES WDT_AO
Reserved
VBO_AO
FRP
Reserved
FWP
Field
U
U
U
U
U
U
U
U
RESET
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Program Memory 0000h
Address
Note: U = Unchanged by Reset. R/W = Read/Write.
Bit
Description
[7]
Watchdog Timer Reset
WDT_RES 0 = Watchdog Timer time-out generates an interrupt request. Interrupts must be globally
enabled for the eZ8 CPU to acknowledge the interrupt request.
1 = Watchdog Timer time-out causes a system reset. This setting is the default for unpro-
grammed (erased) Flash.
[6]
WDT_AO
Watchdog Timer Always ON
0 = Watchdog Timer is automatically enabled upon application of system power. Watchdog
Timer can not be disabled.
1 = Watchdog Timer is enabled upon execution of the WDT instruction. Once enabled, the
Watchdog Timer can only be disabled by a Reset or Stop-Mode Recovery. This setting is
the default for unprogrammed (erased) Flash.
[5:4]
Reserved
These bits are reserved and must be programmed to 11 during writes, and to 11 when read.
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Bit
Description (Continued)
[3]
VBO_AO
Voltage Brown-Out Protection Always ON
0 = Voltage Brown-Out Protection can be disabled in Stop Mode to reduce total power con-
sumption. For the block to be disabled, the power control register bit must also be writ-
ten (see the Power Control Register 0 section on page 31).
1 = Voltage Brown-Out Protection is always enabled including during Stop Mode. This set-
ting is the default for unprogrammed (erased) Flash.
[2]
FRP
Flash Read Protect
0 = User program code is inaccessible. Limited control features are available through the
On-Chip Debugger.
1 = User program code is accessible. All On-Chip Debugger commands are enabled. This
setting is the default for unprogrammed (erased) Flash.
[1]
Reserved
This bit is reserved and must be programmed to 1.
[0]
FWP
Flash Write Protect
This Option Bit provides Flash Program Memory protection:
0 = Programming and erasure disabled for all of Flash Program Memory. Programming,
Page Erase, and Mass Erase through User Code is disabled. Mass Erase is available
using the On-Chip Debugger.
1 = Programming, Page Erase, and Mass Erase are enabled for all of Flash program mem-
ory.
Table 90. Flash Options Bits at Program Memory Address 0001h
Bit
7
6
5
4
3
2
1
0
Reserved
XTLDIS
Reserved
Field
U
U
U
U
U
U
U
U
RESET
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Program Memory 0001h
Address
Note: U = Unchanged by Reset. R/W = Read/Write.
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Bit
Description
Reserved
[7:5]
These bits are reserved and must be programmed to 111 during writes and to 111 when read.
[4]
State of Crystal Oscillator at Reset
XTLDIS This bit only enables the crystal oscillator. Its selection as a system clock must be performed
manually.
0 = The crystal oscillator is enabled during reset, resulting in longer reset timing.
1 = The crystal oscillator is disabled during reset, resulting in shorter reset timing.
Caution: Programming the XTLDIS bit to zero on 8-pin versions of F0823 Series devices pre-
vents any further communication via the debug pin due to the X and DBG functions being
IN
shared on pin 2 of the 8-pin package. Do not program this bit to zero on 8-pin devices unless
no further debugging or Flash programming is required.
[3:0]
Reserved
These bits are reserved and must be programmed to 1111 during writes and to 1111 when read.
Trim Bit Address Space
All available trim bit addresses and their functions are listed in Tables 91 through 93.
Table 91. Trim Options Bits at Address 0000h
Bit
7
6
5
4
3
2
1
0
Field
Reserved
RESET
R/W
U
U
U
U
U
U
U
U
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Address
Information Page Memory 0020h
Note: U = Unchanged by Reset. R/W = Read/Write.
Bit
Description
Reserved
[7:0]
These bits are reserved. Altering this register may result in incorrect device operation.
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Table 92. Trim Option Bits at 0001h
Bit
7
6
5
4
3
2
1
0
Reserved
Field
U
U
U
U
U
U
U
U
RESET
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Information Page Memory 0021h
Address
Note: U = Unchanged by Reset. R/W = Read/Write.
Bit
Description
Reserved
[7:0]
These bits are reserved. Altering this register may result in incorrect device operation.
Table 93. Trim Option Bits at 0002h (TIPO)
Bit
7
6
5
4
3
2
1
0
IPO_TRIM
Field
U
RESET
R/W
R/W
Information Page Memory 0022h
Address
Note: U = Unchanged by Reset. R/W = Read/Write.
Bit
Description
[7:0]
Internal Precision Oscillator Trim Byte
IPO_TRIM Contains trimming bits for the Internal Precision Oscillator.
Zilog Calibration Data
This section briefly describes the features of the following Flash Option Bit calibration
registers.
ADC Calibration Data: see page 155
Serialization Data: see page 156
Randomized Lot Identifier: see page 156
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ADC Calibration Data
Table 94. ADC Calibration Bits
Bit
7
6
5
4
3
2
1
0
ADC_CAL
Field
U
U
U
U
U
U
U
U
RESET
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Information Page Memory 0060h–007Dh
Address
Note: U = Unchanged by Reset. R/W = Read/Write.
Bit
Description
[7:0]
Analog-to-Digital Converter Calibration Values
ADC_CAL Contains factory-calibrated values for ADC gain and offset compensation. Each of the ten
supported modes has one byte of offset calibration and two bytes of gain calibration. These
values are read by the software to compensate ADC measurements as detailed in the Soft-
ware Compensation Procedure section on page 127. The location of each calibration byte is
provided in Table 95.
Table 95. ADC Calibration Data Location
Info Page
Address
Memory
Address
Compensation
Usage
Reference
Type
ADC Mode
60
08
09
63
0A
0B
66
0C
0D
FE60
FE08
FE09
FE63
FE0A
FE0B
FE66
FE0C
FE0D
Offset
Single-Ended Unbuffered
Single-Ended Unbuffered
Single-Ended Unbuffered
Single-Ended Unbuffered
Single-Ended Unbuffered
Single-Ended Unbuffered
Single-Ended Unbuffered
Single-Ended Unbuffered
Single-Ended Unbuffered
Internal 2.0V
Internal 2.0V
Internal 2.0V
Internal 1.0V
Internal 1.0V
Internal 1.0V
External 2.0V
External 2.0V
External 2.0V
Gain High Byte
Gain Low Byte
Offset
Gain High Byte
Gain Low Byte
Offset
Gain High Byte
Gain Low Byte
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Serialization Data
Table 96. Serial Number at 001C–001F (S_NUM)
Bit
7
6
5
4
3
2
1
0
S_NUM
Field
U
U
U
U
U
U
U
U
RESET
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Information Page Memory 001C–001F
Address
Note: U = Unchanged by Reset. R/W = Read/Write.
Bit
Description
[7:0]
Serial Number Byte
S_NUM The serial number is a unique four-byte binary value; see Table 97.
Table 97. Serialization Data Locations
Info Page
Address
Memory
Address
Usage
1C
1D
1E
1F
FE1C
FE1D
FE1E
FE1F
Serial Number Byte 3 (most significant).
Serial Number Byte 2.
Serial Number Byte 1.
Serial Number Byte 0 (least significant).
Randomized Lot Identifier
Table 98. Lot Identification Number (RAND_LOT)
Bit
7
6
5
4
3
2
1
0
RAND_LOT
Field
U
U
U
U
U
U
U
U
RESET
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Interspersed throughout Information Page Memory
Address
Note: U = Unchanged by Reset. R/W = Read/Write.
Bit
Description
[7]
Randomized Lot ID
RAND_LOT The randomized lot ID is a 32-byte binary value that changes for each production lot; see
Table 99.
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Table 99. Randomized Lot ID Locations
Memory
Info Page
Address
Address
FE3C
FE3D
FE3E
FE3F
FE58
FE59
FE5A
FE5B
FE5C
FE5D
FE5E
FE5F
FE61
FE62
FE64
FE65
FE67
FE68
FE6A
FE6B
FE6D
FE6E
FE70
FE71
FE73
FE74
FE76
FE77
FE79
FE7A
FE7C
FE7D
Usage
3C
3D
3E
3F
58
59
5A
5B
5C
5D
5E
5F
61
62
64
65
67
68
6A
6B
6D
6E
70
71
73
74
76
77
79
7A
7C
7D
Randomized Lot ID Byte 31 (most significant)
Randomized Lot ID Byte 30
Randomized Lot ID Byte 29
Randomized Lot ID Byte 28
Randomized Lot ID Byte 27
Randomized Lot ID Byte 26
Randomized Lot ID Byte 25
Randomized Lot ID Byte 24
Randomized Lot ID Byte 23
Randomized Lot ID Byte 22
Randomized Lot ID Byte 21
Randomized Lot ID Byte 20
Randomized Lot ID Byte 19
Randomized Lot ID Byte 18
Randomized Lot ID Byte 17
Randomized Lot ID Byte 16
Randomized Lot ID Byte 15
Randomized Lot ID Byte 14
Randomized Lot ID Byte 13
Randomized Lot ID Byte 12
Randomized Lot ID Byte 11
Randomized Lot ID Byte 10
Randomized Lot ID Byte 9
Randomized Lot ID Byte 8
Randomized Lot ID Byte 7
Randomized Lot ID Byte 6
Randomized Lot ID Byte 5
Randomized Lot ID Byte 4
Randomized Lot ID Byte 3
Randomized Lot ID Byte 2
Randomized Lot ID Byte 1
Randomized Lot ID Byte 0 (least significant)
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On-Chip Debugger
Z8 Encore! XP F0823 Series devices contain an integrated On-Chip Debugger (OCD)
which provides advanced debugging features that include:
•
•
•
•
•
•
Single pin interface
Reading and writing of the register file
Reading and writing of program and data memory
Setting of breakpoints and watchpoints
Executing eZ8 CPU instructions
Debug pin sharing with general-purpose input-output function to maximize the pins
available
Architecture
The on-chip debugger consists of four primary functional blocks: transmitter, receiver,
auto-baud detector/generator, and debug controller. Figure 22 displays the architecture of
the OCD.
System Clock
Auto-Baud
Detector/Generator
Transmitter
Receiver
Debug Controller
DBG Pin
Figure 22. On-Chip Debugger Block Diagram
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Operation
The following section describes the operation of the OCD.
OCD Interface
The OCD uses the DBG pin for communication with an external host. This one-pin inter-
face is a bidirectional open-drain interface that transmits and receives data. Data transmis-
sion is half-duplex, in that transmit and receive cannot occur simultaneously. The serial
data on the DBG pin is sent using the standard asynchronous data format defined in RS-
232. This pin creates an interface from the F0823 Series products to the serial port of a
host PC using minimal external hardware.Two different methods for connecting the DBG
pin to an RS-232 interface are displayed in Figure 23 and Figure 24. The recommended
method is the buffered implementation depicted in Figure 24. The DBG pin has a internal
pull-up resistor which is sufficient for some applications (for more details about the pull-
up current, see the Electrical Characteristics chapter on page 198). For OCD operation at
higher data rates or in noisy systems, Zilog recommends an external pull-up resistor.
For operation of the OCD, all power pins (VDD and AVDD) must be supplied with power,
and all ground pins (VSS and AVSS) must be properly grounded. The DBG pin is open-
drain and may require an external pull-up resistor to ensure proper operation.
Caution:
VDD
RS-232
Transceiver
10 k
Schottky
Diode
RS-232 TX
RS-232 RX
DBG Pin
Figure 23. Interfacing the On-Chip Debugger’s DBG Pin with an RS-232 Interface, # 1 of 2
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VDD
RS-232
Transceiver
10 k
Open-Drain
Buffer
RS-232 TX
RS-232 RX
DBG Pin
Figure 24. Interfacing the On-Chip Debugger’s DBG Pin with an RS-232 Interface, # 2 of 2
Debug Mode
The operating characteristics of the devices in Debug Mode are:
•
The eZ8 CPU fetch unit stops, idling the eZ8 CPU, unless directed by the OCD to ex-
ecute specific instructions
•
•
•
•
The system clock operates unless in Stop Mode
All enabled on-chip peripherals operate unless in Stop Mode
Automatically exits Halt Mode
Constantly refreshes the Watchdog Timer, if enabled.
Entering Debug Mode
The device enters Debug Mode following the operations below:
•
The device enters Debug Mode after the eZ8 CPU executes a BRK (breakpoint) in-
struction
•
If the DBG pin is held Low during the most recent clock cycle of System Reset, the part
enters Debug Mode upon exiting System Reset
Note: Holding the DBG pin Low for an additional 5000 (minimum) clock cycles after reset
(making sure to account for any specified frequency error if using an internal oscillator)
prevents a false interpretation of an autobaud sequence (see the OCD Autobaud Detector/
Generator section on page 161).
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•
If the PA2/RESET pin is held Low while a 32-bit key sequence is issued to the PA0/
DBG pin, the DBG feature is unlocked. After releasing PA2/RESET, it is pulled high.
At this point, the PA0/DBG pin can be used to autobaud and cause the device to enter
Debug Mode. For more details, see the OCD Unlock Sequence (8-Pin Devices Only)
section on page 163.
Exiting Debug Mode
The device exits Debug Mode following any of these operations:
•
•
•
•
•
•
Clearing the DBGMODE bit in the OCD Control Register to 0
Power-On Reset
Voltage Brown-Out reset
Watchdog Timer reset
Asserting the RESET pin Low to initiate a Reset
Driving the DBG pin Low while the device is in Stop Mode initiates a system reset
OCD Data Format
The OCD interface uses the asynchronous data format defined for RS-232. Each character
is transmitted as 1 Start bit, 8 data bits (least-significant bit first), and 1 Stop bit as dis-
played in Figure 25.
START
D0
D1
D2
D3
D4
D5
D6
D7
Stop
Figure 25. OCD Data Format
Note: When responding to a request for data, the OCD may commence transmitting immediately
after receiving the stop bit of an incoming frame. Therefore, when sending the stop bit, the
host must not actively drive the DBG pin High for more than 0.5 bit times. Zilog recom-
mends that, if possible, the host drives the DBG pin using an open-drain output.
OCD Autobaud Detector/Generator
To run over a range of baud rates (data bits per second) with various system clock frequen-
cies, the OCD contains an auto-baud detector/generator. After a reset, the OCD is idle
until it receives data. The OCD requires that the first character sent from the host is the
character 80h. The character 80hhas eight continuous bits Low (one Start bit plus 7 data
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bits), framed between High bits. The auto-baud detector measures this period and sets the
OCD baud rate generator accordingly.
The auto-baud detector/generator is clocked by the system clock. The minimum baud rate
is the system clock frequency divided by 512. For optimal operation with asynchronous
datastreams, the maximum recommended baud rate is the system clock frequency divided
by eight. The maximum possible baud rate for asynchronous datastreams is the system
clock frequency divided by four, but this theoretical maximum is possible only for low
noise designs with clean signals. Table 100 lists minimum and recommended maximum
baud rates for sample crystal frequencies.
Table 100. OCD Baud-Rate Limits
Recommended
Maximum Baud Rate
(kbps)
Recommended
Standard PC Baud
Rate (bps)
System Clock
Frequency (MHz)
Minimum Baud Rate
(kbps)
5.5296
1382.4
4.096
691,200
2400
1.08
0.032768 (32kHz)
0.064
If the OCD receives a Serial Break (nine or more continuous bits Low) the auto-baud
detector/generator resets. Reconfigure the auto-baud detector/generator by sending 80h.
OCD Serial Errors
The OCD detects any of the following error conditions on the DBG pin:
•
•
•
Serial Break (a minimum of nine continuous bits Low)
Framing Error (received Stop bit is Low)
Transmit Collision (OCD and host simultaneous transmission detected by the OCD)
When the OCD detects one of these errors, it aborts any command currently in progress,
transmits a four character long Serial Break back to the host, and resets the auto-baud
detector/generator. A Framing Error or Transmit Collision may be caused by the host
sending a Serial Break to the OCD. Because of the open-drain nature of the interface,
returning a Serial Break break back to the host only extends the length of the Serial Break
if the host releases the Serial Break early.
The host transmits a Serial Break on the DBG pin when first connecting to the F0823
Series devices or when recovering from an error. A Serial Break from the host resets the
auto-baud generator/detector but does not reset the OCD Control Register. A Serial Break
leaves the device in Debug Mode if that is the current mode. The OCD is held in Reset
until the end of the Serial Break when the DBG pin returns High. Because of the open-
drain nature of the DBG pin, the host sends a Serial Break to the OCD even if the OCD is
transmitting a character.
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OCD Unlock Sequence (8-Pin Devices Only)
Because of pin-sharing on the 8-pin device, an unlock sequence must be performed to
access the DBG pin. If this sequence is not completed during a system reset, then the PA0/
DBG pin functions only as a GPIO pin.
The following sequence unlocks the DBG pin:
1. Hold PA2/RESET Low.
2. Wait 5 ms for the internal reset sequence to complete.
3. Send the following bytes serially to the debug pin:
DBG← 80h (autobaud)
DBG← EBh
DBG←5Ah
DBG←70h
DBG←CDh (32-bit unlock key)
4. Release PA2/RESET. The PA0/DBG pin is now identical in function to that of the
DBG pin on the 20- or 28-pin device. To enter Debug Mode, reautobaud and write
80hto the OCD Control Register (see the On-Chip Debugger Commands section on
page 164).
Breakpoints
Execution breakpoints are generated using the BRK instruction (opcode 00h). When the
eZ8 CPU decodes a BRK instruction, it signals the OCD. If breakpoints are enabled, the
OCD enters Debug Mode and idles the eZ8 CPU. If breakpoints are not enabled, the OCD
ignores the BRK signal and the BRK instruction operates as an NOP instruction.
Breakpoints in Flash Memory
The BRK instruction is opcode 00h, which corresponds to the fully programmed state of a
byte in Flash memory. To implement a breakpoint, write 00hto the required break
address, overwriting the current instruction. To remove a breakpoint, the corresponding
page of Flash memory must be erased and reprogrammed with the original data.
Runtime Counter
The OCD contains a 16-bit Runtime Counter. It counts system clock cycles between
breakpoints. The counter starts counting when the OCD leaves Debug Mode and stops
counting when it enters Debug Mode again or when it reaches the maximum count of
FFFFh.
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On-Chip Debugger Commands
The host communicates to the OCD by sending OCD commands using the DBG interface.
During normal operation, only a subset of the OCD commands are available. In Debug
Mode, all OCD commands become available unless the user code and control registers are
protected by programming the Flash Read Protect Option bit (FRP). The Flash Read Pro-
tect Option bit prevents the code in memory from being read out of Z8 Encore! XP F0823
Series products. When this option is enabled, several of the OCD commands are disabled.
Table 101 is a summary of the OCD commands. Each OCD command is described in fur-
ther detail in the pages that follow this table. Table 102 on page 169 also indicates those
commands that operate when the device is not in Debug Mode (normal operation) and
those commands that are disabled by programming the Flash Read Protect Option bit.
Table 101. OCD Commands
Command Enabled when not Disabled by Flash Read Protect
Debug Command
Byte
00h
01h
02h
03h
04h
05h
06h
07h
08h
in Debug Mode? Option Bit
Read OCD Revision
Reserved
Yes
–
–
–
Read OCD Status Register
Read Runtime Counter
Write OCD Control Register
Read OCD Control Register
Write Program Counter
Read Program Counter
Write Register
Yes
–
–
–
Yes
Yes
–
Cannot clear DBGMODE bit.
–
Disabled.
Disabled.
–
–
Only writes of the Flash Memory Con-
trol registers are allowed. Additionally,
only the Mass Erase command is
allowed to be written to the Flash Con-
trol Register.
Read Register
09h
0Ah
–
–
–
–
–
–
–
–
–
–
–
Disabled.
Disabled.
Disabled.
Yes.
Write Program Memory
Read Program Memory
Write Data Memory
Read Data Memory
Read Program Memory CRC
Reserved
0Bh
0Ch
0Dh
–
0Eh
–
0Fh
–
Step Instruction
10h
Disabled.
Disabled.
Disabled.
–
Stuff Instruction
11h
Execute Instruction
Reserved
12h
13h–FFh
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In the following list of OCD Commands, data and commands sent from the host to the
OCD are identified by ’DBG ← Command/Data’. Data sent from the OCD back to the
host is identified by ’DBG → Data’.
Read OCD Revision (00h). The Read OCD Revision command determines the version of
the OCD. If OCD commands are added, removed, or changed, this revision number
changes.
DBG ← 00h
DBG → OCDRev[15:8] (Major revision number)
DBG → OCDRev[7:0] (Minor revision number)
Read OCD Status Register (02h). The Read OCD Status Register command reads the
OCDSTAT Register.
DBG ← 02h
DBG → OCDSTAT[7:0]
Read Runtime Counter (03h). The Runtime Counter counts system clock cycles in
between breakpoints. The 16-bit Runtime Counter counts up from 0000hand stops at the
maximum count of FFFFh. The Runtime Counter is overwritten during the Write Memory,
Read Memory, Write Register, Read Register, Read Memory CRC, Step Instruction, Stuff
Instruction, and Execute Instruction commands.
DBG ← 03h
DBG → RuntimeCounter[15:8]
DBG → RuntimeCounter[7:0]
Write OCD Control Register (04h). The Write OCD Control Register command writes
the data that follows to the OCDCTL register. When the Flash Read Protect Option Bit is
enabled, the DBGMODE bit (OCDCTL[7]) can only be set to 1, it cannot be cleared to 0
and the only method of returning the device to normal operating mode is to reset the
device.
DBG ← 04h
DBG ← OCDCTL[7:0]
Read OCD Control Register (05h). The Read OCD Control Register command reads the
value of the OCDCTL register.
DBG ← 05h
DBG → OCDCTL[7:0]
Write Program Counter (06h). The Write Program Counter command writes the data that
follows to the eZ8 CPU’s Program Counter (PC). If the device is not in Debug Mode or if
the Flash Read Protect Option bit is enabled, the Program Counter (PC) values are dis-
carded.
DBG ← 06h
DBG ← ProgramCounter[15:8]
DBG ← ProgramCounter[7:0]
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Read Program Counter (07h). The Read Program Counter command reads the value in
the eZ8 CPU’s Program Counter (PC). If the device is not in Debug Mode or if the Flash
Read Protect Option bit is enabled, this command returns FFFFh.
DBG ← 07h
DBG → ProgramCounter[15:8]
DBG → ProgramCounter[7:0]
Write Register (08h). The Write Register command writes data to the Register File. Data
can be written 1–256 bytes at a time (256 bytes can be written by setting size to 0). If the
device is not in Debug Mode, the address and data values are discarded. If the Flash Read
Protect Option bit is enabled, only writes to the Flash Control Registers are allowed and
all other register write data values are discarded.
DBG ← 08h
DBG ← {4’h0,Register Address[11:8]}
DBG ← Register Address[7:0]
DBG ← Size[7:0]
DBG ← 1–256 data bytes
Read Register (09h). The Read Register command reads data from the Register File.
Data can be read 1–256 bytes at a time (256 bytes can be read by setting size to 0). If the
device is not in Debug Mode or if the Flash Read Protect Option bit is enabled, this com-
mand returns FFhfor all the data values.
DBG ← 09h
DBG ← {4’h0,Register Address[11:8]
DBG ← Register Address[7:0]
DBG ← Size[7:0]
DBG → 1–256 data bytes
Write Program Memory (0Ah). The Write Program Memory command writes data to
Program Memory. This command is equivalent to the LDC and LDCI instructions. Data
can be written 1–65536 bytes at a time (65536 bytes can be written by setting size to 0).
The on-chip Flash Controller must be written to and unlocked for the programming opera-
tion to occur. If the Flash Controller is not unlocked, the data is discarded. If the device is
not in Debug Mode or if the Flash Read Protect Option bit is enabled, the data is dis-
carded.
DBG ← 0Ah
DBG ← Program Memory Address[15:8]
DBG ← Program Memory Address[7:0]
DBG ← Size[15:8]
DBG ← Size[7:0]
DBG ← 1–65536 data bytes
Read Program Memory (0Bh). The Read Program Memory command reads data from
Program Memory. This command is equivalent to the LDC and LDCI instructions. Data
can be read 1–65536 bytes at a time (65536 bytes can be read by setting size to 0). If the
device is not in Debug Mode or if the Flash Read Protect Option Bit is enabled, this com-
mand returns FFhfor the data.
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DBG ← 0Bh
DBG ← Program Memory Address[15:8]
DBG ← Program Memory Address[7:0]
DBG ← Size[15:8]
DBG ← Size[7:0]
DBG → 1–65536 data bytes
Write Data Memory (0Ch). The Write Data Memory command writes data to Data Mem-
ory. This command is equivalent to the LDE and LDEI instructions. Data can be written
1–65536 bytes at a time (65536 bytes can be written by setting size to 0). If the device is
not in Debug Mode or if the Flash Read Protect Option Bit is enabled, the data is dis-
carded.
DBG ← 0Ch
DBG ← Data Memory Address[15:8]
DBG ← Data Memory Address[7:0]
DBG ← Size[15:8]
DBG ← Size[7:0]
DBG ← 1–65536 data bytes
Read Data Memory (0Dh). The Read Data Memory command reads from Data Memory.
This command is equivalent to the LDE and LDEI instructions. Data can be read 1 to
65536 bytes at a time (65536 bytes can be read by setting size to 0). If the device is not in
Debug Mode, this command returns FFhfor the data.
DBG ← 0Dh
DBG ← Data Memory Address[15:8]
DBG ← Data Memory Address[7:0]
DBG ← Size[15:8]
DBG ← Size[7:0]
DBG → 1–65536 data bytes
Read Program Memory CRC (0Eh). The Read Program Memory Cyclic Redundancy
Check (CRC) command computes and returns the CRC of Program Memory using the 16-
bit CRC-CCITT polynomial. If the device is not in Debug Mode, this command returns
FFFFhfor the CRC value. Unlike most other OCD Read commands, there is a delay from
issuing of the command until the OCD returns the data. The OCD reads the Program
Memory, calculates the CRC value, and returns the result. The delay is a function of the
Program Memory size and is approximately equal to the system clock period multiplied by
the number of bytes in the Program Memory.
DBG ← 0Eh
DBG → CRC[15:8]
DBG → CRC[7:0]
Step Instruction (10h). The Step Instruction steps one assembly instruction at the current
Program Counter (PC) location. If the device is not in Debug Mode or the Flash Read Pro-
tect Option bit is enabled, the OCD ignores this command.
DBG ← 10h
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Stuff Instruction (11h). The Stuff command steps one assembly instruction and allows
specification of the first byte of the instruction. The remaining 0–4 bytes of the instruction
are read from Program Memory. This command is useful for stepping over instructions
where the first byte of the instruction has been overwritten by a Breakpoint. If the device
is not in Debug Mode or the Flash Read Protect Option bit is enabled, the OCD ignores
this command.
DBG ← 11h
DBG ← opcode[7:0]
Execute Instruction (12h). The Execute command allows sending an entire instruction to
be executed to the eZ8 CPU. This command can also step over breakpoints. The number
of bytes to send for the instruction depends on the opcode. If the device is not in Debug
Mode or the Flash Read Protect Option bit is enabled, this command reads and discards
one byte.
DBG ← 12h
DBG ← 1–5 byte opcode
On-Chip Debugger Control Register Definitions
This section describes the features of the On-Chip Debugger Control and Status registers.
OCD Control Register
The OCD Control Register controls the state of the OCD. This register is used to enter or
exit Debug Mode and to enable the BRK instruction. It also resets Z8 Encore! XP F0823
Series device.
A reset and stop function can be achieved by writing 81hto this register. A reset and go
function can be achieved by writing 41hto this register. If the device is in Debug Mode, a
run function can be implemented by writing 40hto this register.
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Table 102. OCD Control Register (OCDCTL)
Bit
7
6
5
4
3
2
1
0
DBGMODE BRKEN DBGACK
Reserved
RST
Field
RESET
R/W
0
0
0
0
0
0
0
0
R/W
R/W
R/W
R
R
R
R
R/W
Bit
Description
Debug Mode
[7]
DBGMODE The device enters Debug Mode when this bit is 1. When in Debug Mode, the eZ8 CPU stops
fetching new instructions. Clearing this bit causes the eZ8 CPU to restart. This bit is auto-
matically set when a BRK instruction is decoded and breakpoints are enabled. If the Flash
Read Protect Option Bit is enabled, this bit can only be cleared by resetting the device. It
cannot be written to 0.
0 = F0823 Series device is operating in Normal Mode.
1 = F0823 Series device is in Debug Mode.
[6]
BRKEN
Breakpoint Enable
This bit controls the behavior of the BRK instruction (opcode 00h). By default, breakpoints
are disabled and the BRK instruction behaves similar to an NOP instruction. If this bit is 1,
when a BRK instruction is decoded, the DBGMODE bit of the OCDCTL register is automati-
cally set to 1.
0 = Breakpoints are disabled.
1 = Breakpoints are enabled.
[5]
DBGACK
Debug Acknowledge
This bit enables the debug acknowledge feature. If this bit is set to 1, the OCD sends a
Debug Acknowledge character (FFh) to the host when a Breakpoint occurs.
0 = Debug Acknowledge is disabled.
1 = Debug Acknowledge is enabled.
[4:1]
Reserved
These bits are reserved and must be 00000 when read.
[0]
RST
Reset
Setting this bit to 1 resets the Z8F04xA family device. The device goes through a normal
Power-On Reset sequence with the exception that the OCD is not reset. This bit is automat-
ically cleared to 0 at the end of reset.
0 = No effect.
1 = Reset the Flash Read Protect Option Bit device.
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OCD Status Register
The OCD Status Register reports status information about the current state of the debugger
and the system.
Table 103. OCD Status Register (OCDSTAT)
Bit
7
6
5
4
3
2
1
0
DBG
HALT
FRPENB
Reserved
Field
RESET
R/W
0
0
0
0
0
0
0
0
R
R
R
R
R
R
R
R
Bit
Description
[7]
DBG
Debug Status
0 = Normal Mode.
1 = Debug Mode.
[6]
HALT
Halt Mode
0 = Not in Halt Mode.
1 = In Halt Mode.
[5]
Flash Read Protect Option Bit Enable
FRPENB 0 = FRP bit enabled to allow disabling of many OCD commands.
1 = FRP bit has no effect.
[4:0]
Reserved
These bits are reserved and must be 00000 when read.
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Oscillator Control
Z8 Encore! XP F0823 Series devices uses three possible clocking schemes, each user-
selectable. These three schemes are:
•
•
•
On-chip precision trimmed RC oscillator
External clock drive
On-chip low power Watchdog Timer oscillator
In addition, F0823 Series devices contain clock failure detection and recovery circuitry,
which allow continued operation despite a failure of the primary oscillator.
Operation
This chapter discusses the logic used to select the system clock and handle primary oscil-
lator failures. A description of the specific operation of each oscillator is outlined else-
where in this document.
System Clock Selection
The oscillator control block selects from the available clocks. Table 104 details each clock
source and its usage.
Table 104. Oscillator Configuration and Selection
Clock Source
Characteristics
Required Setup
Internal Precision
RC Oscillator
• 32.8kHz or 5.53MHz
• ± 4% accuracy when trimmed
• No external components required
• Unlock and write Oscillator Control
Register (OSCCTL) to enable and
select oscillator at either 5.53MHz or
32.8kHz
External Clock
Drive
• 0 to 20MHz
• Accuracy dependent on external clock
source
• Write GPIO registers to configure PB3
pin for external clock function
• Unlock and write OSCCTL to select
external system clock
• Apply external clock signal to GPIO
Internal Watchdog • 10kHz nominal
• Enable WDT if not enabled and wait
until WDT Oscillator is operating.
• Unlock and write Oscillator Control
Register (OSCCTL) to enable and
select oscillator
Timer Oscillator
• ± 40% accuracy; no external compo-
nents required
• Very Low power consumption
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Unintentional accesses to the Oscillator Control Register can actually stop the chip by
switching to a non-functioning oscillator. To prevent this condition, the oscillator control
block employs a register unlocking/locking scheme.
Caution:
OSC Control Register Unlocking/Locking
To write to the Oscillator Control Register, unlock it by making two writes to the OSC-
CTL Register with the values E7hfollowed by 18h. A third write to the OSCCTL Regis-
ter changes the value of the actual register and returns the register to a locked state. Any
other sequence of Oscillator Control Register writes has no effect. The values written to
unlock the register must be ordered correctly, but are not necessarily consecutive. It is pos-
sible to write to or read from other registers within the unlocking/locking operation.
When selecting a new clock source, the primary oscillator failure detection circuitry and
the Watchdog Timer oscillator failure circuitry must be disabled. If POFEN and WOFEN
are not disabled prior to a clock switch-over, it is possible to generate an interrupt for a
failure of either oscillator. The Failure detection circuitry can be enabled anytime after a
successful write of OSCSEL in the Oscillator Control Register.
The internal precision oscillator is enabled by default. If the user code changes to a differ-
ent oscillator, it is appropriate to disable the IPO for power savings. Disabling the IPO
does not occur automatically.
Clock Failure Detection and Recovery
Should an oscillator or timer fail, there are methods of recovery, as this section describes.
Primary Oscillator Failure
Z8 Encore! XP F0823 Series devices can generate non-maskable interrupt-like events
when the primary oscillator fails. To maintain system function in this situation, the clock
failure recovery circuitry automatically forces the Watchdog Timer oscillator to drive the
system clock. The Watchdog Timer oscillator must be enabled to allow the recovery.
Although this oscillator runs at a much slower speed than the original system clock, the
CPU continues to operate, allowing execution of a clock failure vector and software rou-
tines that either remedy the oscillator failure or issue a failure alert. This automatic switch-
over is not available if the Watchdog Timer is the primary oscillator. It is also unavailable
if the Watchdog Timer oscillator is disabled, though it is not necessary to enable the
Watchdog Timer reset function outlined in the the Watchdog Timer section on page 91.
The primary oscillator failure detection circuitry asserts if the system clock frequency
drops below 1kHz ±50%. If an external signal is selected as the system oscillator, it is pos-
sible that a very slow but non-failing clock can generate a failure condition. Under these
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conditions, do not enable the clock failure circuitry (POFEN must be deasserted in the
OSCCTL Register).
Watchdog Timer Failure
In the event of a Watchdog Timer oscillator failure, a similar non-maskable interrupt-like
event is issued. This event does not trigger an attendant clock switch-over, but alerts the
CPU of the failure. After a Watchdog Timer failure, it is no longer possible to detect a pri-
mary oscillator failure. The failure detection circuitry does not function if the Watchdog
Timer is used as the primary oscillator or if the Watchdog Timer oscillator has been dis-
abled. For either of these cases, it is necessary to disable the detection circuitry by deas-
serting the WDFEN bit of the OSCCTL Register.
The Watchdog Timer oscillator failure detection circuit counts system clocks while
searching for a Watchdog Timer clock. The logic counts 8004 system clock cycles before
determining that a failure has occurred. The system clock rate determines the speed at
which the Watchdog Timer failure can be detected. A very slow system clock results in
very slow detection times.
It is possible to disable the clock failure detection circuitry as well as all functioning
clock sources. In this case, the Z8 Encore! XP F0823 Series device ceases functioning
and can only be recovered by Power-On Reset.
Caution:
Oscillator Control Register Definitions
The following section provides the bit definitions for the Oscillator Control Register.
Oscillator Control Register
The Oscillator Control Register (OSCCTL) enables/disables the various oscillator circuits,
enables/disables the failure detection/recovery circuitry and selects the primary oscillator,
which becomes the system clock.
The Oscillator Control Register must be unlocked before writing. Writing the two step
sequence E7hfollowed by 18hto the Oscillator Control Register unlocks it. The register
is locked at successful completion of a register write to the OSCCTL.
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Table 105. Oscillator Control Register (OSCCTL)
Bit
7
6
5
4
3
2
1
0
INTEN
Reserved WDTEN
POFEN
WDFEN
SCKSEL
Field
1
0
1
0
0
0
0
0
RESET
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
F86h
Address
Bit
Description
[7]
INTEN
Internal Precision Oscillator Enable
1 = Internal precision oscillator is enabled.
0 = Internal precision oscillator is disabled.
[6]
Reserved
This bit is reserved and must be programmed to 0 during writes and to 0 when read.
[5]
Watchdog Timer Oscillator Enable
WDTEN 1 = Watchdog Timer oscillator is enabled.
0 = Watchdog Timer oscillator is disabled.
[4]
Primary Oscillator Failure Detection Enable
POFEN 1 = Failure detection and recovery of primary oscillator is enabled.
0 = Failure detection and recovery of primary oscillator is disabled.
[3]
Watchdog Timer Oscillator Failure Detection Enable
WDFEN 1 = Failure detection of Watchdog Timer oscillator is enabled.
0 = Failure detection of Watchdog Timer oscillator is disabled.
[2:0]
System Clock Oscillator Select
SCKSEL 000 = Internal precision oscillator functions as system clock at 5.53MHz.
001 = Internal precision oscillator functions as system clock at 32kHz.
010 = Reserved.
011 = Watchdog Timer oscillator functions as system clock.
100 = External clock signal on PB3 functions as system clock.
101 = Reserved.
110 = Reserved.
111 = Reserved.
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Internal Precision Oscillator
The internal precision oscillator (IPO) is designed for use without external components.
You can either manually trim the oscillator for a non-standard frequency or use the auto-
matic factory-trimmed version to achieve a 5.53MHz frequency. The features of IPO
include:
•
•
•
•
On-chip RC oscillator that does not require external components
Output frequency of either 5.53MHz or 32.8kHz (contains both a fast and a slow mode)
Trimming possible through Flash option bits with user override
Elimination of crystals or ceramic resonators in applications where high timing accu-
racy is not required
Operation
An 8-bit trimming register, incorporated into the design, compensates for absolute varia-
tion of oscillator frequency. Once trimmed the oscillator frequency is stable and does not
require subsequent calibration. Trimming is performed during manufacturing and is not
necessary for you to repeat unless a frequency other than 5.53MHz (fast mode) or
32.8kHz (slow mode) is required. This trimming is done at +30°C and a supply voltage of
3.3 V, so accuracy of this operating point is optimal.
Power down this block for minimum system power. By default, the oscillator is configured
through the Flash Option bits. However, the user code can override these trim values, as
described in the Trim Bit Address Space section on page 153.
Select one of the two frequencies for the oscillator: 5.53MHz and 32.8kHz, using the
OSCSEL bits in the Oscillator Control chapter on page 171.
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eZ8 CPU Instruction Set
This chapter describes the following features of the eZ8 CPU instruction set:
Assembly Language Programming Introduction: see page 176
Assembly Language Syntax: see page 177
eZ8 CPU Instruction Notation: see page 178
eZ8 CPU Instruction Classes: see page 180
eZ8 CPU Instruction Summary: see page 184
Assembly Language Programming Introduction
The eZ8 CPU assembly language provides a means for writing an application program
without concern for actual memory addresses or machine instruction formats. A program
written in assembly language is called a source program. Assembly language allows the
use of symbolic addresses to identify memory locations. It also allows mnemonic codes
(opcodes and operands) to represent the instructions themselves. The opcodes identify the
instruction while the operands represent memory locations, registers, or immediate data
values.
Each assembly language program consists of a series of symbolic commands called state-
ments. Each statement can contain labels, operations, operands, and comments.
Labels are assigned to a particular instruction step in a source program. The label identi-
fies that step in the program as an entry point for use by other instructions.
The assembly language also includes assembler directives that supplement the machine
instruction. The assembler directives, or pseudo-ops, are not translated into a machine
instruction. Rather, the pseudo-ops are interpreted as directives that control or assist the
assembly process.
The source program is processed (assembled) by the assembler to obtain a machine lan-
guage program called the object code. The object code is executed by the eZ8 CPU. An
example segment of an assembly language program is detailed in the following example.
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Assembly Language Source Program Example
; Everything after the semicolon is a comment.
JP START
START:
; A label called ‘START’. The first instruction (JP START) in this
; example causes program execution to jump to the point within the
; program where the START label occurs.
LD R4, R7
; A Load (LD) instruction with two operands. The first operand,
; Working Register R4, is the destination. The second operand,
; Working Register R7, is the source. The contents of R7 is
; written into R4.
LD 234h, #%01
; Another Load (LD) instruction with two operands.
; The first operand, Extended Mode Register Address 234h,
; identifies the destination. The second operand, Immediate Data
; value 01h, is the source. The value 01his written into the
; Register at address 234h.
Assembly Language Syntax
For proper instruction execution, eZ8 CPU assembly language syntax requires that the
operands be written as ‘destination, source’. After assembly, the object code usually has
the operands in the order ‘source, destination’, but ordering is opcode-dependent. The fol-
lowing instruction examples illustrate the format of some basic assembly instructions and
the resulting object code produced by the assembler. You must follow this binary format if
you prefer manual program coding or intend to implement your own assembler.
Example 1
If the contents of registers 43hand 08hare added and the result is stored in 43h, the
assembly syntax and resulting object code is shown in Table 106.
Table 106. Assembly Language Syntax Example 1
Assembly Language Code
Object Code
ADD
04
43h,
08
08h
43
(ADD dst, src)
(OPC src, dst)
Example 2
In general, when an instruction format requires an 8-bit register address, that address can
specify any register location in the range 0–255 or, using Escaped Mode Addressing, a
Working Register R0–R15. If the contents of Register 43hand Working Register R8 are
added and the result is stored in 43h, the assembly syntax and resulting object code is
shown in Table 107.
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Table 107. Assembly Language Syntax Example 2
Assembly Language Code
Object Code
ADD
04
43h,
E8
R8
43
(ADD dst, src)
(OPC src, dst)
See the device-specific Z8 Encore! XP Product Specification to determine the exact regis-
ter file range available. The register file size varies, depending on the device type.
eZ8 CPU Instruction Notation
In the eZ8 CPU Instruction Summary and Description sections, the operands, condition
codes, status flags, and address modes are represented by a notational shorthand that is
noted in Table 108.
Table 108. Notational Shorthand
Notation Description
Operand Range
b
Bit
b
b represents a value from 0 to 7 (000B to 111B).
cc
Condition Code
—
See the Condition Codes overview in the eZ8 CPU
Core User Manual (UM0128).
DA
ER
Direct Address
Addrs
Addrs represents a number in the range of 0000h
to FFFFh.
Extended Addressing Register Reg
Reg represents a number in the range of 000h to
FFFh.
IM
Ir
Immediate Data
#Data
Data is a number between 00h to FFh.
n = 0–15.
Indirect Working Register
Indirect Register
@Rn
IR
@Reg
Reg. represents a number in the range of 00h to
FFh.
Irr
Indirect Working Register Pair @RRp
p = 0, 2, 4, 6, 8, 10, 12, or 14.
IRR
Indirect Register Pair
@Reg
Reg represents an even number in the range 00h
to FEh.
p
Polarity
p
Polarity is a single bit binary value of either 0B or
1B.
r
Working Register
Register
Rn
n = 0–15.
R
Reg
Reg. represents a number in the range of 00h to
FFh.
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Table 108. Notational Shorthand (Continued)
Operand Range
Notation Description
RA
Relative Address
X
X represents an index in the range of +127 to –128
which is an offset relative to the address of the
next instruction
rr
Working Register Pair
Register Pair
RRp
Reg
p = 0, 2, 4, 6, 8, 10, 12, or 14.
RR
Reg. represents an even number in the range of
00h to FEh.
Vector
X
Vector Address
Indexed
Vector
#Index
Vector represents a number in the range of 00h to
FFh.
The register or register pair to be indexed is offset
by the signed Index value (#Index) in a +127 to
–128 range.
Table 109 lists additional symbols that are used throughout the Instruction Summary and
Instruction Set Description sections.
Table 109. Additional Symbols
Symbol
dst
src
@
Definition
Destination Operand
Source Operand
Indirect Address Prefix
Stack Pointer
SP
PC
FLAGS
RP
#
Program Counter
Flags Register
Register Pointer
Immediate Operand Prefix
Binary Number Suffix
Hexadecimal Number Prefix
Hexadecimal Number Suffix
B
%
H
Assignment of a value is indicated by an arrow, as shown in the following example.
dst ← dst + src
This example indicates that the source data is added to the destination data; the result is
stored in the destination location.
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eZ8 CPU Instruction Classes
eZ8 CPU instructions are divided functionally into the following groups:
•
•
•
•
•
•
•
•
Arithmetic
Bit Manipulation
Block Transfer
CPU Control
Load
Logical
Program Control
Rotate and Shift
Tables 110 through 117 contain the instructions belonging to each group and the number
of operands required for each instruction. Some instructions appear in more than one table
as these instruction can be considered as a subset of more than one category. Within these
tables, the source operand is identified as ‘src’, the destination operand is ‘dst’ and a con-
dition code is ‘cc’.
Table 110. Arithmetic Instructions
Mnemonic
ADC
Operands
dst, src
dst, src
dst, src
dst, src
dst, src
dst, src
dst, src
dst, src
dst
Instruction
Add with Carry
ADCX
ADD
Add with Carry using Extended Addressing
Add
ADDX
CP
Add using Extended Addressing
Compare
CPC
Compare with Carry
Compare with Carry using Extended Addressing
Compare using Extended Addressing
Decimal Adjust
CPCX
CPX
DA
DEC
dst
Decrement
DECW
INC
dst
Decrement Word
dst
Increment
INCW
dst
Increment Word
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Table 110. Arithmetic Instructions (Continued)
Mnemonic
MULT
SBC
Operands
dst
Instruction
Multiply
dst, src
dst, src
dst, src
dst, src
Subtract with Carry
SBCX
SUB
Subtract with Carry using Extended Addressing
Subtract
SUBX
Subtract using Extended Addressing
Table 111. Bit Manipulation Instructions
Mnemonic
BCLR
BIT
Operands
bit, dst
p, bit, dst
bit, dst
dst
Instruction
Bit Clear
Bit Set or Clear
Bit Set
BSET
BSWAP
CCF
Bit Swap
—
Complement Carry Flag
Reset Carry Flag
Set Carry Flag
Test Complement Under Mask
RCF
—
SCF
—
TCM
dst, src
dst, src
TCMX
Test Complement Under Mask using Extended
Addressing
TM
dst, src
dst, src
Test Under Mask
TMX
Test Under Mask using Extended Addressing
Table 112. Block Transfer Instructions
Mnemonic
Operands
Instruction
LDCI
dst, src
Load Constant to/from Program Memory and Auto-
Increment Addresses
LDEI
dst, src
Load External Data to/from Data Memory and Auto-
Increment Addresses
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Table 113. CPU Control Instructions
Mnemonic
ATM
CCF
DI
Operands
Instruction
—
—
—
—
—
—
—
—
src
—
—
Atomic Execution
Complement Carry Flag
Disable Interrupts
Enable Interrupts
HALT Mode
EI
HALT
NOP
RCF
SCF
No Operation
Reset Carry Flag
Set Carry Flag
SRP
STOP
WDT
Set Register Pointer
Stop Mode
Watchdog Timer Refresh
Table 114. Load Instructions
Mnemonic
CLR
Operands
dst
Instruction
Clear
LD
dst, src
dst, src
dst, src
Load
LDC
Load Constant to/from Program Memory
LDCI
Load Constant to/from Program Memory and Auto-
Increment Addresses
LDE
dst, src
dst, src
Load External Data to/from Data Memory
LDEI
Load External Data to/from Data Memory and Auto-
Increment Addresses
LDWX
LDX
dst, src
dst, src
dst, X(src)
dst
Load Word using Extended Addressing
Load using Extended Addressing
Load Effective Address
Pop
LEA
POP
POPX
PUSH
PUSHX
dst
Pop using Extended Addressing
Push
src
src
Push using Extended Addressing
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Table 115. Logical Instructions
Mnemonic
AND
Operands
dst, src
dst, src
dst
Instruction
Logical AND
ANDX
COM
Logical AND using Extended Addressing
Complement
OR
dst, src
dst, src
dst, src
dst, src
Logical OR
ORX
Logical OR using Extended Addressing
Logical Exclusive OR
XOR
XORX
Logical Exclusive OR using Extended Addressing
Table 116. Program Control Instructions
Mnemonic
BRK
Operands
Instruction
—
On-Chip Debugger Break
BTJ
p, bit, src, DA Bit Test and Jump
BTJNZ
BTJZ
CALL
DJNZ
IRET
JP
bit, src, DA
Bit Test and Jump if Non-Zero
bit, src, DA
Bit Test and Jump if Zero
Call Procedure
dst
dst, src, RA
Decrement and Jump Non-Zero
Interrupt Return
Jump
—
dst
dst
DA
DA
—
JP cc
JR
Jump Conditional
Jump Relative
JR cc
RET
Jump Relative Conditional
Return
TRAP
vector
Software Trap
Table 117. Rotate and Shift Instructions
Mnemonic
BSWAP
RL
Operands
Instruction
dst
dst
dst
Bit Swap
Rotate Left
RLC
Rotate Left through Carry
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Table 117. Rotate and Shift Instructions (Continued)
Mnemonic
RR
Operands
Instruction
dst
dst
dst
dst
dst
Rotate Right
RRC
Rotate Right through Carry
Shift Right Arithmetic
Shift Right Logical
Swap Nibbles
SRA
SRL
SWAP
eZ8 CPU Instruction Summary
Table 118 summarizes the eZ8 CPU instruction set. The table identifies the addressing
modes employed by the instruction, the effect upon the Flags Register, the number of CPU
clock cycles required for the instruction fetch, and the number of CPU clock cycles
required for the instruction execution.
.
Table 118. eZ8 CPU Instruction Summary
Address
Mode
Symbolic Operation dst src
Flags
C Z S V D H Cycles Cycles
Assembly
Mnemonic
Opcode(s)
(Hex)
Fetch Instr.
ADC dst, src
dst ← dst + src + C
r
r
r
12
13
14
15
16
17
18
19
*
*
*
*
0
*
2
2
3
3
3
3
4
4
3
4
3
4
3
4
3
3
Ir
R
R
R
IR
IM
IM
ER
IM
R
IR
ER
ER
ADCX dst, src
dst ← dst + src + C
*
*
*
*
0
*
Note: Flags Notation:
* = Value is a function of the result of the operation.
– = Unaffected.
X = Undefined.
0 = Reset to 0.
1 = Set to 1.
PS024317-0914
P R E L I M I N A R Y
eZ8 CPU Instruction Summary
Z8 Encore! XP® F0823 Series
Product Specification
185
Table 118. eZ8 CPU Instruction Summary (Continued)
Address
Mode
Flags
C Z S V D H Cycles Cycles
Assembly
Mnemonic
Opcode(s)
(Hex)
Fetch Instr.
Symbolic Operation dst
src
ADD dst, src
dst ← dst + src
r
r
r
02
03
04
05
06
07
08
09
52
53
54
55
56
57
58
59
2F
*
*
*
*
0
*
2
2
3
3
3
3
4
4
2
2
3
3
3
3
4
4
1
3
4
3
4
3
4
3
3
3
4
3
4
3
4
3
3
2
Ir
R
R
R
IR
IM
IM
ER
IM
r
R
IR
ER
ER
r
ADDX dst, src
AND dst, src
dst ← dst + src
*
*
*
*
*
*
0
–
*
dst ← dst AND src
–
0
–
r
Ir
R
R
R
IR
IM
IM
ER
IM
R
IR
ER
ER
ANDX dst, src
ATM
dst ← dst AND src
–
–
*
*
0
–
–
–
–
–
Block all interrupt and
DMA requests during
execution of the next
3 instructions
–
–
BCLR bit, dst
BIT p, bit, dst
BRK
dst[bit] ← 0
r
r
E2
E2
00
E2
D5
F6
F7
–
–
–
–
X
–
–
–
–
–
*
–
–
–
–
*
–
0
–
0
0
–
–
–
–
–
–
–
–
–
–
–
–
–
2
2
1
2
2
3
3
2
2
1
2
2
3
4
dst[bit] ← p
Debugger Break
dst[bit] ← 1
BSET bit, dst
BSWAP dst
r
dst[7:0] dst[0:7]
R
BTJ p, bit, src, if src[bit] = p
dst
r
–
–
PC ← PC + X
Ir
Note: Flags Notation:
* = Value is a function of the result of the operation.
– = Unaffected.
X = Undefined.
0 = Reset to 0.
1 = Set to 1.
PS024317-0914
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eZ8 CPU Instruction Summary
Z8 Encore! XP® F0823 Series
Product Specification
186
Table 118. eZ8 CPU Instruction Summary (Continued)
Address
Mode
Flags
C Z S V D H Cycles Cycles
Assembly
Mnemonic
Opcode(s)
(Hex)
Fetch Instr.
Symbolic Operation dst
src
BTJNZ bit, src, if src[bit] = 1
r
Ir
r
F6
F7
F6
F7
D4
D6
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
3
3
3
3
2
3
3
4
3
4
6
3
dst
PC ← PC + X
BTJZ bit, src,
dst
if src[bit] = 0
PC ← PC + X
Ir
CALL dst
SP ← SP –2
@SP ← PC
PC ← dst
IRR
DA
CCF
C ← ~C
EF
B0
*
–
–
–
–
–
–
– –-
1
2
2
2
2
2
2
3
3
3
3
3
3
4
4
4
4
5
5
4
4
2
2
3
2
3
3
4
3
4
3
4
3
4
3
4
3
4
3
3
3
3
CLR dst
dst ← 00h
R
IR
R
–
–
–
–
–
–
–
B1
COM dst
dst ← ~dst
60
–
*
*
*
*
*
0
*
IR
r
61
CP dst, src
dst - src
r
A2
r
Ir
A3
R
R
A4
R
IR
IM
IM
r
A5
R
A6
IR
r
A7
CPC dst, src
dst - src - C
1F A2
1F A3
1F A4
1F A5
1F A6
1F A7
1F A8
1F A9
A8
*
*
*
*
–
–
r
Ir
R
R
R
IR
IM
IM
ER
IM
ER
IM
R
IR
ER
ER
ER
ER
CPCX dst, src
CPX dst, src
dst - src - C
dst - src
*
*
*
*
*
*
*
*
–
–
–
–
A9
Note: Flags Notation:
* = Value is a function of the result of the operation.
– = Unaffected.
X = Undefined.
0 = Reset to 0.
1 = Set to 1.
PS024317-0914
P R E L I M I N A R Y
eZ8 CPU Instruction Summary
Z8 Encore! XP® F0823 Series
Product Specification
187
Table 118. eZ8 CPU Instruction Summary (Continued)
Address
Mode
Flags
C Z S V D H Cycles Cycles
Assembly
Mnemonic
Opcode(s)
(Hex)
Fetch Instr.
Symbolic Operation dst
src
DA dst
dst ← DA(dst)
dst ← dst - 1
dst ← dst - 1
IRQCTL[7] 0
R
IR
40
41
*
*
*
*
*
*
*
X
–
–
–
–
–
–
2
2
2
2
2
2
1
2
2
3
2
3
5
6
2
3
DEC dst
DECW dst
R
30
–
–
*
IR
31
RR
IRR
80
*
81
DI
8F
–
–
–
–
–
–
–
–
–
–
–
–
DJNZ dst, RA
dst dst – 1
if dst 0
r
0A–FA
PC PC + X
EI
IRQCTL[7] 1
HALT Mode
9F
7F
–
–
–
–
–
*
–
–
*
–
–
–
–
–
–
–
–
–
1
1
2
2
1
2
2
1
2
2
2
3
2
5
6
5
HALT
INC dst
dst dst + 1
R
IR
20
21
r
0E-FE
A0
INCW dst
IRET
dst dst + 1
RR
IRR
–
*
*
*
*
*
*
*
–
*
–
*
A1
FLAGS @SP
SP SP + 1
PC @SP
BF
SP SP + 2
IRQCTL[7] 1
JP dst
PC dst
DA
IRR
DA
8D
C4
–
–
–
–
–
–
–
–
–
–
–
–
3
2
3
2
3
2
JP cc, dst
if cc is true
PC dst
0D-FD
JR dst
PC PC + X
DA
DA
8B
–
–
–
–
–
–
–
–
–
–
–
–
2
2
2
2
JR cc, dst
if cc is true
0B-FB
PC PC + X
Note: Flags Notation:
* = Value is a function of the result of the operation.
– = Unaffected.
X = Undefined.
0 = Reset to 0.
1 = Set to 1.
PS024317-0914
P R E L I M I N A R Y
eZ8 CPU Instruction Summary
Z8 Encore! XP® F0823 Series
Product Specification
188
Table 118. eZ8 CPU Instruction Summary (Continued)
Address
Mode
Flags
C Z S V D H Cycles Cycles
Assembly
Mnemonic
Opcode(s)
(Hex)
Fetch Instr.
Symbolic Operation dst
src
IM
LD dst, rc
dst src
r
r
0C-FC
C7
D7
E3
–
–
–
–
–
–
2
3
3
2
3
3
3
3
2
3
2
2
2
2
2
2
3
4
3
2
4
2
3
3
3
5
9
5
9
9
X(r)
r
X(r)
r
Ir
R
R
R
IR
Ir
R
E4
IR
IM
IM
r
E5
E6
E7
F3
IR
r
R
F5
LDC dst, src
LDCI dst, src
dst src
Irr
Irr
r
C2
C5
D2
C3
D3
–
–
–
–
–
–
–
–
–
–
–
–
Ir
Irr
Ir
dst src
r r + 1
rr rr + 1
Irr
Ir
Irr
LDE dst, src
LDEI dst, src
dst src
r
Irr
r
82
92
83
93
–
–
–
–
–
–
–
–
–
–
–
–
2
2
2
2
5
5
9
9
Irr
Ir
dst src
r r + 1
rr rr + 1
Irr
Ir
Irr
LDWX dst, src dst src
ER
ER
1FE8
–
–
–
–
–
–
5
4
Note: Flags Notation:
* = Value is a function of the result of the operation.
– = Unaffected.
X = Undefined.
0 = Reset to 0.
1 = Set to 1.
PS024317-0914
P R E L I M I N A R Y
eZ8 CPU Instruction Summary
Z8 Encore! XP® F0823 Series
Product Specification
189
Table 118. eZ8 CPU Instruction Summary (Continued)
Address
Mode
Flags
C Z S V D H Cycles Cycles
Assembly
Mnemonic
Opcode(s)
(Hex)
Fetch Instr.
Symbolic Operation dst
src
ER
LDX dst, src
dst src
r
Ir
84
85
86
87
88
89
94
95
96
97
E8
E9
98
99
F4
–
–
–
–
–
–
3
3
3
3
3
3
3
3
3
3
4
4
3
3
2
2
3
4
5
4
4
2
3
4
5
2
2
3
5
8
ER
IRR
IRR
X(rr)
r
R
IR
r
X(rr)
ER
ER
IRR
IRR
ER
ER
r
r
Ir
R
IR
ER
IM
LEA dst, X(src) dst src + X
X(r)
X(rr)
–
–
–
–
–
–
–
–
–
–
–
–
rr
MULT dst
dst[15:0]
RR
dst[15:8] * dst[7:0]
NOP
No operation
0F
42
43
44
45
46
47
48
49
50
51
–
–
–
*
–
*
–
0
–
–
–
–
1
2
2
3
3
3
3
4
4
2
2
2
3
4
3
4
3
4
3
3
2
3
OR dst, src
dst dst OR src
r
r
r
Ir
R
R
R
IR
IM
IM
ER
IM
R
IR
ER
ER
R
ORX dst, src
POP dst
dst dst OR src
–
–
*
*
0
–
–
–
–
–
dst @SP
SP SP + 1
–
–
IR
Note: Flags Notation:
* = Value is a function of the result of the operation.
– = Unaffected.
X = Undefined.
0 = Reset to 0.
1 = Set to 1.
PS024317-0914
P R E L I M I N A R Y
eZ8 CPU Instruction Summary
Z8 Encore! XP® F0823 Series
Product Specification
190
Table 118. eZ8 CPU Instruction Summary (Continued)
Address
Mode
Flags
C Z S V D H Cycles Cycles
Assembly
Mnemonic
Opcode(s)
(Hex)
Fetch Instr.
Symbolic Operation dst
src
POPX dst
PUSH src
dst @SP
SP SP + 1
ER
D8
–
–
–
–
–
–
3
2
SP SP – 1
@SP src
R
IR
IM
70
71
–
–
–
–
–
–
2
2
3
2
3
2
IF70
PUSHX src
SP SP – 1
@SP src
ER
C8
–
–
–
–
–
–
3
2
RCF
RET
C 0
CF
AF
0
–
–
–
–
–
–
–
–
–
–
–
1
1
2
4
PC @SP
SP SP + 2
RL dst
R
90
91
*
*
*
*
–
–
2
2
2
3
C
D7 D6 D5 D4 D3 D2 D1 D0
IR
dst
RLC dst
RR dst
R
10
11
*
*
*
*
*
*
*
*
–
–
–
–
2
2
2
3
C
D7 D6 D5 D4 D3 D2 D1 D0
dst
IR
R
E0
E1
2
2
2
3
D7 D6 D5 D4 D3 D2 D1 D0
dst
C
IR
RRC dst
R
C0
C1
*
*
*
*
–
–
2
2
2
3
D7 D6 D5 D4 D3 D2 D1 D0
dst
C
IR
Note: Flags Notation:
* = Value is a function of the result of the operation.
– = Unaffected.
X = Undefined.
0 = Reset to 0.
1 = Set to 1.
PS024317-0914
P R E L I M I N A R Y
eZ8 CPU Instruction Summary
Z8 Encore! XP® F0823 Series
Product Specification
191
Table 118. eZ8 CPU Instruction Summary (Continued)
Address
Mode
Flags
C Z S V D H Cycles Cycles
Assembly
Mnemonic
Opcode(s)
(Hex)
Fetch Instr.
Symbolic Operation dst
src
SBC dst, src
dst dst – src - C
r
r
r
32
33
34
35
36
37
38
39
DF
D0
D1
*
*
*
*
1
*
2
2
3
3
3
3
4
4
1
2
2
3
4
3
4
3
4
3
3
2
2
3
Ir
R
R
R
IR
IM
IM
ER
IM
R
IR
ER
ER
SBCX dst, src
dst dst – src - C
C 1
*
*
*
*
1
*
SCF
1
*
–
*
–
*
–
0
–
–
–
–
SRA dst
R
D7 D6 D5 D4 D3 D2 D1 D0
dst
C
C
IR
SRL dst
R
1F C0
1F C1
*
*
0
*
–
–
3
3
2
3
0
D7 D6 D5 D4 D3 D2 D1 D0
dst
IR
SRP src
STOP
RP src
IM
01
6F
22
23
24
25
26
27
28
29
F0
F1
–
–
*
–
–
*
–
–
*
–
–
*
–
–
1
–
–
*
2
1
2
2
3
3
3
3
4
4
2
2
2
2
3
4
3
4
3
4
3
3
2
3
STOP Mode
SUB dst, src
dst dst – src
r
r
r
Ir
R
R
R
IR
IM
IM
ER
IM
R
IR
ER
ER
R
SUBX dst, src
SWAP dst
dst dst – src
*
*
*
*
*
*
1
–
*
dst[7:4] dst[3:0]
X
X
–
IR
Note: Flags Notation:
* = Value is a function of the result of the operation.
– = Unaffected.
X = Undefined.
0 = Reset to 0.
1 = Set to 1.
PS024317-0914
P R E L I M I N A R Y
eZ8 CPU Instruction Summary
Z8 Encore! XP® F0823 Series
Product Specification
192
Table 118. eZ8 CPU Instruction Summary (Continued)
Address
Mode
Flags
C Z S V D H Cycles Cycles
Assembly
Mnemonic
Opcode(s)
(Hex)
Fetch Instr.
Symbolic Operation dst
src
TCM dst, src
(NOT dst) AND src
r
r
r
62
63
64
65
66
67
68
69
72
73
74
75
76
77
78
79
F2
–
*
*
0
–
–
2
2
3
3
3
3
4
4
2
2
3
3
3
3
4
4
2
3
4
3
4
3
4
3
3
3
4
3
4
3
4
3
3
6
Ir
R
R
R
IR
R
IM
IM
ER
IM
r
IR
ER
ER
r
TCMX dst, src (NOT dst) AND src
–
–
*
*
*
*
0
0
–
–
–
–
TM dst, src
dst AND src
r
Ir
R
R
R
IR
R
IM
IM
ER
IM
Vector
IR
ER
ER
TMX dst, src
TRAP Vector
dst AND src
–
–
*
*
0
–
–
–
–
–
SP SP – 2
@SP PC
–
–
SP SP – 1
@SP FLAGS
PC @Vector
WDT
5F
–
–
–
–
–
–
1
2
Note: Flags Notation:
* = Value is a function of the result of the operation.
– = Unaffected.
X = Undefined.
0 = Reset to 0.
1 = Set to 1.
PS024317-0914
P R E L I M I N A R Y
eZ8 CPU Instruction Summary
Z8 Encore! XP® F0823 Series
Product Specification
193
Table 118. eZ8 CPU Instruction Summary (Continued)
Address
Mode
Flags
C Z S V D H Cycles Cycles
Assembly
Mnemonic
Opcode(s)
(Hex)
Fetch Instr.
Symbolic Operation dst
src
XOR dst, src
dst dst XOR src
r
r
r
B2
B3
B4
B5
B6
B7
B8
B9
–
*
*
0
–
–
2
2
3
3
3
3
4
4
3
4
3
4
3
4
3
3
Ir
R
R
R
IR
IM
IM
ER
IM
R
IR
ER
ER
XORX dst, src dst dst XOR src
–
*
*
0
–
–
Note: Flags Notation:
* = Value is a function of the result of the operation.
– = Unaffected.
X = Undefined.
0 = Reset to 0.
1 = Set to 1.
PS024317-0914
P R E L I M I N A R Y
eZ8 CPU Instruction Summary
Z8 Encore! XP® F0823 Series
Product Specification
194
Opcode Maps
A description of the opcode map data and the abbreviations are provided in Figure 26.
Figures 27 and 28 provide information about each of the eZ8 CPU instructions. Table 119
lists Opcode Map abbreviations.
Opcode
Lower Nibble
Fetch Cycles
Instruction Cycles
4
3.3
CP
Opcode
Upper Nibble
A
R2,R1
First Operand
After Assembly
Second Operand
After Assembly
Figure 26. Opcode Map Cell Description
PS024317-0914
P R E L I M I N A R Y
Opcode Maps
Z8 Encore! XP® F0823 Series
Product Specification
195
Table 119. Opcode Map Abbreviations
Abbreviation
Description
Abbreviation
Description
b
Bit position
IRR
Indirect Register Pair
Polarity (0 or 1)
cc
X
Condition code
p
r
8-bit signed index or displace-
ment
4-bit Working Register
DA
ER
Destination address
R
8-bit register
Extended Addressing register r1, R1, Ir1, Irr1, IR1,
Destination address
rr1, RR1, IRR1, ER1
IM
Immediate data value
r2, R2, Ir2, Irr2, IR2,
rr2, RR2, IRR2, ER2
Source address
Ir
Indirect Working Register
Indirect register
RA
rr
Relative
IR
Irr
Working Register Pair
Register Pair
Indirect Working Register Pair RR
PS024317-0914
P R E L I M I N A R Y
Opcode Maps
Z8 Encore! XP® F0823 Series
Product Specification
196
Lower Nibble (Hex)
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
1.1
2.2
2.3
2.4
3.3
3.4
3.3
3.4
4.3
4.3
2.3
2.2
JR
cc,X
2.2
LD
r1,IM
3.2
JP
cc,DA
1.2
INC
r1
1.2
NOP
BRK SRP ADD ADD ADD ADD ADD ADD ADDX ADDX DJNZ
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
IM
r1,r2
r1,Ir2
R2,R1
IR2,R1
R1,IM
IR1,IM ER2,ER1 IM,ER1
r1,X
2.2
RLC
R1
2.3
2.3
2.4
3.3
3.4
3.3
3.4 4.3 4.3
See 2nd
Opcode
Map
RLC ADC ADC ADC ADC ADC ADC ADCX ADCX
IR1
r1,r2
r1,Ir2
R2,R1
IR2,R1
R1,IM
IR1,IM ER2,ER1 IM,ER1
2.2
INC
R1
2.3
INC
IR1
2.3
SUB
r1,r2
2.4
3.3
3.4
3.3
3.4 4.3 4.3
SUB SUBX SUBX
IR1,IM ER2,ER1 IM,ER1
1
SUB SUB
r1,Ir2
SUB SUB
IR2,R1
R2,R1
R1,IM
2.2
DEC
R1
2.3
2.3
2.4
3.3
3.4
3.3
3.4
4.3
4.3
DEC SBC
IR1
SBC SBC
r1,Ir2
SBC SBC
IR2,R1
SBC SBCX SBCX
IR1,IM ER2,ER1 IM,ER1
r1,r2
R2,R1
R1,IM
2.2
DA
R1
2.3
DA
IR1
2.3
OR
r1,r2
2.4
OR
r1,Ir2
3.3
OR
R2,R1
3.4
OR
IR2,R1
3.3
OR
R1,IM
3.4
4.3
4.3
OR
ORX ORX
IR1,IM ER2,ER1 IM,ER1
2.2
2.3
2.3
2.4
3.3
3.4
3.3
3.4 4.3 4.3
1.2
WDT
POP POP AND AND AND AND AND AND ANDX ANDX
R1
IR1
r1,r2
r1,Ir2
R2,R1
IR2,R1
R1,IM
IR1,IM ER2,ER1 IM,ER1
2.2
2.3
2.3
2.4
3.3
3.4
3.3
3.4 4.3 4.3
1.2
STOP
COM COM TCM TCM TCM TCM TCM TCM TCMX TCMX
R1
IR1
r1,r2
r1,Ir2
R2,R1
IR2,R1
R1,IM
IR1,IM ER2,ER1 IM,ER1
2.2
2.3
2.3
2.4
TM
r1,Ir2
3.3
TM
R2,R1
3.4
TM
IR2,R1
3.3
TM
R1,IM
3.4
4.3
4.3
1.2
HALT
PUSH PUSH TM
R2
TM
TMX TMX
IR2
r1,r2
IR1,IM ER2,ER1 IM,ER1
2.5
2.6
2.5
2.9
3.2
3.3
LDX
3.4
LDX
3.5
3.4
3.4
1.2
DI
DECW DECW LDE LDEI LDX
RR1
LDX
LDX
LDX
IRR1
r1,Irr2
Ir1,Irr2 r1,ER2 Ir1,ER2 IRR2,R1 IRR2,IR1 r1,rr2,X rr1,r2,X
2.2
RL
R1
2.3
RL
IR1
2.5
2.9
3.2
3.3
LDX
3.4
LDX
3.5
3.3
3.5
1.2
EI
LDE LDEI LDX
r2,Irr1
LDX
LEA
LEA
Ir2,Irr1 r2,ER1 Ir2,ER1 R2,IRR1 IR2,IRR1 r1,r2,X rr1,rr2,X
2.5
2.6
2.3
CP
r1,r2
2.4
CP
r1,Ir2
3.3
CP
R2,R1
3.4
CP
IR2,R1
3.3
CP
R1,IM
3.4
4.3
4.3
1.4
RET
INCW INCW
RR1
CP
CPX
CPX
IRR1
IR1,IM ER2,ER1 IM,ER1
2.2
CLR
R1
2.3
2.3
2.4
3.3
3.4
3.3
3.4 4.3 4.3
1.5
IRET
CLR XOR XOR XOR XOR XOR XOR XORX XORX
IR1
r1,r2
r1,Ir2
R2,R1
IR2,R1
R1,IM
IR1,IM ER2,ER1 IM,ER1
3.4 3.2
LD PUSHX
2.2
2.3
2.5
2.9
2.3
JP
IRR1
2.9
LDC
Ir1,Irr2
1.2
RCF
RRC RRC
R1
LDC LDCI
r1,Irr2
IR1
Ir1,Irr2
r1,r2,X
ER2
2.2
SRA
R1
2.3
SRA
IR1
2.5
2.9
2.6
2.2
3.3
3.4
LD
r2,r1,X
3.2
POPX
ER1
1.2
SCF
LDC LDCI CALL BSWAP CALL
r2,Irr1
Ir2,Irr1
IRR1
R1
DA
2.2
RR
R1
2.3
RR
IR1
2.2
BIT
p,b,r1
2.3
LD
r1,Ir2
3.2
LD
R2,R1
3.3
LD
IR2,R1
3.2
LD
R1,IM
3.3
4.2
4.2
1.2
CCF
LD
LDX
LDX
IR1,IM ER2,ER1 IM,ER1
2.2
2.3
2.6
2.3
LD
Ir1,r2
2.8
MULT
RR1
3.3
LD
3.3
BTJ
3.4
BTJ
SWAP SWAP TRAP
R1
IR1
Vector
R2,IR1 p,b,r1,X p,b,Ir1,X
Figure 27. First Opcode Map
PS024317-0914
P R E L I M I N A R Y
Opcode Maps
Z8 Encore! XP® F0823 Series
Product Specification
197
Lower Nibble (Hex)
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
3
,
3.3
CPC
r1,r2
3.4
4.3
4.4
4.3
4.4
5.3
5.3
CPC CPC
r1,Ir2
CPC CPC
IR2,R1
CPC CPCX CPCX
IR1,IM ER2,ER1 IM,ER1
R2,R1
R1,IM
3.2
SRL
R1
3.3
SRL
IR1
5, 4
LDWX
ER2,ER1
Figure 28. Second Opcode Map after 1Fh
PS024317-0914
P R E L I M I N A R Y
Opcode Maps
Z8 Encore! XP® F0823 Series
Product Specification
198
Electrical Characteristics
The data in this chapter represents all known data prior to qualification and characteriza-
tion of the F0823 Series of products, and is therefore subject to change. Additional electri-
cal characteristics may be found in the individual chapters of this document.
Absolute Maximum Ratings
Stresses greater than those listed in Table 120 may cause permanent damage to the device.
These ratings are stress ratings only. Operation of the device at any condition outside those
indicated in the operational sections of these specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
For improved reliability, tie unused inputs to one of the supply voltages (VDD or VSS).
Table 120. Absolute Maximum Ratings
Parameter
Minimum Maximum
Units
°C
°C
V
Notes
Ambient temperature under bias
Storage temperature
–40
–65
–0.3
–0.3
–0.3
–5
+105
+150
+5.5
+3.9
+3.6
+5
Voltage on any pin with respect to V
1
2
SS
V
Voltage on V pin with respect to V
V
DD
SS
Maximum current on input and/or inactive output pin
Maximum output current from active output pin
µA
mA
–25
+25
8-pin Packages Maximum Ratings at 0°C to 70°C
Total power dissipation
220
60
mW
mA
Maximum current into V or out of V
DD
SS
20-pin Packages Maximum Ratings at 0°C to 70°C
Total power dissipation
430
120
mW
mA
Maximum current into V or out of V
DD
SS
28-pin Packages Maximum Ratings at 0°C to 70°C
Total power dissipation
450
125
mW
mA
Maximum current into V or out of V
DD
SS
Notes: Operating temperature is specified in DC Characteristics.
1. This voltage applies to all pins except the following: V , AV , pins supporting analog input (Port B[5:0], Port
DD
DD
C[2:0]) and pins supporting the crystal oscillator (PA0 and PA1). On the 8-pin packages, this applies to all pins
but V
.
DD
2. This voltage applies to pins on the 20/28 pin packages supporting analog input (Port B[5:0], Port C[2:0]) and pins
supporting the crystal oscillator (PA0 and PA1).
PS024317-0914
P R E L I M I N A R Y
Electrical Characteristics
Z8 Encore! XP® F0823 Series
Product Specification
199
DC Characteristics
Table 121 lists the DC characteristics of the Z8 Encore! XP F0823 Series products. All
voltages are referenced to VSS, the primary system ground.
Table 121. DC Characteristics
T = –40°C to +105°C
A
(unless otherwise specified)
Symbol Parameter
Minimum Typical Maximum Units Conditions
V
V
Supply Voltage
2.7
–
–
3.6
V
V
DD
IL1
Low Level Input
Voltage
–0.3
0.3*V
DD
V
V
High Level Input
Voltage
0.7*V
0.7*V
–
–
5.5
V
V
For all input pins without analog
or oscillator function. For all sig-
nal pins on the 8-pin devices.
Programmable pull-ups must
also be disabled.
IH1
IH2
DD
DD
High Level Input
Voltage
V
+0.3
For those pins with analog or
oscillator function (20-/28-pin
devices only), or when pro-
grammable pull-ups are
enabled.
DD
V
V
V
V
Low Level Output
Voltage
–
2.4
–
–
0.4
V
V
I
= 2mA; V = 3.0V
OL DD
OL1
OH1
OL2
OH2
High Output Drive disabled.
I = –2mA; V = 3.0V
OH
High Level Output
Voltage
–
–
0.6
–
DD
High Output Drive disabled.
Low Level Output
Voltage
–
–
V
I
OL
= 20mA; V = 3.3 V
DD
High Output Drive enabled.
I = –20mA; V = 3.3 V
OH
High Level Output
Voltage
2.4
–
V
DD
High Output Drive enabled.
I
I
I
Input Leakage Cur-
rent
+0.002
+0.007
–
+5
+5
+5
µA
µA
µA
V
V
= V
DD
IH
IN
= 3.3 V
DD
Input Leakage Cur-
rent
–
V
V
= V
SS
IL
IN
= 3.3 V
DD
Tristate Leakage
Current
–
TL
Notes:
1. This condition excludes all pins that have on-chip pull-ups, when driven Low.
2. These values are provided for design guidance only and are not tested in production.
PS024317-0914
P R E L I M I N A R Y
DC Characteristics
Z8 Encore! XP® F0823 Series
Product Specification
200
Table 121. DC Characteristics (Continued)
T = –40°C to +105°C
A
(unless otherwise specified)
Symbol Parameter
Minimum Typical Maximum Units Conditions
I
Controlled Current
Drive
1.8
2.8
7.8
12
–
3
7
4.5
10.5
19.5
30
mA {AFS2,AFS1} = {0,0}.
mA {AFS2,AFS1} = {0,1}.
mA {AFS2,AFS1} = {1,0}.
mA {AFS2,AFS1} = {1,1}.
pF
LED
13
20
2
C
C
C
GPIO Port Pad
Capacitance
8.0
8.0
9.5
–
PAD
XIN
2
2
X
Pad Capaci-
–
–
–
–
pF
pF
IN
tance
X
Pad Capaci-
OUT
XOUT
tance
I
Weak Pull-up Cur-
rent
30
100
350
µA
V
V
= 3.0V–3.6V.
DD
PU
V
RAM Data Reten-
tion Voltage
TBD
Voltage at which RAM retains
static values; no reading or writ-
ing is allowed.
RAM
Notes:
1. This condition excludes all pins that have on-chip pull-ups, when driven Low.
2. These values are provided for design guidance only and are not tested in production.
PS024317-0914
P R E L I M I N A R Y
DC Characteristics
Z8 Encore! XP® F0823 Series
Product Specification
201
Table 122. Power Consumption
V
= 2.7V to 3.6V
DD
2
3
Maximum Maximum
1
Symbol
Parameter
Typical
Std Temp Ext Temp Units Conditions
I
Stop
Supply Current in Stop
Mode
0.1
2
7.5
µA No peripherals enabled.
All pins driven to V or
DD
DD
V
.
SS
I
Halt
Supply Current in Halt
Mode (with all peripher-
als disabled)
35
55
65
µA 32kHz.
DD
520
630
700
µA 5.5MHz.
I
Supply Current in Active
Mode (with all peripher-
als disabled)
2.8
4.5
4.5
5.2
4.8
5.2
mA 32kHz.
DD
mA 5.5MHz.
I
I
I
WDT Watchdog Timer Sup-
ply Current
0.9
350
50
1.0
1.1
µA
DD
DD
DD
IPO
Internal Precision Oscil-
lator Supply Current
500
550
µA
VBO
Voltage Brown-Out Sup-
ply Current
µA For 20-/28-pin devices
4
(VBO only).
4
For 8-pin devices.
I
ADC
Analog-to-Digital Con-
verter Supply Current
(with External Refer-
ence)
2.8
3.1
3.3
3.7
0
3.1
3.6
3.7
4.2
3.2
3.7
3.8
4.3
mA 32kHz.
DD
mA 5.5MHz.
mA 10MHz.
mA 20MHz.
µA See Note 4.
I
ADC Internal Refer-
ence Supply Current
DD
ADCRef
I
CMP Comparator supply Cur-
rent
150
320
180
480
190
500
µA See Note 4.
DD
I
BG
Band Gap Supply Cur-
rent
µA For 20-/28-pin devices.
For 8-pin devices.
DD
Notes:
1. Typical conditions are defined as VDD = 3.3 V and +30°C.
2. Standard temperature is defined as TA = 0°C to +70°C; these values not tested in production for worst case
behavior, but are derived from product characterization and provided for design guidance only.
3. Extended temperature is defined as TA = –40°C to +105°C; these values not tested in production for worst case
behavior, but are derived from product characterization and provided for design guidance only.
4. For this block to operate, the bandgap circuit is automatically turned on and must be added to the total supply
current. This bandgap current is only added once, regardless of how many peripherals are using it.
PS024317-0914
P R E L I M I N A R Y
DC Characteristics
Z8 Encore! XP® F0823 Series
Product Specification
202
AC Characteristics
The section provides information about the AC characteristics and timing. All AC timing
information assumes a standard load of 50 pF on all outputs.
Table 123. AC Characteristics
V
= 2.7V to 3.6V
DD
T = –40°C to +105°C
A
(unless otherwise
stated)
Symbol Parameter
Minimum Maximum Units Conditions
F
System Clock Frequency
–
20.0*
MHz Read-only from Flash memory.
SYSCLK
1
0.032768
20.0
MHz Program or erasure of the
Flash memory.
T
T
T
T
T
System Clock Period
50
20
20
–
–
30
30
3
ns
ns
ns
ns
ns
T
T
T
T
T
= 1/F
.
SYSCLK
XIN
CLK
CLK
CLK
CLK
CLK
System Clock High Time
System Clock Low Time
System Clock Rise Time
System Clock Fall Time
= 50ns.
= 50ns.
= 50ns.
= 50ns.
XINH
XINL
XINR
XINF
–
3
Note: *System Clock Frequency is limited by the Internal Precision Oscillator on the Z8 Encore! XP F0823 Series.
See Table 124 on page 202.
Table 124. Internal Precision Oscillator Electrical Characteristics
V
= 2.7V to 3.6V
DD
T = –40°C to +105°C
A
(unless otherwise stated)
Symbol Parameter
Minimum
Typical Maximum Units Conditions
F
F
F
T
Internal Precision Oscillator
Frequency (High Speed)
5.53
32.7
+1
MHz
kHz
%
V
= 3.3V
DD
IPO
T = 30°C
A
Internal Precision Oscillator
Frequency (Low Speed)
V
= 3.3V
DD
IPO
T = 30°C
A
Internal Precision Oscillator
Error
+4
IPO
Internal Precision Oscillator
Startup Time
3
µs
IPOST
PS024317-0914
P R E L I M I N A R Y
AC Characteristics
Z8 Encore! XP® F0823 Series
Product Specification
203
On-Chip Peripheral AC and DC Electrical Characteristics
Table 125 tabulates the electrical characteristics of the POR and VBO blocks.
Table 125. Power-On Reset and Voltage Brown-Out Electrical Characteristics and Timing
T = –40°C to +105°C
A
Symbol Parameter
Minimum Typical* Maximum Units Conditions
V
Power-On Reset Voltage
Threshold
2.20
2.45
2.40
50
2.70
V
V
= V
POR
DD
POR
V
Voltage Brown-Out Reset Volt-
age Threshold
2.15
2.65
V
V
= V
VBO
DD
VBO
V
to V
hysteresis
VBO
75
–
mV
V
POR
Starting V voltage to ensure
–
–
V
SS
DD
valid Power-On Reset.
T
Power-On Reset Analog Delay
70
–
µs
V
> V
;
POR
ANA
DD
T
Digital
POR
Reset delay fol-
lows T
ANA
T
Power-On Reset Digital Delay
Stop-Mode Recovery
16
µs 66 Internal Preci-
sion Oscillator
cycles + IPO
POR
startup time
(T
)
IPOST
T
T
16
10
µs 66 Internal Preci-
sion Oscillator
cycles
SMR
VBO
Voltage Brown-Out Pulse
Rejection Period
µs Period of time in
–
–
which V
<
DD
V
without
VBO
generating a
Reset.
T
T
Time for V to transition from
0.10
–
100
ms
RAMP
SMP
DD
V
to V
to ensure valid
SS
POR
Reset
Stop-Mode Recovery pin pulse
rejection period
20
ns For any SMR pin
or for the Reset
pin when it is
asserted in Stop
Mode.
Note: *Data in the typical column is from characterization at 3.3 V and 30°C. These values are provided for design
guidance only and are not tested in production.
PS024317-0914
P R E L I M I N A R Y On-Chip Peripheral AC and DC Electrical
Z8 Encore! XP® F0823 Series
Product Specification
204
Table 126. Flash Memory Electrical Characteristics and Timing
= 2.7V to 3.6V
V
DD
T = –40°C to +105°C
A
(unless otherwise stated)
Parameter
Minimum Typical Maximum Units Notes
Flash Byte Read Time
Flash Byte Program Time
Flash Page Erase Time
Flash Mass Erase Time
100
20
–
–
–
–
–
–
40
–
ns
µs
10
ms
ms
200
–
–
Writes to Single Address
Before Next Erase
2
Flash Row Program Time
–
–
8
ms Cumulative program time for
single row cannot exceed limit
before next erase. This param-
eter is only an issue when
bypassing the Flash Controller.
Data Retention
Endurance
100
–
–
–
–
years 25°C
10,000
cycles Program/erase cycles
Table 127. Watchdog Timer Electrical Characteristics and Timing
= 2.7V to 3.6V
V
DD
T = –40°C to +105°C
A
(unless otherwise stated)
Symbol Parameter
Minimum Typical Maximum Units Conditions
F
F
T
WDT Oscillator Frequency
WDT Oscillator Error
10
kHz
%
WDT
WDT
WDT-
+50
WDT Calibrated Timeout
0.98
0.70
0.50
1
1
1
1.02
s
V
= 3.3 V;
DD
T = 30°C
CAL
A
1.30
1.50
s
s
V
= 2.7V to 3.6V
DD
T = 0°C to 70°C
A
V
= 2.7V to 3.6V
DD
T = –40°C to +105°C
A
PS024317-0914
P R E L I M I N A R Y On-Chip Peripheral AC and DC Electrical
Z8 Encore! XP® F0823 Series
Product Specification
205
Table 128. Analog-to-Digital Converter Electrical Characteristics and Timing
= 3.0V to 3.6V
V
DD
T = 0°C to +70°C
A
(unless otherwise stated)
Symbol Parameter
Minimum Typical Maximum Units Conditions
Resolution
10
–
bits
3
Differential Nonlinearity
(DNL)
–1.0
–
–
1.0
LSB External V
= 2.0V;
= 2.0V;
REF
R ← 3.0 kΩ
S
3
Integral Nonlinearity (INL)
–3.0
3.0
LSB External V
REF
R ← 3.0 kΩ
S
3
3
Offset Error with Calibration
+1
+3
LSB
LSB
Absolute Accuracy with
Calibration
V
V
V
Internal Reference Voltage
1.0
2.0
1.1
2.2
1.2
2.4
V
%
%
W
REFSEL=01
REFSEL=10
REF
REF
REF
Internal Reference Varia-
tion with Temperature
+1.0
+0.5
850
Temperature variation
with V = 3.0
DD
Internal Reference Voltage
Supply voltage varia-
Variation with V
tion with T = 30°C
DD
A
R
Reference Buffer Output
Impedance
When the internal ref-
erence is buffered and
driven out to the VREF
pin (REFOUT = 1)
RE-
FOUT
Single-Shot Conversion
Time
–
–
5129
–
–
Sys- All measurements but
tem temperature sensor
clock
cycles
10258
256
Temperature sensor
measurement
Continuous Conversion
Time
Sys- All measurements but
tem temperature sensor
clock
cycles
512
Temperature sensor
measurement
Notes:
1. Analog source impedance affects the ADC offset voltage (because of pin leakage) and input settling time.
2. Devices are factory calibrated at V
conditions.
= 3.3 V and T = +30°C, so the ADC is maximally accurate under these
DD
A
3. LSBs are defined assuming 10-bit resolution.
4. This is the maximum recommended resistance seen by the ADC input pin.
5. The input impedance is inversely proportional to the system clock frequency.
PS024317-0914
P R E L I M I N A R Y On-Chip Peripheral AC and DC Electrical
Z8 Encore! XP® F0823 Series
Product Specification
206
Table 128. Analog-to-Digital Converter Electrical Characteristics and Timing (Continued)
V
= 3.0V to 3.6V
DD
T = 0°C to +70°C
A
(unless otherwise stated)
Symbol Parameter
Signal Input Bandwidth
Minimum Typical Maximum Units Conditions
–
10
kHz As defined by –3 dB
point
4
R
Analog Source Impedance
Input Impedance
–
–
10
kW In unbuffered mode
S
Zin
–
0
150
kW In unbuffered mode at
5
20MHz
Vin
Input Voltage Range
V
V
Unbuffered Mode
DD
Notes:
1. Analog source impedance affects the ADC offset voltage (because of pin leakage) and input settling time.
2. Devices are factory calibrated at V
conditions.
= 3.3 V and T = +30°C, so the ADC is maximally accurate under these
DD
A
3. LSBs are defined assuming 10-bit resolution.
4. This is the maximum recommended resistance seen by the ADC input pin.
5. The input impedance is inversely proportional to the system clock frequency.
Table 129. Comparator Electrical Characteristics
V
= 2.7V to 3.6V
DD
T = –40°C to +105°C
A
Symbol Parameter
Minimum Typical Maximum Units Conditions
V
V
Input DC Offset
5
+5
+3
200
4
mV
%
OS
Programmable Internal
Reference Voltage
20-/28-pin devices
8-pin devices
CREF
%
T
Propagation Delay
Input Hysteresis
ns
mV
V
PROP
V
V
HYS
IN
Input Voltage Range
V
V
–1
DD
SS
General Purpose I/O Port Input Data Sample Timing
Figure 29 displays a timing sequence for the GPIO port input sampling. The input value
on a GPIO port pin is sampled on the rising edge of the system clock. The port value is
PS024317-0914
P R E L I M I N A R Y On-Chip Peripheral AC and DC Electrical
Z8 Encore! XP® F0823 Series
Product Specification
207
available to the eZ8 CPU on the second rising clock edge following the change of the port
value.
TCLK
System
Clock
Port Value
Changes to 0
Port Pin
Input Value
Port Input Data
Register Latch
0 Latched
Into Port Input
Data Register
Port Input Data Register
Value 0 Read
by eZ8
Port Input Data
Read on Data Bus
Figure 29. Port Input Sample Timing
Table 130. GPIO Port Input Timing
Delay (ns)
Parameter Abbreviation
Minimum Maximum
T
T
T
Port Input Transition to X Rise Setup Time (Not pictured)
5
0
–
–
S_PORT
H_PORT
SMR
IN
X
Rise to Port Input Transition Hold Time (Not pictured)
IN
GPIO Port Pin Pulse Width to ensure Stop-Mode Recovery (for
GPIO Port Pins enabled as SMR sources)
1 s
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P R E L I M I N A R Y On-Chip Peripheral AC and DC Electrical
Z8 Encore! XP® F0823 Series
Product Specification
208
General Purpose I/O Port Output Timing
Figure 30 and Table 131 provide timing information for GPIO Port pins.
TCLK
X
IN
T1
T2
Port Output
Figure 30. GPIO Port Output Timing
Table 131. GPIO Port Output Timing
Delay (ns)
Minimum Maximum
Parameter Abbreviation
GPIO Port pins
T
T
X
X
Rise to Port Output Valid Delay
Rise to Port Output Hold Time
–
2
15
–
1
2
IN
IN
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P R E L I M I N A R Y On-Chip Peripheral AC and DC Electrical
Z8 Encore! XP® F0823 Series
Product Specification
209
On-Chip Debugger Timing
Figure 31 and Table 132 provide timing information for the DBG pin. The DBG pin tim-
ing specifications assume a 4 ns maximum rise and fall time.
TCLK
X
IN
T1
T2
T4
DBG
(Output)
Output Data
T3
DBG
(Input)
Input Data
Figure 31. On-Chip Debugger Timing
Table 132. On-Chip Debugger Timing
Delay (ns)
Minimum Maximum
Parameter Abbreviation
DBG
T
T
T
T
X
X
Rise to DBG Valid Delay
–
2
5
5
15
–
1
2
3
4
IN
IN
Rise to DBG Output Hold Time
DBG to X Rise Input Setup Time
–
IN
DBG to X Rise Input Hold Time
–
IN
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P R E L I M I N A R Y On-Chip Peripheral AC and DC Electrical
Z8 Encore! XP® F0823 Series
Product Specification
210
UART Timing
Figure 32 and Table 133 provide timing information for UART pins for the case where
CTS is used for flow control. The CTS to DE assertion delay (T1) assumes the transmit
data register has been loaded with data prior to CTS assertion.
CTS
(Input)
T3
DE
(Output)
T1
TXD
bit 7 parity
stop
start
bit 0
bit 1
(Output)
T2
end of
stop bit(s)
Figure 32. UART Timing With CTS
Table 133. UART Timing With CTS
Delay (ns)
Parameter Abbreviation
UART
Minimum
Maximum
T
CTS Fall to DE output delay
2 * X period 2 * X period +
1
IN
IN
1 bit time
T
T
DE assertion to TXD falling edge (start bit) delay
End of Stop Bit(s) to DE deassertion delay
± 5
± 5
2
3
PS024317-0914
P R E L I M I N A R Y On-Chip Peripheral AC and DC Electrical
Z8 Encore! XP® F0823 Series
Product Specification
211
Figure 33 and Table 134 provide timing information for UART pins for the case where
CTS is not used for flow control. DE asserts after the transmit data register has been writ-
ten. DE remains asserted for multiple characters as long as the transmit data register is
written with the next character before the current character has completed.
T2
DE
(Output)
TXD
(Output)
start
bit0
bit 1
bit 7 parity
stop
T1
end of
stop bit(s)
Figure 33. UART Timing Without CTS
Table 134. UART Timing Without CTS
Delay (ns)
Parameter Abbreviation
UART
Minimum
Maximum
T
T
DE assertion to TXD falling edge (start bit) delay
1 * X period
1 bit time
1
2
IN
End of Stop Bit(s) to DE deassertion delay (Tx data
register is empty)
± 5
PS024317-0914
P R E L I M I N A R Y On-Chip Peripheral AC and DC Electrical
Z8 Encore! XP® F0823 Series
Product Specification
212
Packaging
Zilog’s F0823 Series of MCUs includes the Z8F0113, Z8F0123, Z8F0213, Z8F0223,
Z8F0413, Z8F0423, Z8F0813 and Z8F0823 devices, which are available in the following
packages:
•
•
•
•
•
•
•
•
8-pin Plastic Dual Inline Package (PDIP)
8-Pin Quad Flat No-Lead Package (QFN)/MLF-S1
20-pin Plastic Dual-Inline Package (PDIP)
20-pin Small Outline Integrated Circuit Package (SOIC)
20-pin Small Shrink Outline Package (SSOP)
28-pin Plastic Dual-Inline Package (PDIP)
28-pin Small Outline Integrated Circuit Package (SOIC)
28-pin Small Shrink Outline Package (SSOP)
Current diagrams for each of these packages are published in Zilog’s Packaging Product
Specification (PS0072), which is available free for download from the Zilog website.
1. The footprint of the QFN)/MLF-S package is identical to that of the 8-pin SOIC package, but with a lower profile.
PS024317-0914
P R E L I M I N A R Y
Packaging
Z8 Encore! XP® F0823 Series
Product Specification
213
Ordering Information
Order your F0823 Series products from Zilog using the part numbers shown in Table 135.
For more information about ordering, please consult your local Zilog sales office. The
Sales Location page on the Zilog website lists all regional offices.
Table 135. Z8 Encore! XP F0823 Series Ordering Matrix
Z8 Encore! XP F0823 Series with 8 KB Flash, 10-Bit Analog-to-Digital Converter
Standard Temperature: 0°C to 70°C
Z8F0823PB005SG
Z8F0823QB005SG
Z8F0823SB005SG
Z8F0823SH005SG
Z8F0823HH005SG
Z8F0823PH005SG
Z8F0823SJ005SG
Z8F0823HJ005SG
Z8F0823PJ005SG
8 KB 1 KB
8 KB 1 KB
8 KB 1 KB
6
6
6
12
12
12
18
18
18
18
18
18
2
2
2
2
2
2
2
2
2
4
4
4
7
7
7
8
8
8
1
1
1
1
1
1
1
1
1
PDIP 8-pin package
QFN 8-pin package
SOIC 8-pin package
SOIC 20-pin package
SSOP 20-pin package
PDIP 20-pin package
SOIC 28-pin package
SSOP 28-pin package
PDIP 28-pin package
8 KB 1 KB 16
8 KB 1 KB 16
8 KB 1 KB 16
8 KB 1 KB 22
8 KB 1 KB 22
8 KB 1 KB 22
Extended Temperature: –40°C to 105°C
Z8F0823PB005EG
Z8F0823QB005EG
Z8F0823SB005EG
Z8F0823SH005EG
Z8F0823HH005EG
Z8F0823PH005EG
Z8F0823SJ005EG
Z8F0823HJ005EG
Z8F0823PJ005EG
8 KB 1 KB
8 KB 1 KB
8 KB 1 KB
6
6
6
12
12
12
18
18
18
18
18
18
2
2
2
2
2
2
2
2
2
4
4
4
7
7
7
8
8
8
1
1
1
1
1
1
1
1
1
PDIP 8-pin package
QFN 8-pin package
SOIC 8-pin package
SOIC 20-pin package
SSOP 20-pin package
PDIP 20-pin package
SOIC 28-pin package
SSOP 28-pin package
PDIP 28-pin package
8 KB 1 KB 16
8 KB 1 KB 16
8 KB 1 KB 16
8 KB 1 KB 22
8 KB 1 KB 22
8 KB 1 KB 22
PS024317-0914
P R E L I M I N A R Y
Ordering Information
Z8 Encore! XP® F0823 Series
Product Specification
214
Table 135. Z8 Encore! XP F0823 Series Ordering Matrix (Continued)
Z8 Encore! XP F0823 Series with 8 KB Flash
Standard Temperature: 0°C to 70°C
Z8F0813PB005SG
Z8F0813QB005SG
Z8F0813SB005SG
Z8F0813SH005SG
Z8F0813HH005SG
Z8F0813PH005SG
Z8F0813SJ005SG
Z8F0813HJ005SG
Z8F0813PJ005SG
8 KB 1 KB
8 KB 1 KB
8 KB 1 KB
6
6
6
12
12
12
18
18
18
18
18
18
2
2
2
2
2
2
2
2
2
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
PDIP 8-pin package
QFN 8-pin package
SOIC 8-pin package
SOIC 20-pin package
SSOP 20-pin package
PDIP 20-pin package
SOIC 28-pin package
SSOP 28-pin package
PDIP 28-pin package
8 KB 1 KB 16
8 KB 1 KB 16
8 KB 1 KB 16
8 KB 1 KB 24
8 KB 1 KB 24
8 KB 1 KB 24
Extended Temperature: –40°C to 105°C
Z8F0813PB005EG
Z8F0813QB005EG
Z8F0813SB005EG
Z8F0813SH005EG
Z8F0813HH005EG
Z8F0813PH005EG
Z8F0813SJ005EG
Z8F0813HJ005EG
Z8F0813PJ005EG
8 KB 1 KB
8 KB 1 KB
8 KB 1 KB
6
6
6
12
12
12
18
18
18
18
18
18
2
2
2
2
2
2
2
2
2
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
PDIP 8-pin package
QFN 8-pin package
SOIC 8-pin package
SOIC 20-pin package
SSOP 20-pin package
PDIP 20-pin package
SOIC 28-pin package
SSOP 28-pin package
PDIP 28-pin package
8 KB 1 KB 16
8 KB 1 KB 16
8 KB 1 KB 16
8 KB 1 KB 24
8 KB 1 KB 24
8 KB 1 KB 24
PS024317-0914
P R E L I M I N A R Y
Ordering Information
Z8 Encore! XP® F0823 Series
Product Specification
215
Table 135. Z8 Encore! XP F0823 Series Ordering Matrix (Continued)
Z8 Encore! XP F0823 Series with 4 KB Flash, 10-Bit Analog-to-Digital Converter
Standard Temperature: 0°C to 70°C
Z8F0423PB005SG
Z8F0423QB005SG
Z8F0423SB005SG
Z8F0423SH005SG
Z8F0423HH005SG
Z8F0423PH005SG
Z8F0423SJ005SG
Z8F0423HJ005SG
Z8F0423PJ005SG
4 KB 1 KB
4 KB 1 KB
4 KB 1 KB
6
6
6
12
12
12
18
18
18
18
18
18
2
2
2
2
2
2
2
2
2
4
4
4
7
7
7
8
8
8
1
1
1
1
1
1
1
1
1
PDIP 8-pin package
QFN 8-pin package
SOIC 8-pin package
SOIC 20-pin package
SSOP 20-pin package
PDIP 20-pin package
SOIC 28-pin package
SSOP 28-pin package
PDIP 28-pin package
4 KB 1 KB 16
4 KB 1 KB 16
4 KB 1 KB 16
4 KB 1 KB 22
4 KB 1 KB 22
4 KB 1 KB 22
Extended Temperature: –40°C to 105°C
Z8F0423PB005EG
Z8F0423QB005EG
Z8F0423SB005EG
Z8F0423SH005EG
Z8F0423HH005EG
Z8F0423PH005EG
Z8F0423SJ005EG
Z8F0423HJ005EG
Z8F0423PJ005EG
4 KB 1 KB
4 KB 1 KB
4 KB 1 KB
6
6
6
12
12
12
18
18
18
18
18
18
2
2
2
2
2
2
2
2
2
4
4
4
7
7
7
8
8
8
1
1
1
1
1
1
1
1
1
PDIP 8-pin package
QFN 8-pin package
SOIC 8-pin package
SOIC 20-pin package
SSOP 20-pin package
PDIP 20-pin package
SOIC 28-pin package
SSOP 28-pin package
PDIP 28-pin package
4 KB 1 KB 16
4 KB 1 KB 16
4 KB 1 KB 16
4 KB 1 KB 22
4 KB 1 KB 22
4 KB 1 KB 22
PS024317-0914
P R E L I M I N A R Y
Ordering Information
Z8 Encore! XP® F0823 Series
Product Specification
216
Table 135. Z8 Encore! XP F0823 Series Ordering Matrix (Continued)
Z8 Encore! XP F0823 Series with 4 KB Flash
Standard Temperature: 0°C to 70°C
Z8F0413PB005SG
Z8F0413QB005SG
Z8F0413SB005SG
Z8F0413SH005SG
Z8F0413HH005SG
Z8F0413PH005SG
Z8F0413SJ005SG
Z8F0413HJ005SG
Z8F0413PJ005SG
4 KB 1 KB
4 KB 1 KB
4 KB 1 KB
6
6
6
12
12
12
18
18
18
18
18
18
2
2
2
2
2
2
2
2
2
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
PDIP 8-pin package
QFN 8-pin package
SOIC 8-pin package
SOIC 20-pin package
SSOP 20-pin package
PDIP 20-pin package
SOIC 28-pin package
SSOP 28-pin package
PDIP 28-pin package
4 KB 1 KB 16
4 KB 1 KB 16
4 KB 1 KB 16
4 KB 1 KB 24
4 KB 1 KB 24
4 KB 1 KB 24
Extended Temperature: –40°C to 105°C
Z8F0413PB005EG
Z8F0413QB005EG
Z8F0413SB005EG
Z8F0413SH005EG
Z8F0413HH005EG
Z8F0413PH005EG
Z8F0413SJ005EG
Z8F0413HJ005EG
Z8F0413PJ005EG
4 KB 1 KB
4 KB 1 KB
4 KB 1 KB
6
6
6
12
12
12
18
18
18
18
18
18
2
2
2
2
2
2
2
2
2
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
PDIP 8-pin package
QFN 8-pin package
SOIC 8-pin package
SOIC 20-pin package
SSOP 20-pin package
PDIP 20-pin package
SOIC 28-pin package
SSOP 28-pin package
PDIP 28-pin package
4 KB 1 KB 16
4 KB 1 KB 16
4 KB 1 KB 16
4 KB 1 KB 24
4 KB 1 KB 24
4 KB 1 KB 24
PS024317-0914
P R E L I M I N A R Y
Ordering Information
Z8 Encore! XP® F0823 Series
Product Specification
217
Table 135. Z8 Encore! XP F0823 Series Ordering Matrix (Continued)
Z8 Encore! XP F0823 Series with 2 KB Flash, 10-Bit Analog-to-Digital Converter
Standard Temperature: 0°C to 70°C
Z8F0223PB005SG
Z8F0223QB005SG
Z8F0223SB005SG
Z8F0223SH005SG
Z8F0223HH005SG
Z8F0223PH005SG
Z8F0223SJ005SG
Z8F0223HJ005SG
Z8F0223PJ005SG
2 KB 512 B
2 KB 512 B
2 KB 512 B
6
6
6
12
12
12
18
18
18
18
18
18
2
2
2
2
2
2
2
2
2
4
4
4
7
7
7
8
8
8
1
1
1
1
1
1
1
1
1
PDIP 8-pin package
QFN 8-pin package
SOIC 8-pin package
SOIC 20-pin package
SSOP 20-pin package
PDIP 20-pin package
SOIC 28-pin package
SSOP 28-pin package
PDIP 28-pin package
2 KB 512 B 16
2 KB 512 B 16
2 KB 512 B 16
2 KB 512 B 22
2 KB 512 B 22
2 KB 512 B 22
Extended Temperature: –40°C to 105°C
Z8F0223PB005EG
Z8F0223QB005EG
Z8F0223SB005EG
Z8F0223SH005EG
Z8F0223HH005EG
Z8F0223PH005EG
Z8F0223SJ005EG
Z8F0223HJ005EG
Z8F0223PJ005EG
2 KB 512 B
2 KB 512 B
2 KB 512 B
6
6
6
12
12
12
18
18
18
18
18
18
2
2
2
2
2
2
2
2
2
4
4
4
7
7
7
8
8
8
1
1
1
1
1
1
1
1
1
PDIP 8-pin package
QFN 8-pin package
SOIC 8-pin package
SOIC 20-pin package
SSOP 20-pin package
PDIP 20-pin package
SOIC 28-pin package
SSOP 28-pin package
PDIP 28-pin package
2 KB 512 B 16
2 KB 512 B 16
2 KB 512 B 16
2 KB 512 B 22
2 KB 512 B 22
2 KB 512 B 22
PS024317-0914
P R E L I M I N A R Y
Ordering Information
Z8 Encore! XP® F0823 Series
Product Specification
218
Table 135. Z8 Encore! XP F0823 Series Ordering Matrix (Continued)
Z8 Encore! XP F0823 Series with 2 KB Flash
Standard Temperature: 0°C to 70°C
Z8F0213PB005SG
Z8F0213QB005SG
Z8F0213SB005SG
Z8F0213SH005SG
Z8F0213HH005SG
Z8F0213PH005SG
Z8F0213SJ005SG
Z8F0213HJ005SG
Z8F0213PJ005SG
2 KB 512 B
2 KB 512 B
2 KB 512 B
6
6
6
12
12
12
18
18
18
18
18
18
2
2
2
2
2
2
2
2
2
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
PDIP 8-pin package
QFN 8-pin package
SOIC 8-pin package
SOIC 20-pin package
SSOP 20-pin package
PDIP 20-pin package
SOIC 28-pin package
SSOP 28-pin package
PDIP 28-pin package
2 KB 512 B 16
2 KB 512 B 16
2 KB 512 B 16
2 KB 512 B 24
2 KB 512 B 24
2 KB 512 B 24
Extended Temperature: –40°C to 105°C
Z8F0213PB005EG
Z8F0213QB005EG
Z8F0213SB005EG
Z8F0213SH005EG
Z8F0213HH005EG
Z8F0213PH005EG
Z8F0213SJ005EG
Z8F0213HJ005EG
Z8F0213PJ005EG
2 KB 512 B
2 KB 512 B
2 KB 512 B
6
6
6
12
12
12
18
18
18
18
18
18
2
2
2
2
2
2
2
2
2
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
PDIP 8-pin package
QFN 8-pin package
SOIC 8-pin package
SOIC 20-pin package
SSOP 20-pin package
PDIP 20-pin package
SOIC 28-pin package
SSOP 28-pin package
PDIP 28-pin package
2 KB 512 B 16
2 KB 512 B 16
2 KB 512 B 16
2 KB 512 B 24
2 KB 512 B 24
2 KB 512 B 24
PS024317-0914
P R E L I M I N A R Y
Ordering Information
Z8 Encore! XP® F0823 Series
Product Specification
219
Table 135. Z8 Encore! XP F0823 Series Ordering Matrix (Continued)
Z8 Encore! XP F0823 Series with 1 KB Flash, 10-Bit Analog-to-Digital Converter
Standard Temperature: 0°C to 70°C
Z8F0123PB005SG
Z8F0123QB005SG
Z8F0123SB005SG
Z8F0123SH005SG
Z8F0123HH005SG
Z8F0123PH005SG
Z8F0123SJ005SG
Z8F0123HJ005SG
Z8F0123PJ005SG
1 KB 256 B
1 KB 256 B
1 KB 256 B
6
6
6
12
12
12
18
18
18
18
18
18
2
2
2
2
2
2
2
2
2
4
4
4
7
7
7
8
8
8
1
1
1
1
1
1
1
1
1
PDIP 8-pin package
QFN 8-pin package
SOIC 8-pin package
SOIC 20-pin package
SSOP 20-pin package
PDIP 20-pin package
SOIC 28-pin package
SSOP 28-pin package
PDIP 28-pin package
1 KB 256 B 16
1 KB 256 B 16
1 KB 256 B 16
1 KB 256 B 22
1 KB 256 B 22
1 KB 256 B 22
Extended Temperature: –40°C to 105°C
Z8F0123PB005EG
Z8F0123QB005EG
Z8F0123SB005EG
Z8F0123SH005EG
Z8F0123HH005EG
Z8F0123PH005EG
Z8F0123SJ005EG
Z8F0123HJ005EG
Z8F0123PJ005EG
1 KB 256 B
1 KB 256 B
1 KB 256 B
6
6
6
12
12
12
18
18
18
18
18
18
2
2
2
2
2
2
2
2
2
4
4
4
7
7
7
8
8
8
1
1
1
1
1
1
1
1
1
PDIP 8-pin package
QFN 8-pin package
SOIC 8-pin package
SOIC 20-pin package
SSOP 20-pin package
PDIP 20-pin package
SOIC 28-pin package
SSOP 28-pin package
PDIP 28-pin package
1 KB 256 B 16
1 KB 256 B 16
1 KB 256 B 16
1 KB 256 B 22
1 KB 256 B 22
1 KB 256 B 22
PS024317-0914
P R E L I M I N A R Y
Ordering Information
Z8 Encore! XP® F0823 Series
Product Specification
220
Table 135. Z8 Encore! XP F0823 Series Ordering Matrix (Continued)
Z8 Encore! XP F0823 Series with 1 KB Flash
Standard Temperature: 0°C to 70°C
Z8F0113PB005SG
Z8F0113QB005SG
Z8F0113SB005SG
Z8F0113SH005SG
Z8F0113HH005SG
Z8F0113PH005SG
Z8F0113SJ005SG
Z8F0113HJ005SG
Z8F0113PJ005SG
1 KB 256 B
1 KB 256 B
1 KB 256 B
6
6
6
12
12
12
18
18
18
18
18
18
2
2
2
2
2
2
2
2
2
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
PDIP 8-pin package
QFN 8-pin package
SOIC 8-pin package
SOIC 20-pin package
SSOP 20-pin package
PDIP 20-pin package
SOIC 28-pin package
SSOP 28-pin package
PDIP 28-pin package
1 KB 256 B 16
1 KB 256 B 16
1 KB 256 B 16
1 KB 256 B 24
1 KB 256 B 24
1 KB 256 B 24
Extended Temperature: –40°C to 105°C
Z8F0113PB005EG
Z8F0113QB005EG
Z8F0113SB005EG
Z8F0113SH005EG
Z8F0113HH005EG
Z8F0113PH005EG
Z8F0113SJ005EG
Z8F0113HJ005EG
Z8F0113PJ005EG
1 KB 256 B
1 KB 256 B
1 KB 256 B
6
6
6
12
12
12
18
18
18
18
18
18
2
2
2
2
2
2
2
2
2
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
PDIP 8-pin package
QFN 8-pin package
SOIC 8-pin package
SOIC 20-pin package
SSOP 20-pin package
PDIP 20-pin package
SOIC 28-pin package
SSOP 28-pin package
PDIP 28-pin package
1 KB 256 B 16
1 KB 256 B 16
1 KB 256 B 16
1 KB 256 B 24
1 KB 256 B 24
1 KB 256 B 24
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Ordering Information
Z8 Encore! XP® F0823 Series
Product Specification
221
Table 135. Z8 Encore! XP F0823 Series Ordering Matrix (Continued)
Z8 Encore! XP F0823 Series Development Kit
Z8F08A28100KITG
Z8F04A28100KITG
Z8F04A08100KITG
ZUSBSC00100ZACG
ZUSBOPTSC01ZACG
ZENETSC0100ZACG
Z8 Encore! XP F082A Series Development Kit (20- and 28-Pin)
Z8 Encore! XP F042A Series Development Kit (20- and 28-Pin)
Z8 Encore! XP F042A Series Development Kit (8-Pin)
USB Smart Cable Accessory Kit
Opto-Isolated USB Smart Cable Accessory Kit
Ethernet Smart Cable Accessory Kit
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Z8 Encore! XP® F0823 Series
Product Specification
222
Part Number Suffix Designations
Zilog part numbers consist of a number of components, as indicated in the following
example.
Example. Part number Z8F0423SH005SG is an 8-bit 20MHz Flash MCU with 4KB of
Program Memory and equipped with 6–22 I/O lines and 4–8 ADC channels in a 20-pin
SOIC package, operating within a 0ºC to +70ºC temperature range and built using lead-
free solder.
Z8
F
04 23
S
H
005
S
G
Environmental Flow
G = Green Plastic Packaging Compound
Temperature Range
S = Standard, 0°C to 70°C
E = Extended, –40°C to +105°C
Speed
020 = 20MHz
Pin Count
B = 8
H = 20
J = 28
Package
H = SSOP
P = PDIP
S = SOIC
Device Type
23 = 6–22 I/O lines, 4–8 ADC channels
13 = 6–24 I/O lines, no ADC channels
Memory Size
08 = 8 KB Flash, 1 KB RAM
04 = 4 KB Flash, 1 KB RAM
02 = 2 KB Flash, 512 B RAM
01 = 1 KB Flash, 256 B RAM
Memory Type
F = Flash
Device Family
Z8 = Zilog’s 8-Bit Microcontroller
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Z8 Encore! XP® F0823 Series
Product Specification
223
Index
b 176
Numerics
10-bit ADC 4
baud rate generator, UART 108
BCLR 179
binary number suffix 177
BIT 179
bit 176
A
absolute maximum ratings 196
AC characteristics 200
ADC 178
clear 179
manipulation instructions 179
set 179
set or clear 179
swap 179
architecture 121
block diagram 122
continuous conversion 124
control register 126, 129
control register definitions 126
data high byte register 130
data low bits register 131
electrical characteristics and timing 203
operation 122
test and jump 181
test and jump if non-zero 181
test and jump if zero 181
bit jump and test if non-zero 181
bit swap 181
block diagram 3
block transfer instructions 179
BRK 181
BSET 179
BSWAP 179, 181
BTJ 181
BTJNZ 181
BTJZ 181
single-shot conversion 123
ADCCTL register 126, 129
ADCDH register 130
ADCDL register 131
ADCX 178
ADD 178
add - extended addressing 178
add with carry 178
add with carry - extended addressing 178
additional symbols 177
address space 13
ADDX 178
analog signals 10
analog-to-digital converter (ADC) 121
AND 181
ANDX 181
arithmetic instructions 178
assembly language programming 174
assembly language syntax 175
C
CALL procedure 181
Capture Mode 89
Capture/Compare Mode 89
cc 176
CCF 180
characteristics, electrical 196
clear 180
CLR 180
COM 181
Compare 89
compare - extended addressing 178
Compare Mode 89
compare with carry 178
B
B 177
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Z8 Encore! XP® F0823 Series
Product Specification
224
compare with carry - extended addressing 178
complement 181
Watchdog Timer 202, 204
enable interrupt 180
complement carry flag 179, 180
condition code 176
ER 176
extended addressing register 176
external pin reset 25
eZ8 CPU features 4
eZ8 CPU instruction classes 178
eZ8 CPU instruction notation 176
eZ8 CPU instruction set 174
eZ8 CPU instruction summary 182
continuous conversion (ADC) 124
Continuous Mode 88
control register definition, UART 108
Control Registers 13, 16
Counter modes 89
CP 178
CPC 178
CPCX 178
CPU and peripheral overview 4
CPU control instructions 180
CPX 178
F
FCTL register 141, 148, 149
features, Z8 Encore! 1
first opcode map 194
FLAGS 177
Customer Support 230
flags register 177
flash
D
DA 176, 178
controller 4
data memory 15
DC characteristics 197
debugger, on-chip 156
DEC 178
decimal adjust 178
decrement 178
option bit address space 149
option bit configuration - reset 146
program memory address 0000h 149
program memory address 0001h 150
flash memory 134
arrangement 135
decrement and jump non-zero 181
decrement word 178
DECW 178
byte programming 139
code protection 137
configurations 134
destination operand 177
device, port availability 33
DI 180
direct address 176
disable interrupts 180
DJNZ 181
control register definitions 141, 148
controller bypass 140
electrical characteristics and timing 202
flash control register 141, 148, 149
flash option bits 138
flash status register 142
flow chart 136
dst 177
frequency high and low byte registers 144
mass erase 139
E
operation 135
operation timing 137
page erase 139
EI 180
electrical characteristics 196
ADC 203
page select register 142, 144
FPS register 142, 144
FSTAT register 142
flash memory and timing 202
GPIO input data sample timing 204
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Z8 Encore! XP® F0823 Series
Product Specification
225
indirect register pair 176
G
indirect working register 176
indirect working register pair 176
infrared encoder/decoder (IrDA) 117
Instruction Set 174
instruction set, eZ8 CPU 174
instructions
Gated Mode 89
general-purpose I/O 33
GPIO 4, 33
alternate functions 34
architecture 34
control register definitions 40
input data sample timing 204
interrupts 40
Port A–C Pull-Up Enable subregisterss 47, 48,
49
Port A–H Address registers 41
Port A–H Alternate Function subregisters 43
Port A–H Control registers 42
Port A–H Data Direction subregisters 43
Port A–H High Drive Enable subregisters 45
Port A–H Input Data registers 50
Port A–H Output Control subregisters 44
Port A–H Output Data registers 51
Port A–H Stop-Mode Recovery subregisters 46
port availability by device 33
port input timing 205
ADC 178
ADCX 178
ADD 178
ADDX 178
AND 181
ANDX 181
arithmetic 178
BCLR 179
BIT 179
bit manipulation 179
block transfer 179
BRK 181
BSET 179
BSWAP 179, 181
BTJ 181
BTJNZ 181
BTJZ 181
port output timing 206
CALL 181
CCF 179, 180
CLR 180
COM 181
CP 178
CPC 178
H
HALT 180
Halt Mode 31, 180
hexadecimal number prefix/suffix 177
CPCX 178
CPU control 180
CPX 178
DA 178
DEC 178
DECW 178
DI 180
DJNZ 181
EI 180
HALT 180
INC 178
INCW 178
IRET 181
JP 181
I
I2C 4
IM 176
immediate data 176
immediate operand prefix 177
INC 178
increment 178
increment word 178
INCW 178
indexed 177
indirect address prefix 177
indirect register 176
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Z8 Encore! XP® F0823 Series
Product Specification
226
LD 180
LDC 180
Interrupt Controller 54
interrupt controller
LDCI 179, 180
LDE 180
LDEI 179
architecture 54
interrupt assertion types 57
interrupt vectors and priority 57
operation 56
LDX 180
LEA 180
load 180
logical 181
MULT 179
NOP 180
OR 181
ORX 181
POP 180
POPX 180
register definitions 59
software interrupt assertion 58
interrupt edge select register 66
interrupt request 0 register 59
interrupt request 1 register 60
interrupt request 2 register 61
interrupt return 181
interrupt vector listing 54
interrupts
program control 181
PUSH 180
UART 105
IR 176
PUSHX 180
RCF 179, 180
RET 181
Ir 176
IrDA
architecture 117
RL 181
block diagram 117
RLC 181
rotate and shift 181
RR 182
control register definitions 120
operation 117
receiving data 119
RRC 182
SBC 179
transmitting data 118
IRET 181
SCF 179, 180
SRA 182
SRL 182
IRQ0 enable high and low bit registers 61
IRQ1 enable high and low bit registers 63
IRQ2 enable high and low bit registers 65
IRR 176
SRP 180
STOP 180
Irr 176
SUB 179
SUBX 179
SWAP 182
TCM 179
J
JP 181
TCMX 179
TM 179
TMX 179
jump, conditional, relative, and relative conditional
181
TRAP 181
Watchdog Timer refresh 180
XOR 181
XORX 181
instructions, eZ8 classes of 178
interrupt control register 68
L
LD 180
LDC 180
LDCI 179, 180
LDE 180
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Z8 Encore! XP® F0823 Series
Product Specification
227
LDEI 179, 180
LDX 180
N
NOP (no operation) 180
notation
b 176
LEA 180
load 180
load constant 179
cc 176
DA 176
ER 176
IM 176
IR 176
Ir 176
IRR 176
Irr 176
p 176
R 176
r 176
RA 177
RR 177
rr 177
vector 177
X 177
load constant to/from program memory 180
load constant with auto-increment addresses 180
load effective address 180
load external data 180
load external data to/from data memory and auto-
increment addresses 179
load external to/from data memory and auto-incre-
ment addresses 180
load instructions 180
load using extended addressing 180
logical AND 181
logical AND/extended addressing 181
logical exclusive OR 181
logical exclusive OR/extended addressing 181
logical instructions 181
logical OR 181
logical OR/extended addressing 181
low power modes 30
notational shorthand 176
O
OCD
M
architecture 156
master interrupt enable 56
memory
auto-baud detector/generator 159
baud rate limits 160
block diagram 156
breakpoints 161
commands 162
control register 166
data format 159
DBG pin to RS-232 Interface 157
Debug Mode 158
debugger break 181
interface 157
serial errors 160
status register 168
data 15
program 13
mode
Capture 89
Capture/Compare 89
Continuous 88
Counter 89
Gated 89
One-Shot 88
PWM 89
modes 89
MULT 179
multiply 179
MULTIPROCESSOR mode, UART 103
timing 207
OCD commands
execute instruction (12h) 166
read data memory (0Dh) 165
read OCD control register (05h) 163
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Z8 Encore! XP® F0823 Series
Product Specification
228
read OCD revision (00h) 163
read OCD status register (02h) 163
read program counter (07h) 164
read program memory (0Bh) 164
read program memory CRC (0Eh) 165
read register (09h) 164
power supply signals 10
Power-on and Voltage Brownout electrical charac-
teristics and timing 201
Power-On Reset (POR) 23
program control instructions 181
program counter 177
read runtime counter (03h) 163
step instruction (10h) 165
stuff instruction (11h) 166
write data memory (0Ch) 165
write OCD control register (04h) 163
write program counter (06h) 163
write program memory (0Ah) 164
write register (08h) 164
program memory 13
PUSH 180
push using extended addressing 180
PUSHX 180
PWM mode 89
PxADDR register 41
PxCTL register 42
on-chip debugger (OCD) 156
on-chip debugger signals 10
One-Shot Mode 88
R
R 176
opcode map
r 176
RA
abbreviations 193
cell description 192
first 194
second after 1Fh 195
register address 177
RCF 179, 180
receive
Operational Description 21, 30, 33, 69, 91, 97, 117,
121, 132, 134, 146, 156, 169, 173
OR 181
ordering information 211
ORX 181
IrDA data 119
receiving UART data-interrupt-driven method 102
receiving UART data-polled method 101
register 176
ADC control (ADCCTL) 126, 129
ADC data high byte (ADCDH) 130
ADC data low bits (ADCDL) 131
flash control (FCTL) 141, 148, 149
flash high and low byte (FFREQH and FRE-
EQL) 144
P
p 176
Packaging 210
part selection guide 2
PC 177
peripheral AC and DC electrical characteristics 201
pin characteristics 11
Pin Descriptions 7
flash page select (FPS) 142, 144
flash status (FSTAT) 142
GPIO Port A–H address (PxADDR) 41
GPIO Port A–H alternate function subregisters
44
polarity 176
POP 180
pop using extended addressing 180
POPX 180
GPIO Port A–H control address (PxCTL) 42
GPIO Port A–H data direction subregisters 43
OCD control 166
OCD status 168
port availability, device 33
port input timing (GPIO) 205
port output timing, GPIO 206
UARTx baud rate high byte (UxBRH) 115
UARTx baud rate low byte (UxBRL) 115
UARTx Control 0 (UxCTL0) 112, 115
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Product Specification
229
UARTx control 1 (UxCTL1) 113
UARTx receive data (UxRXD) 109
UARTx status 0 (UxSTAT0) 110
UARTx status 1 (UxSTAT1) 111
UARTx transmit data (UxTXD) 109
Watchdog Timer control (WDTCTL) 94, 133
watch-dog timer control (WDTCTL) 172
Watchdog Timer reload high byte (WDTH) 95
Watchdog Timer reload low byte (WDTL) 95
Watchdog Timer reload upper byte (WDTU)
95
software trap 181
source operand 177
SP 177
SRA 182
src 177
SRL 182
SRP 180
stack pointer 177
STOP 180
Stop Mode 30, 180
Stop-Mode Recovery
sources 26
register file 13
register pair 177
register pointer 177
reset
using a GPIO port pin transition 27, 28
using Watchdog Timer time-out 27
SUB 179
and Stop Mode characteristics 21
and Stop-Mode Recovery 21
carry flag 179
subtract 179
subtract - extended addressing 179
subtract with carry 179
subtract with carry - extended addressing 179
SUBX 179
sources 23
RET 181
return 181
SWAP 182
RL 181
RLC 181
swap nibbles 182
symbols, additional 177
rotate and shift instructions 181
rotate left 181
rotate left through carry 181
rotate right 182
rotate right through carry 182
RP 177
RR 177, 182
rr 177
T
TCM 179
TCMX 179
test complement under mask 179
test complement under mask - extended addressing
179
test under mask 179
test under mask - extended addressing 179
timer signals 9
RRC 182
S
timers 69
SBC 179
architecture 70
SCF 179, 180
block diagram 70
second opcode map after 1Fh 195
set carry flag 179, 180
set register pointer 180
shift right arithmetic 182
shift right logical 182
signal descriptions 9
single-sho conversion (ADC) 123
Capture Mode 78, 79, 89
Capture/Compare Mode 82, 89
Compare Mode 80, 89
Continuous Mode 71, 88
Counter Mode 72, 73
Counter modes 89
Gated Mode 81, 89
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Product Specification
230
One-Shot Mode 70, 88
UxSTAT1 register 111
operating mode 70
UxTXD register 109
PWM mode 75, 76, 89
reading the timer count values 83
reload high and low byte registers 84
timer control register definitions 83
timer output signal operation 83
V
vector 177
Voltage Brownout reset (VBR) 24
timers 0-3
control registers 86, 87
high and low byte registers 83, 86
TM 179
TMX 179
tools, hardware and software 220
W
Watchdog Timer
approximate time-out delay 91
CNTL 24
transmit
control register 94, 171
electrical characteristics and timing 202, 204
interrupt in normal operation 92
interrupt in Stop Mode 92
refresh 92, 180
reload unlock sequence 93
reload upper, high and low registers 94
reset 25
IrDA data 118
transmitting UART data-polled method 99
transmitting UART dat-interrupt-driven method
100
TRAP 181
U
reset in normal operation 93
reset in Stop Mode 93
time-out response 92
UART 4
architecture 97
baud rate generator 108
control register definitions 108
controller signals 9
interrupts 105
Watchdog Timer Control Register (WDTCTL) 94
WDTCTL register 94, 133, 172
WDTH register 95
WDTL register 95
MULTIPROCESSOR mode 103
receiving data using interrupt-driven method
102
WDTU register 95
working register 176
working register pair 177
receiving data using the polled method 101
transmitting data using the interrupt-driven
method 100
X
transmitting data using the polled method 99
x baud rate high and low registers 115
x control 0 and control 1 registers 112
x status 0 and status 1 registers 110, 111
UxBRH register 115
X 177
XOR 181
XORX 181
UxBRL register 115
UxCTL0 register 112, 115
UxCTL1 register 113
UxRXD register 109
UxSTAT0 register 110
Z
Z8 Encore!
block diagram 3
features 1
part selection guide 2
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Z8 Encore! XP® F0823 Series
Product Specification
231
Customer Support
To share comments, get your technical questions answered, or report issues you may be
experiencing with our products, please visit Zilog’s Technical Support page at
http://support.zilog.com.
To learn more about this product, find additional documentation, or to discover other fac-
ets about Zilog product offerings, please visit the Zilog Knowledge Base at http://
zilog.com/kb or consider participating in the Zilog Forum at http://zilog.com/forum.
This publication is subject to replacement by a later edition. To determine whether a later
edition exists, please visit the Zilog website at http://www.zilog.com.
PS024317-0914
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Customer Support
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