Z90102 [ZILOG]
40-Pin Low-Cost Digital Television Controller; 40引脚低成本的数字电视控制器
| 型号： | Z90102 |
| 厂家： | 
ZILOG, INC. |
| 描述： | 40-Pin Low-Cost Digital Television Controller |
| 文件： | 总36页 (文件大小：233K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRODUCT SPECIFICATION
1
Z90102/103/104
1
40-PIN LOW-COST DIGITAL
TELEVISION CONTROLLER
FEATURES
■ Clock Speed up to 4 MHz
8-Bit CMOS Microcontroller for Consumer
Television, Cable and Satellite Receiver Ap-
plications.
■ On-Chip Oscillator that Accepts a Crystal, Ceramic
Resonator, LC or External Clock Drive
ROM
(KB)
RAM*
(Bytes)
■ Permanently Enabled
Device
I/O
Watch-Dog/Power-On Reset Timer
Z90102
Z90103
Z90104
4
6
8
236
236
236
24
24
24
■ 3K x 6-Bit Character Generator ROM
■ 120 x 7-Bit Video RAM
Note: *General-Purpose
■ Mask Programmable 96-Character Set Display. The
90102 and 90103 6-Row x 20 Column Format, 12x15
Pixel Character Cell. The 90104 8-Row x 20 Column
Format 12x15 Pixel Character Cell. The 90102, 90103
90104 Capable of supporting English, Korean, Thai,
Chinese and Japanese High Resolution Characters.
■ Lowest Cost DTC Family Member
■ Low Power Consumption
■ Fast Instruction Pointer - 1.5 ms @ 4 MHz
■ Two Standby Modes - STOP and HALT
■ Fully Programmable Color Attributes Including Row
Character,
Row
Background/Fringes,
Frame
■ Low Voltage Detection/Voltage Sensitive Reset
Background/Position, Bar Graph Color Change, and
Character Size.
■ Port 2 (8-Bit Programmable I/O) and Port 3 (2-Bit Input,
3-Bit Output) Register Mapped Ports
■ Programmable Display Position and Character Size
Control
■ Port 6 (6-Bit Input and Tristate Comparator AFC Input)
Memory Mapped I/O Ports
■ One Pulse Width Modulator (14-Bit Resolution) for
Voltage Synthesis Tuner Control.
■ All Digital CMOS Levels Schmitt-Triggered
■ Three Pulse Width Modulator (8-Bit Resolution) for
■ Two Programmable 8-Bit Counter/Timers each with 6-
Picture Control
Bit Programmable Prescaler.
■ Three Pulse Width Modulators (6-Bit Resolution) for
■ Six Vectored, Priority Interrupts from Six Different
Audio Control
Sources
GENERAL DESCRIPTION
The Z90102/3/4 40-pin Low-Cost Digital Television Con-
troller are members of the Z8 STOP Mode MCU single-
CMOS compatible. The DTC offers mask programmed
ROM which enables the Z8 MCU to be used in a high vol-
®
®
chip family with 4, 6, and 8 KB of ROM and 236 bytes of
RAM. The device is offered in a 40-pin package and is
ume production application device embedded with a cus-
tom program (customer supplied program) and combines
DS97TEL1902
1
Z90102/90103/90104
40-Pin Low-Cost Digital Television Controller
Zilog
GENERAL DESCRIPTION (Continued)
together with the Z86C27 and Z86127 to provide support
for mid range and low end TV applications.
For DTC applications demanding powerful I/O capabili-
ties, the Z90102/3/4 fulfills this with 24 I/O pins dedicated
to input and output. These lines are grouped into three
ports, and are configurable under software control to pro-
vide timing, status signals, parallel I/O and an address/da-
ta bus for interfacing to external memory.
Zilog’s DTC offers fast execution, efficient use of memory,
sophisticated interrupts, input/output bit manipulation ca-
pabilities, and easy hardware/software system expansion
along with low cost and low power consumption. The de-
vice provides an ideal performance and reliability solution
for consumer and industrial television applications.
There are three basic address spaces available to support
this wide range of configurations: Program Memory, Video
RAM, and Register File. The Register File is composed of
236 bytes of general-purpose registers, two I/O Port regis-
ters, 15 control and status registers and three reserved
registers.
The Z90102/3/4 architecture is characterized by utilizing
Zilog’s advanced Superintegration™ design methodology.
The device has an 8-bit internal data path controlled by a
Z8 microcontroller and On Screen Display (OSD) logic cir-
cuits and Pulse Width Modulators (PWM). On-chip periph-
erals include two register mapped I/O ports (Ports 2 and
3), interrupt control logic (one software, two external and
three internal interrupts) and a standby mode recovery in-
put port (Port 3, P30).
To unburden the program from coping with the real-time
problems such as counting/timing and data communica-
tion, the DTC offers two on-chip counter/timers with a large
number of user selectable modes (Figure 1).
Notes: All signals with a preceding front slash, "/", are ac-
tive Low. For example, B//W (WORD is active Low); /B/W
(BYTE is active Low, only).
The OSD control circuits support 6 rows x 20 columns of
characters. The character color is specified by row. One of
the six rows is assigned to show two kinds of colors for bar
type displays such as volume control. The OSD is capable
of displaying either low resolution (5 x 7 dot pattern) or high
resolution (11 x 15 dot pattern) characters.
Power connections follow conventional descriptions be-
low:
Connection
Power
Circuit
Device
A 14-bit PWM port provides enough voltage resolution for
a voltage synthesizer tuning system. Three 6-bit PWM
ports are used for controlling audio signal levels. Three 8-
bit PWM ports used to vary picture levels.
V
V
DD
CC
Ground
GND
V
SS
2
DS97TEL1902
Z90102/90103/90104
40-Pin Low-Cost Digital Television Controller
Zilog
XTAL1
XTAL2
/RESET
P27
P26
P25
RESET
Oscillator
WDT
4, 6 or 8 KB
Program ROM
1
Counter
Timer
Port 2
P24
P23
Z8 CPU
Core
Counter
Timer
P22
P21
P20
P30
P31
P34
P35
P36
Port 3/
Interrupt
PWM 1
14 -bit
PWM 1
256 Byte
Register File
P60
P61
P62
PWM 6
to
PWM 8
6-bit
PWM 6
PWM 7
PWM 8
Port 6
P63
P64
P65
Port 0
A8-15
Port 1
AD0-7
AFCIN
PWM 9
to
PWM 11
8-bit
PWM 9
PWM 10
PWM 11
OSCIN
OSCOUT
HSYNC
120 Byte
On-Screen
Display
Character RAM
VSYNC
VRED
VGREEN
VBLUE
3 Kbyte
Character ROM
VBLANK
Figure 1. Functional Block Diagram
DS97TEL1902
3
Z90102/90103/90104
40-Pin Low-Cost Digital Television Controller
Zilog
PIN DESCRIPTION
1
PWM1
P35
21
PWM6
PWM7
PWM8
PWM9
PWM10
PWM11
P27
P26
P25
P24
P23
P36
P34
P31
P30
XTAL1
XTAL2
/RESET
P60
Z90102
Z90103
Z90104
40-Pin DIP
GND
P61
P22
P62
P21
VCC
P20
P63
P64
P65
VBLANK
VBLUE
VGREEN
VRED
VSYNC
HSYNC
AFCIN
OSCIN
OSCOUT
20
40
Figure 2. 40-Pin Mask-ROM Plastic DIP
Table 1. 40-Pin Mask-ROM Plastic DIP
Function
40-Pin
Name
Direction
1
PWM1
P35-36
P34
Pulse Width Modulator 1
Port 3, Pins 5, 6
Port 3, Pin 4
Output
Output
Output
Input
2, 3
4
5
P31
Port 3, Pin 1
6
P30
Port 3, Pin 0
Input
7
XTAL1
XTAL2
/RESET
P60
Crystal Oscillator
Crystal Oscillator
System Reset
Port 6, Pin 0
Input
8
Output
Input
9
10
11
12
13
14
Input
GND
P61
Ground
Input
Port 6, Pin 1
Input
P62
Port 6, Pin 2
Input
V
Power Supply
Input
CC
15, 16, 17
18
P63-65
AFC
Port 6, Pins 3, 4, 5
AFC Voltage Level
Input
Input
IN
19
20
OSC
OSC
Video Dot Clock Osc
Video Dot Clock Osc
Input
IN
Output
OUT
21
22
23
HSYNC
VSYNC
Vred
Horizontal Sync
Vertical Sync
Video Red
Input
Input
Output
4
DS97TEL1902
Z90102/90103/90104
40-Pin Low-Cost Digital Television Controller
Zilog
Table 1. 40-Pin Mask-ROM Plastic DIP
40-Pin
Name
Function
Direction
24
Vgreen
Vblue
Video Green
Output
Output
Output
In/Output
Output
Output
Output
Output
Output
Output
1
25
Video Blue
26
Vblank
P20-27
PWM11
PWM10
PWM9
PWM8
PWM7
PWM6
Video Blank
27-34
35
Port 2, Pins 0,1,2,3,4,5,6,7
Pulse Width Modulator 11
Pulse Width Modulator 10
Pulse Width Modulator 9
Pulse Width Modulator 8
Pulse Width Modulator 7
Pulse Width Modulator 6
36
37
38
39
40
DS97TEL1902
5
Z90102/90103/90104
40-Pin Low-Cost Digital Television Controller
Zilog
PIN DESCRIPTION
XTAL1, XTAL2. (time-based input, output, respectively).
These pins connect to the internal parallel-resonant clock
crystal (4 MHz max) oscillator circuit with two capacitors
to GND. XTAL1 is also used as an external clock input.
Port 3 (P30, P31, P34-P36). Port 3, P30 input, is read di-
rectly. If appropriately enabled, a negative edge event is
latched in IRQ3 to initiate an IRQ3 vectored interrupt. An
application could place the device in STOP Mode when
P30 goes Low (in the IRQ3 interrupt routine). P30 initiates
a STOP Mode recovery when it subsequently goes to a
High. Port 3, P31 are read directly. If appropriately en-
abled, a negative edge event is latched in IRQ2 to initiate
an IRQ2 vectored interrupt. P31 High is signified as the
TIN signal to Timer1. Port 3, P34 and P35 are general-pur-
pose output lines. Port 3, P36 can be used as a general-
purpose output or as an output for TOUT (from Timer1 or
Timer2) or SCLK (Figure 10).
SCLK System Clock. SCLK is the internal system clock.
It can be used to clock external glue logic.
HSYNC (input, Schmitt triggered, CMOS level). Horizontal
Sync is an input pin that accepts an externally generated
Horizontal Sync signal of either negative or positive polar-
ity.
VSYNC (input,Schmitt-triggered, CMOS level). Vertical
Sync is an input pin that accepts an externally generated
Vertical Sync signal of either negative or positive polarity.
Port 6 (P65-P60). Port 6 is a 6-bit, Schmitt triggered
CMOS compatible, input port. The outputs of the AFC
comparators internally feed into the Port 6, bit 6 and bit 7
inputs (Figure 11).
OSCIN, OSCOUT (Video Oscillator input, output, respec-
tively). Oscillator input and output pins for on-screen dis-
play circuits. These pins connect to an inductor and two
capacitors to generate the character dot clock (typically
around 6 MHz). The dot clock frequency determines the
character pixel width and phase synchronized to HSYNC.
AFCIN (Comparator input port, memory mapped). The in-
put signal is supplied to two comparators with VTH1=2/5
V
and VTH2=3/5 V
typical threshold voltage. The
CC
CC
comparator outputs are internally connected to Port 6, bit
6 and bit 7. AFCIN is typically used to detect AFC voltage
level to accommodate digital automatic fine tuning func-
tions (Figure 12).
Vblank Video Blank (output). CMOS output, programma-
ble polarity. Used as a superimpose control port to display
characters from video RAM. The signal controls Y signal
output of the CRT and turns off the incoming video display
while the characters in video RAM are superimposed on
the screen. The red, green, and blue outputs drive the
three electron guns on the CRT directly, while the blank
output turns off the Y signal.
Pulse Width Modulator 1 (PWM). PWM1 is typically used
as the D/A converter for Voltage Synthesis Tuning sys-
tems. It is a push-pull output with 14-bit resolution.
Pulse Width Modulator 6-8 (PWM). PWM8-PWM6 are
Pulse Width Modulators with 6-bit resolution.
Vblue Video Blue (output). CMOS Output of the Blue vid-
eo signal (B-Y) and is programmable for either polarity.
Pulse Width Modulator 9, 10, 11 (PWM). Pulse Width
Modulator circuits with 8-bit resolution. These PWMs are
12 volt, open-drain outputs.
Vgreen Video Green (output). CMOS Output of the Green
video signal (G-Y) and is programmable for either polarity.
Pulse Width Modulator 1, 6, 7, 8 (PWM). Can be pro-
Vred Video Red (output). CMOS Output of the Red video
signal (R-Y) and is programmable for either polarity.
grammed as general-purpose outputs. PWM 1 is 5 V
OH
push-pull, and PWMs 6, 7, 8 are 12 volt open-drain out-
puts.
Port 2 (P27-P20). Port 2 is an 8-bit port, CMOS-compati-
ble, bit programmable for either input or output. Input buff-
ers are Schmitt triggered. Bits programmed as outputs
may be globally programmed as either push pull or open-
drain (Figure 9).
/RESET System Reset. Code is executed from memory
address 000CH after the /RESET pin is set to a high level.
The reset function is also carried out by detecting a V
CC
transition state (automatic Power-On Reset) so that the
external reset pin can be permanently tied to V . A low
CC
level on /RESET forces a restart of the device.
6
DS97TEL1902
Z90102/90103/90104
40-Pin Low-Cost Digital Television Controller
Zilog
ABSOLUTE MAXIMUM RATINGS
Stresses greater than those listed under Absolute Maxi-
mum Ratings may cause permanent damage to the de-
vice. This is a stress rating only; operation of the device at
any condition above those indicated in the operational sec-
tions of this specification is not implied. Exposure to abso-
lute maximum rating conditions for extended periods may
affect device reliability.
1
Symbol
Parameters
Min
Max
Units
Notes
V
Power Supply
Voltage*
–0.3
+7
V
CC
V
V
Input Voltage
–0.3
–0.3
–0.3
V
V
+0.3
V
I
CC
Input Voltage
+0.3
V
1
I
CC
V
Output Voltage
13.2
V
2, 3
O
I
I
I
I
Output Current High
Output Current High
Output Current Low
Output Current Low
–10
–100
20
mA
mA
mA
mA
1 pin
OH
All total
1 pin
OH
OL
OL
200
All total
T
Operating
†
A
Temperature
T
Storage
–65
+150
C
STG
Temperature
Notes:
1. Port 2 open-drain
2. PWM open-drain outputs
3. Absolute maximum operating voltage 13.2V.
Absolute maximum momentary (non-operating) voltage is 16.0V.
* Voltage on all pins with respect to GND.
† See Ordering Information
STANDARD TEST CONDITIONS
The characteristics listed below apply for standard test
conditions as noted. All voltages are referenced to GND.
Positive current flows into the referenced pin (Figure 3).
VDD
RLL
From Output
Under Test
RLH
150 pF
Figure 3. Test Load Diagram
DS97TEL1902
7
Z90102/90103/90104
40-Pin Low-Cost Digital Television Controller
Zilog
CAPACITANCE
T = 25°C; V = GND = 0V; Freq =1.0 MHz; unmeasured pins to GND.
A
CC
Parameter
Max
Units
Input capacitance
10
20
pF
pF
Output
capacitance
I/O capacitance
25
10
pF
pF
AFCIN input
capacitance
DC CHARACTERISTICS
T = 0°C to +70°C; V = +4.5V to +5.5V; FOSC = 4 MHz
A
CC
T = 0°C to +70°C
Typical
A
Sym
Parameter
Min
Max
0.2 V
@ 25°C
1.48
Units
Conditions
V
Input Voltage Low
Input XTAL/Osc In Low
0
V
V
IL
CC
V
0.07 V
0.98
External Clock
ILC
CC
Generator Driven
V
Input Voltage High
0.7 V
0.8 V
V
V
3.0
3.2
V
V
IH
CC
CC
CC
V
Input XTAL/Osc In High
External Clock
Generator Driven
IHC
CC
V
V
Schmitt Hysteresis
0.1 V
0.8
V
V
HY
CC
Maximum Pull-Up
Voltage
13.2
1, 2
PU
V
Output Voltage Low
0.4
0.4
0.16
0.19
V
V
I
I
=1.00 mA
OL
OL
=0.75 mA 1
OL
V
AFC Level 01 In
AFC Level 11 In
Output Voltage High
Reset Input Current
Input Leakage
0.45 V
0.75 V
1.9
V
V
00-01
01-11
CC
V
0.5 V
3.12
4.75
–46
CC
CC
V
V
–0.4
V
I
=–0.75 mA
OH
CC
OH
I
–80
3.0
3.0
mA
mA
mA
V
=0
IR
RL
V
CC
CC
II
–3.0
–3.0
0.01
0.02
0V, V
0V, V
L
I
Tristate Leakage
Supply Current
OL
CC
I
20
6
10
13.2
3.2
2.0
mA
mA
mA
All inputs at rail &
outputs floating
I
I
CC1
CC2
Notes:
1. PWM open-drain
2. Recommended operating voltage 12V with maximum positive
tolerance 10%, i.e., 13.2V.
8
DS97TEL1902
Z90102/90103/90104
40-Pin Low-Cost Digital Television Controller
Zilog
AC CHARACTERISTICS
Timing Diagrams
1
3
1
XTAL1
3
2
2
Figure 4. External Clock
7
5
TIN
4
6
Figure 5. Counter Timer
IRQN
8
9
Figure 6. Interrupt Request
DS97TEL1902
9
Z90102/90103/90104
40-Pin Low-Cost Digital Television Controller
Zilog
VCC
11
10
Internal /RESET
12
External /RESET
Figure 7. Power-On Reset
HSYNC
OSC2
13
14
Figure 8. On-Screen Display
10
DS97TEL1902
Z90102/90103/90104
40-Pin Low-Cost Digital Television Controller
Zilog
AC CHARACTERISTICS
T = 0° C to +70° C; V = +4.5V to +5.5V; F
= 4 MHz
A
CC
OSC
1
No
Symbol
Parameter
Min
Max
Unit
1
TpC
Input Clock Period
250
1000
15
ns
ns
ns
ns
2
TrC,TfC
TwC
Clock Input Rise and Fall
Input Clock Width
3
125
70
4
TwTinL
TwTinH
TpTin
Timer Input Low Width
Timer Input High Width
Timer Input Period
5
3TpC
8TpC
6
7
TrTin,TfTin
TwIL
Timer Input Rise and Fall
Int Req Input Low
100
100
ns
ns
8a
8b
9
70
3TpC
3TpC
25
TwIL
TwIH
Int Request Input High
Power On Reset Delay
Low Voltage Detect to
10
11
TdPOR
TdLVIRES
ms
ns
200
Internal RESET
Condition
12
13
TwRES
TdHsOI
Reset Minimum Width
5TpC
2TpV
HSYNC Start to VOSC
Stop
3TpV
1TpV
12
14
TdHsOh
TdWDT
HSYNC End to VOSC
Start
15
WDT Refresh Time
ms
Notes:
Refer to DC Characteristics for details on switching levels.
DS97TEL1902
11
Z90102/90103/90104
40-Pin Low-Cost Digital Television Controller
Zilog
FUNCTIONAL DESCRIPTION
The Z8 DTCincorporates special functions to enhance the
Z8’s versatility in consumer, industrial and television con-
trol applications.
PWM1. It is a push-pull output.
PWMs 6 through 11. They have their maximum values
(on times) when all 1s are loaded in their PWM Value reg-
isters (and minimum value for all 0s). PWM1 has a maxi-
mum value for all 0s and minimum value for all 1s.
Pulse Width Modulator (PWM). The has seven PWM
channels (Figure 9). There are three types of PWM cir-
cuits: PWM1 (one channel of 14-bit resolution) typically
used for Voltage Synthesis Tuning, PWM8-PWM6 (three
channels of 6-bit resolution) typically used for audio level
control, and PWM9, 10, 11 (three channels of 8-bit resolu-
tion) typically used for picture level control. The PWM con-
trol registers are mapped into external memory and are ac-
cessed through LDE and LDEI instructions.
On-Screen Display (OSD). The OSD has a capability of
displaying 6 rows x 20 columns of 96 kinds of characters
for high resolution (11 x 15 dots) patterns (Figures 10 and
11).
/RESET
AD7-0
AD7-0
PWM Output
Port Reg
PWM Mod Reg
14-Bit Binary
XTAL
Down Counter
FC11h
7-0
FC10h
7-0
13-0
6-0
7-Bit
Comparator
Upper 7-Bit
Lower 7-Bit
13-7
0
14-Bit
PWM1
Reg
RS & DFF
PWM1 push-pull
output
13-7
6-0
AD7-0
Pulse
Distributor
FC12-3h
5-0
5-0
PWM6 (open-drain)
PWM7 (open-drain)
PWM8 (open-drain)
MPX
6-Bit
PWM6
Reg
RSFF
RSFF
RSFF
5-0
6-Bit
Comparator
AD7-0
FC18h
FC19h
FC1Ah
7-0
7-0
8-Bit
Comparator
8-Bit
PWM9
Reg
RSFF
RSFF
RSFF
PWM9 (open-drain)
PWM10 (open-drain)
PWM11 (open-drain)
7-0
AD7-0
FC1Bh
FC1Ch
FC1Dh
Figure 9. Pulse Width Modulator Block Diagram
12
DS97TEL1902
Z90102/90103/90104
40-Pin Low-Cost Digital Television Controller
Zilog
1
Figure 10. On-Screen Display Block Diagram
DS97TEL1902
13
Z90102/90103/90104
40-Pin Low-Cost Digital Television Controller
Zilog
FUNCTIONAL DESCRIPTION (Continued)
The OSD features are as follows:
characters. LDE or LDEI instructions are required to ac-
cess the Video RAM (Figure 11).
■ Character Color: Seven kinds of color are specified on
a row basis.
Hex
■ Character Pixel Size: Four character pixel sizes are
selected for a high resolution (1HL, 2HL, 3HL, and 4HL)
Horizontal Line (HL).
Address
FD00
Row 1 Attribute (ROW1_ATTR)
Row 1 Column 1 Character Data
■ Polarity Selections: Can select active low or high for
FD01
FD02
FD13
FD14
horizontal/vertical sync input and RGB outputs.
Row 1 Column 2 Through
Column 19 Character Data
■ Display Position: Can display 64 vertical positions by
4HL units and 64 horizontal positions by a 4-dot clock.
Row 1 Column 20 Character Data
■ Inter Row Spacing: Inter row vertical line spacing is set
FD20
from 2HL to 17HL.
Row 2 Attribute (ROW2_ATTR)
Row 2 Column 1 Character Data
FD21
FD22
FD33
■ Fade In/Out Control: Fade position can be determined
in vertical direction.
Row 2 Column 2 Through
Column 19 Character Data
■ Bar Line Type Display: One of the rows is selected to
display an analog bar line every half column by setting
second color with proper character set.
FD34
Row 2 Column 20 Character Data
FD40
FD54
Row 3 Video RAM Buffer
■ Fringe Function: Fringe off/on and the color selected.
FD60
FD74
■ Background Color: Eight kinds of color including black
Row 4 Video RAM Buffer
Row 5 Video RAM Buffer
Row 6 Video RAM Buffer
background color.
FD80
FD94
FDA0
■ ON/OFF Control: Character display, backgrounds are
turned on and off.
■ Number of Display Characters: 6 rows x 20 columns.
■ Character Set: 96 (11 x 15 dots).
FDB4
(7 Bits Wide)
MSB
LSB
Character Generator ROM. The character generator
ROM is organized as 3 KB of six bits. The ROM defines ei-
ther 11 x 15 dot (high resolution)
Figure 11. Video RAM Configuration
Video RAM. The Video RAM is organized as 8-row arrays
(21 x 7 bits each, Figure 11). The first location of each row
array contains the attribute for that row. Row attributes in-
clude programmable character color, row background col-
or and control for background off/on. The next 20 bytes
contain row character data. Each character byte contains
the ASCII code in order to select one of the 96 displayable
14
DS97TEL1902
Z90102/90103/90104
40-Pin Low-Cost Digital Television Controller
Zilog
( 7 Bits Wide)
Row 1 Attribute
ROW1
ROW2
FD20H
ROW3
ROW4
FD60H
FD00H
1
ROW5
FD80H
ROW6
FD40H
FDA0H
Row 1 Column 1 Character
Row 1 Column 2 Character
Row 1 Column 3 Character
FD01H
FD02H
FD03H
FD21H
FD22H
FD23H
FD41H
FD42H
FD43H
FD44H
FD61H
FD62H
FD63H
FD81H
FDA1H
FD82H
FD83H
FDA2H
FDA3H
FDA4H
Row 1 Column 4 Character
Row 1 Column 5 Character
FD04H
FD05H
FD24H
FD25H
FD26H
FD27H
FD28H
FD64H
FD65H
FD66H
FD67H
FD68H
FD84H
FD85H
FD86H
FD87H
FD88H
FD45H
FD46H
FD47H
FD48H
Row 1 Column 6 Character
Row 1 Column 7 Character
Row 1 Column 8 Character
Row 1 Column 9 Character
Row 1 Column 10 Character
FD06H
FD07H
FD08H
FD09H
FD0AH
FDA5H
FDA6H
FDA7H
FD29H
FD2AH
FD2BH
FD2CH
FD2DH
FD2EH
FD49H
FD4AH
FD4BH
FD4CH
FD4DH
FD4EH
FDA8H
FDA9H
FD69H
FD6AH
FD6BH
FD6CH
FD6DH
FD6EH
FD89H
FD8AH
Row 1 Column 11 Character
Row 1 Column 12 Character
Row 1 Column 13 Character
Row 1 Column 14 Character
Row 1 Column 15 Character
Row 1 Column 16 Character
Row 1 Column 17 Character
Row 1 Column 18 Character
Row 1 Column 19 Character
Row 1 Column 20 Character
FD0BH
FD0CH
FD0DH
FD0EH
FD0FH
FD10H
FD11H
FD12H
FD13H
FDAAH
FDABH
FDACH
FDADH
FD8BH
FD8CH
FD8DH
FD8EH
FD2FH
FD30H
FD4FH
FD50H
FDAEH
FDAFH
FD6FH
FD70H
FD8FH
FD90H
FD91H
FD92H
FD93H
FD31H
FD32H
FD51H
FD52H
FDB0H
FDB1H
FDB2H
FDB3H
FD71H
FD72H
FD73H
FD33H
FD53H
FD54H
FD14H FD34H
FD74H
FD94H
MSB
FDB4H
LSB
Figure 12. Video RAM Map
(Write/Read Registers)
DS97TEL1902
15
Z90102/90103/90104
40-Pin Low-Cost Digital Television Controller
Zilog
FUNCTIONAL DESCRIPTION (Continued)
Must be 00H
at each pattern
Hex
Address
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
0
0
0
1
0
0
0
0
1
0
1
0
0
0
1
1
0
0
0
1
1
1
0
1
1
0
0
1
0
1
1
1
0
0
1
1
0
0
1
0
0
1
0
0
0
0
1
1
0
0
0
0
1
0
0
0
0
1
1
0
0
0
1
0
0 0
0 0
1 0
1 0
1 0
1 0
0 1
1 0
0 0
1 0
0 0
1 0
0 0
1 0
1 1
1 1
1 0
1 0
1 0
1 0
1 1
1 0
1 0
1 0
1 0
1 1
1 1
1 0
1 0
1 0
1 1
1 0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
1
1
0
0
0
1
1
1
0
1
1
0
0
1
0
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Left Half
Right Half
20
¯
3F
High Resolution
Character Pattern
FC0
¯
FDF
High Resolution
Character Pattern
FE0
¯
FFF
High Resolution
Character Pattern
MSB
(6 Bits Wide)
LSB
Figure 13. High Resolution Character ROM Configuration
16
DS97TEL1902
Z90102/90103/90104
40-Pin Low-Cost Digital Television Controller
Zilog
Program Memory. The program ROM size is 6 KB (Figure
14). The IRQ vector table is located in the lower address
space. The vector address is fetched after the correspond-
ing interrupt and program control is passed to the specified
vector address. IRQ1 vector is fixed to VSYNC interrupt re-
quest and occurs at the leading edge of the filtered VSYNC
input. Program memory start at address 000CH after re-
set.
1
Hex
Hex
Address
Address
0000
0001
0002
0003
0004
0005
0006
0007
IRQ0 (High Byte)
IRQ0 (Low Byte)
OSD Control (OSD_CNTRL)
Vertical Position (VERT_POS)
Horizontal Position (HOR_POS)
Display Attribute (DISP_ATTR)
Row Space (ROW_SPACE)
Fade Position (FADE_POS)
Bar Line Control (BAR_CNTRL)
Bar Position (BAR_POS)
FC00
FC01
FC02
FC03
FC04
FC05
FC06
FC07
VSYNC IRQ1 (High Byte)
VSYNC IRQ1 (Low Byte)
P31 IRQ2 (High Byte)
P31 IRQ2 (Low Byte)
P30 IRQ3 (High Byte)
P30 IRQ3 (Low Byte)
T0 IRQ4 (High Byte)
T0 IRQ4 (Low Byte)
T1 IRQ5 (High Byte)
T1 IRQ5 (Low Byte)
Reset Start Address
0008
0009
000A
000B
000C
PWM Mode (PWM_MODE)
PWM Output Port (PWM_OUT)
PWM1 High 6-Bit (PWM1_HI)
PWM1 Low 8-Bit (PWM_LO)
FC10
FC11
FC12
FC13
FC14
FC15
FC16
FC17
FC18
FC19
FC1A
FC1B
FC1C
FC1D
FC1E
FC1F
¯
On-Chip Program ROM
(6 KByte)
17FF
Reserved
1800
¯
Reserved
FBFF
FC00
PWM6 6-Bit Register (PWM6)
PWM7 6-Bit Register (PWM7)
PWM8 6-Bit Register (PWM8)
PWM9 8-Bit Register (PWM9)
PWM10 8-Bit Register (PWM10)
PWM11 8-Bit Register (PWM11)
Write
Only
¯
Memory Mapped I/O
Reserved
FC32
FC33
¯
FCFF
FD00
Reserved
¯
Video Refresh RAM
Reserved
FDB4
FDB5
Reserved
Reserved
FC30
FC31
FC32
¯
FFFF
Port 6 Input Port (PORT6)
Figure 14. Program Memory
DS97TEL1902
17
Z90102/90103/90104
40-Pin Low-Cost Digital Television Controller
Zilog
FUNCTIONAL DESCRIPTION (Continued)
Memory Mapped Register. All control registers and I/O
ports (except Port 2 and Port 3) are assigned to program
memory space. Address space FC00H contains OSD con-
trol registers, PWM output registers and Port 6 I/O regis-
ters. Two bits of the decoded AFCIN port are assigned to
Port 6 input port. LDE and LDEI instructions are required
to transfer data between the Register File and the Memory
Mapped Registers.
Note: Register Bank E0-EF is only accessed through a
working register and indirect addressing modes.
r7 r6 r5 r4
r3 r2 r1 r0
R253
(Register Pointer)
Register File. A total of 253 byte registers are implement-
ed in the Z8 core. Address 00H, 01H and FOH are re-
served. The register file consists of two I/O Port registers,
236 general-purpose registers and 15 control and status
registers (Figure 19). The instructions can access regis-
ters directly or indirectly with an 8-bit address field. This
also allows short 4-bit register addressing using the Reg-
ister Pointer. In the 4-bit mode, the register file is divided
into sixteen working-register groups, each occupying 16
continuous locations. The Register Pointer addresses the
starting location of the active working-register group (Fig-
ure 15).
The upper nibble of the register file address
provided by the register pointer specifies
the active working-register group.
FF
F0
R15 to R0
•
•
•
•
•
•
•
•
•
•
•
•
•
•
Hex
Address
The lower nibble
of the register
file address
provided by the
instruction points
to the specified
register.
Specified Working
Register Group
2F
20
1F
Port 2 (P2)
Port 3 (P3)
02
03
04
Register Group 1
R15 to R0
10
0F
R15 to R4
R3 to R0
Register Group 0
I/O Ports
General-Purpose
Registers
00
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
Reserved
Figure 16. Register Pointer
Timer Mode (TMR)
Timer/Counter1(T1)
T1 Prescaler (PRE1)
Timer/Counter0 (T0)
T0 Prescaler (PRE0)
Port 2 Mode (P2M)
Port 3 Mode (P3M)
Port 0-1 Mode (P01M)
Interrupt Priority Reg (IPR)
Interrupt Request Reg (IRQ)
Interrupt Mask Reg (IMR)
Condition Flag (FLAGS)
Register Pointer (RP)
Stack Pointer High (SPH)
Stack Pointer Low (SPL)
Figure 15. Register File Configuration
18
DS97TEL1902
Z90102/90103/90104
40-Pin Low-Cost Digital Television Controller
Zilog
Z8 STANDARD CONTROL REGISTERS
1
RESET CONDITION
D7 D6 D5 D4 D3 D2 D1 D0
REGISTER
REGISTER POINTER
% FF
% FE
% FD
% FC
% FB
% FA
% F9
% F8
% F7
% F6
% F5
% F4
% F3
% F2
% F1
% F0
SPL
U
U
U
U
U
U
U
U
6P
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
7
6
5
4
0
0
0
0
RP
Working Register
Group Pointer
FLAGS
IMR
U
0
U
U
0
U
U
0
U
U
0
U
U
0
U
U
0
U
U
0
U
U
0
Must be "0"
IRQ
0
IPR
U
0
U
1
U
1
U
0
U
1
U
1
U
0
U
1
Reserved
P3M
P2M
PRE0
T0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
U
U
U
U
0
U
U
U
U
0
U
U
U
U
0
U
U
U
U
0
U
U
U
U
0
U
U
U
U
0
U
U
0
0
U
0
Z8 Reg. File
PRE1
T1
U
0
U
0
%FF
%FO
TMR
Reserved
%7F
Reserved
%0F
%00
EXPANDED REG. GROUP (0)
REGISTER
RESET CONDITION
Legend:
U = Unknown
% (0) 03
P3
U
U
1
1
1
U
U
U
U
U
U
U
U
% (0) 02
% (0) 01
% (0) 00
P2
U
U
U
Reserved
Reserved
Note: All General-Purpose registers, PWM Registers,
and Video RAM registers, Port 4, 5, and 6
registers are undefined after reset.
Figure 17. Z90102/3/4 Register File Reset Condition
DS97TEL1902
19
Z90102/90103/90104
40-Pin Low-Cost Digital Television Controller
Zilog
FUNCTIONAL DESCRIPTION (Continued)
Stack. Either the internal register file or the external data
memory is used for the stack. An 8-bit Stack Pointer is
used for the internal stack that resides within the 236 gen-
eral-purpose registers.
er, the T0 prescaler is driven by the internal clock only (Fig-
ure 18).
The counter, but not the prescalers, are read at any time
without disturbing their value or count mode. The clock
source for T1 is user definable and is the internal micropro-
cessor clock (XTAL clock/4), or an external signal input
through Port 3, P31. The counter/timers are programmably
cascaded by connecting the T0 output to the input of T1.
Counter/Timers. There are two 8-bit programmable
counter/timers (T0-T1), each driven by its own 6-bit pro-
grammable prescaler (PRE0 and PRE1). The T1 prescaler
can be driven by internal or external clock sources; howev-
Internal Data Bus
Write
Write
Read
PRE0
Initial Value
Register
T0
T0
Initial Value
Register
Current Value
Register
OSC
6-Bit
Down
8-Bit
Down
¸4
Counter
Counter
Internal
Clock
IRQ4
Serial I/O
Clock
TOUT
P36
¸2
External Clock
Clock
Logic
6-Bit
Down
8-Bit
Down
IRQ5
¸4
Counter
Counter
Internal Clock
Gated Clock
Triggered Clock
PRE1
Initial Value
Register
T1
T1
Initial Value
Register
Current Value
Register
TIN P31
Write
Internal Data Bus
Write
Read
Figure 18. Counter/Timer Block Diagram
20
DS97TEL1902
Z90102/90103/90104
40-Pin Low-Cost Digital Television Controller
Zilog
Interrupts. The DTC has six different interrupts from six
different sources. These interrupts are maskable and pri-
oritized (Figure 19). The six sources are divided as follows:
two sources are claimed by Port 3 (P30, P31), one by
VSYNC, two by the counter/timers, and one is software
triggered only.
1
IRQ
IRQ
IMR
6
Global
Interrupt
Enable
IPR
Interrupt
Request
Priority
Logic
Vector Select
Figure 19. Interrupt Block Diagram
DS97TEL1902
21
Z90102/90103/90104
40-Pin Low-Cost Digital Television Controller
Zilog
FUNCTIONAL DESCRIPTION (Continued)
HALT Mode. The Z90102/3/4 is driven by two internal
clocks, TCLK and SCLK. They both oscillate at the crystal
frequency. TCLK provides the clock signal for the counter-
timers and the interrupt block. SCLK provides the clock
signal for all other CPU blocks. HALT Mode turns off the
internal CPU clock (SCLK), but not the XTAL oscillation.
The counter/timers and external interrupts remain active.
The device may be recovered by interrupts, either exter-
nally or internally generated. An interrupt request may be
executed (enabled) to exit HALT Mode. After the interrupt
service routine, the program continues from the instruction
after the HALT.
the HALT or STOP instructions. This is required because
of instruction pipelining, i.e.:
FF NOP
; clear the pipeline
; enter STOP Mode
or
6F STOP
FF NOP
7F HALT
; clear the pipeline
; enter HALT Mode
Notes: In STOP Mode, XTAL2 pin has an internal pull-up
on it and OSCOUT has an internal pull-down.
Clock. The Z90102/3/4 on-chip oscillator has a high-gain,
parallel-resonant amplifier for connection to a crystal, ce-
ramic resonator, or any suitable external clock source
(XTAL1 = Input, XTAL2 = Output). The crystal is an AT cut,
parallel resonant, 4 MHz max with a series resistance (RS)
less than or equal to 100 Ohms.
STOP Mode. The STOP instruction stops crystal oscilla-
tion, thereby stopping both SCLK and TCLK. The device
ceases to operate. The STOP Mode can be released by
two methods. The first method is to reset the device. A
high input condition on Port 3 P30 is the second method.
After releasing the STOP Mode by using either one of the
two methods, program execution begins at location
000CH. To complete an instruction prior to entering the
standby modes, a NOP instruction has to be placed before
The crystal source is connected across XTAL1 and XTAL2
using the crystal manufacturer's recommended capacitors
(10 pF < CL < 300 pF, where C1=C2=CL) from each pin to
device ground (Figure 20).
XTAL1
XTAL1
C1
* VSS
XTAL2
XTAL2
C2
* VSS
External Clock
Ceramic Resonator
or Crystal
XTAL1
27mH
6.8kW
XTAL2
33pF
33pF
MPU
* VSS
* VSS
LC Oscillator Circuits
* Must be connected to VSS pin and not
system ground.
Figure 20. Oscillator Configuration
22
DS97TEL1902
Z90102/90103/90104
40-Pin Low-Cost Digital Television Controller
Zilog
Watch-Dog Timer (WDT). The Z90102/3/4 is equipped
with a permanently enabled Watch-Dog Timer which must
be refreshed every 12 ms. Failure to refresh the timer re-
sults in a reset of the device. The WDT is permanently en-
abled and is initially reset upon POR. Every subsequent
WDT instruction resets the timer. The Watch-Dog Timer
may or may not be enabled during the STOP Mode. The
instruction WDT 4F (HEX) enables the timer during HALT.
If the WDH instruction is used, and if the HALT Mode is not
released and the Watch-Dog Timer is not retriggered (by
the WDT instruction) within 12 ms, a device reset occurs.
The WDT instruction affects the Z (Zero) S (Sign), and V
(Overflow) flags. WDT does not run during STOP Mode.
1
V
Voltage Sensitive Reset (VSR). Reset is globally
CC
driven if V is below the specified voltage (Figure 21).
CC
VBO 3.80
3.60
3.40
3.20
3.00
2.80
2.60
2.40
-60
-40
-20
+0
20
40
60
80
100
120
140
Temperature
(°C)
Figure 21. Voltage Sensitive Reset vs Temperature
DS97TEL1902
23
Z90102/90103/90104
40-Pin Low-Cost Digital Television Controller
Zilog
STANDARD CHARACTER SETS
24
DS97TEL1902
Z90102/90103/90104
40-Pin Low-Cost Digital Television Controller
Zilog
SUMMARY
Input/Output Circuits
1
VCC
VCC
OEN
P
PAD
PAD
20 Ohm
IN
N
20
Ohm
OUT
IN
Figure 22. Input Only
(Pad Type 1)
Figure 25. Input/Output Tristate
(Pad Type 4)
VCC
VCC
OD
OEN
P
PAD
20 Ohm
PAD
IN
N
20
Ohm
OUT
IN
Figure 23. Input Only, Schmitt-Triggered
(Pad Type 2)
Figure 26. Input/Output,Tristate, Open-Drain
VCC
VCC
OEN
P
P
N
PAD
PAD
OUT
N
OUT
Figure 27. Output Only,Tristate
Figure 24. Output Only
(Pad Type 3)
DS97TEL1902
25
Z90102/90103/90104
40-Pin Low-Cost Digital Television Controller
Zilog
SUMMARY (Continued)
VCC
VCC
PAD
N
STOP
P
VCC
2R
1R
N
VCC
-
OUT
N
P67
P66
N
+
PAD
20 Ohm
-
+
2R
Figure 28. Output Only, 12-Volt Open-Drain
(Pad Type 7)
Figure 30. AFC Input Circuit
(Pad Type 9)
VCC
Table 2. Mapping of Symbolic Pad Types to Pin
Functions
RPU
Pin Name
Pad Type
PAD
XTAL1, OSCIN
XTAL2, OSCOUT
/RESET
1
*
20 Ohm
RESET
8
5
2
3
2
9
2
3
3
3
7
P20-P27
N
P30-P31
P34-P36
P60-P65
AFCIN
HSYNC, VSYNC
VRED, VBLUE, VGREEN,
VBLANK
Figure 29. Reset Input Circuit
(Pad Type 8)
PWM1
PWM [6 -11]
Note:
*High gain start, low gain run amplifier circuit.
26
DS97TEL1902
Z90102/90103/90104
40-Pin Low-Cost Digital Television Controller
Zilog
DTC CONTROL REGISTER DIAGRAMS
Port Registers
1
03H
P3
02H
D7 D6 D5 D4 D3 D2 D1 D0
P2
D7 D6 D5 D4 D3 D2 D1 D0
P30 Input Port
Stop-Mode Recovery Input
P31 Input/T1 (input)
P34 Output Port
Input/Output Port
0 Logic Level 0
1 Logic Level 1
P35 Output Port
P36 Output/T1, T0 (output)
Reserved
Figure 31. Port 2 Register
(Read/Write)
Figure 33. Port 3 Register
(P30, P31 Read Only)
(P34, P35, P36 Write Only)
P2M
F6H
Input/Output Mode
0 Output Mode
1 Input Mode
D7 D6 D5 D4 D3 D2 D1 D0
P6
FC32H
D7 D6 D5 D4 D3 D2 D1 D0
Figure 32. Port 2 Mode Register
(Write Only)
Port 6 Input
0 Logic Level 0
1 Logic Level 1
Port 6 Comparator Input
00 GND thru V1
0 1 V1 thru V2
11 V2 thru VCC
Figure 34. Port 6 Register
(Read Only)
DS97TEL1902
27
Z90102/90103/90104
40-Pin Low-Cost Digital Television Controller
Zilog
DTC CONTROL REGISTER DIAGRAMS
PWM Registers
FC1AH
D7 D6 D5 D4 D3 D2 D1 D0
PWM8 VAL
PWM1 UPPER
FC12H
D7 D6 D5 D4 D3 D2 D1 D0
PWM8 Value
Reserved (Must be 0)
PWM1 High Byte
Reserved (Must be 0)
Figure 39. PWM 8 Value
(Write Only)
Figure 35. PWM 1 High Value
(Write Only)
FC1BH
D7 D6 D5 D4 D3 D2 D1 D0
FC13H
D7 D6 D5 D4 D3 D2 D1 D0
PWM9 VAL
PWM1 LOWER
PWM1 Low Byte
PWM9 Value
Figure 36. PWM 1 Low Value
(Write Only)
Figure 40. PWM 9 Value
(Write Only)
FC18H
PWM6 VAL
FC1CH
PWM10 VAL
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
PWM6 Value
Reserved (Must be 0)
PWM10 Value
Figure 37. PWM 6 Value
Figure 41. PWM 10 Value
(Write Only)
(Write Only)
FC19H
PWM7 VAL
FC1DH
PWM11 VAL
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
PWM7 Value
Reserved (Must be 0)
PWM11 Value
Figure 38. PWM 7 Value
(Write Only)
Figure 42. PWM 11 Value
(Write Only)
28
DS97TEL1902
Z90102/90103/90104
40-Pin Low-Cost Digital Television Controller
Zilog
PWM MODE
FC10H
FC11H
D7 D6 D5 D4 D3 D2 D1 D0
PWM OUT
Output Control
0 = Logic Level 1
1 = Logic Level 0
Mode Control
0 PWM
1 Output Port
1
D7 D6 D5 D4 D3 D2 D1 D0
Reserved (Must be 0)
Reserved (Must be 0)
Figure 43. PWM Mode Register
(Write Only)
Figure 44. PWM Port Output Register
(Write Only)
DS97TEL1902
29
Z90102/90103/90104
40-Pin Low-Cost Digital Television Controller
Zilog
Z8 REGISTER DIAGRAMS
FC00H
D7 D6 D5 D4 D3 D2 D1 D0
OSDC CNTRL
FC03H
D7 D6 D5 D4 D3 D2 D1 D0
DISP ATTR
Retrace Blanking
Blue Background
Green Background
Red Background
High Resolution
Must be 1
X4HL
RGB Polarity
0 - Positive
1 - Negative
Pixel Size
00 x 1
01 x 2
Reserved (Must be 0)
10 x 3
11 x 4
Fringe On-Off
0 - Off
1 - On
Background On-Off
0 - Off
1 - On
Sync Polarity
0 Positive
1 Negative
Reserved (Must be 0)
Display On-Off
0 - Off
1 - On
Figure 45. OSD Control Register
(Write Only)
Figure 48. OSD Display Attribute Register
(Write Only)
FC01H
VERT POS
D7 D6 D5 D4 D3 D2 D1 D0
FC04H
D7 D6 D5 D4 D3 D2 D1 D0
ROW SPACE
Vertical Position Control
x 4 Horizontal Lines
Inter Row Space
Reserved (Must be 0)
Reserved (Must be 0)
Fade Direction
0 - Fade After
1 - Fade Before
Figure 46. OSD Vertical Position Register
(Write Only)
Fade On-Off
0 - Off
1 - On
FC02H
D7 D6 D5 D4 D3 D2 D1 D0
HOR POS
Figure 49. OSD Row Space Register
(Write Only)
Horizontal Position Control
x 4 DOT Clocks
Reserved (Must be 0)
FC05H
D7 D6 D5 D4 D3 D2 D1 D0
FADE POS
Figure 47. OSD Horizontal Position Register
(Write Only)
Vertical Index
Reserved (Must be 0)
Figure 50. OSD Fade Position Register
(Write Only)
30
DS97TEL1902
Z90102/90103/90104
40-Pin Low-Cost Digital Television Controller
Zilog
BAR CNTRL
FC06H
FD00H,FD20H,FD40H,
FD60H,FD80H,FDA0H
ROW_ ATTR
D7 D6 D5 D4 D3 D2 D1 D0
1
D7 D6 D5 D4 D3 D2 D1 D0
Row Address
Reserved (Must be 0)
Red Bar Color
Row Background Color
Red
Green
Green Bar Color
Blue Bar Color
Blue
Bar Color Enable
Row Background On-Off
0 Off
1 On
Character Color
Red
Figure 51. OSD Bar Control Register
(Write Only)
Green
Blue
Reserved (Must be 0)
FC07H
BAR POS
D7 D6 D5 D4 D3 D2 D1 D0
Figure 54. ROW_ATTR Register
(Write Only)
Bar Column Position
Reserved (Must be 0)
F2H
R242 T1
D7 D6 D5 D4 D3 D2 D1 D0
Figure 52. OSD Bar Position Register
(Write Only)
T1 Initial Value
(When Written)
(Range: 1-256 Decimal
01-00 Hex)
T1 Current Value
(When Read)
F1H
D7 D6 D5 D4 D3 D2 D1 D0
R241 TMR
Figure 55. Counter Timer 1 Register
(F1H: Read/Write)
0 - No Function
1 - Load T0
0 -Disable T0 Count
1 -Enable T0 Count
0 - No Function
1 - Load T1
F3H
D7 D6 D5 D4 D3 D2 D1 D0
R243 PRE1
0 - Disable T1 Count
1 - Enable T1 Count
TIN Modes
00 External Clock Input
01 Gate Input
10 Trigger Input
(Non-retriggerable)
11 Trigger Input
(Retriggerable)
Count Mode
0 T1 Single Pass*
1 T1 Modulo N
Clock Source
1 T1 Internal
0 T1 External Timing Input*
(TIN) Mode
Prescaler Modulo
(Range: 1-64 Decimal
01-00 Hex)
TOUT Modes
00 Not Used
01 T0 Out
10 T1 Out
11 Internal Clock Out
* Default After Reset
Figure 53. Timer Mode Register
(F1H: Read/Write)
Figure 56. Prescaler 1 Register
(F3H:Write Only)
DS97TEL1902
31
Z90102/90103/90104
40-Pin Low-Cost Digital Television Controller
Zilog
Z8 REGISTER DIAGRAMS (Continued)
F7H
D7 D6 D5 D4 D3 D2 D1 D0
R247 P3M
F4H
D7 D6 D5 D4 D3 D2 D1 D0
R244 T0
0 - Port 2 Open-Drain
1 - Port 2 Push-Pull
Reserved (Must be 0)
T0 Initial Value
(When Written)
(Range: 1-256 Decimal
01-00 Hex)
T0 Current Value
(When Read)
0
P32 - Input P35 - Output
(Must be 0)
00 P33 - Input P34 - Output
(Must be 0)
11 Reserved
0 P31 - Input (TIN) P36 - Output (TOUT)
0 P30 - Input
Reserved (Must be 0)
Figure 57. Counter/Timer 0 Register
(F4H: Read/Write)
Figure 60. Port 3 Mode Register
(F6H;Write Only)
F5H
D7 D6 D5 D4 D3 D2 D1 D0
R245 PRE0
F9H
R249 IPR
D7 D6 D5 D4 D3 D2 D1 D0
Count Mode
0 T0 Single Pass*
1 T0 Modulo-N
Interrupt Group Priority
000 Reserved
Reserved (Must be 0)
001 C > A > B
010 A > B > C
011 A > C > B
100 B > C > A
101 C > B > A
110 B > A > C
111 Reserved
Prescaler Modulo
(Range: 1-64 Decimal
01-00 Hex)
* Default After Reset
IRQ1, IRQ4 Priority (Group C)
0 IRQ1 > IRQ4
1 IRQ4 > IRQ1
Figure 58. Prescaler 0 Register
(F5H:Write Only)
IRQ1, IRQ2 Priority (Group B)
0 IRQ2 > IRQ0
1 IRQ0 > IRQ2
IRQ3, IRQ5 Priority (Group A)
0 IRQ5 > IRQ3
1 IRQ3 > IRQ5
F6H
R246 P2M
D7 D6 D5 D4 D3 D2 D1 D0
Reserved (Must be 0)
Figure 61. Interrupt Priority Register
(F9H:Write Only)
P27 - P20 I/O Definition
0 Defines Bit as Output
1 Defines Bit as Input
Figure 59. Port 2 Mode Register
(F6H:Write Only)
32
DS97TEL1902
Z90102/90103/90104
40-Pin Low-Cost Digital Television Controller
Zilog
FAH
R250 IRQ
FDH
R253 RP
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
1
IRQ - Software only
IRQ1 - VSYNC
IRQ2 - P31 Input
IRQ3 - P30 Input
IRQ4 - T0
Reserved (Must be 0)
Register Pointer
Reset Condition = 00H
IRQ5 - T1
Reserved (Must be 0)
Reset Condition = 00H
Figure 65. Register Pointer
(FDH: Read/Write)
Figure 62. Interrupt Request Register
(FAH: Read/Write)
FEH
D7 D6 D5 D4 D3 D2 D1 D0
R254 GP
FBH
D7 D6 D5 D4 D3 D2 D1 D0
R251 IMR
0 = Level 0
1 = Level 1
Reset Condition = Undefined
1 - Enables IRQ5 - IR0
(D0 - IRQ0)
Reserved (Must be 0)
Figure 66. General-Purpose
(FEH: Read/Write)
1 - Enables Interrupts
0* Disable Interrupts
* Default after Reset
FFH
D7 D6 D5 D4 D3 D2 D1 D0
R255 SPL
Figure 63. Interrupt Mask Register
(FBH: Read/Write)
Stack Pointer Upper
Byte (SP7-SP0)
FCH
R252 FLAGS
D7 D6 D5 D4 D3 D2 D1 D0
Figure 67. Stack Pointer
(FFH: Read/Write)
User Flag F1
User Flag F2
Half Carry Flag
Decimal Adjust Flag
Overflow Flag
Sign Flag
Zero Flag
Carry Flag
Figure 64. Flag Register
(FCH: Read/Write)
DS97TEL1902
33
Z90102/90103/90104
40-Pin Low-Cost Digital Television Controller
Zilog
PACKAGE INFORMATION
Figure 68. 40-Pin DIP Package Diagram
34
DS97TEL1902
Z90102/90103/90104
40-Pin Low-Cost Digital Television Controller
Zilog
ORDERING INFORMATION
Z90102, Z90103, Z90104
4 MHz
40-pin DIP
1
Z90102/3/404PSC
For fast results, contact your local Zilog sales office for as-
sistance in ordering the part desired.
CODE
Package
Speed
P = Plastic DIP
Temperature
04 = 4 MHz
Environmental
C = Plastic Standard
S = 0°C to +70°C
Example:
Z 890103 04 P S C
is an 86227, 4 MHz, DIP, 0°C to +70°C, Plastic Standard Flow
Environmental Flow
Temperature
Package
Speed
Product Number
Zilog Prefix
DS97TEL1902
35
Z90102/90103/90104
40-Pin Low-Cost Digital Television Controller
Zilog
36
DS97TEL1902
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