Z90371 [ZILOG]
RISC Microcontroller, 16-Bit, OTPROM, 12MHz, CMOS, PDIP52, SDIP-52;
| 型号： | Z90371 |
| 厂家： | 
ZILOG, INC. |
| 描述： | RISC Microcontroller, 16-Bit, OTPROM, 12MHz, CMOS, PDIP52, SDIP-52 可编程只读存储器 时钟 微控制器 光电二极管 外围集成电路 |
| 文件： | 总188页 (文件大小：1246K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Z90376 ROM
Z90371 OTP
64 KWORD TELEVISION CONTROLLER WITH OSD
PRODUCT SPECIFICATION
PS005600-TVC1199
ZiLOG WORLDWIDE HEADQUARTERS • 910 E. HAMILTON AVENUE • CAMPBELL, CA 95008
Document Disclaimer
© 1999 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices, applications, or
technology described is intended to suggest possible uses and may be superseded. ZiLOG, INC. DOES NOT
ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION, DEVICES,
OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZiLOG ALSO DOES NOT ASSUME LIABILITY FOR
INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES,
OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. Except with the express written approval ZiLOG, use
of information, devices, or technology as critical components of life support systems is not authorized. No
licenses or other rights are conveyed, implicitly or otherwise, by this document under any intellectual property
rights.
Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
Table of Contents
1 OVERVIEW ........................................................................................ 11
1.1 Block Diagram ................................................................................ 13
1.2 Pin Description ............................................................................... 14
2 OPERATION ...................................................................................... 17
2.1 CPU Descriptions ........................................................................... 17
2.2 Memory (ROM and RAM) .............................................................. 24
2.3 Clock Circuit Description ............................................................... 26
2.4 Reset Conditions ............................................................................ 28
2.5 Power Management ...................................................................... 30
2.6 I/O Port Configurations .................................................................. 30
2.7 Interrupts ........................................................................................ 32
2.8 Timers ............................................................................................. 33
2.9 ADC ................................................................................................. 34
2.10 Pulse Width Modulation ............................................................... 36
2.11 I2C Interface .................................................................................. 36
2.12 Progressive Scan .......................................................................... 42
2.13 On-Screen Display (OSD) ............................................................. 42
2.14 Cursor ............................................................................................ 50
2.15 Color Palette Assignment ............................................................ 54
2.16 Other Functions ............................................................................ 55
3 REGISTER GROUPS ......................................................................... 57
3.1 Register Description ...................................................................... 58
3.2 Bank0 (I/O Ports, I2C Interface, PLL Frequency, Cursor) Control
Registers ...................................................................................59
3.3 Bank1 (Control Registers) .............................................................. 64
3.4 Bank2 (PWM Registers) ................................................................. 77
3.5 Bank3 (On Screen Display [OSD] registers) ................................. 79
4 INSTRUCTION SET .......................................................................... 92
4.1 Instruction Summary ..................................................................... 92
4.2 Instruction Operands ..................................................................... 95
4.3 Instruction Format ......................................................................... 96
4.4 Instruction Bit Codes ..................................................................... 98
4.5 Instruction Format Examples ...................................................... 102
PS005600-TVC1299
Preliminary
3
Z90376 ROM and Z90371OTP
64 KWord Television Controller with OSD
4.6 Instruction Timing ........................................................................ 107
4.7 Instruction Op Codes ................................................................... 108
5 Electrical Characteristics ............................................................... 179
5.1 DC Peripherals .............................................................................. 180
5.2 AC Characteristics ........................................................................ 182
5.3 ANALOG RGB ............................................................................... 182
6 SYSTEM DESIGN CONSIDERATIONS .......................................... 184
7 PACKAGING ................................................................................... 186
PS005600-TVC1299
Preliminary
4
Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
List of Figures
Figure 1
Code Development Environment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
52-Pin SDIP Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
AR Register Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
RAM, ROM, and Pointer Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 23
ROM Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
RAM Allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Clock Switching Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
32-KHz Oscillator Recommended Circuit . . . . . . . . . . . . . . . . . . . . . . . 27
Bidirectional Port Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Bidirectional Pins Multiplexed with I2C Port . . . . . . . . . . . . . . . . . . . . 31
Bidirectional Pins Multiplexed with ADC Inputs . . . . . . . . . . . . . . . . . 32
IR Capture Register Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
ADC Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
ADC Data Packing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Master Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Progressive Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Blank and V1, V2, V3 Outputs in Digital Mode . . . . . . . . . . . . . . . . . . 44
V1, V2, and V3 Outputs in Analog (Palette) Mode . . . . . . . . . . . . . . . . 45
Character Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Cursor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Programmable Palette Control at AR Register . . . . . . . . . . . . . . . . . . 54
IR Capture Register Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Loop Filter Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
Pipeline Execution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Recommended Application Schematics . . . . . . . . . . . . . . . . . . . . . . 183
System Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 185
52-Pin SDIP Package Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 186
Figure 2
Figure 3
Figure 4
Figure 5
Figure 6
Figure 7
Figure 8
Figure 9
Figure 10
Figure 11
Figure 12
Figure 13
Figure 14
Figure 15
Figure 16
Figure 17
Figure 18
Figure 19
Figure 20
Figure 21
Figure 22
Figure 23
Figure 24
Figure 25
Figure 26
Figure 27
Figure 28
Figure 29
Figure 30
Figure 31
PS005600-TVC1299
Preliminary
5
Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
PS005600-TVC1299
Preliminary
6
Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
List of Tables
Table 1
Table 2
Table 3
Table 4
Table 5
Table 6
Table 7
Table 8
Table 9
Table 10
Table 11
Table 12
Table 13
Table 14
Table 15
Z90376 or Z90371 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Internal Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
RPL Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Additional Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Reset Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
ADC Inputs Typical Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
2
Master I C Bus Bit Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
2
Master I C Bus Interface Commands . . . . . . . . . . . . . . . . . . . . . . . . . . 38
2
Slave I C Bus Interface Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Character Expansion Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Attribute Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Cursor Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Memory Allocation for Cursor Bitmap . . . . . . . . . . . . . . . . . . . . . . . . . 52
Fixed Palette Color Assignment
(Color0 is Black; Color7 is White) . . . . . . . . . . . . . . . . . . . . . . . . 54
Table 16
Table 17
Table 18
Table 19
Table 20
Table 21
Table 22
Table 23
Table 24
Table 25
Table 26
Table 27
Table 28
R4(1)<e:d> Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Bank Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Register1, R1(0) Cursor Palette . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Register2, R2(0) PLL Frequency Data Register . . . . . . . . . . . . . . . . . . 59
Register3, R3(0) I2C Interface Register . . . . . . . . . . . . . . . . . . . . . . . . . 61
Register4, R4(0) Port 0 Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Register5, R5(0) Port 1 Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Register6, R6(0) Port 0 Direction Register . . . . . . . . . . . . . . . . . . . . . . 63
Register7, R7(0) Port 1 Direction Register . . . . . . . . . . . . . . . . . . . . . . 63
Register0, R0(1) Clamp Position Register . . . . . . . . . . . . . . . . . . . . . . 64
Register1, R1(1) Speed Control Register . . . . . . . . . . . . . . . . . . . . . . . 66
Register2, R2(1) WDT/STOP (write only) and
9-bit Counter (read only) Control Register . . . . . . . . . . . . . . . . 68
Table 29
Table 30
Table 31
Table 32
Table 33
Register3, R3(1) Standard Control Register . . . . . . . . . . . . . . . . . . . . . 69
Register 4, R4(1) ADC Control Register . . . . . . . . . . . . . . . . . . . . . . . . 70
Register5, R5(1)Timer Control Register . . . . . . . . . . . . . . . . . . . . . . . . 72
Register6, R6(1) Clock Switch Control Register . . . . . . . . . . . . . . . . . . 73
Register7, R7(1) Interrupts/WDT/SMR Control Register . . . . . . . . . . . 76
PS005600-TVC1299
Preliminary
7
Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
Table 34
Table 35
Table 36
Table 37
Table 38
Interrupt Priority . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Register0–Register5, R0(2)–R5(2) PWM 1–6 Registers . . . . . . . . . . . . 77
Register6, R6(2) Shadow Control Register . . . . . . . . . . . . . . . . . . . . . . 78
Register7, R7(2) CGROM Offset Register . . . . . . . . . . . . . . . . . . . . . . . 79
Register0–Register2 Read Operation
R0(3)–R2(3) Character Multiple Registers . . . . . . . . . . . . . . . . . 80
Table 39
Register0–Register1 Write Operation
R0(3)–R1(3) Shift Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Table 40
Table 41
Register2 — R2(3) Attributes Register, Write Operation . . . . . . . . . . . 81
Register3 Read Operation
R3(3) Attributes Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 42
Table 43
Table 44
Table 45
Table 46
Register3, R3(3) Write Operation
Attribute Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Display Character Format for Attribute Data Register R3(3)
OSD Mode Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Control Character Format, OSD Mode Write Operation
Attribute Data Register R3(3) . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Display Character Format, Attribute Data Register R3(3)
Write Operation CCD Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Control Character Format, Attribute Data Register R3(3)
CCD Mode, Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Table 47
Table 48
Table 49
Table 50
Table 51
Table 52
Table 53
Table 54
Table 55
Table 56
Table 57
Table 58
Table 59
Table 60
Table 61
Table 62
Table 63
Table 64
Table 65
Register4—R4(3) OSD Control Register . . . . . . . . . . . . . . . . . . . . . . . . 88
Register5, R5(3) Capture Register, Read Operation . . . . . . . . . . . . . . 89
Register6, R6(3) Palette Control Register . . . . . . . . . . . . . . . . . . . . . . . 90
Register7, R7(3) Output Palette Control Register . . . . . . . . . . . . . . . . 91
Instruction Format Mnemonics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Accumulator Modification Instructions . . . . . . . . . . . . . . . . . . . . . . . . 93
Arithmetic Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Load Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Logical Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Program Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Rotate and Shift Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Instruction Operand Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Instruction Mnemonics/Operands . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Condition Code Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Accumulator Modification Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Flag Modification Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Register Pointer/ Data Pointer Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
PS005600-TVC1299
Preliminary
8
Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
Table 66
Table 67
Table 68
Table 69
Table 70
Table 71
Table 72
Table 73
Table 74
Table 75
Table 76
Table 77
Table 78
Table 79
Table 80
Table 81
Table 82
Table 83
Table 84
General Instruction Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Accumulator Modification Format . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Flag Modification Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Direct Internal Addressing Format . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Short Immediate Addressing Format . . . . . . . . . . . . . . . . . . . . . . . . . 105
Long Immediate Addressing Format . . . . . . . . . . . . . . . . . . . . . . . . . 106
Jump, Call Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Instruction Op Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Instruction Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Instruction Format Mnemonics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
Absolute Maximum and Minimum Ratings . . . . . . . . . . . . . . . . . . . . 179
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 179
V1, V2, and V3 (R,G,B) Analog Output . . . . . . . . . . . . . . . . . . . . . . . . 180
ADC0/Small Range* . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
ADC1-ADC4/Full range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
RGB Voltage Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 182
RGB Time Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 183
Controlling Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 187
PS005600-TVC1299
Preliminary
9
Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
PS005600-TVC1299
Preliminary
10
Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
1
OVERVIEW
The Z90376 and Z90371 are the ROM and OTP versions of a Television Controller with
On-Screen Display (OSD) that contains 64 KWords of program memory and 1K words of
RAM.
•
The Z90371 is the one-time programmable (OTP) controller used to develop code
and prototypes for specific television applications or initial limited production.
Program ROM and Character Generation ROM (CGROM) in the Z90371 are both
programmable.
The Z90371 requires ZiLOG’s Z90369ZEM Emulator with its proprietary ZiLOG
Developmental Studio (ZDS) software for programing. To view code effects, the
emulator uses a ZOSD board that connects directly to a television screen. Refer to
Figure 1.
Z90369 In-Circuit
Emulation Kit
ZOSD Board
Z90379
Z90371
Develop
code on PC
Download Code to
Z90379 ICE chip
Converts to
Video Display
Review Code
on TV Display
Program the
Z90371 OTP
Figure 1
Code Development Environment
•
The Z90376 incorporates the ROM code developed by the customer with the
Z90371. Customer code is masked into both program ROM and CGROM.
ZiLOG WORLDWIDE HEADQUARTERS • 910 E. HAMILTON AVENUE • CAMPBELL, CA 95008
TELEPHONE: 408.558.8500 • FAX: 408.558.8300 • HTTP://WWW.ZILOG.COM
Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
The Z90376 Television Controller with OSD is based on ZiLOG’s Z89C00 RISC
processor core. The Z89C00 is a second-generation, 16-bit, fractional, two’s complement
CMOS Digital Signal Processor (DSP). Most instructions are accomplished in a single
clock cycle. This processor features a 24-bit Arithmetic Logic Unit (ALU) and a 24-bit
Accumulator. The processor also contains a six-level stack and three vectored interrupts.
Note: The Z89C00 multiplier is disabled in the Z90376 controller.
The Z90376 contains 64 KWords of program ROM and 1 KWord of on-chip data RAM.
Program ROM space can hold an unlimited number of characters with a 16x16, 16x18,
and 16x20 programmable matrix in relocated Character Generation ROM (CGROM),
which is only restricted by the available ROM. In addition, the Z90376 contains four
external register banks with eight registers each. Additional Control Registers (AR) are
available to control new peripheral blocks like palette banks and memory management.
An internal 24-MHz/2 system clock has a Phase Lock Loop (PLL) driven by an external
32.768-KHz crystal.
A six-channel, 4-bit Analog to Digital Converter (ADC) supports the following:
•
•
•
Analog control panel buttons
Audio level input
Vertical Blank Interval (VBI) data capture
Six Pulse Width Modulator (PWM) outputs allow low-cost digital-to-analog conversion
(DAC). The PWMs have 8-bit resolution to control video and audio attributes.
2
A Master/Slave I C (Inter Integrated Circuit) bus interface provides serial system
interconnect to common peripheral functions.
Twenty-five programmable I/O pins provide flexibility for other digital input/output
functions.
An IR (InfraRed) remote capture register facilitates reliable remote data capture.
On-chip Horizontal Synchronization (H
) and Vertical Synchronization (V
)
SYNC
SYNC
circuits generate a video time base (typically used for VCR and set-top applications) in the
absence of an available video signal.
Micro-programmable OSD generation logic provides flexibility to tailor OSD features and
functions. In addition to normal OSD functions, Closed Caption is supported in
accordance with FCC Report and Order on GEN Docket No. 91-1, dated April 12, 1991.
Expanded Data Service (XDS) capability is supported as well.
The Z90376 is packaged in a 52-pin SDIP package.
Figure 2 is a block diagram of the internal structure of the chip. Figure 3 illustrates the pin
locations, and Table 1 describes the function of each pin.
PS005600-TVC1299
Preliminary
12
Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
1.1
Block Diagram
PWM
IR IN
IR CAPTURE
COUNTER
PWM1
PWM2
PWM3
PWM4
PWM5
PWM6
ADC
ADC0
ADC1
ADC2
ADC3
ADC4
Port17
Port 00
Port 05
Port 04
PORT0
PORT00
PORT01
PORT02
PORT03
PORT04
PORT05
PORT06
PORT07
PORT08
PORT09
PORT0A
PORT0B
PORT0C
PORT0D
PORT0E
PORT1
PORT10
PORT11
PORT12
PORT13
PORT14
PORT15
PORT16
PORT17
2
I C
2
I CMC1
2
I CMD1
2
Port 11
Port 12
Port 01
Port 02
I CMC2
2
CONTROL
XTAL1
XTAL2
I CMD2
2
I CSC1
2
I CSD1
LPF
OSD
& LB V1
V2
V3
VBLANK
Reg Addr/Data
HSYNC
VSYNC
RESET
SVBLANK
CPU
Address
Data
RAM
ROM Addr
ROM Data
Port 0F
ROM
64K
Words
Z89C00
CORE
1 KWord
Figure 2
Block Diagram
PS005600-TVC1299
Preliminary
13
Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
1.2
Pin Description
1
2
3
4
5
6
7
8
52
51
50
49
48
47
46
45
44
43
42
41
40
Port16/SCLK
IRIN
Port15/B1
Port14/B0
Port13/G1
Port18/G0
Port08/R1
Port10/R0
PWM6/HSYNC2
PWM5
PWM4
PWM3
PWM2
PWM1
AGND
Port0C
Port0B
Port0A
Port09
Port0D
Port07/CSYNC
Port06/CNTR
Port03/1xHSYNC
Port01/I2CSC
Port02/I2CSD
CVI/ADC0
Z90376
or
Z90371
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
Top View
LPF
AGND
ADC5
V
39
38
37
36
35
34
33
32
31
30
29
28
27
CC
GND
XTAL2
XTAL1
RESET
I2CMC1
I2CMD1
Port0E
Port11/I2CMC2
Port12/I2CMD2
VSYNC
Port04/ADC4
Port05/ADC3
Port00/ADC2
Port17/ADC1
AGND
AV
CC
Port0F/SVBLANK
V3/B
V2/G
V1/R
HSYNC
VBLANK
Figure 3
52-Pin SDIP Pinout
PS005600-TVC1299
Preliminary
14
Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
Table 1
Symbol
Z90376 or Z90371 Pin Description
Pin #
Function
Direction
P16/SCLK
IRIN
1
2
3
4
5
6
7
8
9
P16 or internal process SCLK
Infrared remote capture input
Port 0, bit C
I/O
I
P0C
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
P0B
Port 0, bit B
P0A
Port 0, bit A
P09
Port 0, bit 9
P0D
Port 0, bit D
P07/CSYNC
P06/CNTR
P07 or composite sync output
P06 or counter input
P03/1xHSYNC
P03/1xHSYNC 10
2
2
P01/I CSC
11
12
13
14
15
16
17
18
19
20
21
22
P01 or slave I C clock I/O
2
2
P02/I CSD
P02 or slave I C data I/O
CVI/ADC0
LPF
ADC0 input or Composite Video Input AI
Loop Þlter
AI/AO
AGND
Analog ground
ADC5 input
Power
I
ADC5
P04/ADC4
P05/ADC3
P00/ADC2
P17/ADC1
AGND
P04 or ADC4 input
P05 or ADC3 input
P00 or ADC2 input
P17 or ADC1 input
Analog ground
Analog +5V
I/O or AI
I/O or AI
I/O or AI
I/O or AI
Power
Power
AVCC
P0F/SVBLANK 23
P0F or OSD semi-transparency output I/O
V3 (B)
24
25
26
27
28
29
OSD video output to drive Blue
OSD video output to drive Green
OSD video output to drive Red
OSD overlay output
O/AO
V2 (G)
O/ AO
O/AO
O
V1 (R)
VBLANK
HSYNC
VSYNC
Horizontal sync
I/O
Vertical sync
I/O
PS005600-TVC1299
Preliminary
15
Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
Table 1
Symbol
Z90376 or Z90371 Pin Description (Continued)
Pin #
Function
Direction
2
2
P12/I CMD2
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
P12 or master2 I C data I/O
I/O
I/O
I/O
I/O
I/O
I
2
2
P11/I CMC2
P11 or master2 I C clock I/O
P0E
Port 0, bit E
2
2
I CMD1
Master1 I C data I/O
2
2
I CMC1
Master1 I C clock I/O
RESET
XTAL1
XTAL2
GND
Reset
Crystal oscillator input
Crystal oscillator output
Digital ground
AI
AO
Power
Power
Power
O
VCC
Digital Vcc
AGND
PWM1
PWM2
PWM3
PWM4
PWM5
Analog ground
8-bit PWM output
8-bit PWM output
O
8-bit PWM output
O
8-bit PWM output
O
8-bit PWM output
O
PWM6/HSYNC2 46
8-bit PWM output/HSYNC2
P10 or output of RGB matrix
P08 or output of RGB matrix
P18 or output of RGB matrix
P13 or output of RGB matrix
P14 or output of RGB matrix
P15 or output of RGB matrix
I/O
I/O
I/O
I/O
I/O
I/O
I/O
P10/R0
P08/R1
P18/G0
P13/G1
P14/B0
P15/B1
47
48
49
50
51
52
PS005600-TVC1299
Preliminary
16
Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
2
OPERATION
2.1
CPU Descriptions
The Z89C00 core is a high-performance DSP that has a modified Harvard-type
architecture with separate program and data memories. The design has been optimized for
processing power and silicon space.
The Z89C00 used in the Z90376 device has been modified. The multiplier is disabled and
is not accessible. However, the X and Y registers in the multiplier are still available and
can be used as general-purpose registers. Refer to ZiLOG’s Z89C00 documentation.
ALU
The 24-bit ALU has two input ports, one of which is connected to the output of the 24-bit
Accumulator. The other input is connected to the 24-bit P-Bus; the upper 16 bits are
connected to the 16-bit D-Bus.
Instruction Timing
Several instructions are executed in one machine cycle. Long immediate instructions and
Jump or Call instructions are executed in two machine cycles. When the program memory
is referenced in internal RAM indirect mode, it requires three machine cycles. An
additional machine cycle is required if the PC is selected as the destination of a data
transfer instruction. This only occurs with a register indirect branch instruction.
Hardware Stack
A six-level hardware stack is connected to the D-Bus to hold subroutine return addresses
or data. The CALL instruction pushes PC+2 onto the stack. The RET instruction returns
the contents of the stack to the PC.
CPU Registers
The Z90376 has 11 physical internal registers and four banks of eight external registers. In
addition, it has nine virtual registers. The 11 internal registers are defined in Table 2, and
the status register is defined in Table 3.
PS005600-TVC1299
Preliminary
17
Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
Internal Registers
Table 2
Internal Registers
Register
Register DeÞnition
X
X, 16 bits
Y
Y, 16 bits
A
Accumulator, 24 bits
Status Register, 16 bits
SR
Pn:b
PC
Six RAM Address Pointers, 8 bits each
Program Counter, 16 bits
Table 3
Status Register
Bit/Field
Bit Position
R/W
Description
N
15
14
13
12
11
10
9
R
R
ALU Negative
ALU Overßow
ALU Zero
OV
Z
R
L
R
Carry
Reserved
R
Reserved
Reserved
R
Reserved
Reserved
R
Reserved
OP
8
R/W
R/W
R/W
Overßow Protection
Interrupt Enable
IE
7
Register Bank Selector
6,5
00 Register Bank 0
01 Register Bank 1
10 Register Bank 2
11 Register Bank 3
SFD
RPL
4,3
2-0
R/W
R/W
ÒShort Form DirectÓ Bits
RAM Pointer Loop Size
X and Y are 16-bit general purpose registers.
A is a 24-bit Accumulator. The output of the ALU is sent to this register. When 16-bit data
is transferred into this register, it goes into the 16 MSBs and the least significant eight bits
PS005600-TVC1299
Preliminary
18
Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
are set to zero. Only the upper 16 bits are transferred to the destination register when the
Accumulator is selected as a source register in transfer instruction.
SR is the Status Register that contains the ALU status and the control bits listed in
Table 3. The status register is always read in its entirety. S15-S12 are set/reset by the
hardware and can only be read through software. They are set or reset by the ALU after an
operation.
S8-S0 can be written by software. S8, if 0 (reset), allows the hardware to overflow. If S8 is
set, the hardware clamps at maximum positive or negative values instead of overflowing.
S7 enables interrupts. S6–S5 are used for “short form direct” addresses, which are
described below. The definitions of S2-S0 are listed in Table 4.
Table 4
S2
RPL Description
S1
S0
Loop Size
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
256
2
4
8
16
32
64
128
Pn:b are the pointer registers for accessing data RAM.
(n= 0, 1, 2 refer to the pointer number)
(b = 0, 1 refers to RAM bank 0 or 1).
They can be read from or written to directly and can point directly to locations in data
RAM or indirectly to Program Memory.
PC is the Program Counter. When this register is assigned as a destination register, one
NOP machine cycle is automatically added to adjust the pipeline timing.
PS005600-TVC1299
Preliminary
19
Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
External Registers
The Z90376 module is capable of accessing eight external registers directly using only the
three external register address signals that are normally available. Two user bits (Status
register S6-S5) are combined with the register address signals to provide the ability to
address four banks of eight registers each. The registers most critical for speed are located
together in Bank 3. In this specification, all external registers are referred to
RX(Y)<Z>
where:
X is a register number within a register bank;
Y is a bank number; and
Z is a bit field number
An external register bank can be selected by setting bits 6 and 5 in the status register to
define the bank, then specifying the address of the register on the external register address
bus.
External registers reside on the chip and are used to control the operation of all the
peripheral modules in the device. By reading or writing to the fields in the external
registers, the user can interact with the peripheral devices on the chip.
Virtual Registers
BUS is a read-only register that, when accessed, returns the contents of the D-Bus. It is
a virtual register. (Physical RAM does not exist on the chip.)
Dn:b These eight data pointers refer to possible locations in RAM that can be used as
pointers to locations in program memory. The programmer decides which location to
choose two bits from in the status register and which two bits in the operand. This means
only the lower 16 possible locations in RAM can be specified. At any one time there are
eight usable pointers, four per bank, and the four pointers are in consecutive locations in
RAM.
For example, if S3/S4 = 01 in the status register, then D0:0/D1:0/D2:0/D3:0 refers to
locations 4/5/6/7 in RAM bank 0.
Note: When the data pointers are being written to, a number is actually being loaded to
Data RAM, so they can be used as a limited method for writing to RAM.
PS005600-TVC1299
Preliminary
20
Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
Additional Control Registers (AR)
Additional Control Registers (AR) control new peripheral blocks like palette banks and
memory management. To activate ARs, R0(1)<b> must be set to “1.” ARs can be disabled
by setting R0(1)<b> = 0, (POR) for software backward compatibility or if access to RAM
location 1FFh is required.
The 128 eight-bit control registers (referred as AR or ARx<y:z>) use RAM-mapped I/O
access. Location 1FFh in RAM is used to address up to 128 byte-width ARs. The AR
number and written data are encoded into the data field as illustrated in Figure 4.
15 14
8
7
0
DWB
AR number
Data
Figure 4
AR Register Format
When writing to address 1FFh, the Data Write Bit (DWB) and AR number are latched,
depending on whether the DWB data field is either written to the selected port (latched) or
discarded (not latched). The AR number and corresponding data are read after reading
from the previously latched DWB address 1FFh.
To write to the AR, the data must be written to address 1FFh; DWB must be set to “1,” the
port number must be specified in bits 8–14, and actual data must be specified in bits 0–7.
Example
LD
LD
A, #(%8000 + 29*256 + %57); write 57 (hex) into the AR29
%1FF, A;
Note: The DWB and port number are latched for further reading if necessary.
To read from the AR, the address must be previously latched by writing it to address 1FFh
with DWB set to “0.” Bits 0–7 have no meaning. Because the bits are not going to be
written in this mode, only the port number is latched.
Example
LD A, #%1E00; latch AR30, data is not written
LD %1FF, A;
LD A, %1FF; read from AR30-%1EXX, where XX is current content
At least one cycle delay (NOP) is required between two consecutive accesses to the AR. If
access is performed by a two-cycle instruction, no delay is necessary.
External memory must exhibit access times of less than 60 ns. Table 5 lists the additional
control registers.
PS005600-TVC1299
Preliminary
21
Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
Table 5
Additional Control Registers
Bit
AR #
Name
position Data
Function
0
Palette_8
Palette_8
Palette_8
Palette_8
Palette_8
Palette_8
Palette_8
Palette_8
Palette_9
76------ %D
Reserved
--543210 %DD Palette8/Color0ÑR1R0G1G0B1B0
76------ %D Reserved
--543210 %DD Palette8/Color1ÑR1R0G1G0B1B0
76------ %D Reserved
--543210 %DD Palette8/Color2ÑR1R0G1G0B1B0
76------ %D Reserved
--543210 %DD Palette8/Color3ÑR1R0G1G0B1B0
76------ %D Reserved
--543210 %DD Palette8/Color4ÑR1R0G1G0B1B0
76------ %D Reserved
--543210 %DD Palette8/Color5ÑR1R0G1G0B1B0
76------ %D Reserved
--543210 %DD Palette8/Color6ÑR1R0G1G0B1B0
76------ %D Reserved
--543210 %DD Palette8/Color7ÑR1R0G1G0B1B0
76543210 %DD Same as AR 0Ð7 for Palette9
76543210 %DD Same as AR 0Ð7 for Palette10
76543210 %DD Same as AR 0Ð7 for Palette11
76543210 %DD Same as AR 0Ð7 for Palette12
76543210 %DD Same as AR 0Ð7 for Palette13
76543210 %DD Same as AR 0Ð7 for Palette14
76543210 %DD Same as AR 0Ð7 for Palette15
Reserved
1
2
3
4
5
6
7
8Ð15
16Ð23 Palette_10
24Ð31 Palette_11
32Ð39 Palette_12
40Ð47 Palette_13
48Ð55 Palette_14
56Ð63 Palette_15
64Ð123
124
PgLocation0 7------- 0
Page0 is located internallyÐPOR
Page0 is located externally
Internal ROM is enabledÐPOR
Internal ROM is disabled (low power
consumption)
1
-6------ 0
1
--543210 %DD Page0Ñexternal (physical) page number
PS005600-TVC1299
Preliminary
22
Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
Table 5
Additional Control Registers
Bit
AR #
Name
position Data
Function
125
PgLocation1 7------- 0
Page1 is located internallyÐPOR
Page1 is located externally
Reserved
1
-6------ 0
--543210 1
%DD
Page1Ñexternal (physical) page number
126
127
PgLocation2 76543210 %DD Same as above for Page2
PgLocation3 76543210 %DD Same as above for Page3
RAM Addressing
The addresses in RAM can be specified in one of three ways. Refer to Figure 5.
RAM Pointers
%37
RAM Pointers
RAM 0
RAM1
%FF
%FF
P0:0
P0:1
256X16-BIT
256X16-BIT
P1:0
P2:0
P1:1
P2:1
@P1:0
%37
%04
%00
%0321
%0321
S4/S3 = 01
%00
Data Pointers
%0321
Internal ROM
%8000
D0:0
D1:0
D2:0
D3:0
@D0:1
D0:1
D1:1
D2:1
D3:1
64Kx16-Bit
%1234
@@P1:0
%0321
%0000
Figure 5
RAM, ROM, and Pointer Architecture
PS005600-TVC1299
Preliminary
23
Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
2.2
Memory (ROM and RAM)
The Z90376 has 64K words of Read Only Memory (ROM) and 1K words of Random
Access Memory (RAM).
ROM
The 64K words mask ROM is designed to provide storage for both program memory
(PROGROM) and character set graphic pixel arrays (CGROM). The address boundary
between these applications is dependent on the storage required for character graphics.
The program ROM section can, in theory, be accessed anywhere in the addressable ROM
space; however, because CGROM usually starts at location 0000h, program ROM resides
in the higher address locations. The maximum available ROM space for program memory
depends on the ROM reserved for CGROM (for an application) and the ROM size of the
device selected.
CGROM can be placed anywhere in the 64K ROM address space by setting the CGROM
address offset register R7(2). This offset is added to the character address before accessing
ROM. By modifying the CGROM offset, several fonts can be accessed (limited by ROM
size only). When reset, R7(2) =0 (no offset) for backward compatibility with existing
software. Refer to Figure 6.
PS005600-TVC1299
Preliminary
24
Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
64K
Int0 vector
%FFFF
Int1 vector
Int2 vector
%FFFE
%FFFD
%FFFC
Reset vector
Program ROM or CGROM
Up to 5K
%140
0
CGROMÑBank 0, Scan lines 19, 20
or Bank1 or Program ROM
Up to 4.5K
%1200
%1000
%10*n
CGROMÑBank 0, Scan lines 17, 18
or Bank 1, or Program ROM
4K
Program ROM
Up to 4K
CGROM-Bank 0 (n Characters)
Scan lines 1-16
%0000
Figure 6
ROM Map
RAM
The 1K words RAM is organized in four banks of 256 words consisting of 16 bits each.
Bankl.0 is always accessible. Bank0.0 is mapped to other bank(s); only one gauge from 0.X
is active through bit selection. See Figure 7.
256
256
256
256
words
words
Bank0.2
Bank0.1
Bank1.0
Bank0.0
Figure 7
RAM Allocation
PS005600-TVC1299
Preliminary
25
Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
2.3
Clock Circuit Description
The processor is able to operate from several clock sources:
•
•
•
Primary Phase Lock Loop VCO source (PVCO)
Secondary Phase Lock Loop (SVCO)
32.768-KHz oscillator clock (OSC)
In addition, the processor clock can be halted temporarily to select the clock source or
access ROM without disrupting normal operation of the processor.
An external crystal controls the internal 32.768-KHz oscillator. The crystal is used as the
clock reference for the internal Phase Locked Loop (PLL). The PLL provides the internal
PVCO clock for processor operation. SCLK is generated internally by dividing the
frequency of an appropriate oscillator (PVCO) by 2. The frequency of the SCLK after
POR is 12.058 MHz.
The SCLK signal can be sent to the Port16 output pin under software control by setting
bit 9 in register R3(1). The SVCO must be used as the system clock when the OSD is
generated.
The clock switch control register R6(1) defines the source of the SCLK for the Z90376
core. The block diagram in Figure 8 represents the clock switch circuit.
12-MHz
SVCO
SVCO/PVCO
SWITCH1
0
Fast/Slow
SWITCH3
0
No_Switch
SWITCH2
0
SCLK
32.768-KHz
oscillator
12 MHz
PVCO
2
2
PLL
1
1
2
1
PLL
Filter
Divider
R6(1)<5>
R6(1)<4>
R1(1)<0>
Figure 8
Clock Switching Block Diagram
PS005600-TVC1299
Preliminary
26
Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
Input/Drive Circuits
The 32-KHz oscillator circuit in Figure 9 is suggested for proper clock operation.
Z90376
XTAL1
22 pF
XTAL2
68 KΩ
47 pF
Figure 9
32-KHz Oscillator Recommended Circuit
PS005600-TVC1299
Preliminary
27
Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
2.4
Reset Conditions
Reset conditions including addresses and registers are listed in Table 6.
Table 6
Reset Conditions
----------------------------- Reset Condition -------------------------
Addr Register
15 14 13 12 11 10 9
8
x
x
7
x
x
6
x
x
5
x
x
4
x
x
3
x
x
2
x
x
1
x
x
0
x
x
Comments
R0(0) reserved
x
x
x
x
x
x
x
x
x
x
x
Not available
R1(0) Cursor Palette x
0
0
Cursor palette
gauge
R2(0) pll_freq
0
0
0
0
1
0
0
0
0
0
0
x
0
x
0
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
PLL frequency
control
2
2
R3(0) I C_int
I C interface
register
R4(0) port0
R5(0) port1
R6(0) dir0
x
x
1
x
x
1
x
x
1
x
x
1
x
x
1
x
x
1
x
x
1
x
x
1
x
x
1
x
x
1
x
x
1
x
x
1
x
x
1
x
x
1
x
x
1
x
x
1
16-bit I/O port 0
9-bit I/O port 1
16-bit port 0
direction
R7(0) dir1
x
x
x
x
x
x
x
1
0
1
0
1
x
1
x
1
x
1
x
1
x
1
x
1
x
9-bit port 1 direction
R0(1) clamp_pos
1
1
1
1
0
0
0
position of video
clamp pulse
R1(1) sclk_freq
R2(1) 9-bit cntr
R3(1) standard_ctl
R4(1) ADC_ctl
x
x
0
0
x
0
x
0
0
x
0
0
x
0
x
0
0
x
0
0
x
0
x
0
0
x
0
0
x
0
x
0
0
x
0
0
0
0
x
0
0
x
0
0
0
0
x
0
0
x
0
0
x
0
x
0
0
x
0
0
x
0
x
0
0
x
0
0
x
0
0
x
x
0
0
0
x
0
x
x
x
0
0
0
x
x
x
x
x
0
x
0
x
1
x
x
0
0
x
x
x
x
x
x
0
0
x
x
x
x
x
x
0
0
0
x
x
x
x
x
0
0
0
x
x
x
x
x
Stop/sleep/normal
mode
Stop and WDT, 9-
bit counter
Output H/VSYNC/
Blink Control
A/D converter
control
R5(1) cap_1s_ctl
R6(1) clock_ctl
R7(1) wdt_smr_ctl
R0(2) pwm_data1
Counter timers
control
Clock control
(switch VCO/DOT)
SMR and WDT
control/interrupt
8-bit PWM 1 data
PS005600-TVC1299
Preliminary
28
Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
Table 6
R1(2) pwm_data2
Reset Conditions
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
x
x
x
x
x
x
0
x
x
x
x
x
x
0
x
x
x
x
x
x
0
x
x
x
x
x
x
0
x
x
x
x
x
x
0
x
x
x
x
x
x
0
x
x
x
x
x
x
0
x
x
x
x
x
x
0
8-bit PWM 2 data
8-bit PWM 3 data
8-bit PWM 4 data
8-bit PWM 5 data
8-bit PWM 6 data
Shadow color ctrl
R2(2) pwm_data3
R3(2) pwm_data4
R4(2) pwm_data5
R5(2) pwm_data6
R6(2) Shadow Ctrl
R7(2) CGROM offset 0
CGROM offset
register
R0(3) hi_x2_hi_x3
R1(3) lo_x2_mid_x3
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Character multiple/
current data
Character multiple/
next or previous
data
R2(3) Ch_x1_lo_x3
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
Character multiple/
character graphics
attribute
R3(3) attr_data
R4(3) osd_cntl
R5(3) cap_data
R6(3) palette_color
x
x
x
0
x
x
x
0
x
x
x
0
x
x
x
0
x
x
x
0
x
x
x
0
x
x
x
0
x
x
x
0
x
x
x
0
x
x
x
0
x
x
x
0
x
x
x
0
x
x
x
0
x
x
x
0
x
x
x
0
x
x
x
0
Character attribute/
video RAM data
On screen display
control
Capture register
data
Display palette
color/underline
color
R7(3) output palette
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Output palette
PS005600-TVC1299
Preliminary
29
Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
2.5
Power Management
There are two low-power operating modes for Z90376: SLEEP mode and STOP mode.
SLEEP Mode
In SLEEP mode, the controller uses the 32.768-KHz clock for the SCLK to reduce power
consumption.
STOP Mode
In STOP mode, the processor is suspended, and the power consumption is minimized.
2.6
I/O Port Configurations
User control can be monitored either through the keypad scanning port or the 16-bit
remote control capture register.
Two input/output port blocks are available for general-purpose digital I/O application.
Each port bit can be programmed to be either an input or output port. To conserve the
device pin count, some port pins are mapped to provide I/O to the ADC converter block
2
and I C interface block.
The 25 configurable I/O pins are general-purpose pins for functions such as serial data
2
I/O, LED control, key scanning, power control and monitoring, and I C serial data
communications.
Port 0and 1directions are defined in R6(0)and R7(0),respectively. R4(0)and
R5(0)are data registers for both Ports 0and 1. Figure 10, Figure 11, and Figure 12
indicate I/O configuration and sharing with other functional units.
PS005600-TVC1299
Preliminary
30
Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
Direction
V
CC
1ÑIN
0ÑOUT
Pad
Output
20 Ω
Input
Figure 10 Bidirectional Port Pins
Direction
1- IN
VCC
0- OUT
PAD
I2C
Output
PORT
Onput
20 Ω
Input
Figure 11 Bidirectional Pins Multiplexed with I2C Port
PS005600-TVC1299
Preliminary
31
Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
Direction
V
CC
1ÑIN
0ÑOUT
PAD
Output
Input
20 Ω
Analog
MUX
Figure 12 Bidirectional Pins Multiplexed with ADC Inputs
2.7
Interrupts
The Z90376 has three external interrupt signals. There are four interrupt sources as
follows:
•
•
•
•
Horizontal sync (H
)
SYNC
Vertical sync (V
Capture timer
)
SYNC
multiplexed
External event (Port09)
}
All interrupts are vectored. The capture timer and Port09 are multiplexed to the same
interrupt.
Interrupt priorities are programmable. Each interrupt can be masked by setting fields in the
external registers.
When the Z90376 receives an interrupt request from one of the interrupt sources, it
executes the interrupt service routine directly for that source.
External register R7(1)controls interrupts.
PS005600-TVC1299
Preliminary
32
Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
2.8
Timers
Watch-Dog Timer
The watch-dog timer resets the CPU when it times out.
External register R7(1)controls the watch-dog timer.
Real Time Clock
A clock timer, in real time, generates ticks every 1000, 250, 62.5 or 15.625 ms. External
register R5(1)controls the real time clock.
IR Capture Timer
A capture timer measures time between edges of the IR signal. This timer can be
programmed to measure timing from rising-to-rising, falling-to-rising, rising-to-falling, or
falling-to-falling edges.
The IR capture timer is controlled by External register R5(1).Figure 13 is a block
diagram of the IR capture register structure.
CAP_Glitch
CAP_Edge
Halt capture timer
R5(1)<6>
Capture
Register
Glitch
Filter
Edge
Detector
Capture
Time
Captured data
R5(3)
IR
Falling edge is captured
Reset R5(1)<e>
Capture
Flags
Prescaler
Raising edge is captured/
Reset R5(1)<f>
CAP_speed
R5(1)<1:0>
Timeout/
Reset R5(1)<c>
Figure 13 IR Capture Register Block Diagram
PS005600-TVC1299
Preliminary
33
Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
2.9
ADC
This function employs a 4-bit resolution, flash A-to-D converter. The six-to-one analog
input multiplexor and conversion start circuits are controlled by the user program. The
4-bit conversion result is available to be read by the CPU at the end of each conversion.
One input channel (ADC0) is dedicated for quantizing VBI (vertical blank interval) data
for subsequent digital signal processing. Another channel, ADC5, is typically used for
VSYNC separation from the composite TV signal. These channels (ADC0 and ADC5)
feature a special video clamp circuit that provides DC restoration of the composite video
input signal. Typical VBI applications include Line 21 Closed Caption, Electronic Data
Services, and StarSight Telecast. The range of ADC0 and ADC5 is from 1.5 to 2.0 V.
The four remaining channels of ADC (ADC1, ADC2, ADC3, and ADC4) are general pur-
pose. They are typically used for tuner automatic frequency control and analog key entry.
The range of ADC1–ADC4 is from 0 to 5.0 V.
The 4-bit ADC in the Z90376 features six multiplexed inputs.
The allowed range for input signals differs for various ADC inputs according to Table 7.
Table 7
ADC Inputs Typical Range
Input
Range (V)
Clamping
Typical application
CVI/ADC0
ADC1/P17
ADC2/P00
ADC3/P05
ADC4/P04
ADC5
1.5Ð2.0
0Ð5.0
Yes (RefÐ)
CCD sampling input
AFC input
No
0Ð5.0
No
Key scanning input
Key scanning input
Key scanning input
0Ð5.0
No
0Ð5.0
No
1.5Ð2.0
Yes (Ref+)
VSYNC decoder
sampling input
Reference voltages that have been generated internally define the maximum range of the
input signal for the ADC.
Nominal values are as follows:
Ref+ = 2.0 V
Ref– = 1.5 V @ V = 5.0 V
CC
For other V values, the reference voltages must be prorated as follows:
CC
Ref+ = 0.4 * V
CC
Ref– = 0.3 * V
CC
PS005600-TVC1299
Preliminary
34
Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
The maximum sampling rate of the ADC converter is 3 MHz. It takes 4 SCLK cycles for
valid output data from the ADC to become available. This is especially important if the
application uses the single-shot mode.
The ADC exhibits monotonous conversion characteristics with a nonlinearity of less than
0.5 LSB. ADC0. The ADC has a range of 0.5V (from 1.5V to 2.0V) and is directly
multiplexed to the input of the ADC. The remaining ADC inputs (ranging from 0V to 5V)
use AGND and AV voltage as a reference.
CC
Figure 14 is a block diagram of the ADC inner structure, and Figure 15 illustrates ADC
input circuits.
Z90376
REF+
CLAMP
ADC5 (VSYNC decoder)
ADC4/P04
4
6x1
MUX
ADC
ADC3/P05
ADC2/P00
ADC1/P17
CONVERTER
ADC0 (CCD decoder)
CLAMP
REFÐ
Figure 14 ADC Block Diagram
ADC Data Packing
Up to four 4-bit ADC data samples can be packed into one 16-bit word without software
overhead. If R4(1)<9> = 1, every reading of R4(1) returns the result, where the High 12
bits are the three previous ADC samples and the Low 4 bits are the current one, as
illustrated in Figure 15.
PS005600-TVC1299
Preliminary
35
Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
15
11 108
7
4
3
0
ADC sample (T-3)
ADC sample (T-2)
ADC sample (T-1)
ADC sample (T)
Figure 15 ADC Data Packing
NOPs between ADC accesses are omitted.
LD SR,%#20; select RegBank1
LD A,EXT4; turn “ADC data packing” mode on
OR A, #%0200;
LD EXT4, A;
LD A, EXT4; read first ADC sample, A = %0005
LD A, EXT4; read second ADC sample, A = %005E
LD A, EXT4; read third ADC sample, A = %05E7
LD A, EXT4; read forth ADC sample, A= %5E74
LD A, EXT4; read fifth ADC sample, first sample is thrown away, A = %E741
The ADC is controlled by the external register R4(1).
2.10 Pulse Width Modulation
Pulse Width Modulation is used in conjunction with external low-pass filters to perform
digital-to-analog conversion. Six PWMs (8-bit resolution each) generate signals for the
control of video and sound attributes. In case of a chassis employing a frequency synthesis
tuner, these PWMs can also control video or sound attributes.
Each PWM circuit features a data register whose contents are set under program control.
The data in the register determines the ratio of PWM High to PWM Low time. PWM data
registers are not initialized when reset. In order to eliminate a potential glitch on a PWM
output, it is recommended to initialize PWM data registers before enabling the VCOs.
External registers R0(2) to R5(2) are data registers for PWM1 to PWM6 accordingly.
2.11 I2C Interface
2
There are two hardware modules that support standard I C bus protocol according to the
2
2
I C bus specification published by Philips in 1992, entitled I C Peripherals for
Microcontrollers Data Handbook.
PS005600-TVC1299
Preliminary
36
Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
The first module, the Master, can be configured for fast (400 KHz) or slow (100 KHz) bit
rates and can be used in applications with a single master.
The second module, the Slave, supports a 7-bit addressing format with both fast and slow
bit rates.
TheZ90376addstwoadditionalnonstandardbitrates(50KHzand10KHz)andanadditional
2
multiplexed master port that is controlled by the I CM_mux control bit.
2
Table 8 lists the bit rates for the Master I C Bus.
2
Table 8
Master I C Bus Bit Rates
2
Mode
I C mode
Bit Rate
Actual Bit Rate
LO/Slow
HI/Slow
LO/Fast
HI/Fast
Ñ
0Ð10 KHz
0Ð50 KHz
0Ð100 KHz
0Ð400 KHz
10 KHz
44 KHz
91 KHz
334 KHz
Ñ
Slow
Fast
To suppress possible problems on both data (SDA) and clock (SCL) lines, digital filters are
2
available for all inputs of the I C bus interface. These filters exhibit a time constant equal
to 3T
= 250 ns.
SCLK
2
If the Master or Slave I C interface is enabled, corresponding I/Os (Port01 and Port02 for
the slave, Port11 and Port12 for the master) must be assigned as outputs.
2
Master and Slave modules cannot be used simultaneously because of the shared I C data
2
register (see the Register 3(0) data field). The software activates I C modules by writing
2
appropriate commands into the control register. To control the I C bus interface, the
control register R3(0) toggle bit <c> must point to an appropriate interface (Master or
Slave).
2
M_disable or S_disable bits allow either the Master or Slave I C interface to be disabled
so as not to interfere with any activity associated with the Port pins. At Power-on Reset
2
2
(POR), both I C interfaces are enabled. To use the I C interface, the corresponding Port
2
pin (multiplexed with the I C Data and Clock) must be configured as an output, while
M_disable or S_disable bits must be reset to 0.
2
2
External register R3(0) controls the I C. Table 9 lists the Master I C bus interface
2
commands. Table 10 lists the Slave I C bus interface commands. Figure 16 and Figure 17
are flow charts of the Master and Slave modes.
PS005600-TVC1299
Preliminary
37
Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
2
Table 9
Master I C Bus Interface Commands
Command
Notes/Function
0 0 0
This command sends a start bit, followed by an address byte speciÞed in
the ÒdataÓ Þeld (bits <7:0>), then fetches an acknowledgment in bit <0>.
This command initializes communication and generates 9 SCL cycles.
0 0 1
0 1 0
This command sends one byte of data speciÞed in the ÒdataÓ Þeld (bits
<7:0>), then fetches an acknowledgment in bit <0>. This command is
used in a WRITE frame and generates 9 SCL cycles.
This command sends bit <7> as an acknowledgment (ACK = 0, NAK =
1), then receives a data byte. This command is used in a READ frame
when the next data byte is expected and generates 9 SCL cycles.
Received data appears in the ÒdataÓ Þeld (bits <7:0>).
0 1 1
This command sends bit <7> as an acknowledgment (ACK = 0, NAK =
1). This command is used in a READ frame to terminate data transfer
and generates one SCL cycle.
1 0 0
1 0 1
A NULL operation. This command must be used with a ÒRESETÓ bit <b>
and/or a ÒTOGGLEÓ bit <c>.
Using the ÒRESETÓ and/or ÒTOGGLEÓ bits with any other command
2
interferes with the logic of the I C interface.
1 1 0
1 1 1
This command receives one data byte. It is used in a READ frame to
receive the Þrst data byte after the address byte is transmitted. It
generates 8 SCL cycles.
This command sends a stop bit and generates one SCL cycle.
PS005600-TVC1299
Preliminary
38
Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
2
Table 10
Slave I C Bus Interface Commands
Command
Notes/Function
0 0 0
0 0 1
Reserved. Cannot be used.
This command sends bit <7> as an acknowledgment (ACK = 0 only),
then receives one data byte. This command is used in a WRITE frame
and requires 9 SCL cycles. Received data is read as a ÒdataÓ Þeld (bits
<7:0>).
0 1 0
0 1 1
This command sends one byte of data speciÞed in a ÒdataÓ Þeld (bits
<7:0>), then fetches an acknowledgment in bit <0>. This command is
used in a READ frame and requires 9 SCL cycles.
Reserved. Cannot be used.
1 0 0
1 0 1
A NULL operation. This command must be used with a ÒRESETÓ bit <b>
and/or ÒTOGGLEÓ bit <c>.
Using the ÒRESETÓ and/or ÒTOGGLEÓ bits with any other command
2
interferes with the logic of the I C interface.
1 1 0
This command sends a bit <7> as a not acknowledgment (NAK = 1 only)
in a WRITE or READ frame. This command terminates I C
2
communication and requires one SCL cycle. The ÒSulfonamideÓ bit <a>
is automatically reset when a ÒbusyÓ bit <9> goes Low.
This command sends a bit <7> as an acknowledgment (ACK = 0 only) in
a READ frame and requires one SCL cycle. The Send data command
(010) must be executed next. This command acknowledges an address
byte in a READ frame.
1 1 1
Reserved. Cannot be used.
PS005600-TVC1299
Preliminary
39
Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
START
yes
no
Read R3(0)<8>
ÒBusyÓ ==0?
Send a start bit followed
by a 7-bit Address byte
Write R3(0)
{0000,0xxx,Addr,R/W}
no
yes
ÒBusyÓ==1
Read R3(0)<0>
(Read Ack bit)
no (Nak)
R3(0)<0>==0?
yes
(Ack)
Read frame
Write frame
Write R3(0)
More bytes
to send?
no
{1100,0xxx,xxxx,xxxx}
(Ask slave to send Data byte)
yes
Write R3(0)
yes
{0010,0xxx,Data}
(Send Data byte)
ÒBusyÓ==1?
no
Read R3(0)
yes
no
ÒBusyÓ==1?
{xxxx,xxxx,Data}
(Read Data byte)
Write R3(0)
Write R3(0)
no
{0110,0xxx,1xxx,xxxx}
(Nak Data byte)
{0110,0xxx,0xxx,xxxx}
Receive more bytes?
yes
(Ack Data byte)
Write R3(0)
{0100,0xxx,0xxx,xxxx}
(Acknowledge Data byte)
yes
no
ÒBusyÓ==1?
Write R3(0)
{1110,0xxx,xxxx,xxxx}
(Send a ÒStopÓ bit)
Note:
Shaded blocks are executed in software
Figure 16 Master Mode
PS005600-TVC1299
Preliminary
40
Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
START
yes
no
ÒStartÓ condition
detected
Set R3(0)<9>
Reset R3(0)<9>
yes
Set slave modeR3(0)<a>
no
Address matches
Reset R3(0)<a>
Hold the bus
Stretch clock
Reset slave busyR3(0)<9>
(Nak Master)
Write R3(0)
Ignore master
Ack master
{1100,0xxx,1xxx,xxxx}
Read frame
Write frame
R3(0)<0>=0
R3(0)<0>=1
Read R3(0)<0>
(R/W bit)
(Ack Master)
Write R3(0)
{1100,0xxx,0xxx,xxxx}
(Nak master)
Write R3(0)
1100,0xxx,1xxx,xxxx 0010,0xxx,0xxx,xxxx
(Ack master)
Write R3(0)
no
Slave = 1,Busy = 0
R3(0)<a:9>
no
Slave = 1,Busy = 0
Wait here for Òsend
first byteÓ command
R3(0)<a:9>
yes
yes
(Send data)
Write R3(0)
hold the bus
stretch clock
{0100,0xxx,Data}
no
(Get Data)
Slave = 1,Busy = 0
R3(0)<a:9>
Read R3(0)
Wait for Ack
from master
yes
goto Ack Master
no (Nak)
Read R3(0)<0>
Ack==0?
yes (Ack)
hold the bus
stretch clock
Note:
Shaded blocks are executed in software
Note: If a “Stop” condition is detected at any point, the hardware resets the “Slave” bit
2
(R3(0)<a>) and releases the I C bus.
Figure 17 Slave Mode
PS005600-TVC1299
Preliminary
41
Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
2.12 Progressive Scan
Using Progressive Scan in the Z90376 produces a high-quality picture which eliminates
dithering and flickering. The Z90376 in Progressive Scan mode displays every line of the
OSD twice. The refresh rate of the OSD matches the video signal refresh rate. The
effective vertical resolution of the OSD is reduced by a factor of two when Progressive
scan is activated. Register R1(1) controls the operation of progressive scan.
Figure 18 illustrates how progressive scan works on the screen.
Video line N is displayed.
First half of Buffer0 is filled.
No OSD is displayed.
Video line N+1 is displayed.
Second half of Buffer0 is filled.
No OSD is displayed.
Video line N+2 is displayed.
First half of Buffer1 is filled.
Buffer0 is displayed.
Video line N+3 is displayed.
Second half of Buffer1 is filled.
Buffer0 is displayed again.
Video line N+4 is displayed.
First half of Buffer0 is filled.
Buffer1 is displayed.
Figure 18 Progressive Scan
2.13 On-Screen Display (OSD)
The Z90376 provides sophisticated on-screen display features. On-Screen Display has the
following two modes:
•
•
OSD Used to generate TV control OSD
CCD Used to display Closed Caption information
OSD mode provides access to the full set of control attributes including latched and
unlatched attributes. Unlatched attributes can be modified on a character-by-character
basis. Control characters change latched attributes.
PS005600-TVC1299
Preliminary
42
Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
Any 256-character set can be displayed with many display attributes, including
underlining, italics, blinking, eight foreground and background colors, character position
offset delay, and background transparency. A 16-bit display character represents
foreground color, background color, and underline attributes, which can be modified
character by character. In addition, the Z90371 supports eight fixed plus eight
programmable color palettes out of 64 colors, independent left and right shadows with
color control. Shadows are available on transparent and nontransparent backgrounds.
Semitransparency is supported on a character-by-character basis. A character’s pixel array
is stored as 16, 18, or 20 words in Character Generation ROM (CGROM).
Additional hardware provides the capability to display characters at two and three times
normal size. The smoothing logic contained in the on-screen display improves the
appearance of two and three times normal size characters. Shadows can be activated to
improve the visibility of characters by adding a border (one pixel wide) on each side.
The Z90376 provides RGB signals and a video blank signal. RGB outputs are available in
two modes: digital and analog. In digital mode, the output RGB signals correspond to a
primary colors palette. Analog mode supports 15 different palettes, which can be chosen
under software control. In analog mode, each RGB output is generated by a 2-bit digital-
to-analog converter. The user can switch the 2-bit digital inputs of the digital-to-analog
converter to Port pins (P10, P13, P14, P15, P18 and P08) under software control by setting
bit9 in register R3(1).
Video synchronization is normally obtained from H_FLYBACK and V_FLYBACK but
can be generated by the Z90376 and driven to the external deflection unit using the
bidirectional SYNC ports when external video synchronization signals are not present.
OSD is completely software controlled. Hardware supports the optimum generation of the
character-based OS; however, the CPU can bypass it and generate pixels and attributes
directly. The block diagram in Figure 19 illustrates the OSD data flow.
Figure 20 and Figure 21 indicate the V1, V2, V3, and Blank output circuits.
PS005600-TVC1299
Preliminary
43
Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
Shift
Register
P
a
l
Video RAM
OSD:At7Ch8
or Attr15
CCD:Char7
orAttr7
CGROM
Pixels: 1x
2x
3x
Full attrib
3
x
D
A
C
R
G
B
e
t
t
e
s
Attribute
Memory Rd
CPU
Figure 19 Data Flow
V
CC
P
PAD
Output
N
Figure 20 Blank and V1, V2, V3 Outputs in Digital Mode
PS005600-TVC1299
Preliminary
44
Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
V
V
V
CC
CC
CC
I ≈ 800 mA
I / 2
I / 4
Vx<1>
Vx<0>
PAD
R ≈ 3 K
Figure 21 V1, V2, and V3 Outputs in Analog (Palette) Mode
Closed Caption Data Capture
Closed-caption text can be decoded directly from the composite video signal using the
processor’s digital signal processing capabilities and displayed on the screen. The
character representation in this mode provides simple attribute control by inserting control
characters. Each word of video RAM specifies two displayed characters.
The 4-bit flash A/D converter, with proper clamping, provides the ability to receive the
composite video signal directly and process the closed-caption text embedded in the
signal. Signal processing can be applied directly to the signal to improve decoder
performance.
CGROM Relocation
CGROM can be placed anywhere in the 64K ROM address space by setting the CGROM
address offset register R7(2). This offset is added to the CGROM address before accessing
the ROM. By modifying the CGROM offset, several fonts can be accessed (limited only
PS005600-TVC1299
Preliminary
45
Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
by ROM size). When reset, R7(2) = 0 (no offset), making the Z90376 backward-
compatible with existing OSD control software.
The character scan line from CGROM addressed by the character register is fetched and
stored into the CGROM capture register. If a pixel is set to 1, it displays the foreground
color. If a pixel is set to 0, it displays the background color. The scan line can be stretched
by the character multiplier to be two or three times normal character size by duplicating
each bit in the word.
Controlling Character Expansion
The character size can be stretched to two or three times its size the size of the scan line.
Hardware fetches data from CGROM and stretches the data to be read from registers
R0(3), R1(3), and R2(3). Figure 22 is a block diagram of the structure of the character
expansion multiplexor, and Table 11 lists bit functions.
16
ROM data
CGROM data
capture register
16
control
x1, x2, x3
Character
Expansion
Multiplexor
48
16
16
16
R0(3)
R1(3)
R2(3)
char_mult_high
char_mult_mid
char_mult_low
Processor EXTERNAL bus
Figure 22 Character Expansion
PS005600-TVC1299
Preliminary
46
Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
Table 11
Character Expansion Register
Capture
Register
Contents
Char_mult_high
Char_mult_mid
Char_mult_low
x1 operation
x2 operation
x3 operation
abcdefghijklmnop
aabbccddeeffgghh iijjkkllmmnnoopp
aaabbbcccdddeeef ffggghhhiiijjjkk klllmmmnnnoooppp
Displayed Data Formats
The Z90376 hardware supports the following two different data formats:
•
•
OSD mode, R4(3)<d> = 1 supports a standard OSD with full set of features.
CCD mode, R4(3)<d> = 0 supports reduced features which comply with the
recommendations of the FCC on Closed Caption support.
In CCD mode, the background color of the characters cannot be changed and is always
preset to BLACK.
OSD Mode
In OSD mode, each character occupies a 16-bit word in VRAM. There are two possible
character formats defined: a “display” character and a “control” character. The code stored
in “display” character format defines a character code and up to 7 attributes of the
character.
The “control” character defines latched attributes and is presented on-screen as a space
character. The combination of “display” and “control” characters provides versatile OSD
generation.
Smoothing is supported for double-size (x2) and triple-size (x3) characters only.
CCD Mode
In CCD mode, each character occupies 8 bits (one byte) in VRAM. The CCD characters
must be mapped into a 16-bit VRAM data field. The hardware supports compressed
placement of characters in VRAM. Each word in VRAM is represented by a High byte
and a Low byte. A currently active byte is selected by R4(3)<c>. The format and data
representation in both bytes is exactly the same.
There are two possible character formats defined: a “display” character and a “control”
character. The code stored in “display” character format defines a character code. The
PS005600-TVC1299
Preliminary
47
Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
“control” character defines up to five attributes (foreground color, italic, underline,
blinking, and transparent). It is presented on screen as a space character. The combination
of Display and Control characters provides the basis for a specified range of attributes
defined by FCC specifications for CCD.
Shadows/Fringing
Shadows (fringing), if enabled, are active on both transparent and nontransparent
backgrounds. Two bits in the AttributeWR and AttributeRD registers, (R2(3)<1:0> and
R3(3)<1:0>), control the type of shadow. Refer to Figure 23.
Background
R2(3)<1:0>,
R3(3)<1:0>
Function
Foreground
00
01
10
11
No shadows
Left shadow
Right shadow
Right shadow
Both shadows (fringing)
Left shadow
Figure 23 Table Settings
The smoothing attribute has been moved to R7(3)<5>.
The bit assignment in the Latched Attribute follows the bit assignment in R2(3).
The left and right shadow colors are independently controlled by R6(2)<d:b> and
R6(2)<a:8>.
Note: The smoothing control bit R7(3)<5> must be set to a “1” in order to activate
fringing.
Semi-Transparent
Both semi-transparency (pin name SOVL) and transparency (pin name OVL) attributes are
supported. The semi-transparency mode can be enabled through either latched or
unlatched attributes. Latched attributes remain set until they are reset. Unlatched attributes
remain set for only one character, which means the attribute must be constantly refreshed
on a character-by-character basis.
PS005600-TVC1299
Preliminary
48
Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
Activation
To activate semi-transparency output, two bits must be set properly. Port 0F must be in
output mode [R6(0)<f> = 0], and the SOVL/port0F control bit must be in SOVL mode
[R3(1)<6> = 1].
Latched Semi-Transparency
The latched semi-transparency attribute is controlled by bit [R2(3)<6>].
Unlatched Semi-Transparency
The unlatched semi-transparency attribute is controlled by bit [R3(3)<8>]. This bit has
one of four possible assignments depending on how it is set up in [R7(3)<7:6>]. The four
assignments are underline, semi-transparency, blinking, and CGROM bank select.
Notes:
1.
The semi-transparency signal (SVBLANK), when active, is only valid with the
background color. With the foreground color, SVBLANK is inactive. Therefore,
characters do NOT take on a semi-transparent appearance (only the background
does). This condition allows characters to be read without interference.
2.
If both the transparency (background and foreground color are equal) and semi-
transparency are activated, the transparency takes precedence over the semi-
transparency. The VBLANK signal is High, and the SVBLANK signal is Low.
Attribute_8 Assignment
Depending on R7(3)<7:6>, bit 8 of the Attribute_Data register, R3(3) (in character mode)
can be assigned to control either “1st underline,” “semi-transparency,” “blinking,” or
“CGROM bank select,” as indicated in Table 12.
Table 12
Attribute Assignment
R3(3)<8>
R7(3)<7:6>
00
01
10
11
1st underline (POR)
Semi-transparency
Blinking
CGROM bank1 select
PS005600-TVC1299
Preliminary
49
Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
2.14 Cursor
The cursor is a one-line pixel buffer. The cursor buffer is loaded via the DMA on every
line where the cursor is displayed (no software support is required). Horizontal size is
programmable at 16, 32, or 48 pixels wide, and vertical size is programmable from 1 to 63
lines per field. The color depth is 2 bits per pixel, 3 programmable colors and the
transparency. Depending on R1(0)<d>, the cursor’s colors can be selected either from a
current palette (R1(0)<d> = 0) or from Palette #6 (R1(0)<d> = 1). Refer to Table 15. The
cursor image is stored in ROM as a bitmap. The number of cursors is limited by ROM size
only.
The cursor is positioned by initializing cursor parameters in the beginning of every field.
Initialization occurs by setting the Cursor_Info_Load bit R7(3)<4> to 1, then writing
sequentially to the R3(3) 16-bit parameters (COLOR, HPARAM, VPARAM and CADDR,
respectively).
The cursor buffer is loaded from ROM at the leading edge of HSYNC wherever the
horizontal line requires a cursor. This process halts the CPU for 3/5/7 cycles depending on
the cursor’s horizontal size. The cursor bitmap address pointer (CADDR) is incremented
automatically.
Though the cursor can be displayed anywhere on the screen, limiting the cursor to the
OSD area is best. Outside of the OSD area, the cursor can jitter or become distorted.
The cursor bitmap is organized as pixel data placed sequentially in the ROM. The data
format is described below.
For the interlaced mode, even and odd cursor bitmaps must be defined separately. Proper
selection occurs during the cursor initialization at the beginning of every field. See Figure
24, Table 13, and Table 14.
Focus
(X,Y)
Horizontal position (X: 1Ð1023)
Vertical
position
(Y: 1Ð1023)
63 lines max
(00) transparent
(01) color 1
(10) color 2
(11) color 3
(2*63 in progressive
scan mode)
48 pixels max
Figure 24 Cursor
PS005600-TVC1299
Preliminary
50
Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
Example
LD
OR
LD
LD
LD
LD
SR,%#60; select RegBank3
EXT7,#%0010; enable Cursor_Info_Load
EXT3,#(3*64 + 7*8 + 2); load CCOLOR: color3 = 3, color2 = 7, color1 = 2
EXT3,#(2*1024 + 120); load HPARAM: hsize = 2 (32 pixels), hpos = 120
EXT3,#(28*1024 + 55); load VPARAM: vsize = 28, vpos = 55
EXT3,#%6000; load CADDR—cursor bitmap address
AND EXT7,#%FFEF; disable Cursor_Info_Load, ready for OSD
Table 13
Cursor Parameters
Parameter Reg Þeld Bit position
Data
Description
CADDR CADDR fedcba9876543210 %DDDD Cursor bitmap address
(pointer to cursor bitmap in ROM)
Vertical size (lines in one Þeld)
------9876543210 1Ð1023 Vertical position (lines in one Þeld)
VPARAM VSIZE
VPOS
fedcba---------- 1Ð63
HPARAM n/a
HSIZE
fedc------------ n/a
Reserved
----ba---------- 00
No cursor
01
10
11
16 pixels wide
32 pixels wide
48 pixels wide
HPOS
------9876543210 1Ð1023 Horizontal position (pixels from
trailing edge of HSYNC)
CCOLOR n/a
Color3
fedcba9--------- n/a
-------876------ 0Ð7
----------543--- 0Ð7
-------------210 0Ð7
Reserved
Cursor Color 2 assignment
Cursor Color 1 assignment
Cursor Color 0 assignment
Color2
Color1
PS005600-TVC1299
Preliminary
51
Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
Table 14
Memory Allocation for Cursor Bitmap
16 Pixels Wide Mode
AddrN:
L0_P15_B0, L0_P14_B0, L0_P13_B0, ... , L0_P1_B0, L0_P0_B0
L0_P15_B1, L0_P14_B1, L0_P13_B1, ... , L0_P1_B1, L0_P0_B1
L1_P15_B0, L1_P14_B0, L1_P13_B0, ... , L1_P1_B0, L1_P0_B0
L1_P15_B1, L1_P14_B1, L1_P13_B1, ... , L1_P1_B1, L1_P0_B1
AddrN+1:
AddrN+2:
AddrN+3:
..................................................
AddrN+2n: Ln_P15_B0, Ln_P14_B0, Ln_P13_B0, ... , Ln_P1_B0, Ln_P0_B0
AddrN+2n+1: Ln_P15_B1, Ln_P14_B1, Ln_P13_B1, ... , Ln_P1_B1, Ln_P0_B1
32 Pixels Wide Mode
AddrN:
L0_P31_B0, L0_P30_B0, L0_P29_B0, ... , L0_P17_B0, L0_P16_B0
L0_P31_B1, L0_P30_B1, L0_P29_B1, ... , L0_P17_B1, L0_P16_B1
L0_P15_B0, L0_P14_B0, L0_P13_B0, ... , L0_P1_B0, L0_P0_B0
L0_P15_B1, L0_P14_B1, L0_P13_B1, ... , L0_P1_B1, L0_P0_B1
L0_P31_B0, L0_P30_B0, L0_P29_B0, ... , L0_P17_B0, L0_P16_B0
L0_P31_B1, L0_P30_B1, L0_P29_B1, ... , L0_P17_B1, L0_P16_B1
AddrN+1:
AddrN+2:
AddrN+3:
AddrN+4:
AddrN+5:
..................................................
AddrN+4n: Ln_P31_B0, Ln_P30_B0, Ln_P29_B0, ... , Ln_P17_B0, Ln_P16_B0
AddrN+4n+1 Ln_P31_B1, Ln_P30_B1, Ln_P29_B1, ... , Ln_P17_B1, Ln_P16_B1
:
AddrN+4n+2 Ln_P15_B0, Ln_P14_B0, Ln_P13_B0, ... , Ln_P1_B0, Ln_P0_B0
:
AddrN+4n+3 Ln_P15_B1, Ln_P14_B1, Ln_P13_B1, ... , Ln_P1_B1, Ln_P0_B1
:
48 Pixels Wide Mode
AddrN:
L0_P47_B0, L0_P46_B0, L0_P45_B0, ... , L0_P13_B0, L0_P32_B0
L0_P47_B1, L0_P46_B1, L0_P45_B1, ... , L0_P33_B1, L0_P32_B1
L0_P31_B0, L0_P30_B0, L0_P29_B0, ... , L0_P17_B0, L0_P16_B0
L0_P31_B1, L0_P30_B1, L0_P29_B1, ... , L0_P17_B1, L0_P16_B1
L0_P15_B0, L0_P14_B0, L0_P13_B0, ... , L0_P1_B0, L0_P0_B0
L0_P15_B1, L0_P14_B1, L0_P13_B1, ... , L0_P1_B1, L0_P0_B1
L0_P47_B0, L0_P46_B0, L0_P45_B0, ... , L0_P33_B0, L0_P32_B0
AddrN+1:
AddrN+2:
AddrN+3:
AddrN+4:
AddrN+5:
AddrN+6:
PS005600-TVC1299
Preliminary
52
Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
Table 14
Memory Allocation for Cursor Bitmap (Continued)
AddrN+7:
..................................................
AddrN+6n: Ln_P47_B0, Ln_P46_B0, Ln_P45_B0, ... , Ln_P33_B0, Ln_P32_B0
L0_P47_B1, L0_P46_B1, L0_P45_B1, ... , L0_P33_B1, L0_P32_B1
AddrN+6n+1 Ln_P47_B1, Ln_P46_B1, Ln_P45_B1, ... , Ln_P33_B1, Ln_P32_B1
:
AddrN+6n+2 Ln_P31_B0, Ln_P30_B0, Ln_P29_B0, ... , Ln_P17_B0, Ln_P16_B0
:
AddrN+6n+3 Ln_P31_B1, Ln_P30_B1, Ln_P29_B1, ... , Ln_P17_B1, Ln_P16_B1
:
AddrN+6n+4 Ln_P15_B0, Ln_P14_B0, Ln_P13_B0, ... , Ln_P1_B0, Ln_P0_B0
:
AddrN+6n+5 Ln_P15_B1, Ln_P14_B1, Ln_P13_B1, ... , Ln_P1_B1, Ln_P0_B1
:
where
Lx_Py_Bz
Line 0
=
=
=
=
line X, pixel Y, bit Z;
Þrst (top) cursorÕs line;
Pixel 0
Þrst (left) cursorÕs pixel
Bit 1, Bit 0
most and least signiÞcant bits of the cursorÕs color deÞned as
00 = transparent
01 = Color 1
10 = Color 2
11 = Color 3
PS005600-TVC1299
Preliminary
53
Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
2.15 Color Palette Assignment
The Z90376 features a total of 16 color palettes, 8 of which are fixed and 8 of which are
programmable. Palettes are selected by setting R7(3)<3:0>. Fixed palettes are defined in
Table 15.
Table 15
Fixed Palette Color Assignment
(Color0 is Black; Color7 is White)
Color1
G
Color2
G
Color3
G
Color4
G
Color5
G
Color6
G
Palette Description
R
B
R
B
R
B
R
B
R
B
R
B
0
1
2
3
4
5
6
7
Digital RGB
00 00 11 00 11 00 00 11 11 11 00 00 11 00 11 11 11 00
00 00 11 00 11 00 00 11 11 11 00 00 11 00 11 11 11 00
01 01 01 10 10 10 11 11 11 00 00 00 01 01 01 10 10 10
00 00 00 01 01 01 01 01 01 10 10 10 10 10 10 11 11 11
00 00 11 00 11 00 00 11 11 11 00 00 01 01 01 10 10 10
Analog RGB
Greyscale_1
Greyscale_2
RGB_Cyan_2Grey
RGB_Magenta_2Grey 00 00 11 00 11 00 01 01 01 11 00 00 11 00 11 10 10 10
RGB_Yellow_2Grey
StarSight
00 00 11 00 11 00 01 01 01 11 00 00 10 10 10 11 11 00
00 11 11 10 11 10 10 10 10 11 01 01 11 11 10 11 11 00
Programmable palettes (8–15) are mapped to AR0–AR63 (8 registers per palette). The
register and bit assignments for Palette # 11 are listed in Figure 25.
Programmable palettes are grouped into 2 banks (palettes 8–11 and 12–15). Palettes in the
bank cannot be modified if another palette from the same bank is displayed. An
interleaving palette bank access must be created if on-the-fly palette modifications are
required. One palette bank is used to display four colors, and the other bank is used for
updates. See Figure 25.
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
N/A
R
N/A
R
N/A
R
N/A
R
N/A
R
N/A
R
N/A
R
N/A
R
G
G
G
G
G
G
G
G
B
B
B
B
B
B
B
B
Color0
AR24
Color1
AR25
Color2
AR26
Color3
AR27
Color4
AR28
Color5
AR29
Color6
AR30
Color7
AR31
Figure 25 Programmable Palette Control at AR Register
PS005600-TVC1299
Preliminary
54
Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
2.16 Other Functions
Video and Sound Attribute Control
Basic receiver functions such as color and volume can be controlled directly by six 6-bit
pulse-width modulated ports.
InfraRed Capture Function
The Infrared Remote Control data capture feature uses a capture register to hold the time
value from one transition of IR data to the next.
Software periodically checks and reads the capture status and the value if a new capture
occurs. Subsequent decoding and command passing of the received IR signal is under
software control. Figure 26 illustrates the IR input circuit.
20 Ω
PAD
IR Input
Figure 26 IR Capture Register Input
Loop Filter
The Loop Filter pin configuration is represented in Figure 27.
V
V
CC
CC
PD ÒpositiveÓ out
PD ÒnegativeÓ out
PAD
20 Ω
To VCO driver
Figure 27 Loop Filter Pin ConÞguration
PS005600-TVC1299
Preliminary
55
Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
Hardware Accelerated 4-Bit and 8-Bit Shifts
Hardware-accelerated byte and nibble shifts significantly reduce software overhead. Shifts
are created by assigning one particular RAM location (%1FE) a special meaning.
Depending on the R4(1)<e:d> settings, data read from this address are either unmodified,
rotated 4 bits left, 4 bits right, or byte swapped. See Table 16.
Table 16
R4(1)<e:d> Settings
Function
R4(1)<e:d>
00
01
10
11
Direct (unmodiÞed)ÐPOR
4-bit left rotate
4-bit right rotate
Byte swap
Example
LD
LD
SR,#%20; Select RegBank1
A,EXT4; turn “hardware-supported shift” mode on
AND A, #%9FFF;
OR
LD
LD
LD
LD
LD
OR
LD
LD
A, #%4000;
EXT4, A; select “4-bit right rotate”
A, #%3ED7; load A = %3ED7
%1FE, A; write A to the RAM
A, %1FE; A = %73ED
A,EXT4; turn “hardware-supported rotate” mode on
A,#%6000;
EXT4, A; select “byte swap”
A, %1FE; A = %D73E
PS005600-TVC1299
Preliminary
56
Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
3
REGISTER GROUPS
Table 17 provides a summary of the registers in external banks.
Table 17
Register Summary
WRITE
Bank Sub READ
Bank Address Register
Register
Description
Bank0 7
dir1
9-bit I/O port 1 direction control
16-bit I/O port 0 direction control
9-bit I/O port 1
6
dir0
5
port1
port0
4
16-bit I/O port 0
2
2
3
I C_int
I C interface register
2
pll_freq
PLL frequency control
1
write control register
Reserved
Cursor palette gauge Write control register
Reserved
0
Bank1 7
wdt_smr_ctl/Interrupt
clock_ctl
SMR and WDT control and interrupt
Clock control (switch VCO/DOT)
Counter timers control
6
5
cap_1s_ctl
4
ADC_ctl
A/D converter control
3
standard_ctl
9-bit counter
sclk_freq
Output H/VSYNC/blnk control
Stop and WDT instructions, 9-bit counter
Stop/sleep/normal mode
DeÞnes position of video clamp pulse
CGROM offset register
2
STOP/WDT
1
0
clamp_pos
Bank2 7
CGROM offset register
Shadow Control register
pwm_data6
6
5
4
3
2
1
0
DeÞnes right and left shadow color
8-bit PWM 6 data
pwm_data5
8-bit PWM 5 data
pwm_data4
8-bit PWM 4 data
pwm_data3
8-bit PWM 3 data
pwm_data2
8-bit PWM 2 data
pwm_data1
8-bit PWM 1 data
PS005600-TVC1299
Preliminary
57
Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
Table 17
Register Summary (Continued)
Bank Sub READ
WRITE
Bank Address Register
Register
Description
Bank3 7
output palette
Output palette
6
5
4
3
2
palette_color
capture_data
osd_control
Display palette color/underline color
2
I C slave addr. Capture register data
On screen display control
attribute_data
ch_x1_lo_x3
vram_data
Character attribute/video RAM data
cg_attribute
Character multiple/character graphics
attribute
1
0
lo_x2_mid_x3
hi_x2_hi_x3
cg_nxt_prv
cg_current
Character multiple/next or previous data
Character multiple/current data
3.1
Register Description
The register file in the Z90376 is organized into four banks that can be selected by writing
to bits 5 and 6 (Register Bank Selector bits) in the Status Register of the Z90376 core.
All registers are mapped into an external register space; each bank consists of 8 registers.
The Status register is available to read or write at any time. The appropriate bank of
registers must be selected before accessing the register. The software must keep track of
which register bank is accessible at any time. Refer to Table 18 for register bank
assignments.
Table 18
Bank
Bank Assignments
Status Register
Bank Functions
2
Bank0
Bank1
Bank2
Bank3
xxxx xxxx x00x xxxx b I/O ports, I C interface, PLL frequency, cursor
xxxx xxxx x01x xxxx b Control registers
xxxx xxxx x10x xxxx b PWM1ÐPWM5
xxxx xxxx x11x xxxx b OSD, palette control
PS005600-TVC1299
Preliminary
58
Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
3.2
Bank0 (I/O Ports, I2C Interface, PLL Frequency, Cursor) Control Registers
Table 19 defines the bits for Register1–R1(0) Cursor Palette Control Register. Table 20
defines the bits for Register2–R2(0) PLL Frequency Data Register.
Table 19
Bit
Register1, R1(0) Cursor Palette
15
14
13
12
11
10
9
8
R/W
R/W
x
R/W
x
R/W
0
R/W
0
R/W
x
R/W
x
R/W
x
R/W
x
Reset
Bit
7
6
5
4
3
2
1
0
R/W
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
Reset
Note: R = Read W = Write X = Indeterminate
Reg Field
Bit Position
R
W Data
Description
Reserved
fe-------------- R
0
Reserved
No effect
W 0
Cursor Palette --d-------------
W 1
0
Palette #6 (recommended)
Current paletteÑPOR
PgWritenEn
PageWrite
---c------------ R W 1
Page Write Enable
Page Write DisableÑPOR
0
----ba9876543210 R W xxxx
WritePage#
Table 20
Bit
Register2, R2(0) PLL Frequency Data Register
15
14
13
12
11
10
9
8
R/W
R/W
0
R/W
0
R/W
1
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Reset
Bit
7
6
5
4
3
2
1
0
R/W
R/W
0
R/W
1
R/W
1
R/W
1
R/W
0
R/W
0
R/W
0
R/W
0
Reset
Note: R = Read W = Write X = Indeterminate
PS005600-TVC1299
Preliminary
59
Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
Reg Field Bit Position
R
W
Data Description
2
M_disable f--------------- R W
1
0
I C Master interface disabled
2
I C Master interface enabledÐPOR
2
S_disable -e-------------- R W
1
0
I C Slave interface disabled
2
I C Slave interface enabledÐPOR
2
2
2
I CM_mux --d------------- R W
1
0
Select I MSD2, I MSC2ÐPOR
2
2
Select I MSD1, I MSC1
2
I C_Out_ ---c------------ R W
1
0
600Ω output resistance
Normal CMOS port output
resistanceÐPOR
Resistance
2
I C_speed ----b----------- R W
1
0
Low speed range (10 KHz, 50 KHz)
High speed range (100 KHz, 400
KHz)ÐPOR
_range
Reserved -----a---------- R
Return Ò0Ó
No effect
W
P46/
HSYNC2
------9--------- R W
1
0
HSYNC logic takes input from Pin 46
HSYNC logic takes input from
HSYNC pinÐPOR
P07/
ComSYNC
-------8-------- R W
1
0
Composite Sync Output
P07 I/OÐPOR
PLL_data --------76543210 R W
xx PLL divider = 256 + xx
2
If the master or slave I C interface is enabled, the corresponding I/Os (Port01 and Port02
for the slave, Port11 and Port12 for the master) must be assigned as outputs.
The VCO, DOT, and SCLK frequency are defined as the following:
F
= F
= F
= XTAL * (256 + PLL
)
DATA
VCO
DOT
SCLK
Therefore, XTAL = 32.768 KHz
At POR, the PLL frequency data register is preset to %70, which corresponds to the VCO
frequency of 12.058 MHz.
The PLL_data field can be loaded with any value from %00. This value corresponds to an
SCLK = 256*XTAL up to %FF, which corresponds to an SCLK = 511*XTAL.
Table 21 through Table 25 describe the bits in registers 3 through 7.
PS005600-TVC1299
Preliminary
60
Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
2
Table 21
Bit
Register3, R3(0) I C Interface Register
15
14
13
12
11
10
9
8
R/W
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
1
R/W
x
R/W
x
Reset
Bit
7
6
5
4
3
2
1
0
R/W
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
Reset
Note: R = Read W = Write X = Indeterminate
Reg Field
Bit Position
R W Data Description
Return 0
Command fed------------- R
W %D See Table 9 and Table 10 for a full
description.
Toggle
Reset
---c------------ R
----b----------- R
1
0
1
0
Slave interface
Master interfaceÐPOR condition
2
W
W
Toggle active I C interface
No effect
Return 0
2
1
0
Reset Slave I C interface if bit <c> =1
Reset Master I C interface if bit <c> =0
2
No effect
Slave_mode -----a---------- R
SlaveBusy ------9--------- R
MasterBusy -------8-------- R
1
0
Slave mode is active (POR condition)
Slave mode is inactive
No effect
W
W
2
1
0
Slave I C interface is busy
2
Slave I C interface is idle
No effect
2
1
0
Master I C interface is busy
2
Master I C interface is idle
W
W
No effect
Data
--------76543210 R
xx Received data
xx Data to be sent
Data written to R3(0)<cb> requires 4 cycles before being applied. Consecutive writings to
these bits require at least a 6-cycle delay.
The received data is available for reading only when the “busy” bit is reset to a “0.” When
2
POR, the speed of the I C interface is set to “Low.”
PS005600-TVC1299
Preliminary
61
Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
Table 22
Bit
Register4, R4(0) Port 0 Data Register
15
14
13
12
11
10
9
8
R/W
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
Reset
Bit
7
6
5
4
3
2
1
0
R/W
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
Reset
Note: R = Read W = Write X = Indeterminate
Reg Field Bit Position
R
W
Data Description
Port_data fedcba9876543210
R
xxxx If a port is conÞgured in Input
mode, enter the input data onto the
port pins.
W
xxxx If a port is conÞgured in Output
mode, then the data is written
directly to the port data.
Table 23
Bit
Register5, R5(0) Port 1 Data Register
15
14
13
12
11
10
9
8
R/W
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
Reset
Bit
7
6
5
4
3
2
1
0
R/W
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
Reset
Note: R = Read W = Write X = Indeterminate
Reg Field
Bit Position
R
W
Data Description
Reserved
fedcba9---------
R
Return 0
No Effect
W
PS005600-TVC1299
Preliminary
62
Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
Reg Field
Bit Position
R
W
Data Description
Port_data
-------876543210
R
xxxx If a port is conÞgured in Input
mode, enter the input data onto the
port pins.
W
xxxx If a port is conÞgured in Output
mode, then the data is written
directly to the port data.
Table 24
Bit
Register6, R6(0) Port 0 Direction Register
15
14
13
12
11
10
9
8
R/W
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
Reset
Bit
7
6
5
4
3
2
1
0
R/W
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
Reset
Note: R = Read W = Write X = Indeterminate
Reg Field
Bit Position
R
W
Data Description
Port_direction fedcba9876543210
R
W
xxxx 1: Input mode for
corresponding bit
0: Output mode for
corresponding bit
Table 25
Bit
Register7, R7(0) Port 1 Direction Register
15
14
13
12
11
10
9
8
R/W
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
1
Reset
Bit
7
6
5
4
3
2
1
0
R/W
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
R/W
1
Reset
Note: R = Read W = Write X = Indeterminate
PS005600-TVC1299
Preliminary
63
Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
Reg Field
Bit Position
R
W
Data Description
Reserved
fedcba9---------
R
Return 0
No Effect
W
Port_direction -------876543210
R
xxxx 1: Input mode for
corresponding bit
W
0: Output mode for
corresponding bit
3.3
Bank1 (Control Registers)
Table 26 through Table 33 provide bit functions for Bank 1 Control registers.
Table 26
Bit
Register0, R0(1) Clamp Position Register
15
14
13
12
11
10
9
8
R/W
R/W
1
R/W
1
R/W
1
R/W
1
R/W
0
R/W
0
R/W
0
R/W
0
Reset
Bit
7
6
5
4
3
2
1
0
R/W
R/W
0
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
Reset
Note: R = Read W = Write X = Indeterminate
Reg Field
Bit Position
R W Data Description
Disable_clamp_1 f--------------- R W
Disable_clamp_2 -e-------------- R W
Disable_tip_clamp --d------------- R W
1
0
ADC0 Clamp generation is
disabled
ADC0 Clamp generation is
enabled
1
0
ADC5 Clamp generation is
disabled
ADC5 Clamp generation is
enabled
1
0
ADC0 Tip clamp is disabledÐ
POR
ADC0 Tip clamp is enabled
PS005600-TVC1299
Preliminary
64
Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
Reg Field
Bit Position
R W Data Description
Counter_input
---c------------ R W
1
0
Counter takes input from P06Ð
POR
Counter takes input from
internal HSYNC Separator
ARenable
Reserved
Position
----b----------- R
1
0
AR enabled
AR disabledÐPOR
W
-----a987------- R
Return Ò0Ó
No effect
W
---------6543210 R W xx Position of clamp pulse (from
leading edge of the H-
FLYBACK)
At POR the disable_clamp bit is set to 1.
The clamp pulse is generated if Enabled (bit <f>) and the SCLK frequency is switched
back to PVCO. The SVCO/PVCO flag in R6(1) must be reset to 0before the current
HSYNC, regardless of whether the SVCO is enabled or disabled.
The clamp position is defined by the Position field. The width of the clamp pulse cannot be
modified and is set to 1µs. The value that can be assigned to the “Position” field must be
>%10 and <%7F. The time interval between the leading edge of the H-FLYBACK and the
beginning of the clamp pulse can be calculated from the following equation:
1
TDELAY = Position -------- = Position× 82ns
TSCLK
PS005600-TVC1299
Preliminary
65
Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
Table 27
Bit
Register1, R1(1) Speed Control Register
15
14
13
12
11
10
9
8
R/W
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Reset
Bit
7
6
5
4
3
2
1
0
R/W
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Reset
Note: R = Read W = Write X = Indeterminate
Reg Field
Bit Position
R
W Data Description
Reserved (Return 0)
Reserved
f---------------
Mode selection
-e-------------- R
W
1
0
Standard interlace mode (single
scan)
Double scan -POR
H_SHIFT
1xHSYNC
--dcba98-------- R
W
--------7------- n/a W
---------6------ n/a W
----------5----- n/a W
1
0
1xHSYNC connected to Port03
1xHSYNC is 2xHSYNC/2-POR
Skip_HSYNC
Frame_start
OSD_black
1
0
Skip next HSYNC
Do not skip next HSYNC
1
0
Field start initializaiton
No effect
-----------4---
R
W
W
W
W
W
1
0
Next output line is OSD
Next output line is black
Line_buffer_mode ------------3--- R
1
0
Interlaced(OSD/black)
Progressive (OSD/OSD)-POR
2x_RGB
-------------2-- R
--------------1- R
---------------0 R
1
0
Double RGB output
Normal RGB output-POR
Fast_enable
Fast_slow
1
0
PVCO/SVCO enabled
PVCO/SVCO disabledÐPOR
1
0
SCLK is 12.058 MHz
SCLK is 32.768 KHzÐPOR
When a POR, SMR, or WDT reset occurs, both the Fast_enable and Fast/Slow are reset
to 0. This event corresponds to an SCLK frequency of 32.768 KHz.
To switch from a 32.768 KHz SCLK to 12 MHz, use the following procedure:
PS005600-TVC1299
Preliminary
66
Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
1.
2.
3.
Set the H_Position field R6(1)<3:0> to a nonzero value.
Enable the primary and secondary VCOs (set the Fast_enable bit R1(1)<1> to “1”).
Wait for one second (1s) for the 12 MHz PLL to stabilize (about 50000 clock
cycles). The delay depends on the external PLL filter and can vary significantly.
4.
5.
Switch the SCLK to a fast clock (set Fast/Slow bit R1(1)<0> to 1).
At the same time, set the H_Position field R6(1)<3:0> to 0FHand the No_Switch
field R6(1)<4> to 1(no clock switch).
To switch from the 12 MHz SCLK to 32.768 KHz, use the following procedure:
1.
2.
Switch the SCLK to a 32.768 KHz clock (set Fast/Slow bit R1(1)<0> to 0).
Wait for more than R2(0)<7:0> + 256 clock cycles (approximately 32 µS) for the
SCLK to be switched.
3.
4.
Set the HSYNC_DELAY field R6(1)<3:0> to 0FH.
Disable the primary and secondary VCOs (set the Fast_enable bit R1(1)<1> to 0).
Progressive Scan
To active Progressive Scan, set R1(1)<e> to “0”, this is the default (POR) condition.
Hardware must be initialized hardware by writing “1” into R1(1)<5> one time every
VSYNC.
Clock switching must be disabled by setting R6(1)<4> to “1”. Horizontal position in
R6(1)<3:0> must be set to “F”. The actual horizontal position adjustment is controlled by
R1(1)<c:7>.
If R1(1)<3> is set to “1” (Interlaced OSD/Black), the interleaving of OSD and Black can
be controlled by writing “1” or “0” into R1(1)<4>; this must be done once every VSYNC.
To come into sync with the original 1x HSYNC, implement a “skip next 2x HSYNC”
function by writing a “1” to R1(1)<6>. This action results in skipping the next HSYNC
pulse and is recommended at power-up and after changing channels.
If a 1xHSYNC is available externally, it can be fed in through the Port03 pin. R1(1)<7>
controls the source of 1xHSYNC. Port03 must be assigned as an input.
If R1(1) is set to “1”, RGB output current is doubled.
If the OSD disable bit R3(1)<5> is set to “0”, both the OSD and line buffers are shut down
to reduce EMI is there is no screen display.
The OSD in internal HSYNC and VSYNC is supported only in standard Interlaced mode.
PS005600-TVC1299
Preliminary
67
Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
Table 28
Bit
Register2, R2(1) WDT/STOP (write only) and
9-bit Counter (read only) Control Register
15
14
13
12
11
10
9
8
R/W
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
Reset
Bit
7
6
5
4
3
2
1
0
R/W
R/W
x
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Reset
Note: R = Read W = Write X = Indeterminate
Reg Field
Bit Position
R
W
Data Description
Counter_value fedcba987-------
R
R
R
Counter on Port06 value
No effect
W
W
Reserved
---------65432--
--------------1-
Return 0
No effect
WDT_instr
1
0
Return 0
WDT enable, WDT reset
No effect
W
W
STOP_instr
---------------0
R
Return 0
Stop
No effect
1
0
When a POR, SMR or a WDT reset occurs, the WDT is disabled. The WDT can be
reenabled only after the PVCO and SVCO are enabled, and the part is switched into a Fast
mode (SCLK = 12 MHz).
When switching the part into a SLOW mode (SCLK = 32.768 KHz), the WDT halts. To
return to Fast mode, the WDT must be initialized again.
PS005600-TVC1299
Preliminary
68
Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
Table 29
Bit
Register3, R3(1) Standard Control Register
15
14
13
12
11
10
9
8
R/W
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Reset
Bit
7
6
5
4
3
2
1
0
R/W
R/W
0
R/W
0
R/W
0
R/W
x
R/W
x
R/W
x
R/W
0
R/W
0
Reset
Note: R = Read W = Write X = Indeterminate
Reg Field
Bit Position
R W Data Description
Counter_ reset
f--------------- R
1
0
Return 0
Reset Counter on Port06
No effect
W
Counter_ON/OFF
Mask_HVSYNC
-e-------------- R W
--d------------- R W
---c------------ R W
1
0
Counter on Port06 is ON
Counter is OFFÐPOR condition
1
0
Disable HVSYNC output
HVSYNC IN/OUTÐPOR condition
Char_size_16_18/20
1
0
16x20 character matrix
16x16 or 16x18 character matrixÐ
POR
Bank0_sel
----ba---------- R W 00 RAM Bank 00ÐPOR
01 RAM Bank 01
10 RAM Bank 02
11 Reserved
RGBC/Port1
------9--------- R W
1
0
SCLK, R<1:0>, G<1:0>, B<1:0>
P16,P08,P10,P13,P18,P15,P14
2
I C_HI/LO_speed
-------8-------- R W
--------7------- R W
1
0
HI speed (400/50 KHz)
LO speed (100/10 KHz)ÐPOR
CGROM bank
1
0
Bank1 is selected (starts
@%1000)
Bank0 is selected (starts
@%0000)
SVBLANK/P0f
OSD_on/off
---------6------ R W
----------5----- R W
1
0
Semi-transparency
P0f output
OSD is enabled
OSD is disabledÐPOR
1
0
PS005600-TVC1299
Preliminary
69
Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
Reg Field
Bit Position
R W Data Description
RGB_polarity
-----------4----
R
R
R
R
W
W
W
W
1
0
Negative
Positive
Positive/Negative
SYNC/BLANK
------------3---
-------------2--
--------------10
1
0
Negative HVSYNC in output mode
Positive HVSYNC in output mode
1
0
HVBLANK outputs
HVSYNC outputs
25/30_Hz and
HV_polarity
Internal mode only (TV Standard)
10 50 Hz/625 lines support
00 60 Hz/525 lines supportÐPOR
External mode only (HV Polarity)
11 Positive
01 Negative
Two bits define the polarity of the HVSYNC signals. Bit <3> defines the polarity of the
signals when they are configured as outputs (it does not affect internal HV–SYNC
signals). Bit <1> defines the polarity of the external HV–SYNC signals which affect the
device synchronization.
Notes:
1.
2.
The composite SYNC is active in internal mode only.
When using the internally-generated COMPOSITE SYNC signal, be sure the SCLK
is set to 12.09 MHz (R2(0)<7:0> = %71). This action helps ensure the best HSYNC
frequency approximation.
Table 30
Bit
Register 4, R4(1) ADC Control Register
15
14
13
12
11
10
9
8
R/W
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Reset
Bit
7
6
5
4
3
2
1
0
R/W
R/W
0
R/W
0
R/W
0
R/W
0
R/W
x
R/W
x
R/W
x
R/W
x
Reset
Note: R = Read W = Write X = Indeterminate
PS005600-TVC1299
Preliminary
70
Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
Reg Field
Bit Position
R W Data Description
Reserved
f--------------- R
0
Reserved
No Effect
W
W
HW_shift
-ed------------- R
00 Direct (unmodiÞed)ÐPOR
01 4-bit shift left
10 4-bit shift right
11 Byte swap
HSYNC_edge* ---c------------ R W
1
0
HSYNC is leading edge active
HSYNC is trailing edge activeÐPOR
ADC_ref
----b----------- R W
1
0
ADCs use AV and AGND as
reference voltage
ADCs use 2.0V and 1.5V as
reference voltageÐPOR
CC
ADC_select
-----a---------- R W
1
0
ADC4, ADC5 select
ADC0, ADC1, ADC2, ADC3 selectÐ
POR condition
ADCdata-
Packing
------9--------- R
ADC data packing is on
ADC data packing is offÑPOR
W
Reserved
-------8-------- R
Return Ò0Ó
No effect
W
ADCspeed
--------76------ R W 00 Single conversionÐPOR condition
01 SCLK/4
10 SCLK/6
11 SCLK/8
ADCsource
ADCdata
----------54---- R W 00 ADC0 (CVI)/ADC4 (P04)ÐPOR
01 ADC1 (P17)/ADC5
10 ADC2 (P00)
11 ADC3 (P05)
------------3210 R
%D ADC data
No effect
W
Note: *If HSYNC is Leading Edge Active (R4(1)<c> = 1),the actual interrupt is delayed
from the leading edge of HSYNC by 72 cycles (~6µS @12 MHz).
ADC0 has a signal range from 1.5 to 2.0 V. This field is always connected to the
Composite Video Input pin and can be clamped to a Ref– voltage (1.5V).
ADC1, ADC2, ADC3, and ADC4 have a signal range from 0 to 5.0 V.
ADC5 features a signal range from 1.5 to 2.0 V. For this field, the input signal can be
clamped to a Ref+ voltage (2.0V).
PS005600-TVC1299
Preliminary
71
Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
To use the I/O pin as an ADC input, the corresponding port must be set up as an input
(refer to R4(0) and R6(0)).
Table 31
Bit
Register5, R5(1)Timer Control Register
15
14
13
12
11
10
9
8
R/W
R/W
x
R/W
x
R/W
x
R/W
x
R/W
0
R/W
0
R/W
x
R/W
x
Reset
Bit
7
6
5
4
3
2
1
0
R/W
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
Reset
Note: R = Read W = Write X = Indeterminate
Reg Field
Bit Position
R
W
Data Description
CAPint_r
f---------------
R
1
0
1
0
Rising edge is captured
No rising edge is captured
Reset ßag
W
No effect
CAPint_f
Tout_1s
-e--------------
--d-------------
---c------------
R
R
R
1
0
1
0
Falling edge is captured
No falling edge is captured
Reset ßag
W
W
W
No effect
1
0
1
0
Timeout of 1s timer
No timeout of 1s timer
Reset ßag
No effect
Tout_CAP
1
0
1
0
Timeout of Capture timer
No timeout of Capture timer
Reset ßag
No effect
Reserved
Speed_1s
----ba----------
------98--------
R
R
Return Ò0Ó
No effect
W
W
00
01
10
11
1s
250 ms
62.5 ms
15.625 ms
Port09/
CAP_int*
--------7-------
R
W
1
0
int2 source is Port09
int2 source is Capture timer
PS005600-TVC1299
Preliminary
72
Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
Reg Field
Bit Position
R
W
Data Description
CAP_halt* ---------6------
R
W
1
0
Capture timer is halted
Capture timer is running
CAP_edge* ----------54----
R
R
R
W
W
W
00
01
10
11
No Capture
Capture on rising edge only
Capture on falling edge only
Capture on both edges
CAP_glitch* ------------32--
00
01
10
11
Glitch Þlter is disabled
<8TSCLK is Þltered out
<32TSCLK is Þltered out
<128TSCLK is Þltered out
CAP_speed --------------10
*
00
01
10
11
SCLK/4
SCLK/8
SCLK/16
SCLK/32
*Resetting a Capture Timer flag does not modify Capture Counter or Capture register data. When the
glitch filter is enabled, the duration of the pulse is decreased by the CAP_glitch value.
Table 32
Bit
Register6, R6(1) Clock Switch Control Register
15
14
13
12
11
10
9
8
R/W
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Reset
Bit
7
6
5
4
3
2
1
0
R/W
R/W
0
R/W
0
R/W
0
R/W
1
R/W
x
R/W
x
R/W
x
R/W
x
Reset
Note: R = Read W = Write X = Indeterminate
Reg Field
Bit Position
R
W
Data Description
Reserved
fedcba9876------
R
Return 0
No effect
W
SVCO/PVCO ----------5-----
R
1
0
1
0
SCLK = SVCO (ßag)
SCLK = PVCO (ßag) POR
Switch SCLK to PVCO
No effect
W
PS005600-TVC1299
Preliminary
73
Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
Reg Field
Bit Position
R
W
Data Description
No_Switch
-----------4----
R
W
1
0
SCLK = PVCO, no clock
switchingÑPOR
Clock switching is enabled
H_Position
------------3210
R
W
%D DeÞnes delay of H
interrupt
SYNC
by 4X SCLK cycles
H_Position
The H_position field must be set to “F”. The actual horizontal position adjustment is
controlled by R1(1)<c:7>.
No_Switch
The No_switch bit determines if the system clock is permanently set to the Primary VCO
(PVCO) or allowed to switch between PVCO and the Secondary VCO (SVCO). This bit is
set to 1 (NO clock switching) at power up reset.
Caution: After the system has been switched to fast (12 MHz) clock both signals feeding
into this switch MUST be PVCO BEFORE the switch setting is changed. Otherwise a
short system clock can result which causes the processor to run at a higher frequency than
specified. The instruction fetched from memory, at the location with the out-of-spec
frequency, can be corrupted!
To ensure safe clocks, the following practices are recommended:
1.
Set the No_switch to the required setting before switching from the 32.768 KHz to
the fast (12 MHz) clock and leave it there permanently.
2.
Use the following procedure when changing from Switching VCO to permanent
PVCO while running from the fast clock:
-
Simultaneously set the H_position delay to 0x0, while leaving the No_switch
enabled (0), and the SVCO/PVCO left as (0).
-
-
Wait a minimum of 80 clock cycles to flush any H-sync out of the system.
Simultaneously Switch SVCO/PVCO to PVCO (write 1 into R6(1)<5>),
while leaving the No_switch enabled (0), and the H_position delay at 0x0.
-
-
Wait for 3 system clock cycles to be sure that the clock has had time to switch
to PVCO.
Switch No_switch to No clock switch (write 1 into R6(1)<6>). The
H_position can be set to none-zero at this time as well.
PS005600-TVC1299
Preliminary
74
Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
3.
Use the following procedure when changing from permanent PVCO to Switching
VCO while running from the fast clock.
-
Simultaneously set the H_position delay to 0x0, while leaving the No_switch
disabled (1), and the SVCO/PVCO setting as don’t care (0).
-
-
Wait a minimum of 80 clock cycles to flush residual H-sync out of the system.
Simultaneously switch SVCO/PVCO to PVCO (write 1 into R6(1)<5>),
while leaving the No_switch disabled (1), and the H_position delay at 0x0.
-
-
Wait 3 system clock cycles to be sure that the clock has had time to switch to
PVCO.
Switch No_switch to Clock switching is Enabled (write 0 into R6(1)<6>).
The H_position can be set to none-zero at this time as well.
SVCO/PVCO
The SVCO/PVCO bit when read back determines the current setting of the system clock.
Writing a 1to this bit switches the system clock from its current setting to PVCO. This
switch has a glitch filter that removes random voltage spikes. It must be changed back to
PVCO. The Z90376 switches to the SVCO automatically when it receives an H-sync
interrupt. This mechanism exists to synchronize the system clock exactly with the H-sync
trailing edge. The result is a sharp start of the OSD, jitter free.
An example of a typical SVCO/PVCO switching follows:
1.
2.
System clock is set to PVCO.
H-sync interrupt occurs. (The system clock has automatically been set to the
SVCO). OSD code is executed inside of the H-sync Interrupt Service Routine (ISR).
3.
Before leaving the ISR, the user switches the clock back to PVCO.
The clamp pulse (defined in R0(1)) is generated only if the SVCO/PVCO switch is set to
PVCO before receiving an H . The software provides the correct switch setting before
SYNC
every H
.
SYNC
Table 33 lists the interrupt/WDT for the WST/SMR control register.
PS005600-TVC1299
Preliminary
75
Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
Table 33
Bit
Register7, R7(1) Interrupts/WDT/SMR Control Register
15
14
13
12
11
10
9
8
R/W
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
Reset
Bit
7
6
5
4
3
2
1
0
R/W
R/W
0
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
Reset
Note: R = Read W = Write X = Indeterminate
Reg Field
Int_priority fed-------------
Int_mask ---cba----------
Bit Position
R
W
Data Description
See Table 34.
R
R
W
W
x
1xx int2 is enabled
0xx int2 is disabled
x1x int1 is enabled
x0x int1 is disabled
xx1 int0 is enabled
xx0 int0 is disabled
WDTspeed ------98--------
R
R
W
00 1.83 ms
01 7.68 ms
10 31.12 ms
11 124.8 ms
SMRßag
--------7-------
---------6------
0
1
No Stop-Mode RecoveryÐPOR
Stop-Mode Recovery
No effect
W
W
SMR
R
R
0
1
OR of all SMR sources
NAND of all SMR sources
polarity
SMRsource ----------543210
W
xx Bit which corresponds to a Ò1Ó in xx
binary representation is active
smr5
smr4
smr3
smr2
smr1
smr0
----------5-----
-----------4----
------------3---
-------------2--
--------------1-
---------------0
p09
p14
p13
p12
p11
p10
The final result of the Stop-Mode Recovery (SMR) is RESET. Ports selected for SMR
must be assigned as inputs, while the other SMR ports must be assigned as outputs
exhibiting an inactive value. If any SMR source is active, and the Stop Mode is executed,
the part resets immediately.
PS005600-TVC1299
Preliminary
76
Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
All core interrupts are set to int0 > int1 > int2. These priorities cannot be changed and are
embedded into the core. However, Z90376 architecture provides flexibility to change the
priority of the interrupts by switching the interrupt sources between interrupt inputs of the
Z90376 core. The correspondence between H
, V
and 1s/CAP interrupts
SYNC SYNC
sources, and int0, int1, and int2 interrupts inputs of the Z90376 are listed in Table 34.
Table 34
Interrupt Priority
Int_Priority
Field
HSYNC Is
VSYNC Is
1s/CAP Is
Int_Priority
Switched To: Switched To: Switched To: Field
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
int0
int0
int1
int2
int1
int2
int1
int2
int0
int0
int2
int1
int2
int1
int2
int1
int0
int0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
3.4
Bank2 (PWM Registers)
Table 35 lists the bits for the PWM registers.
Table 35
Bit
Register0ÐRegister5, R0(2)ÐR5(2) PWM 1Ð6 Registers
15
14
13
12
11
10
9
8
R/W
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Reset
Bit
7
6
5
4
3
2
1
0
R/W
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
Reset
Note: R = Read W = Write X = Indeterminate
Reg Field
Bit Position
R
W
Data Description
Reserved
fedcba98--------
R
Return 0
No effect
W
PS005600-TVC1299
Preliminary
77
Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
Reg Field
Bit Position
R
W
Data Description
xx 8-bit PWM data
PWM_data --------76543210
R
W
All of the PWMs feature push-pull. Outputs from all PWMs are staged by one PVCO
clock. The repetition frequency of the PWM output signals can be calculated from the
following equation:
F
12MHz
2048
PVCO
F
= ---------- = ---------- = 6kHz
PWM
8– 256
When reset, PWM_data registers are not initialized; however, PWM output is set to 0.
Because the PWM is clocked with PVCO, it is better to initialize the PWM_data before
enabling PVCO.
Table 36 lists the bits for the shadow control register.
Table 37 lists the bits for the CGROM offset register.
Table 36
Bit
Register6, R6(2) Shadow Control Register
15
14
13
12
11
10
9
8
R/W
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Reset
Bit
7
6
5
4
3
2
1
0
R/W
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
Reset
Note: R = Read W = Write X = Indeterminate
Reg Field
Bit Position
R
W
Data Description
Reserved
fe--------------
R
Return 0
No effect
W
W
W
Lshadow-Color --dcb-----------
Rshadow-Color -----a98--------
R
R
xx
xx
Left shadow color-POR = 0
Right shadow color-POR =
0
Reserved
--------76543210
R
Return 0
No effect
W
PS005600-TVC1299
Preliminary
78
Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
Table 37
Bit
Register7, R7(2) CGROM Offset Register
15
14
13
12
11
10
9
8
R/W
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Reset
Bit
7
6
5
4
3
2
1
0
R/W
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Reset
Note: R = Read W = Write X = Indeterminate
Reg Field
Bit Position
R
W
Data Description
xxxx CGROM offset, POR=0
CGoffset
fedcba9876543210
R
W
3.5
Bank3 (On Screen Display [OSD] registers)
Table 38 lists the R0(3)- R2(3) character multiplier registers (Read operation).
Table 39 lists the R0(3)–R1(3) Shift Registers (Write operation).
Table 40 lists the R2(3) Attributes Register (Write operation).
PS005600-TVC1299
Preliminary
79
Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
Table 38
Bit
Register0ÐRegister2 Read Operation
R0(3)ÐR2(3) Character Multiple Registers
15
14
13
12
11
10
9
8
R/W
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
Reset
Bit
7
6
5
4
3
2
1
0
R/W
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
Reset
Note: R = Read W = Write X = Indeterminate
Reg Name
CGROM Data
Reg Add
Description
R0(3)
High word of double size character
R4(3)<6> = 0
cgrom_x2_hi
ffeeddccbbaa9988
High word of triple size character
R4(3)<6> = 1
cgrom_x3_hi
cgrom_x2_lo
fffeeedddcccbbba
7766554433221100
R1(3)
R2(3)
Low word of double size character
R4(3)<6> = 0
Middle word of triple size character
R4(3)<6> = 1
cgrom_x3_mid aa99988877766655
Single size character R4(3)<6> = 0
cgrom_x1
fedcba9876543210
5444333222111000
Low word of triple size character
R4(3)<6> = 1
cgrom_x3_lo
Table 39
Register0ÐRegister1 Write Operation
R0(3)ÐR1(3) Shift Registers
Bit
15
14
13
12
11
10
9
8
R/W
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
Reset
Bit
7
6
5
4
3
2
1
0
R/W
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
Reset
Note: R = Read W = Write X = Indeterminate
PS005600-TVC1299
Preliminary
80
Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
Reg Name
CGROM Data
Reg Address Description
current_reg
R0(3)
R1(3)
current line shift register
fedcba9876543210
fedcba9876543210
next/previous_reg
next/previous line shift register
Registers R1(3) and R0(3) must be loaded with video data one time every 16 cycles. To
support smoothing, register R1(3) must be updated every 16 cycles. The current line
register is loaded first, followed by next/previous register during the next cycle. The next/
previous register is loaded only if smoothing/fringing attributes are activated for the
current character. If neither register is loaded, the space character is displayed. There is no
difference between loading 0000hinto either register or not loading at all.
Table 40
Bit
Register2 Ñ R2(3) Attributes Register, Write Operation
15
14
13
12
11
10
9
8
R/W
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
Reset
Bit
7
6
5
4
3
2
1
0
R/W
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
Reset
Note: R = Read W = Write X = Indeterminate
Reg Field
Bit Position
Data Description
No effect
Reserved
f---------------
-edc------------
x
Background color
000 Black
001 Blue
010 Green
011 Cyan
100 Red
101 Magenta
110 Yellow
111 White
Foreground color NOT ----ba9---------
%D Same as Background mode
Palette Mode
Palette selection
Palette Mode
----ba----------
00
01
10
11
Palette0
Palette1
Palette2
Palette3
PS005600-TVC1299
Preliminary
81
Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
Reg Field
Bit Position
Data Description
2nd_underline
Palette Mode
------9---------
-------8--------
--------7-------
1
0
Second Underline is active
Second Underline is NOT active
1st_underline
1
0
First Underline is active
First Underline is NOT active
Shift_video
1
0
Video signal is delayed by 8
pixels
Standard character positioning
Semi-Transparent
---------6------
1
0
Semi-Transparent background
Background color deÞned by
Òbackground colorÓ Þeld
Blinking
Italic
----------5-----
-----------4----
------------32--
1
0
Blinking character
Not blinking character
1
0
Italic character
Not italic character
Color_delay
00
01
10
11
Character color changes
instantly
Color changes with 4 pixels
delay
Color changes with 8 pixels
delay
Color changes with 12 pixels
delay
Shadowing/Fringing
--------------10
00
01
10
11
No shadowing (no fringing)
Left shadow
Right shadow
Both shadows (fringing)
Note: *If both the background and foreground colors of a character are set to be the same,
the character’s background is displayed as transparent.
The attributes register must be loaded 8 cycles after the current line register R0(3) is
loaded. Loading the attributes register enables the OSD logic during the next 16 cycles. If
the attributes register is not loaded, there is no active OSD, even if the current line register
R0(3) is loaded. See Table 41.
PS005600-TVC1299
Preliminary
82
Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
Table 41
Bit
Register3 Read Operation
R3(3) Attributes Register
15
14
13
12
11
10
9
8
R/W
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
Reset
Bit
7
6
5
4
3
2
1
0
R/W
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
Reset
Note: R = Read W = Write X = Indeterminate
Reg Field
Same as R2(3)
Bit Position
Data
Description
The data read from the attribute register is a combination of attribute fields from the most
recently displayed character and control character codes loaded into the attribute_data
register. Character codes are fetched from Video RAM and must be loaded into the
attribute_data register R3(3). Bit <f> of the attribute_data register (during a read) indicates
whether the most recent character was a control or displayed character. The data read from
the attribute_data register must be directly loaded into attribute register R2(3). Refer to
Table 42.
Table 42
Register3, R3(3) Write Operation
Attribute Data Register
Bit
15
14
13
12
11
10
9
8
R/W
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
Reset
Bit
7
6
5
4
3
2
1
0
R/W
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
Reset
Note: R = Read W = Write X = Indeterminate
Reg Field
Bit Position
Data Description
xxxx Character code fetched from VRAM
VRAM_data
fedcba9876543210
PS005600-TVC1299
Preliminary
83
Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
Loading VRAM data into an attribute_data register initializes a CGROM access cycle.
Four clock cycles after the LD instruction, the Z90376 halts for three clock cycles to fetch
the data from CGROM and latch it into a CGROM data capture register. After the
CGROM data is latched, core operations are resumed. When a control character code is
loaded into the attribute_data register, the CGROM data from address 0000hex is
fetched. Therefore, ZiLOG recommends placing a space character at location 0000hex in
CGROM. Refer to Table 43 through Table 46 for the various VRAM data formats loaded
in R3(3).
Table 43
Display Character Format for Attribute Data Register R3(3)
OSD Mode Write Operation
Bit
15
14
13
12
11
10
9
8
R/W
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
Reset
Bit
7
6
5
4
3
2
1
0
R/W
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
Reset
Note: R = Read W = Write X = Indeterminate
Reg Field
Bit Position
Data Description
Display character
Control bit
f---------------
0
Background color* -edc------------ 000 Black
001 Blue
010 Green
011 Cyan
100 Red
101 Magenta
110 Yellow
111 White
Foreground color ------ba9------- %D Same as Background_color
(Not Palette mode)
Foreground palette --------ba------
00 Palette 0 (deÞned in R6(3)<8Ð6>
(Palette mode)
01 Palette 1 (deÞned in R6(3)<bÐ9>
10 Palette 2 (deÞned in R6(3)<5Ð3>
11 Palette 3 (deÞned in R6(3)<2Ð0>
Second underline -------9---------
(Palette mode)
1
0
Second underline attribute is active
Second underline attribute is inactive
PS005600-TVC1299
Preliminary
84
Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
Reg Field
Bit Position
Data Description
Attribute8
-------8--------
1
0
Selected attribute (R7(3),<76>) is
active
Selected attribute (R7(3),<76>) is
inactive
Character code
--------76543210 %DD DeÞnes the character in CGROM
Note: *If both the background and foreground colors of a character are set to be the same, the
character’s background is displayed as transparent.
Table 44
Control Character Format, OSD Mode Write Operation
Attribute Data Register R3(3)
Bit
15
14
13
12
11
10
9
8
R/W
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
Reset
Bit
7
6
5
4
3
2
1
0
R/W
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
1
Reset
Note: R = Read W = Write X = Indeterminate
Reg Field
Bit Position
Data Description
Control bit
Reserved
Shift_video
f---------------
-edcba98--------
--------7-------
1
x
Control character
ReservedÑdoes not affect OSD
1
0
Video signal is delayed by 8 pixels
Standard character positioning
Transparent ---------6------
1
0
Transparent background
Background color deÞned by Òbackground
colorÓ Þeld
Blinking
Italic
----------5-----
-----------4----
1
0
Blinking character
Not blinking character
1
0
Italic character
Not italic character
Color_delay ------------32--
00 Character color changes instantly
01 Color changes with 4 pixels delay
10 Color changes with 8 pixels delay
11 Color changes with 12 pixels delay
PS005600-TVC1299
Preliminary
85
Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
Reg Field
Bit Position
Data Description
Shadowing/ --------------10
Fringing
00 No shadowing (no fringing)
01 Left shadow
10 Right shadow
11 Both shadows (fringing)
Smoothing is supported for double size (x2) and triple size (x3) characters only.
At reset, the background color in OSD mode is black. Foreground color, background
color, blinking and italic attributes are delayed by 3/4 character. The smoothing attribute is
enabled.
Table 45
Bit
Display Character Format, Attribute Data Register R3(3)
Write Operation CCD Mode
15
14
13
12
11
10
9
8
R/W
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
Reset
Bit
7
6
5
4
3
2
1
0
R/W
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
Reset
Note: R = Read W = Write X = Indeterminate
Reg Field
Bit Position
Data Description
Display character
%DD DeÞnes the character in CGROM.
Control bit
7-------
-6543210
0
Character code
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64 KWord Television Controller with OSD
Table 46
Bit
Control Character Format, Attribute Data Register R3(3)
CCD Mode, Write Operation
15
14
13
12
11
10
9
8
R/W
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
Reset
Bit
7
6
5
4
3
2
1
0
R/W
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
Reset
Note: R = Read W = Write X = Indeterminate
Reg Field
Bit Position Data Description
Control bit
7-------
-6------
1
Control character
Transparent background
Background color deÞned by Òbackground
colorÓ Þeld
Transparent
1
0
Blinking
Italic
--5-----
---4----
1
0
Blinking character
Not blinking character
1
0
Italic character
Not italic character
Foreground color ----321-
000 Black
001 Blue
010 Green
011
Cyan
100 Red
101 Magenta
110
111
Yellow
White
First underline
-------0
1
0
Underline attribute is active
Underline attribute is inactive
In CCD mode, each character occupies 8 bits (one byte) in VRAM. The CCD characters
must be mapped into a 16-bit VRAM data field. The hardware supports compressed
character placement in VRAM. Each word in VRAM is represented by HIGH byte and
LOW byte. A currently active byte is selected by R4(3)<c>. The format and data
representation for both bytes is the same.
There are two possible character formats defined: a “display” character and a “control”
character. The code stored in “display” character format defines a character code. The
PS005600-TVC1299
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64 KWord Television Controller with OSD
“control” character defines up to seven attributes of the next character and is presented on
screen as a space character.
Combining display and control characters generates of a CCD OSD according to FCC
specification. Refer to Table 47.
Table 47
Bit
Register4ÑR4(3) OSD Control Register
15
14
13
12
11
10
9
8
R/W
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
Reset
Bit
7
6
5
4
3
2
1
0
R/W
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
Reset
Note: R = Read W = Write X = Indeterminate
Reg Field
Bit Position
R
W Data Description
Underline
fe--------------
R
W
1x Second underline is active
0x Second underline is inactive
x1 First underline is active
x0 First underline is inactive
OSD/CCD
--d-------------
R
R
W
W
1
0
OSD mode
CCD mode
CCD_top/btm ---c------------
1
0
The upper byte in VRAM is used
The lower byte in VRAM is used
Italic_shift
----ba98--------
--------7-------
R
R
W
W
x
DeÞnes delay of the character
Blink_off/on
0
1
Blinking character is displayed
Blinking character is NOT
displayed (hidden)
MPX_bus
----------65----
-----------43210
R
R
W
W
00 x1 character size
01 x2 character size
10 x3 character size
11 Reserved
CGROM
%D DeÞnes CGROM addressing
scan_line
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64 KWord Television Controller with OSD
The Underline field must be set by firmware when scan lines that contain underline
information are displayed. The underline bits are ANDed with the second and first
underline active fields of data loaded into attribute register R2(3), causing the screen
character to be underlined.
The Italic shift field defines a delay of video data. It is used to generate italic characters.
The firmware decrements by 1(the value of the Italic_shift field) for each consecutive
line. The video signal is delayed only for characters that have the R2(3)<4> (“italic”) bit
set to 1.
Table 48 lists the bits for the capture register.
Table 48
Bit
Register5, R5(3) Capture Register, Read Operation
15
14
13
12
11
10
9
8
R/W
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
Reset
Bit
7
6
5
4
3
2
1
0
R/W
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
R/W
x
Reset
Note: R = Read W = Write X = Indeterminate
Reg Field Bit Position
R
W
Data Description
Cap_data fedcba9876543210
Reserved fedcba98-------0
R
R
%xxxx 16-bit captured data
Return 0
No effect
W
W
2
I2C_saddr --------7654321-
%DD I C Slave interface address
In Read mode, R5(3) returns the 16-bit captured data from the IRIN pin.
2
In Write mode, the 7-bit I C slave interface address must be put in bit 7-1.
Table 49 lists the bits for the palette control register.
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64 KWord Television Controller with OSD
Table 49
Bit
Register6, R6(3) Palette Control Register
15
14
13
12
11
10
9
8
R/W
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Reset
Bit
7
6
5
4
3
2
1
0
R/W
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Reset
Note: R = Read W = Write X = Indeterminate
Reg Field Bit Position
R
W
Data Description
Palette
f---------------
R
W
1
0
Palette mode is active
Palette mode is INACTIVE
Underline -edc------------
color
R
W
000
001
010
011
100
101
110
111
Black
Blue
Green
Cyan
Red
Magenta
Yellow
White
Palette1
Palette0
Palette3
Palette2
----ba9---------
-------876------
----------543---
-------------210
R
R
R
R
W
W
W
W
%D
%D
%D
%D
Same as Underline color
Same as Underline color
Same as Underline color
Same as Underline color
At POR the palette control register is reset to 0.
Table 50 lists the bits for the output palette control register.
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64 KWord Television Controller with OSD
Table 50
Bit
Register7, R7(3) Output Palette Control Register
15
14
13
12
11
10
9
8
R/W
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Reset
Bit
7
6
5
4
3
2
1
0
R/W
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
Reset
Note: R = Read W = Write X = Indeterminate
Reg Field
Bit Position
R W Data Description
BLANK_delay
fedc------------ R W
VBlank and SVBLANK delay
valueÑ%00ÐPOR condition
Background_on/off ----b----------- R W
1
0
Master background is on
Master background is offÐPOR
condition
Background_color -----a98-------- R W %D DeÞnes the color of the Master
background (same as the
palette)
AttrSelect
--------76------ R W 00 1st underlineÑPOR
01 Semi-transparency
10 Blinking
11 CGROM bank select
Smoothing
----------5----- R W
0
1
Smoothing logic disabledÑPOR
Smoothing logic enabled
Cursor Write
Enable
-----------4---- R
Return Ò0Ó
Cursor parameters write
disabledÑPOR
W
0
1
Cursor parameters write enabled
Palette #
------------3210 R W %D Palette number
At POR the Output palette register is set to 0for digital output.
Table 15 is the look-up table for the color palettes.
PS005600-TVC1299
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Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
4
INSTRUCTION SET
The processor instruction set consists of 30 basic instructions. It has been optimized for
high code density and reduced execution time. Single-cycle instruction execution is
possible on most instructions.
The format for Op Codes and addressing modes is provided in the following tables but is
normally not required. The assembler removes the burden of hand constructing the
instruction format. by translating the mnemonics. System designers can access the
instruction format when debugging.
4.1
Instruction Summary
The DSP instruction set can be broken down into the following types of instructions:
•
•
•
•
•
•
•
Accumulator Modification
Arithmetic
Bit Manipulation
Load
Logical
Program Control
Rotate and Shift
Instruction format mnemonics are in Table 51. Table 52 through Table 58 list other
instructions.
Table 51
Instruction Format Mnemonics
Mnemonic
Description
A
Address
am
Accumulator ModiÞcation
b
RAM Bank
Condition Code
Constant Expression
Destination Address
Destination Value
Flag ModiÞcation
Op Code
cc
const exp
d
dest
fm
op
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Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
Table 51
Instruction Format Mnemonics (Continued)
Mnemonic
Description
rp
s
Register Pointer
Source Address
Source Value
src
Table 52
Accumulator ModiÞcation Instructions
Mnemonic
Operands
Instruction
ABS
CP
<cc>, A
A, <src>
<cc>, A
<cc>, A
<cc>, A
Absolute Value
Comparison
Decrement
Increment
DEC
INC
NEG
Negate
Table 53
Arithmetic Instructions
Operands
Mnemonic
Instruction
ADD
CP
<cc>, A
A, <src>
A, <src>
Add
Compare
Subtract
SUB
Table 54
Bit Manipulation Instructions
Mnemonic
Operands
Instruction
CCF
None
None
None
None
None
None
Clear Carry Flag
CIEF
COPF
SCF
Clear Interrupt Enable Flag
Clear Overßow Protection Flag
Set Carry Flag
SIEF
SOPF
Set Interrupt Enable Flag
Set Overßow Protection Flag
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Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
Table 55
Load Instructions
Operands
Mnemonic
Instruction
LD
<dest>, <src>
<dest>
Load
Pop
POP
PUSH
<src>
Push
Table 56
Logical Instructions
Operands
Mnemonic
Instruction
AND
OR
A, <src>
A, <src>
A, <src>
Logical AND
Logical OR
XOR
Logical Exclusive OR
Table 57
Program Control Instructions
Mnemonic
Operands
Instruction
CALL
JP
A
Call Procedure
Jump
A
RET
None
Return
Table 58
Rotate and Shift Instructions
Mnemonic
Operands
Instruction
RL
<cc>, A
<cc>, A
<cc>, A
<cc>, A
Rotate Left
RR
Rotate Right
SLL
SRA
Shift Left Logical
Shift Right Arithmetic
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Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
4.2
Instruction Operands
To access the operands for the DSP, use the Register Pointers, Data Pointers, Hardware
Registers, Direct Addressing, Immediate Data and Memory. There are nine distinct types
of instruction operands. Table 59 and Table 60 describe these instructions.
Table 59
Instruction Operand Summary
Symbolic Name
Syntax
Description
<pregs>
<dregs>
<hwregs>
Pn:b
Dn:b
Register Pointer
Data Pointer
X, Y, PC, SR,
EXTn, A, BUS
Hardware Registers
<accind>
<direct>
<limm>
@A
Accumulator Indirect
<const exp>
#<const exp>
#<const exp>
Direct Address Expression
Long (16-Bit) Immediate
Short (8-Bit) Immediate Value
Indirect Addressing of RAM
<simm>
<regind>
@Pn:b
@Pn:b+
@Pn:b+Loop
@Pn:b-Loop
<memind>
@Dn:b
@Dn:b
@@Pn:b
Indirect Addressing of ROM
@@Pn:b+
@@Pn:b+Loop
@@Pn:b-Loop
Table 60
Instruction Mnemonics/Operands
Instruction Mnemonic/Operand Representation
#
1
2
3
4
5
6
7
LD
P2:0, #%F2
X, @A
LD
<pregs>, <simm>
<hwreg>, <accind>
<hwreg>, <limm>
A, <memind>
A, <memind>
A, <direct>
LD
LD
LD
Y, #%3CF5
A, @@P2:0
A, @D2:0
D A, %F2
LD
SUB
OR
AD
SUB
OR
ADD
PUSH
PUSH D1:1
<dregs>
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Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
<pregs> The register pointer mode is used for loading the pointer with the appropriate
RAM address. This address references the RAM location that stores the requested data.
The pointer can also be used to store 8-bit data when used as a temporary register. The
pointers are connected to the lower 8 bits of the D-bus. Instruction 1loads Pointer 2,
RAM Bank0with the value F2H.
<regind> The register indirect mode is used for indirect access to RAM. As noted in
Instruction 2, the register indirect address method is used to get the operand to multiply it
with the accumulator.
<dregs> The data-pointer mode is used as an indirect addressing method similar to
@P2:0. The data pointers access the lower 16 bits of each RAM bank. Instruction 8 uses
indirect addressing to PUSHinformation onto the stack.
<memind> Pointer or data registers can be used to access program memory. Both are
commonly used to reference program memory. Instructions 5 and 6 display this addressing
method. Either pointer is automatically incremented to assist in transferring sequential
data.
<accind> Another method of indirect addressing is using the accumulator to store the
address. Instruction 3 describes how to use this method.
<direct> The absolute RAM address is used in the direct mode. A range between 0and
511 (000H to 1FFH)is allowed. The accumulator is used in conjunction with this
method as a source or destination operand. Instruction 7 displays the accumulator as the
destination.
<limm> This instruction indicates a long immediate load. A 16-bit word can be copied
directly from the operand into the specified register or memory. Instruction 4 uses this
method.
<simm> This instruction can only be used for immediate transfer of 8-bit data in the
operand to the specified RAM pointer.
4.3
Instruction Format
The instruction format that specifies to the processor the action to be taken consists of the
Op Code, destination, source, and other special bits. The assembler makes this operation
transparent by providing mnemonics. Occasionally, the instruction format and
development code can assist in debugging. Examples to clarify the various instruction
formats and explain how specific bit patterns are developed and evaluated are provided
below.
Most instructions require one 16-bit word containing the information necessary for the
processor to execute the instruction correctly. This process requires one clock cycle for
PS005600-TVC1299
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Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
execution. Immediate addressing, immediate operands, JUMPand CALLinstructions
require two 16-bit words (two clock cycles). Each instruction type has a unique Op Code
and format to differentiate various instructions. Different operations also have unique
formats.
The variables a, op, b, d, s, cc, am, fm, rpare used in the instruction
format to depict bits determined by the active instruction.
ADDITION and INC Formats
The Op Code and format for an instruction differ to allow the processor to differentiate
between the instructions. For example, the ASSITION instruction requires that two
operands be defined in the instruction.
ADD A, <regind>
15 14 13 12 11 10
9
1
8
1
7
0
6
0
5
0
4
0
3
2
1
0
1
0
0
0
0
0
S
S
S
S
Op Code
RAM
Bank
Condition Code
ModiÞcation Code
The INC(increment) instruction requires that a condition and modification code be
specified.
INC A
15 14 13 12 11 10
9
0
8
0
7
0
6
1
5
0
4
0
3
1
2
0
1
1
0
0
1
0
0
1
0
0
Op Code
Condition Code
ModiÞcation Code
INC and SLL Formats
The INCand SLLinstructions have the same Op Code with an accumulator modification
format. The most recent four bits, the modification code, determine the type of operation
the accumulator performs.
INC A
15 14 13 12 11 10
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
1
0
0
1
0
0
1
0
0
Op Code
Condition Code
ModiÞcation Code
SLL A
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Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
15 14 13 12 11 10
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
1
0
1
1
0
0
1
0
0
Op Code
Condition Code
ModiÞcation Code
4.4
Instruction Bit Codes
The values in a series of bits in a register form patterns called bit codes.Types of bit
codes include the following:
•
•
•
•
•
Condition Codes
Accumulator Modification Code
Flag Modification Codes
Source/Destination Field Designators
Register Pointer/Data Pointer
The following tables list the options available and their corresponding instructions.
Condition Codes
Table 61 lists the condition codes that are used in accumulator modification, CALL, and
JUMPinstructions.
Table 61
Condition Code Bits
Mnemonic
Code Value
Condition
Code Value
Condition
Code
Bit Code
F
False
00000
00001
00010
00011
00100
00101
00110
00111
01xxx
10000
Unused
NU0
NU1
NC
UI0 is set to 0
UI1 is set to 0
C is set to 0
Z is set to 0
OV is set to 0
N is set to 0
Not User Zero
Not User One
No Carry
NZ
Not Zero (Not Equal)
No Overßow
Plus (Not Negative)
Unused
NOV
PL
T
True
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Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
Table 61
Bit Code
Condition Code Bits (Continued)
Mnemonic
Code Value
Condition
Code Value
Condition
Code
Unused
10001
10010
10011
10100
10101
10110
10111
11xxx
U0
U1
C
UI0 is set to 1
UI1 is set to 1
C is set to 1
Z is set to 1
OV is set to 1
N is set to 1
User Zero
User One
Carry
Z
Zero (Equal)
Overßow
OV
MI
Minus (Negative)
Unused
Accumulator ModiÞcation Codes
Accumulator modification codes determine the type of modification made to the value in
the accumulator. See Table 62. Condition codes are also used with CALL,and JUMP
instructions.
Table 62
Accumulator ModiÞcation Bits
Bit Code
Mnemonic
RR
Operation
Rotate Right
Rotate Left
Shift Right
Shift Left
0000
0001
0010
0011
0100
0101
0110
0111
RL
SR
SL
INC
Increment
Decrement
Negate
DEC
NEG
ABS
Absolute
Flag ModiÞcation Codes
Flag modifications initialize or set/reset bits to accommodate interrupts, overflows, and
carrys. See Table 63.
PS005600-TVC1299
Preliminary
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Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
Table 63
Bit Code
Flag ModiÞcation Bits
Mnemonic
CCF
Operation
Flag
C
Value
Clear Carry
0
1
0
1
0
1
xx10
xx11
x1x0
x1x1
1xx0
1xx1
SCF
Set Carry
C
CIEF
Clear Interrupt Enable
Set Interrupt Enable
IE
SIEF
IE
COPF
SOPF
Clear Overßow Protection OP
Set Overßow Protection OP
Source/Destination Field Designators
Register pointers and data pointers provide convenient access to data. The pointers are a
source or destination field in instructions. Specific bit codes are listed in Table 64. The
register pointer offers optional incrementing or decrementing. This option is specified by
the following instruction:
LD A, @P2:1+
Table 64
Bit Code
Register Pointer/ Data Pointer Bits
Mnemonic
NOP
00xx
01xx
10xx
11xx
xx00
xx01
xx10
0011
0111
1011
1111
+1
-1/loop
+1/loop
P0:0 or P0:1
P1:0 or P1:1
P2:0 or P2:1
D0:0 or D0:1
D1:0 or D1:1
D2:0 or D2:1
D3:0 or D3:1
PS005600-TVC1299
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Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
Data pointers are automatically incremented when accessing program memory (for
example, LD A, @D0:0) and do not require an incrementing option. Code in xx11
format is designated for a data pointer when source or destination format is used.
Additional source or destination designators include the other hardware registers provided
by the processor. To determine if a data pointer, register pointer or a register is used as a
source or destination is discussed in the next section.
Table 65 lists the bit code for mnemonic resister names.
Table 65
Bit Code
Register Bits
Mnemonic
Bus
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
X
Y
A
SR
STACK
PC
Reserved
EXT0
EXTI
EXT2
EXT3
EXT4
EXT5
EXT6
EXT7
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Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
4.5
Instruction Format Examples
Refer to the following examples indicating how bit codes are used in an instruction format.
Instruction Format
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
op op op op op op op cc cc cc cc cc am am am am
Op Code
Condition Code
ACC ModiÞcation
Accumulator ModiÞcation Format
15 14 13 12 11 10
op op op op op op op cc cc cc cc cc am am am am
Op Code Condition Code ACC ModiÞcation
9
8
7
6
5
4
3
2
1
0
Notes:
1.
The Variables a, op, b, d, s, cc, am, fm, rpare used in the
instruction format to depict bits determined by the instruction.
2.
The General Instruction Format requires an Op Code, RAM bank bit, destination
and source addresses. For example, LD A, @P2:1+
Load Instruction Format
15 14 13 12 11 10
9
1
8
1
7
0
6
0
5
1
4
1
3
0
2
1
1
1
0
0
0
0
0
0
0
0
Op Code
RAM
Bank
Destination
Source
The Op Code (0000001) provides a unique signature for the LDcommand. The
processor uses this signature to determine the instruction format. The RAM bank bit is
high (equal to 1) because of the instruction definition b=1 (Pn:b). The destination bit
code is 0011which corresponds to the accumulator. The source 0110 corresponds to the
+1option and P2:0 or P2:1. The RAM bank bit indicates that the processor loaded the
accumulator with the operand designated by Pointer 2 Bank1 (P2:1).
Source and destination fields can be accessed from the register pointers, data pointers, or
registers. The Op Code specifies the type of source and destination. An Op Code of
0000101specifies that the source is an indirect address to program memory (@@P0.0
or @D0:0) and the destination is a register.
PS005600-TVC1299
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Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
Instruction Format Listing
Instruction formats and applicable instructions are listed in Table 66 through Table 72.
Notes:
1.
Several instructions provide various addressing modes to obtain operands; therefore,
the same instruction can have several different formats depending on the addressing
mode.
2.
The variables a, op, b, d, s, ce, am, fm, rpare used in the
instruction format to depict bits determined by the specific instruction used.
General Instruction Format
15 14 13 12 11 10
9
8
b
7
d
6
d
5
d
4
d
3
s
2
s
1
s
0
s
op op op op op op op
Op Code
RAM
Bank
Destination
Source
Table 66
General Instruction Format
Mnemonic
ADD
AND
CP
Operands
A, @P0:0
A, D11
A,X
Bit Code
Hex
8200
AB07
6001
0037
0015
0253
0065
2B07
F202
1000001 0 0000 0000
1100110 1 0000 0111
0110000 0 0000 0001
0000000 0 0011 0111
0000000 0 0001 0101
0000001 0 0101 0011
0000000 0 0110 0101
0010101 1 0000 0111
1111001 0 0000 0010
LD
A,P
POP
PUSH
RET
X
D0:0
SUB
A,@D1:1
A,P2:0
XOR
Accumulator ModiÞcation Format
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
op op op op op op op cc cc cc cc cc am am am am
Op Code Condition Code ACC ModiÞcation
PS005600-TVC1299
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103
Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
Table 67
Accumulator ModiÞcation Format
Hex
Mnemonic
ABS
DEC
INC
Operands
Z, A
Bit Code
Representation
9157
9005
9054
9006
9020
9071
9143
9132
1001000 10101 0111
1001000 00000 0101
1001000 00101 0100
1001000 00000 0110
1001000 00010 0000
1001000 00111 0001
1001000 10100 0011
1001000 10011 0010
A
NZ, A
A
NEG
RR
NU0, A
PL, A
C, A
RL
SLL
SRA
U1, A
Flag ModiÞcation Format
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
op op op op op op op cc cc cc cc cc fm fm fm fm
Op Code
Condition Code
Flag ModiÞcation
Table 68
Flag ModiÞcation Format
Bit Code
Mnemonic
Hex Representation
CCF
1001010 00000 0010
1001010 00000 0100
1001010 00000 1000
1001010 00000 0011
1001010 00000 0101
1001010 00000 1001
9402
9404
9408
9403
9405
9409
CIEF
COPF
SCF
SIEF
SOPF
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Preliminary
104
Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
Direct Internal Addressing Format
15 14 13 12 11 10
9
8
a
7
a
6
a
5
a
4
a
3
a
2
a
1
a
0
a
op op op op op op op
Op Code
9-Bit Internal Address
Table 69
Direct Internal Addressing Format
Hex
Mnemonic
Operands
Bit Code
Representation
ADD
AND
CP
A, %FF
A, 255
A, 255
1000011 011111111
1010011 011111111
0110011 011111111
0000111 000010010
86FF
A6FF
66FF
0E12
LD
Short Immediate Addressing Format
15 14 13 12 11 10
op op op op op rp
Op Code
9
8
7
a
6
a
5
a
4
a
3
a
2
a
1
a
0
a
rp
rp
Register
Pointer
8-Bit Immediate Address/Data
Table 70
Short Immediate Addressing Format
Hex
Mnemonic Operands
LD P1:1, #%FA
Bit Code
Representation
00011 101 11111010
1DFA
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Preliminary
105
Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
Long Immediate Addressing Format
15 14 13 12 11 10
9
8
b
7
d
6
d
5
d
4
d
3
s
2
s
1
s
0
s
op op op op op op op
Op Code
RAM
Bank
Destination
Source
15 14 13 12 11 10
9
a
8
a
7
a
6
a
5
a
4
a
3
a
2
a
1
a
0
a
a
a
a
a
a
a
16-Bit Address/Data
Table 71
Long Immediate Addressing Format
Mnemonic
Operands
Hex Representation
ADD
AND
LD
A, #%1234
A, #% 26A4
X, #%6FFC
#%C32C
8800 1234
A800 26A4
0810 6FFC
0850 C32C
2800 2444
E800 AFC2
PUSH
SUB
XOR
A, #%2444
A,#%AFC2
JUMP, CALL Format
15 14 13 12 11 10
9
0
8
7
6
5
4
3
2
1
s
0
s
1
0
0
0
1
1
cc cc cc cc cc
Condition Code
s
s
Op Code
Not Used
15 14 13 12 11 10
9
a
8
a
7
a
6
a
5
a
4
a
3
a
2
a
1
a
0
a
a
a
a
a
a
a
16-Bit Address
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Preliminary
106
Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
Table 72
Jump, Call Format
Operands
Mnemonic
Hex Representation
CALL
JP
END
4800 0004
4D30 0004
U1, END
4.6
Instruction Timing
The DSP can be executed with single cycle instructions using independent data memory
and program memory buses in the system architecture and pipeline instructions. This
method allows the instruction fetch and execution cycles to overlap. Figure 28 illustrates
the execution sequence. The first instruction takes two clock cycles to execute; subsequent
executions occur in a single cycle. All instruction fetch cycles have the same machine
timing regardless of whether external or internal memory is used. Because the DSP
contains a two-level pipeline, the JUMPand CALL instructions do not disrupt the
execution process
In two-byte instructions, the second byte is fetched while the first byte is executing.
Because the processor knows that the instruction is a JUMPor CALL, the second byte is
transferred to the program counter and the correct address is fetched into the pipeline.
There is no disruption or pipeline flushing. The pipeline flow is affected when the program
counter is the destination for a load. Because the load (LD) instruction is a single word
instruction, the next instruction is fetched during load execution. To compensate for the
instruction in the pipeline, that instruction is executed as a NOP.
Fetch 1
Execute 1
Fetch 2
Execute 2
Figure 28 Pipeline Execution
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107
Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
4.7
Instruction Op Codes
Table 73 summarizes essential information about the instruction set.
Table 73
Description
Instruction Op Codes
Op Code Synopsis
Inst
Operands
<cc>,A
Words Cycles Examples
ABS
Absolute Value
ABS[<cc>,] <src>
1
1
1
1
2
1
1
1
1
1
2
3
ABS NC, A
ABS A
1001000
1001000
1001001
1000001
1000100
1000101
A
ADD
Addition
ADD<dest>, <src>
A,<pregs>
A,<dregs>
A,<limm>
A,<memind>
ADD A, P0:0
ADD A, D0:0
ADD A, #%1234
ADD A,
@@P0:0
A,<direct>
A<regind>
A,<hwregs>
A,<pregs>
A,<dregs>
A,<limm>
1
1
1
1
1
1
ADD A, %F2
ADD A, @P1:1
ADD A, X
1000011
1000001
1000000
1011001
1010001
1010100
1010101
1010001
1010001
AND
Bitwise AND
AND <dest>, <src>
1
1
2
1
1
1
1
1
2
3
1
1
AND A, P2:0
AND A, D0:1
AND A, #%1234
AND A, @@P1:0
AND A, %2C
A,<memind>
A,<direct>
A,<regind>
AND A,
@1:2+LOOP
A,<hwregs>
1
2
2
1
1
1
1
2
2
1
1
1
AND A, EXT3
CALL sub1
CALL Z, sub2
CCF
1010000
0010100
0010100
1001010
1001010
1001010
CALL Subroutine Call
CALL <cc>, <address> <cc>,<direct>
<direct>
CCF
Clear Carry Flag
CCF
None
None
None
CIEF Clear Carry Flag
COPF Clear OP Flag
CIEF
COPF
CIEF
COPF
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Preliminary
108
Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
Table 73
Description
Instruction Op Codes (Continued)
Inst
Op Code Synopsis
Operands
Words Cycles Examples
CP
Comparison
CP<src1>,<src2>
A, <pregs>
A, <dregs>
A, <memind>
A, <direct>
A, <regind>
A, <hwregs>
A, <Iimm>
<cc>, A
1
1
1
1
1
1
2
1
1
1
1
1
1
3
1
1
1
2
1
1
1
1
2
2
CP A, P0:0
CP A, D3:1
CP A, @@P0:0
CP A, %FF
CP A, @P2:1+
CP A, STACK
CP A, #%FFCF
DEC NZ, A
DEC A
0111001
0110001
0110101
0110011
0110001
0110000
0110100
1001000
1001000
1001000
1001000
0100110
0100110
DEC
INC
JP
Decrement
Increment
Jump
DEC [<cc>,] <dest>
INC [<cc>,] <dest>
A
<cc>, A
INC PL, A
A
INC A
JP [<cc>,] <address> <cc>, <direct> 2
<direct>
JP NIE, Label
JP Label
2
PS005600-TVC1299
Preliminary
109
Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
Table 73
Description
Instruction Op Codes (Continued)
Inst
Op Code Synopsis
Operands
A, <hwregs>
A, <dregs>
A, <pregs>
A, regind>
Words Cycles Examples
LD
Load Destination
with Source
LD <dest>,<src>
1
1
1
1
1
1
1
1
3
LD A, X
0000000
0000001
0001001
0000001
0000101
LD A, D0:0
LD A, P0:1
LD A, @P1:1
LD A, @D0:0
A, <memind>, 1
<memind>
A, <direct>
<direct>, A
1
1
1
1
1
1
LD A, 124
0000011
0000111
0000100
LD 124, A
<dregs>,
<hwregs>
LD D0:0, EXT7
<pregs>,
<simm>
1
1
1
1
1
1
1
1
LD P1:1, #%FA
LD P1:1, EXT1
0001100
0001010
0000110
0000010
0001001
0000001
0000100
0100101
0000101
0000001
0000000
<pregs>,
<hwregs>
<regind>,
<limm>
LD @P1:1,
#%1234
<regind>,
<hwregs>
LD @PM+, X
<hwregs>,
<pregs>
1
1
LD Y, P0:0
<hwregs>,
<dregs>
1
2
1
1
1
1
1
2
3
3
1
1
LD SR, D0:0
LD PC, #%1234
LD X, @A
<hwregs>,
<limm>
<hwregs>,
<accind>
<hwregs>,
<memind>
LD Y, D0:0
<hwregs>,
<regind>
LD A,
@P0:0-LOOP
<hwregs>,
<hwregs>
LD X, EXT6
When <dest> is <hwregs>, <dest> cannot be P.
When<dest> is <hwregs> and <src> is <hwregs>,
<dest> cannot be EXTn if <src> is EXTn, <dest>
cannot be X if <src> is X, <dest> cannot be SR if
<src> is SR.
When <src> is <accind> <dest> cannot be A.
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Preliminary
110
Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
Table 73
Description
Instruction Op Codes (Continued)
Inst
Op Code Synopsis
Operands
<cc>, A
A
Words Cycles Examples
NEG
Negate
NEG <cc>, A
1
1
1
1
1
1
NEG NZ,A
NEG A
NOP
1001000
1001000
0000000
NOP
OR
No Operation
Bitwise OR
NOP
None
OR <dest>, <src>
A, <pregs>
A, <dregs>
A, <limm>
1
1
2
1
1
1
2
3
OR A, P0:1
OR A, D0:1
OR A,#%202
1101001
1100001
1100100
1100101
A, <memind>
OR
A, @@P2:1+
A, <direct>
A, <regind>
1
1
1
1
OR A, %2C
1100011
1100001
OR A,
@P1:0-LOOP
A, <hwregs>
<pregs>
1
1
1
1
1
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
2
3
3
2
OR A, EXT6
POP P0:0
1100000
0001010
0000100
0000010
0000000
0001001
0000001
0000001
0000000
0000100
0100101
0000101
0000000
POP
Pop a Value from
the Stack
POP <dest>
<regs>
POP D0:1
<regind>
<hwregs>
POP @P0:0
POP A
PUSH Push a Value
onto the Stack
PUSH <src>, <pregs>
PUSH P0:0
PUSH D0:1
PUSH @P0:0
PUSH BU.S
PUSH #%2345
PUSH @A
PUSH @@P0:0
RET
<dregs>
<regind>
<hwregs>
<limm>
<accind>
<memind>
None
RET
RL
Return from
Subroutine
RET
Rotate Left
RL <cc>, A
<cc>, A
1
1
1
1
1
1
1
1
RL NZ, A
RL A
1001000
1001000
1001000
1001000
A
RR
Rotate Right
RR <cc>, A
<cc>, A
A
RR C, A
RR A
PS005600-TVC1299
Preliminary
111
Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
Table 73
Description
Instruction Op Codes (Continued)
Inst
SCF
SIEF
SLL
Op Code Synopsis
Operands
None
Words Cycles Examples
Set C Flag
SCF
SIEF
SLL
1
1
1
1
1
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
2
3
1
1
SCF
1001010
1001010
1001000
1001000
1001010
1001000
1001000
0011001
0010011
0010100
0010101
0010011
0010001
Set IE Flag
None
SIEF
Shift Left Logical
[<cc>,] A
A
SLL NZ, A
SLL A
SOPF Set OP Flag
SOPF
None
SOPF
SRA
Shift Right
Arithmetic
Subtract
SRA <cc>, A
<cc>, A
A
SRA NZ, A
SRA A
SUB
SUB <dest>,
<src>
A, <pregs>
A, <dregs>
A, <limm>
A, <memind>
A, <direct>
A, <regind>
SUB A, P1:1
SUB A, D0:1
SUB A, #%2C2C
SUB A, @D0:1
SUB A, %15
SUB A,
@P2:0-LOOP
A, <hwregs>
1
1
SUB A, STACK
0010000
XOR
Bitwise Exclusive
OR
XOR <dest>, <src>
A, <pregs>
A, <dregs>
A, <limm>
1
1
2
1
1
1
1
1
1
2
3
1
1
1
XOR A, P2:0
1111001
1110001
1110100
1110001
1110011
1110001
1110000
XOR A, D0:1
XOR A, #%3933
XOR A, @P2:1+
XOR A, %2F
A, <memind>
A, <direct>
A, <regind>
A, <hwregs>
XOR A, @P2:0
XOR A, BUS
Instruction Descriptions
The DSP instruction set consists of 30 basic instructions, optimized for high-code density
and reduced execution time. Single-cycle instruction execution is possible because of the
Z90376 pipeline and system architecture. Table 74 contains a description for each
instruction.
PS005600-TVC1299
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64 KWord Television Controller with OSD
Table 74
Instruction Descriptions
Mnemonic Expansion
Mnemonic
Instruction Operands Lists the types of addressing methods for a speciÞc
instruction (ABS A or ABS <cc>, A).
Instruction Format
Operation
Displays instruction format for register indirect addressing.
Displays operation sequence.
Affected Flags
Description
Lists ßags affected by operation.
Describes the instruction operation.
Examples
A simple example displays the instruction operation and
how registers are affected. The example includes
initialization, instruction and result. It also includes the
number of cycles and instruction length.
Note: Each Assembly Instruction includes an example for each addressing mode
available for the specific instruction.
The mnemonics listed in Table 75 are used in the instruction format.
Table 75
Instruction Format Mnemonics
Mnemonic
Description
Mnemonic
dest
Description
A
Address
Destination Value
Flag ModiÞcation
Op Code
am
Accumulator ModiÞcation fm
b
RAM Bank
op
rp
s
cc
Condition Code
Constant Expression
Destination Address
Register Pointer
Source Address
Source Value
const exp
d
src
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Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
ABS
Absolute Value
ABS
Instruction Word
15 14 13 12 11 10
9
0
8
7
6
5
4
3
0
2
1
1
1
0
1
1
0
0
1
0
0
cc cc cc cc cc
Condition Code
Op Code
ACC ModiÞcation
Syntax
ABS <cc>, A
ABS A
Operation
If ACC < 0 then -(ACC) -> ACC
Flags: N: Set if the accumulator has 800000H(see below).
Description
If the contents of the accumulator are determined to be less then 0(a negative number),
the absolute value of the accumulator is calculated (accumulator replaced by its two's
complement value). Using the condition code provides an additional method to evaluate a
status flag before the absolute value of the accumulator is calculated.
Note: If the accumulator contains 800000H, the ABS Ainstruction stores the value of
the two's complement at address 800000Hand sets the Overflow and Negative
status bits. There is no overflow protection.
Example
ABS A
Initialization: Accumulator contains FFEB00H
SR contains 0000H
Instruction:
Result:
ABS A
Accumulator contains 001500H
SR contains 1000H
This example uses one word of memory and executes in one machine cycle. Because the
value in the accumulator is less then zero, the two's complement is performed and the
result is placed in the accumulator ABS(FFEBH)=001500H. The carry bit is set.
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Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
Example
ABS <cc>, A
Initialization: Accumulator contains 456400H
Instruction:
Result:
ABS MI, A
Accumulator contains 456400H
This example uses one word of memory and executes in one machine cycle. The condition
code (negative bit) is not set because the accumulator value is positive; therefore, the
instruction is not executed.
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Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
ADD
Addition
ADD
Instruction Word
15 14 13 12 11 10
9
1
8
b
7
0
6
0
5
0
4
0
3
s
2
s
1
s
0
s
1
0
0
0
0
0
Op Code
RAM
Bank
Destination
Source
Syntax
ADD
A,
A,
A,
A,
A,
A,
A,
<regind>
<memind>
<limm>
ADD
ADD
ADD
<hwregs>
<direct>
<pregs>
<dregs>
ADD
ADD
ADD
Operation
ACC + <source> -> ACC
Flags: C
N:
Set if carry from the most significant bit is found.
Set if result in the accumulator is negative.
Set if result is 0.
Z:
OV:
Set if addition exceeds upper (FFFFFH)
or lower (800000H) limit of the accumulator.
Description
The addressed data memory operand is added to the accumulator. The result is loaded into
the accumulator.
Note: The lower eight bits of the accumulator are unchanged while the add instruction is
executed.
Example
ADD A, <regind>
PS005600-TVC1299
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Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
Initialization: Accumulator contains 123456H
P0:0 contains 4DH
RAM Bank1: 4DH contains 8746H
Instruction:
Result:
ADD A, @P0:0
A contains 997A56H
@P0:0 contains 746H
This example uses one word of memory and executes in one machine cycle. The pointer
P0:0contains the RAM register location (4DH). The contents of RAM register 4DHare
added to the accumulator to obtain the sum (874600H + 123456H = 997A56H). The
sum is contained in the accumulator and the pointer is left unchanged. The direct
addressing equivalent is ADD A, %4D or ADD A, 77(4DH = 77 decimal).
Example
ADD A, <memind>
Initialization: Accumulator contains 123400H
P0:0 contains 21H
RAM Bank0: 21H contains 247AH
ROM Address: 247AHcontains 0C12H
Instruction:
Result:
ADD A, @@P0:0
A contains lE4600H
P0:0 contains 21H
RAM Bank0: 21H contains 247BH
This example uses one word of memory and executes in three machine cycles. The pointer
P0:0contains the RAM register location (21H). The contents of this register have a ROM
address. This address refers to the ROM data placed in the specified accumulator by an
ANDinstruction 123400H + 0C1200H = 1E4600H. When memory indirect
addressing is used, the ROM address is automatically incremented. to provide a
convenient method of accessing sequential data. Using ADD A, @@P0:0+performs the
same operation and also increments the P0:0content to 22H.
Example
ADD A, <limm>
Initialization: Accumulator contains 123400H
Instruction:
Result:
ADD A, #%0C12
A contains lE4600H
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Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
This example uses two words of memory and executes in two machine cycles. The
immediate operand 0C12His added to the accumulator to obtain the sum 123400H +
0C1200H = 1E4600H.
Example
ADD A,<hwregs>
Initialization: Accumulator contains 23400H
Register X contains 0C12H
Instruction:
Result:
ADD A, X
A contains 1E4600H
This example uses one word of memory and executes in one machine cycle. The contents
of register X are added to the accumulator to obtain the sum. 123400H + 0C1200H =
1E4600H. All hardware registers can transfer from <hwregs>.
Example
ADD A,<direct>
Initialization: Accumulator contains 123400H
RAM Bank0: F3Hcontains 0C12H
Instruction:
Result:
ADD A,%F3
A contains 1E4600H
This example uses one word of memory and executes in one machine cycle. Register F3H
is added to the accumulator to obtain the sum. 123400H + 0C1200H = 1E4600H.
An equivalent instruction is ADD A, 243(F3H = 243 decimal).
Example
ADD A, <pregs>
Initialization: Accumulator contains 123400H
P0:0 contains 56H
Instruction:
Result:
ADD A, P0:0
Accumulator contains 128A00H
This example uses one word of memory and executes in one machine cycle. The contents
of the pointer register P0:0is added to the accumulator. 123400H + 005600H =
128A00H. The Pointer Register is connected to the lower 8 bits of the D-bus. The D-bus
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Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
is connected to the upper 16-bits of the P-bus. This causes the pointer register operand to
become 005600Hbefore being added to the accumulator.
Example
ADD A,<dregs>
Initialization: Accumulator contains 123400H
D0: 1 contains 8746H
Instruction:
Result:
ADDA,D0:1
A contains 997A00H
D0: 1 contains 8746H
This example uses one word of memory and executes in one machine cycle. The contents
of the data pointer D0:1are added to the accumulator. The sum is contained in the
accumulator and the pointer is left unchanged. The data pointer contains 8746H.
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AND
BITWISE AND
AND
Instruction Word
15 14 13 12 11 10
9
0
8
b
7
0
6
0
5
0
4
0
3
s
2
s
1
s
0
s
1
0
1
1
1
0
Op Code
RAM
Bank
Destination
Source
Syntax
AND A, <regind>
AND A, <memind>
AND A, <limm>
AND A, <hwregs>
AND A, <direct>
AND A, <pregs>
AND A, <dregs>
AND A, <simm>
Operation
<accumulator>. AND.<source> —> <accumulator>
Flags: N:
Set if accumulator result is less than 0.
Z:
Set if accumulator result is 0.
Description
Data is stored in the specified accumulator by an ANDinstruction. The lower eight bits of
the accumulator are cleared when this instruction is executed.
Example
AND A, <regind>
Initialization: Accumulator contains 123456H
P0A contains 45H
RAM Bank1: 45H contains 8746H
Instruction:
Result:
AND A, @P0:1
Accumulator contains 020400H
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This example uses one word of memory and executes in one machine cycle. The data in
RAM Bank1, referenced by RAM pointer 0, is stored in the specified accumulator using
an ANDinstruction 123456H.AND.874600H = 020400H.
Example
AND A, <memind>
Initialization: Accumulator contains 123400H
P0:0 contains45H
RAM Bank0: 45H contains 047AH
ROM Address: 047AH contains 8746H
Instruction:
Result:
AND A, @@P0:0
A contains 020400H
P0:0 contains 45H
RAM Bank0: 45H contains 247BH
This example uses one word of memory and executes in three machine cycles. The pointer
P0:0contains the RAM register location (45H). The contents of this register has a ROM
address. This address refers to the ROM data that is placed in the specified accumulator by
an AND instruction 123400H.AND.874600H = 020400H. With memory-indirect
addressing, the ROM address is automatically incremented. This provides a convenient
method to access sequential data. Using AND A, @@P0:0+performs the same operation
and also increments the P0:0content to 46H.
Example
AND A, <limm>
Initialization: Accumulator contains 362400H
Instruction:
Result:
AND A, #%1234
Accumulator contains 122400H
This example uses two words of memory and executes in two machine cycles. The
immediate operand 1234Hand an accumulator address are processed with an AND
instruction to produce the result, 362400H.AND.123400H = 122400H.
Example
AND A, <simm>
Initialization: Accumulator contains 123456H
Instruction:
AND A, #%1F
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Result:
Accumulator contains 001400H
This example uses one word of memory and executes in one machine cycle. The data in
the immediate field and the contents of the accumulator are processed with an AND
instruction. 123456H.AND.001F00H = 001400H.
Example
AND A, <hwregs>
Initialization: Accumulator contains 123400H
Register X contains OC12H
Instruction:
Result:
AND A, X
A contains 001000H
This example uses one word of memory and executes in one machine cycle. Use an AND
instruction to send the contents of Register Xto the accumulator to obtain the result
123400H.AND.0C1200H = 001000H. All hardware registers can transfer from
<hwregs>.
Example
AND A, <direct>
Initialization: Accumulator contains 123400H
RAM Bank0: F3H contains 0C12H
Instruction:
Result:
AND A, %F3
A contains 001000H
This example uses one word of memory and executes in one machine cycle. Use an AND
instruction to send Register F3Hto the accumulator to obtain the result 123400H AND
OC1200H = 001000H. An equivalent instruction is AND A, 243(F3H= 243
decimal).
Example
AND A, <pregs>
Initialization: Accumulator contains 123400H
P0:0 contains 56H
Instruction:
Result:
AND A, P0:0
Accumulator contains 001400H
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This example uses one word of memory and executes in one machine cycle. Use an AND
instruction to send the contents of the pointer register P0:0to the accumulator
123400H.AND.005600H = 001400H. The Pointer Register is connected to the
lower 8 bits of the D-bus. The D-bus is connected to the upper 16 bits of the P-bus. This
action changes the pointer register operand to 005600Hbefore being added to the
accumulator.
Example
AND A, <dregs>
Initialization: Accumulator contains 123400H
D0:1 contains 2645H
Instruction:
Result:
AND A, 00:0
Accumulator contains 020400H
This example uses one word of memory and executes in one machine cycle. The data
register, D0:0, references the operand 2645H. Use an ANDinstruction to send this data
register to the accumulator to produce the result 123400H.AND.2645H = 020400H.
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CALL
SUBROUTINE CALL
CALL
Instruction Word
15 14 13 12 11 10
9
0
8
b
7
6
5
4
3
s
2
s
1
s
0
s
0
0
0
0
0
0
cc cc cc cc
Condition Code
Op Code
Not Used
15 14 13 12 11 10
9
a
8
a
7
a
6
a
5
a
4
a
3
a
2
a
1
a
0
a
a
a
a
a
a
a
16-Bit Address
Syntax
CALL <cc>,<direct>
CALL <direct>
Operation
PC + 2 —> STACK
16-Bit Address —> PC
Flags: None
Description
The current Program Counter (PC) register content is incremented by two and placed on
the stack. The address of the specified label in the CALLinstruction is then placed in the
PCregister. The jump is made to the appropriate subroutine via the PC. The condition
code option is used if CALLis executed.
Example
CALL <direct>
Cycles: 2
Words: 2
Initialization: PC contains 1FFBH
FFT2 subroutine address contains F234H
Stack Level 0 contains 0025H
Instruction:
CALL FFT2
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Result:
PC contains F234H
Stack Level 0 contains 1FFDH
Stack Level 1 contains 0025H
This example uses two words of memory and executes in two machine cycles. The call to
the subroutine FFT2places PC+2(1 FFDH) on the stack. All information currently on
the stack is pushed up the stack. The subroutine address is then placed in the PCregister.
The processor executes the next instruction addressed by the PC, the FFT2subroutine.
Example
CALL <cc>, <direct>
Initialization: PC contains 1FFBH
FFT2 subroutine address contains F234H
Stack Level 0 contains 0025H
UO (User Zero Bit) contains 1
Instruction:
Result:
CALL UO, FFT2
PC = F234H
Stack Level 0= 1FFDH
Stack Level 1= 0025H
This example uses two words of memory and executes in two machine cycles. The
condition code UOis tested by the processor before executing the CALLinstruction.
Because the UObit is enabled, the CALLroutine is executed exactly like the example
above. The condition code UOis input to the processor that determines if subroutine FFT2
is used. Another CALLinstruction can determine if another subroutine, FFT1, is used.
Example
CALL <direct>
Initialization: PC contains 1FFBH
FFT2 subroutine address contains F234H
Stack Level 0 contains 0025H
Instruction:
Result:
CALL FFT2
PC containsF234H
Stack Level 0 contains 1FFDH
Stack Level 1 contains 0025H
This example uses two words of memory and executes in two machine cycles. The call to
the subroutine FFT2places PC+2 (1 FFDH) on the stack. All information currently on
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the stack is pushed up the stack. The subroutine address is then placed in the PCregister.
The processor executes the next instruction addressed by the PC, the FFT2subroutine.
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CCF
CLEAR CARRY FLAG
CCF
Instruction Word
15 14 13 12 11 10
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
1
0
0
1
0
0
1
0
1
Op Code
Condition Code
Flag ModiÞcation
Syntax
CCF
Operation
Zero —> Carry Bit
Flags: C: Set to 0.
Description
The Clear Carry Flag instruction resets the carry flag with a 0.
Example
CCF
Initialization: SR contains 3000H
Instruction:
Result:
CCF
SR contains 2000H
C contains 0
This example uses one word of memory and executes in one machine cycle.
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CIEF
CLEAR INTERRUPT ENABLE FLAG
CIEF
Instruction Word
15 14 13 12 11 10
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
1
1
0
0
0
1
0
0
1
0
1
Op Code
Condition Code
Flag ModiÞcation
Syntax
CIEF
Operation
Zero —> IE bit
Flags: IE: Set to 0.
Description
The Clear Interrupt Enable Flag instruction sets the IE flag to 0.
Example
CIEF
Initialization: SR contains 3080H
Instruction:
Result:
CIEF
SR contains 3000H
IE contains 0
This example uses one word of memory and executes in one machine cycle.
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COPF CLEAR
OVERFLOW PROTECTION FLAG
COPCLEAR
Instruction Word
15 14 13 12 11 10
9
0
8
0
7
0
6
0
5
0
4
0
3
1
2
0
1
0
0
0
1
0
0
1
0
1
Op Code
Condition Code
Flag ModiÞcation
Syntax
COPF
Operation
Zero —> OP bit
Flags: P: Set to 0.
The Clear Overflow Protection Flag instruction resets the OPflag to 0.
Example
COPF
Initialization: SR contains 0100H
Instruction:
Result:
COPF
SR contains 0000H
OP contains 0
This example uses one word of memory and executes in one machine cycle.
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CP
COMPARISON
CP
Instruction Word
15 14 13 12 11 10
9
0
8
b
7
0
6
0
5
0
4
0
3
s
2
s
1
s
0
s
0
1
1
0
0
1
Op Code
RAM
Bank
Destination
Source
Syntax
CP
A,
A,
A,
A,
A,
A,
A,
A,
<regind>
<memind>
<limm>
CP
CP
CP
<hwregs>
<direct>
<pregs>
<dregs>
<simm>
CP
CP
CP
CP
Operation
A - <source> —> set appropriate status bits
Flags: C:
Set if carry is required for operation.
Set if operands are equal.
Z:
OV:
Set if operation exceeds the low (800000H) or high
limit (7FFFFFH) of accumulator.
Set if result is negative.
N:
Description
The contents of the register specified in the instruction are compared to the contents of the
accumulator in 16-bit mode. The register specified is subtracted from the accumulator and
the appropriate flags are set. Because the registers are 16-bit, a comparison with the 24-bit
accumulator requires that the lower eight bits of the accumulator be filled with zeros for
accurate comparisons. The instruction does not affect the contents of the accumulator
except when the overflow protection bit is set and an overflow occurs after the compare is
executed. The accumulator updates with the appropriate low (800000H) or high
(7FFFFFH) limit.
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Example
CP A, <regind>
Initialization: A contains 7A2500H
P2:1 contains A4H
RAM Bank1: A4H contains 5463H
Instruction:
Result:
CP A, @P2:1
A contains 7A2500H
SR contains 1000H
This example uses one word of memory and executes in one machine cycle. The operand
referenced by P2:1is subtracted from the accumulator. 7A2500H - 546300H =
25C200H. Because the comparison does not yield a 0, Bit 0 is not set. The content of the
P2:1 register is appended with eight additional 0bits. For consistent comparisons, the
accumulator must contain zeros in the lower eight bits.
Note: The accumulator is unaffected by the operation.
Example
CP A, <memind>
Initialization: A contains 7A2500H
P2:1 contains A4H
RAM Bank1: A4H contains 5463H
ROM Address: 5463H contains OC12H
Instruction:
Result:
CP A, @@P2:1
A contains 7A2500H
P2:1 contains A4H
RAM Bank1: A4Hcontains 5464H
SR contains 1000H
This example uses one word of memory and executes in three machine cycles.The pointer
P2:1contains the RAM register location (A4H). The contents of this register have a ROM
address. This address refers to the ROM data compared to the accumulator 7A2500H -
OC1200H = 6E1300H. Because the comparison does not yield a 0, Bit 0 is not set.
With memory indirect addressing, the ROM address is automatically incremented. Using
CP A,@@P2:1 +performs the same operation and also increments P2:1content to
A5H.
Example
CP A, <limm>
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Initialization: A contains 7A2500H
Instruction:
Result:
CP A, #%7A25
A contains 7A2500H
SR contains 3000H
This example uses two words of memory and executes in two machine cycles. The
immediate operand is compared to the accumulator. Because they are equal, the Zero Flag
is set.
Example
CP A, <hwregs>
Initialization: A contains 7A2500H
SR contains 0000H
BUS contains 7A25H
Instruction:
Result:
CP A, BUS
A contains 7A2500H
SR contains 3000H
This example uses one word of memory and executes in one machine cycle. The
<hwreg> operand is subtracted from the accumulator. Because the two operands are
equal, the zero-status bit is set High. <hwregs> can be compared from all hardware
registers.
Example
CP A, <direct>
Initialization: Accumulator contains 7A2500H
RAM Bank0 F3H contains 5463H
Instruction:
Result:
CP A, %F3
A contains 7A2500H
SR contains 1000H
This example uses one word of memory and executes in one machine cycle. Register F3H
is compared to the accumulator. 7A2500H - 546300H = 25C200H.An equivalent
instruction is CP A,243(173H= 243 decimal).
Example
CP A, <pregs>
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Initialization: Accumulator contains 123400H
P0:0 contains 56H
Instruction:
Result:
CP A, P0:0
Accumulator contains 123400H
SR contains 1000H
This example uses one word of memory and executes in one machine cycle. The contents
of the pointer register P0:0are compared to the accumulator. 123400H - 005600H
= 11DE00HThe Pointer Register is connected to the lower 8 bits of the D-bus. The
D-bus is connected to the upper 16 bits of the P-bus. This action changes the pointer
register operand to 005600Hbefore being compared to the accumulator.
Example
CP A, <dregs>
Initialization: A contains 7A2500H
D2:1 contains 5463H
Instruction:
Result
CP A, D2:1
A contains 7A2500H
SR contains 1000H
This example uses one word of memory and executes in one machine cycle. The contents
of the data pointer D2:1are compared to the accumulator. 7A2500H - 546300H =
25C200H.
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DEC
DECREMENT
DEC
Instruction Word
15 14 13 12 11 10
9
0
8
7
6
5
4
3
0
2
1
1
0
0
1
1
0
0
1
0
0
cc cc cc cc cc
Condition Code
Op Code
ACC ModiÞcation
Syntax
DEC A
DEC <cc>, A
Operation
ACC - 1 —> ACC
Flags: C:
Set if carry is required for operation
Set if result is 0.
Set if decrement results in a value less then 0.
Z:
N:
OV:
Set if upper (7FFFFFH)or lower (800000H)limits
are exceeded.
Description
The accumulator decrements by 1. A condition code can be used to test for a specific
condition before decrementing.
Example
DEC A
Initialization: A contains 7A2500H
Instruction:
Result:
DEC A
A contains 7A24FFH
This example uses one word of memory and executes in one machine cycle. The value in
the accumulator decrements by 1.
Example
DEC <cc>, A
Initialization: A contains 7A2500H
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Instruction:
Result:
DEC MI, A
A contains 7A2500H
This example uses one word of memory and executes in one machine cycle. Because the
accumulator is not negative, the decrement instruction is not executed.
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INC
INCREMENT
INC
Instruction Word
15 14 13 12 11 10
9
0
8
7
6
5
4
3
0
2
1
1
0
0
0
1
0
0
1
0
0
cc cc cc cc cc
Condition Code
Op Code
ACC ModiÞcation
Syntax
INC <cc>, A
INC A
Operation
ACC + 1 —> ACC
Flags: C:
Set if carry is required for operation.
Set if result is 0.
Set if results in a value less then 0.
Z:
N:
OV:
Set if upper (7FFFFFH)or lower (800000H)limits
are exceeded.
Description
The Increment instruction adds one to the accumulator. A condition code can be used to
test for a specific condition for an increment to occur.
Example
INC <cc>, A
Initialization: A contains 7A2500H
Instruction:
Result:
INC MI, A
A contains 7A2500H
This example uses one word of memory and executes in one machine cycle. Because the
accumulator is not negative, the increment instruction is not executed.
Example
INC A
Initialization: A contains 7A2500H
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Instruction:
Result:
INC A
A contains 7A2501H
This example uses one word of memory and executes in one machine cycle. The value in
the accumulator is incremented by 1.
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JP
JUMP
JP
Instruction Word
15
1
14 13 12 11 10
9
0
8
7
6
5
4
3
0
2
0
1
0
0
0
0
0
0
1
1
cc cc cc cc cc
Condition Code
Op Code
14 13 12 11 10
Not Used
15
a
9
a
8
a
7
a
6
a
5
a
4
a
3
a
2
a
1
a
0
a
a
a
a
a
a
16-Bit Address
Syntax
JP
<cc>,
<direct>
<direct>
JP
Operation
16-Bit address —> PC
Flags: None
Description
The instruction places the address of the referenced ROM location in the Program Counter
(PC). Because the processor obtains its next instruction address from the PC, the processor
jumps to the appropriate location. A condition code can be used to test for a specific
condition for a JUMPto occur.
Example
JP <cc>, <direct>
Initialization: Routine 1 address contains 1455H
PC contains 1343H
User 0 input contains 1
Instruction:
Result:
JP NUO, Routine 1
PC contains 1343H
This example uses two words of memory and executes in two machine cycles. Because the
User 0input is set High, the condition code is not met. Therefore, the JUMP instruction
does not execute. The User 0input is used to control the flow of the software.
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Example
JP <direct>
Initialization: Routine 1 address contains 1455H
PC contains 1343H
Instruction:
Result:
JP Routine 1
PC contains 1455H
This example uses two words of memory and executes in two machine cycles. The value
in the program counter is replaced by the Routine 1 address (1455H).
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LD
LOAD
LD
Instruction Word
15 14 13 12 11 10
9
1
8
b
7
0
6
0
5
1
4
1
3
s
2
s
1
s
0
s
0
0
0
0
0
0
Op Code
RAM
Bank
Destination
Source
Syntax
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
LD
A,
<pregs>
A
<direct>,
<hwregs>,
A,
<dregs>
<dregs>
<hwregs>
<limm>
<dregs>,
<hwregs>,
A,
<memind>
<simm>
<pregs>,
<hwregs>,
A,
<accind>
<direct>
<hwreg>
<memind>
<regind>
<limm>
<pregs>,
<hwregs>,
A,
<regind>,
<hwregs>,
A,
<regind>
<hwregs>
< pregs>
<hwregs>
<hwregs>,
<hwregs>,
Operation
<source> —> <destination>
Flags: None
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Description
The LOADcommand provides the ability to transfer data to several different locations in
the processor including hardware registers, accumulator, stack, pointers and memory. All
transfers across the various internal buses are transparent to the user.
Notes:
1.
A load using the Xor Yregister provides an automatic multiply operation. This
means the operand can be obtained from any register location.
2.
The Pregister is a read-only register, therefore the destination of the load cannot be
the Pregister.
3.
4.
LD EXTN, EXTNis not allowed.
A LOADinstruction to the accumulator clears the lower 8 bits of the 24-bit
accumulator.
Example 1
LD A, <regind>
Initialization: A contains 7A2500H
P2:1 contains A4H
RAM Bank1: A4H contains 5463H
LD A, @P2:1
A contains 546300H
Instruction:
Result:
This example uses one word of memory and executes in one machine cycle. Indirect
addressing through the pointer registers provides access to RAM data. The data in RAM
Bank 1, register A4is transferred to the accumulator. The contents of the P2:1register
are appended with eight additional 0bits. This is added to verify a correct arithmetic
comparison.
Example 2
LD A, <memind>
Initialization: Accumulator contains 123400H
P0:0 contains 21H
RAM Bank0: 21Hcontains 247AH
ROM Address: 247AHequals OC1 2H
Instruction:
Result:
LD A, @@P0:0
A contains OC1 200H
P0:0 contains 21H
RAM Bank0: 21H contains 247BH
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This example uses one word of memory and executes in three machine cycles. The pointer
P0:0contains the RAM register location (21H). The contents of this register have a
ROM address. This address refers to the ROM data that loads to the accumulator. When
memory indirect addressing is used, the ROM address is automatically incremented.
Using LD A, @@P0:0+has the same result, also incrementing the P0:0content to
22H.
Example 3
LD A, <limm>
Cycles: 2
Words: 2
Initialization: Accumulator contains 123400H
Instruction:
Result:
LD A, #%2474
A contains 247400H
This example uses two words of memory and executes in two machine cycles. The
immediate operand 2474Hloads to the accumulator.
Example 4
LD A, <hwregs>
Initialization: Accumulator contains 123400H
Register X contains OC12H
Instruction:
Result:
LD A, X
A contains OC1200H
This example uses one word of memory and executes in one machine cycle. The contents
of Register Xare loaded to the accumulator. All hardware registers can transfer from
<hwregs>.
Example 5
LD A, <direct>
Initialization: Accumulator contains 123400H
RAM Bank0 F3H contains OC12H
Instruction:
Result:
LD A, %F3
A contains OC1200H
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This example uses one word of memory and executes in one machine cycle. Register F3H
is loaded to the accumulator. An equivalent instruction is LD A,243(F3H= 243
decimal).
Example 6
LD A, <dregs>
Initialization: Accumulator contains123400H
D0: 1 contains 8746H
Instruction:
Result:
LD A, D0:1
A contains 874600H
D0: 1 contains 8746H
This example uses one word of memory and executes in one machine cycle. The contents
of the data pointer D0:1load to the accumulator.
Example 7
LD A, <pregs>
Initialization: Accumulator contains 123400H
P0:0 contains 56H
Instruction:
Result:
LD A, P0:0
Accumulator contains 005600H
This example uses one word of memory and executes in one machine cycle. The contents
of the pointer register P0:0are loaded to the accumulator. The Pointer Register is
connected to the lower 8 bits of the D-bus. The D-bus is connected to the upper 16 bits of
the P-bus. This operation causes the pointer register operand to become 005600Hbefore
being loaded into the accumulator.
Example 8
LD <direct>, A
Initialization: Accumulator contains 123400H
RAM Bank0: 3CH contains 5678H
Instruction:
Result:
LD %3C, A
Accumulator contains 123400H
RAM Bank0: 3CH contains 1234H
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This example uses one word of memory and executes in one machine cycle. The current
value in the accumulator is loaded to the register addressed by the instruction (3CH). An
equivalent instruction is LD 60, A. (3CH= 60 decimal).
Example 9
LD <pregs>, <simm>
Initialization: P2:0 contains 2FH
RAM Bank0: 3FH contains 254645H
Instruction:
Result:
LD P2:0, #%3F
P2:0 contains 3FH
RAM Bank0: 3FHcontains 254645H
This example uses one word of memory and executes in one machine cycle. The
immediate data (3FH) is loaded into the pointer register P2:0. This action provides a
convenient method for initializing pointer registers.
Example 10
LD <pregs>, <hwregs>
Initialization: P0: 1 contains 2FH
Y contains 2376H
Instruction:
Result:
LD P0:1, Y
P0: 1 contains 76H
Y contains 2376H
This example uses one word of memory and executes in one machine cycle. The lower
8-bits of the Yregister are transferred to the pointer register P0:1. All hardware registers
can transfer from <hwregs>.
Example 11
LD <regind>, <limm>
Initialization: P0:1 contains 2FH
RAM Bank0: 2FH contains 2376H
Instruction:
Result:
LD @P0:1, #%35B8
P0:1 contains 2FH
RAM Bank1: 2FH contains 35B8H
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This example uses two words of memory and executes in two machine cycles. The
immediate operand 35B8His transferred to the Register 2FHof RAM Bank1.
Example 12
LD <hwregs>, <pregs>
Initialization: P2:0 contains 2FH
X Register contains 8B87H
Instruction:
Result:
LD X,P2:0
P2:0 contains 2FH
X Register contains 002FH
This example uses one word of memory and executes in one machine cycle. The contents
of the P2:0pointer (2FH) are loaded into the Xregister. Transfer to <hwreg> is possible
to all hardware registers except the read-only Pregister.
Example 13
LD <hwregs>, <dregs>
Initialization: D2:0 contains 3C87H
Accumulator contains 8BB722H
Instruction:
Result:
LD A,D2:0
D2:0 contains 3C87H
Accumulator contains 3C8700H
This example uses one word of memory and executes in one machine cycle. The contents
of the D2:0pointer (3C87H) are loaded into the accumulator. Transfer to <hwregs> is
possible to all hardware registers except the read-only Pregister.
Example 14
LD <hwregs>, <limm>
Initialization: Stack0 contains 8B2FH
Stack1 contains 0000H
Instruction:
Result:
LD Stack, #%35B8
Stack0 contains 35B8H
Stack1 contains 8B2FH
This example uses two words of memory and executes in two machine cycles. The
immediate data is pushed onto the stack as previous stack data is pushed up the stack.
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Transfer to <hwregs> is possible to all hardware registers except the read-only P
register.
Example 15
LD <hwregs>, <accind>
Initialization: EXT7 Register contains 8B87H
Accumulator contains 77B6H
ROM 77B6Hcontains 387DH
Instruction:
Result:
LD EXT7, @A
EXT7 Register contains 387DH
Accumulator contains 77B6H
This example uses one word of memory and executes in one machine cycle. The contents
of the ROM Register 77B6H(387DH) are loaded into External Register 7. Transfer to
<hwregs> is possible to all hardware registers except the read-only Pregister and the
accumulator register.
Example 16
LD <hwregs>, <memind>
Initialization: Y Register contains 1234H
P0:0 contains 21H
RAM Bank0: 21Hcontains 247AH
ROM Address: 247AHcontains 0C12H
Instruction:
Result:
LID Y, @@P0:0
Y Register contains 0C12H
P0:0 contains 21H
RAM Bank0: 21Hcontains 247BH
This example uses one word of memory and executes in three machine cycles. The pointer
P0:0contains the RAM register location (21H). The contents of this register have a ROM
address that refers to the ROM data that loads to the Yregister. Transfer to <hwregs> is
possible to all hardware registers except the read-only Pregister. When memory indirect
addressing is used the ROM address is automatically incremented. Using LD
A,@@P0:0+ performs the same operation and also increments the P0:0content to 22H.
Example 17
LD <hwregs>, <regind>
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Initialization: X Register contains 7A25H
P21 contains A4H
RAM Bank1: A4Hcontains 5463H
Instruction:
Result:
LD X, @P2:1
X Register contains 5463H
This example uses one word of memory and executes in one machine cycle. Indirect
addressing through the pointer registers provides access to RAM data. The data in RAM
bank 1, register A4is transferred to the Xregister. Transfer to <hwreg> is possible to all
hardware registers except the read-only Pregister.
Example 18
LD <hwregs>, <hwregs>
Initialization: X Register contains 7A25H
EXT5 Register contains 789AH
Instruction:
Result:
LD X, EXT5
X Register contains 789AH
EXT5 Register contains 789AH
This example uses one word of memory and executes in one machine cycle. The EXT5
Register contents are transferred to the Xregister. Transfer to <hwregs> is possible to all
hardware registers except the read-only Pregister.
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NEG
NEGATE
NEG
Instruction Word
15 14 13 12 11 10
9
0
8
7
6
5
4
3
0
2
1
1
1
0
0
1
0
0
1
0
0
cc cc cc cc cc
Condition Code
Op Code
ACC ModiÞcation
Syntax
NEG A
NEG <cc>, A
Operation
-ACC —> ACC
Flags: N Set if result is a negative number.
Two special cases are:
1.
If ACC contains 000000after execution, then Nand 0Vare cleared, and Zand C
are set
2.
If ACC contains 800000after execution, then N and 0Vare set; and Zand Care
cleared.
The accumulator is replaced with a negative of the current value. To achieve this
state, the two's complement is performed.
Example 1
NEG A
Initialization: A contains 003654H
Instruction:
Result:
NEG A
A contains FFC9ACH
This example uses one word of memory and executes in one machine cycle.
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Example 2
NEG <cc>, A
Initialization: A contains 000111H
Carry bit contains 1
Instruction:
Result:
NEG C, A
A contains FFFEEFH
This example uses one word of memory and executes in one machine cycle.
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NOP
NO OPERATION
NOP
Instruction Word
15 14 13 12 11 10
9
0
8
0
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
0
0
0
0
0
0
Syntax
NOP
Operation
PC+ 1—> PC
Flags:
None
Description
The NOPinstruction causes the processor to continue operation for one cycle without
affecting previous registers and I/0.
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OR
BITWISE OR
OR
Instruction Word
15 14 13 12 11 10
9
1
8
b
7
0
6
0
5
0
4
0
3
s
2
s
1
s
0
s
1
1
0
0
0
0
Op Code
RAM
Bank
Destination
Source
Syntax
OR A, <regind>
OR A, <memind>
OR A, <limm>
OR A, <hwregs>
OR A, <direct>
OR A, <pregs>
OR A, <dregs>
OR A, <simm>
Operation
ACC .OR. source —> ACC
Flags: N
Set If result in accumulator is negative.
Z
Set If result is 0.
Description
The accumulator performs an ORinstruction on the contents of the specified register. The
upper 16 bits of the accumulator are used. The result is placed in the accumulator. The OR
instruction is frequently used to compare specific bits to assist in program control.
Note: The lower eight bits of the accumulator are unchanged after execution of the OR
instruction.
Example
OR A, <regind>
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Initialization: Accumulator contains 3264A0H
P0:0 contains E2H
RAM Bank0: E2Hcontains 1126H
Instruction:
Result:
OR A, @P0:0
A contains 336600H
This example uses one word of memory and executes in one machine cycle. Use an OR
instruction to reference the operand P0:0with the upper 16 bits of the accumulator. The
result is stored in the accumulator. 3264A0H OR. 1126A0H = 3366A0H.
Example 2
OR A,<memind>
Initialization: A contains 3264A0H
P2:11 contains A4H
RAM Bank 1: A4H contains 5463H
ROM Address: 5463H contains 1126H
Instruction:
Result
OR A, @@P2:1
A contains 3366A0H
P2:1 contains A4H
RAM Bank0: A4Hcontains 5464H
SR contains 0000H
This example uses one word of memory and executes in three machine cycles. The pointer
P2:1contains the RAM register location (A4H). The contents of this register have a ROM
address. This address refers to the ROM data that is compared to the accumulator.
3264A0H.OR.112600H = 3366A0H. With memory indirect addressing, the ROM
address is automatically incremented. Using ORA,@@P0:0+performs the same operation
and also increments the P0:0content to A5H.
Example 3
OR A, <limm>
Initialization: A contains 3264A0H
Instruction:
Result:
OR A, #%1126
A contains 3366A0H
SR contains 0000H
This example uses two words of memory and executes in two machine cycles. The
accumulator performs an ORinstruction on the immediate data.
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POP
POP VALUE FROM STACK
POP
Instruction Word
15 14 13 12 11 10
9
8
b
7
d
6
d
5
d
4
d
3
s
2
s
1
s
0
s
op op op op op op op
Op Code
RAM
Bank
Destination
Source
Syntax
POP <pregs>
POP <dregs>
POP <regind>
POP <hwregs>
Operation
STACK 0 —> <destination>
Stack n —> Stack N-1
Flags: None
Description
The current value of the stack is copied to the specified register. Because the stack is a
last-in, first-out (LIFO) hard-wired architecture, the copy and shift of data remaining in
the stack are all performed in a single cycle.
The POPinstruction provides the ability to control information sent to the stack, making it
possible to expand the stack using software.
Example 1
POP <pregs>
Initialization: Stack 1 contains 0426H
Stack 0 contains 0C06H
P0:0 contains 24H
Instruction:
Result
POP P0:0
Stack 0 contains 0426H
P0:0 contains 06H
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This example uses one word of memory and executes in one machine cycle. The
destination of Stack 0(item on top of stack) is P0:0. The 8-LSBs of the data in
stack 0are loaded into P0:0. At transfer, Stack 1is automatically moved to Stack
0.
Example 2
POP <dregs>
Initialization: Stack 1 contains 0426H
Stack 0 contains 0C06H
D0:0 contains 7676H
Instruction:
Result:
POP D0:0
Stack 0 contains 0426H
D0:0 contains 0C06H
This example uses one word of memory and executes in one machine cycle. The
destination of the Stack 0(item on top of stack) is given by D0:0. When transferred,
Stack 1is automatically moved to Stack 0.
Example 3
POP <regind>
Initialization: Stack 1 contains 0426H
Stack 0 contains 0C06H
P0:0 contains 24H
RAM Bank0: 24H contains 42A4H
Instruction:
Result
POP @P0:0
Stack 0 contains 0426H
RAM Bank0: 24Hcontains 0C06H
This example uses one word of memory and executes in one machine cycle. The
destination of the Stack 0(item on top of stack) is given by P0:0. 24His the register
location in RAM Bank0 to which the stack item is transferred. At transfer, Stack 1 is
automatically moved to Stack 0.
Example 4
POP <hwregs>
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Initialization: Stack 1 contains 0426H
Stack 0 contains 0C06H
X Register contains 089CH
Instruction:
Result:
POP X
Stack 0 contains 0426H
X Register contains 0C06H
This example uses one word of memory and executes in one machine cycle. The
destination of the Stack 0 (item on top of stack) is given by the X Register. At transfer,
Stack 1 is automatically moved to Stack 0. Transfer to <hwregs> is possible to all
hardware registers except the read-only P register.
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PUSH
PUSH VALUE ONTO STACK
PUSH
Instruction Word
15 14 13 12 11 10
9
1
8
b
7
0
6
0
5
0
4
0
3
s
2
s
1
0
s
1
1
0
0
0
0
s
Op Code
RAM
Bank
Destination
Source
Syntax
PUSH <pregs>
PUSH <dregs>
PUSH <memind>
PUSH <accind>
PUSH <regind>
PUSH <hwregs>
PUSH <direct>
PUSH <limm>
Operation
<source> —> Stack
Stack n —> Stack n+ 1
Flags: None
Description
The contents of the specified register are placed on the stack. Because the stack is a last-in,
first-out (LIFO) hard-wired architecture, the placement and shifting of current stack data is
performed in a single cycle.
The PUSHinstruction provides the ability to control information sent to the stack, making
it possible to expand the stack through software.
Example 1
PUSH <pregs>
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Initialization: Stack 0 contains 0C06H
P1:1 contains A4H
Instruction:
Result
PUSH P1:1
Stack 1 contains 0C06H
Stack 0 contains 00A4H
This example uses one word of memory and executes in one machine cycle. The pointer
P1:1contains the 8-bit value A4H. The
16-bit value, 00A4H, is pushed onto the stack. At transfer, Stack 0 is automatically moved
to Stack 1.
Example 2
PUSH <dregs>
Initialization: Stack 1 contains 0426H
Stack 0 contains 0C06H
D1:1 contains 42A4H
Instruction:
Result
PUSH D1:1
Stack 1 contains 0C06H
Stack 0 contains 42A4H
This example uses one word of memory and executes in one machine cycle. The pointer
D1:1 is pushed onto the stack. At transfer, Stack 0 is automatically moved to Stack 1.
Example 3
PUSH <memind>
Initialization: Stack 1 contains 0426H
Stack 0 contains 0C06H
RAM Bank0: 24Hcontains 42A4H
P1:1 contains A4H
RAM Bank1: A4Hcontains 5463H
ROM Address 5463Hcontains 1126H
Instruction:
Result:
PUSH @@P1:1
Stack 1 contains 0C06H
Stack 0 contains 1126H
RAM Bank1: A4Hcontains 5464H
This example uses one word of memory and executes in three machine cycles. When
memory indirect addressing is used, the ROM address is automatically incremented.
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Using OR A,@@P0:0+performs the same operation and also increments the P0:0
content to A5H.
Example 4
PUSH <accind>
Initialization: Stack 1 contains 0426H
Stack 0 contains 0C06H
Accumulator contains 42A4H
ROM address 42A4H contains 4C45H
Instruction:
Result
PUSH @A
Stack 1 contains 0C06H
Stack 0 contains 4C45H
This example uses one word of memory and executes in one machine cycle. Indirect
addressing with the accumulator points to the ROM memory (42A4H) The data in this
location is pushed onto the stack. At transfer, Stack 0 is automatically moved to Stack 1.
Example 5
PUSH <regind>
Initialization: Stack 1 contains 0426H
Stack 0 contains 0C06H
P1:1 contains A4H
RAM Bank1: A4Hcontains 42A4H
Instruction:
Result:
PUSH @P1:1
Stack 1 contains 0C06H
Stack 0 contains 42A4H
RAM Bank1: A4H contains 42A4H
This example uses one word of memory and executes in one machine cycle. The pointer
P1:1contains the RAM register location (A4H). The data at this location is pushed onto
the stack. At transfer, Stack 0 is automatically moved to Stack 1.
Example 6
PUSH <hwregs>
Initialization: Stack 1 contains 0426H
Stack 0 contains 0C06H
X Register contains 42A4H
Instruction:
PUSH X
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Result:
Stack 1 contains 0C06H
Stack 0 contains 42A4H
This example uses one word of memory and executes in one machine cycle. The data in
the Xregister is pushed onto the stack. At transfer, Stack 0is automatically moved to
Stack 1. Transfer from <hwregs> is possible from all hardware registers.
Example 7
PUSH <direct>
Initialization: Stack 1 contains 0426H
Stack 0 contains 0C06H
RAM Bank0: 24Hcontains 42A4H
Instruction:
Result:
PUSH %24
Stack 1 contains 0C06H
Stack 0 contains 42A4H
This example uses one word of memory and executes in one machine cycle. The
instruction (24H) provides the direct register address. The value contained in this register
is pushed onto the stack (42A4H). At transfer, Stack 0 is automatically moved to Stack 1.
Example 8
PUSH <limm>
Initialization: Stack 1 contains 0426H
Stack 0 contains 0C06H
Instruction:
Result:
PUSH #%5757
Stack 1 contains 0C06H
Stack 0 contains 5757H
This example uses two words of memory and executes in two machine cycles. The
immediate operand 5757His pushed onto the stack. At transfer, Stack 0 is automatically
moved to Stack 1.
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RET
RETURN FROM SUBROUTINE
RET
Instruction Word
15 14 13 12 11 10
9
0
8
0
7
0
6
1
5
1
4
0
3
0
2
1
1
0
0
1
0
0
0
0
0
0
Op Code
RAM
Bank
Destination
Source
Syntax
RET
Operation
Stack 0 —> PC
Stack n —> Stack n-1
Flags: None
Description
The current stack information is popped from the stack and placed in the Program Counter
(PC) register. The jump is made from the subroutine via the PC.
Example
RET
Initialization: Stack 1 contains 0624
Stack 0 contains 0401
PC contains 06DF
Instruction:
Result:
RET
Stack 0 contains 0624
PC contains 0401H
This example uses one word of memory and executes in one machine cycle.
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RL
ROTATE LEFT
RL
Instruction Word
15 14 13 12 11 10
9
0
8
7
6
5
4
3
0
2
1
1
1
0
1
1
0
0
1
0
0
cc cc cc cc cc
Condition Code
Op Code
ACC ModiÞcation
Syntax
RL A
RL <cc>,A
Operation
C <= 23 ------------ < ---------- 8 <= C
Flags: N
Set if result of accumulator is negative
Set if result is zero.
Set if MSB is set before rotate.
Z
C
Description
The upper 16 bits of the accumulator are rotated left through the carry bit. The lower 8 bits
remain unchanged while the resultant LSB, bit 0, is placed with the value 0(see the
accumulator section).
Example 1
RL A
Initialization: A contains 226A84H
Carry bit contains 1
Instruction:
Result:
RL A
A contains 44D584H
Carry bit contains 0
This example uses one word of memory and executes in one machine cycle. The upper 16
bits (226AH) are shifted left through the carry bit to produce 44D5H. The lower 8 bits
(84H) remain unchanged.
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Example 2
RL <cc>, A
Initialization: A contains 226A84H
Carry bit contains 0, Z=0
Instruction:
Result:
RL Z, A
A contains 226A84H
This example uses one word of memory and executes in one machine cycle. The condition
code 0is not set; therefore, the instruction is not executed.
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RR
ROTATE RIGHT
RR
Instruction Word
15 14 13 12 11 10
9
0
8
7
6
5
4
3
0
2
0
1
0
0
0
1
0
0
1
0
0
cc cc cc cc cc
Condition Code
Op Code
ACC ModiÞcation
Syntax
RR A
RR <cc>, A
Operation
C =>23 ---- > 8 = => 7 - -> -- 0 —> discarded
Flags: N
Set if result of accumulator is negative.
Set if result is 0.
Set if LSB is set before rotate.
Z
C
Description
The upper 16 bits of ACC are rotated right through the carry bit. The MSB of the lower 8
bits also obtains the data shifted from the LSB of upper 16 bits. The lower 8 bits are
shifted right with the LSB being discarded.
Example 1
RR A
Initialization: A contains 226A84H
Carry bit contains 0
Instruction:
Result:
RR A
A contains 113542H
This example uses one word of memory and executes in one machine cycle. The upper 16
bits (226AH) are shifted right through the carry bit to produce 1135H. The lower 8 bits
(84H) are shifted right to provide 42H.
Example 2
RR <cc>, A
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Initialization: A contains 226A84H
Carry bit contains 0, Z=0
Instruction:
Result:
RR Z, A
A contains 226A84H
This example uses one word of memory and executes in one machine cycle. The condition
code 0is not set; therefore, the instruction is not executed.
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SCF
SET CARRY FLAG
SCF
Instruction Word
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
op op op op op op op cc cc cc cc cc fm fm fm fm
Op Code Condition Code Flag ModiÞcation
Syntax
SCF
Operation
1 —> Carry Bit
Flags: C Set to 1.
Description
The Set Carry Flag instruction places a one in the carry bit (bit 12 of the Status Register).
Example
SCF
Initialization: SR contains 2000H
Instruction:
Result:
SCF
SR contains 3000H
C contains 1
This example uses one word of memory and executes in one machine cycle.
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SIEF
SET INTERRUPT ENABLE FLAG
SIEF
Instruction Word
15 14 13 12 11 10
9
0
8
7
6
5
4
3
0
2
1
1
0
0
1
1
0
0
1
0
1
cc cc cc cc cc
Condition Code
Op Code
Flag ModiÞcation
Syntax
SIEF
Operation
1 —> IE bit
Flags: None
Description
The instruction places a 1in bit 7 of the status register and is used to enable interrupts.
Example
SIEF
Initialization: SR contains 3000H
Instruction:
Result:
SIEF
SR contains 3080H
IE contains 1
This example uses one word of memory and executes in one machine cycle.
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SLL
SHIFT LEFT LOGICAL
SLL
Instruction Word
15 14 13 12 11 10
9
0
8
7
6
5
4
3
0
2
0
1
1
0
1
1
0
0
1
0
0
cc cc cc cc cc
Condition Code
Op Code
ACC ModiÞcation
Syntax
SLL A
SLL <cc>, A
Operation
discarded <— C <= 23 - - - - < - - - -0 <= 0
Flags: N
Set if result of accumulator is negative
(bit 23 set to 1).
Z
C
Set if result is 0.
Set if MSB is set before shift.
Description
All 24 bits of the accumulator are shifted left through the carry bit. The MSB, bit 23,
passes through the carry bit before being discarded. The LSB, bit 0, is filled with a zero.
Subsequent shifts cause additional zeroes to be shifted in.
Example 1
SLL A
Initialization: A contains 226A84H
Carry bit contains 0
Instruction:
Result:
SLL A
A contains 226A84H
This example uses one word of memory and executes in one machine cycle. All 24 bits of
the accumulator are shifted left through the carry bit, producing the result 44D508H.
Example 2
SLL <cc>, A
PS005600-TVC1299
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Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
Initialization: A contains 226A84H
Carry bit contains 0
Instruction:
Result:
SLL MI, A
A contains 226A84H
This example uses one word of memory and executes in one machine cycle. The condition
code Nis not set, and the instruction is not executed.
PS005600-TVC1299
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Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
SOPF
SET OVERFLOW PROTECTION FLAG
SOPF
Instruction Word
15 14 13 12 11 10
9
0
8
0
7
0
6
0
5
0
4
0
3
1
2
0
1
0
0
1
1
0
0
1
0
1
Op Code
Condition Code
Flag ModiÞcation
Syntax
SOPF
Operation
1 —> OP bit
Flags: None
Description
The Set Overflow Protection Flag instruction places a one in bit 8 of the status register. If
an ALU operation exceeds the limits of the processor, the overflow protection sets the
overflow flag (OV)and holds the limit value in the accumulator.
Example
SOPF
Initialization: SR contains 0000H
Instruction:
Result:
SOPF
SR contains 0100H
OP contains 1
This example uses one word of memory and executes in one machine cycle.
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Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
SRA
SHIFT RIGHT ARITHMETIC
SRA
Instruction Word
15 14 13 12 11 10
9
0
8
7
6
5
4
3
0
2
0
1
0
0
0
1
0
0
1
0
0
cc cc cc cc cc
Condition Code
Op Code
ACC ModiÞcation
Syntax
SRA A
SRA
<cc>, A
Operation
23 => 23 --- > ---- 0 => discarded
Flags: N
Set if result of accumulator is negative.
Set if result is 0.
Set if LSB is set before the shift.
Z
C
Description
All 24 bits of the accumulator are shifted right with sign extension through the carry bit.
The MSB, bit 23, is replicated in vacated bits. The LSB, bit 0, is passed through the carry
before it is discarded.
Example 1
SRA A
Initialization: A contains 226A84H
Carry bit contains 0
Instruction:
Result:
SRA A
A contains 113542H
Carry bit contains 0
This example uses one word of memory and executes in one machine cycle. All 24 bits of
the accumulator are shifted right. The MSB, bit 23, is copied into bit 22. The LSB, bit 0,
is discarded.
Example 2
SRA
<cc>, A
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170
Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
Initialization: A contains 226A84H
Carry bit contains0,N=0
Instruction:
Result:
SRA A
A contains 113542H
Carry bit contains 0
This example uses one word of memory and executes in one machine cycle. The condition
code is set; therefore, the instruction is executed. The initialization of the accumulator sets
the PL(NN) condition code.
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Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
SUB
SUBTRACT
SUB
Instruction Word
15 14 13 12 11 10
9
1
8
b
7
0
6
0
5
0
4
0
3
s
2
s
1
s
0
s
0
0
1
0
0
0
Op Code
RAM
Bank
Destination
Source
Syntax
SUB A, <regind>
SUB A, <memind>
SUB A, <limm>
SUB A, <hwregs>
SUB A, <direct>
SUB A, <pregs>
SUB A, <dregs>
SUB A, <simm>
Operation
ACC – (Source) —> ACC
Flags: C
Set if a carry from the most significant bit is
performed.
N
Z
Set if the result in the accumulator is negative.
Set if the result is 0.
OV
Set if the addition exceeds the upper (7FFFFFH)
or lower (800000H) limit of the accumulator.
Description
The addressed data memory operand is subtracted from the accumulator. The result is
loaded into the accumulator.
The lower eight bits of the accumulator are cleared by the execution of the subtract
instruction.
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Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
Example 1
SUB A, <regind>
Initialization: Accumulator contains 874600H
P0: 1 contains 45H
RAM Bank1: 45Hcontains 1234H
Instruction:
Result:
SUB A, @P0:1
A contains 751200H
@P0:1 contains 1234H
This example uses one word of memory and executes in one machine cycle. The contents
of the register pointed by P0:1are subtracted from the accumulator. The difference is
contained in the accumulator and the pointer is left unchanged. The register pointer
contains 45H. Because the pointer references RAM Bank1, the absolute register is 145H
(325). Therefore, the contents of register 145Hare subtracted from the accumulator.
874600H - 123400H = 751200H. The direct addressing equivalent is SUB
A,%145or SUB A,325.
Example 2
SUB A, <memind>
Initialization: Accumulator contains 874600H
P0:0 contains 21H
RAM Bank0: 21Hcontains 247AH
ROM Address: 247AHcontains 1234H
Instruction:
Result:
SUB A, @@P0:0+
A contains 751200H
P0:0 contains 22H
RAM Bank0: 21 Hcontains 247BH
This example uses one word of memory and executes in three machine cycles. The pointer
is used for memory indirect addressing. The pointer contains the address of the RAM
(address 247AH). The RAM contains the address of the requested ROM data (data
247AH). This operand is subtracted from the accumulator. 874600H - 123400H =
751200H.
Example 3
SUB A, <limm>
Initialization: Accumulator contains 874600H
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Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
Instruction:
Result:
SUB A, #%1234
Accumulator contains 751200H
This example uses two words of memory and executes in two machine cycles. The
immediate operand 8746His subtracted from the accumulator. 874600H - 123400H
= 751200H.
Example 4
SUB A, <hwregs>
Initialization: Accumulator contains 874600H
Register X contains 1234H
Instruction:
Result:
SUB A, X
A contains 751200H
This example uses one word of memory and executes in one machine cycle. The contents
of Register Xare subtracted from the accumulator. 874600H - 123400H =
751200H. Transfer from <hwregs> is possible from all hardware registers.
Example 5
SUB A, <direct>
Initialization: Accumulator contains 874600H
RAM Bank0: F3Hcontains 1234H
Instruction:
Result:
SUB A, %F3
A contains 751200H
This example uses one word of memory and executes in one machine cycle. The contents
of register F3Hare subtracted from the accumulator. 874600H - 123400H =
751200H. An equivalent instruction is SUB A, 243(F3H= 243 decimal).
Example 6
SUB A, <dregs>
Initialization: Accumulator contains 874600H
D0: 1 contains 1234H
Instruction:
Result:
SUB A, D0:1
A contains 751200H
D0:1 contains 1234H
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174
Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
This example uses one word of memory and executes in one machine cycle. The contents
of the data pointer D0:1are subtracted from the accumulator. The difference is contained
in the accumulator and the pointer is left unchanged.
Example 7
SUB A, <pregs>
Initialization: Accumulator contains 874600H
P0:0 contains 56H
Instruction:
Result:
SUB A, P0:0
Accumulator contains 86F000H
This example uses one word of memory and executes in one machine cycle. The contents
of pointer register P0:0are subtracted from the accumulator. 874600H - 005600H =
86F000H.The Pointer Register is connected to the lower 8 bits of the D-bus. The D-bus
is connected to the upper 16 bits of the P-bus. This causes the pointer register operand to
become 005600Hbefore it is subtracted from the accumulator.
PS005600-TVC1299
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Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
XOR
BITWISE EXCLUSIVE OR
XOR
Instruction Word
15 14 13 12 11 10
9
1
8
b
7
0
6
0
5
0
4
0
3
s
2
s
1
s
0
s
1
1
1
0
0
0
Op Code
RAM
Bank
Destination
Source
Syntax
XOR A, <regind>
XOR A, <memind>
XOR A, <limm>
XOR A, <hwregs>
XOR A, <direct>
XOR A, <pregs>
XOR A, <dregs>
XOR A, <simm>
Operation
A.XOR.<operand> —> A
Flags: C
Set if carry from the most significant bit is
performed.
N
Z
Set if result in the accumulator is negative.
Set if result is 0.
OV
Set if operation exceeds upper (7FFFFFH) or lower
(800000H) limit of accumulator.
Description
With the accumulator, perform an XORinstruction on the addressed data memory operand.
The result loads into the accumulator.
The lower eight bits of the accumulator are cleared by the XORinstruction.
Example 1
XOR A, <regind>
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Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
Initialization: Accumulator contains 005600H
P0:0 contains 00H
RAM Bank0: 00Hcontains 1234H
Instruction:
Result:
XOR A, @P0:0
A contains 126200H
This example uses one word of memory and executes in one machine cycle. The pointer is
used for memory indirect addressing. The pointer contains the address of the RAM
(address 00H). Location 00Hhas operand 1234H. With the accumulator, 005600H,
perform an XORinstruction to obtain the result 126200H.
Example 2
XOR A, <memind>
Initialization: A contains 3264A0H
P21 contains A4H
RAM Bank1: A4Hcontains 5463H
ROM Address: 5463Hcontains 1126H
Instruction:
Result
XOR A, @@P2:1
A contains 2342A0H
P2:1 contains A41H
RAM Bank1: A4Hcontains 5464H
SR contains 0000H
This example uses one word of memory and executes in three machine cycles. The pointer
P2:1contains the RAM register location(A4H). The contents of this register have a ROM
address. This address refers to the ROM data compared to the accumulator.
3264A0H.XOR.112600H = 2342A0H. When indirect memory addressing is used,
the ROM address is automatically incremented. Using XOR A, @@P2:1+performs the
same operation and also increments the P21content to A5H.
Example 3
XOR A, <limm>
Initialization: A contains 3264A0H
Instruction:
XOR A, #%1126
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Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
Result:
A contains 2342A0H
SR contains 0000H
This example uses two words of memory and executes in two machine cycles. Perform an
XORinstruction on the immediate data.
Example 4
XOR A, <hwreg>
Initialization: A contains 3264A0H
SR contains 0000H
BUS contains 1126H
Instruction:
Result:
XOR A, BUS
A contains 2342A0H
SR contains
This example uses one word of memory and executes in one machine cycle. With the
accumulator, perform an XORinstruction on the <hwreg> operand.
Example 5
XOR A, <direct>
Initialization: Accumulator contains 3264A0H
RAM Bank0: F3Hcontains 1126H
Instruction:
Result:
XOR A, %F3
A contains 2342A0H
SR contains 0000H
This example uses one word of memory and executes in one machine cycle. Register F3H
is compared to the accumulator. 3264A0H.XOR.112600H = 2342A0H.An
equivalent instruction is XOR A, 243(F3H= 243 decimal).
PS005600-TVC1299
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Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
5
Electrical Characteristics
Table 76
Parameter
Absolute Maximum and Minimum Ratings
Sym
Min
Max
Units
Conditions
V
V
V
V
V
Power supply voltage
Input voltage
0
7
V
V
CC
ID
IA
O
Ð0.3
Ð0.3
Ð0.3
Ð0.3
V
+0.3
Digital inputs
Analog inputs (A/D0ÐA/D4)
All push-pull digital outputs
PWM outputs
one pin
CC
CC
CC
CC
Input voltage
V
V
V
+0.3
+0.3
+0.3
V
Output voltage
V
Output voltage
V
O
I
I
I
I
Output current high
Output current high
Output current low
Output current low
Operating temperature
Storage temperature
Ð10
mA
mA
mA
mA
OH
Ð100
20
all pins
OH
OL
OL
one pin
200
70
all pins
o
T
0
C
A
o
T
Ð65
150
C
S
Table 77
Symbol Parameter
DC Characteristics
Min
Typ
Max
5.25
0.2 V
Units
Conditions
V
V
V
V
Power supply voltage
Input voltage low
4.75
0
5.00
0.4
3.6
4.2
V
V
V
V
CC
IL
CC
Input voltage high
0.7V
V
IH
CC
CC
Input voltage High on
Reset pin
0.75
V
IHR
CC
V
CC
V
Maximum pull-up
voltage
V
V
For PWM
PU
CC
V
V
Output voltage low
Output voltage high
0.16
4.75
0.4
V
V
@ I = 1 mA
OL
OL
V
Ð
@ I = Ð0.75 mA
OH
OH
CC
0.4
7.2
12
I
I
I
Output current low
Output current low
Output current high
12
20
mA
mA
mA
@ V = 0.4v
OL
OL
@ V = 0.8v
OL1
OH
OL
4.0
7.0
@ V = V Ð0.4
OH CC
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Preliminary
179
Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
Table 77
Symbol Parameter
DC Characteristics (Continued)
Min
Typ
Max
Units
Conditions
@ V = 2.4v
I
I
I
I
I
Output current high
Output current Low
Output current Low
Output current High
Output current High)
16
20
0.65
1.1
mA
mA
mA
mA
mA
V
OH1
OH
0.35
0.65
0.35
1.1
@ V = 0.4v
OL
OL
@ V = 0.8v
OL1
OH
OL
0.65
2.5
@ V = V Ð0.4
OH CC
@ V = 2.4V
OH1
OH
V
Input voltage XTAL1
low
0.3 V
External clock generator
driven
XL
CC
V
Input voltage XTAL1
high
0.6
V
XH
V
CC
I
I
I
Reset input current
Input leakage
25
Ð3.0
90
0.01
60
150
3.0
µA
µA
V
= 0V
RL
IR
@ 0V and V
IL
CC
Supply current
100
mA
All ports are inputs, RGB is in
digital mode
CC
I
Supply current
30
50
mA
All ports are inputs, RGB is in
analog mode
CC
I
I
Supply current
Supply current
5
10
mA
Sleep mode @ 32.768 KHz
CC1
50
100
µA
Stop mode all PWM outputs
CC2
are @ V = 0V
IN
5.1
DC Peripherals
Table 78
V1, V2, and V3 (R,G,B) Analog Output
Output Voltage (30KΩ Load)
Settling Time
@ V = 4.75V
@ V = 5.00V
@ V = 5.25V
70% of DC Level, 10pF
Load
CC
CC
CC
data = 00
data = 01
data = 10
data = 11
0.00VÐ0.65V
1.70VÐ0.20V
2.80VÐ0.25V
3.90VÐ0.30V
0.00VÐ0.70V
1.80VÐ0.20V
2.90VÐ0.25V
4.00VÐ0.30V
0.00VÐ0.75V
1.90VÐ0.20V
3.00VÐ0.25V
4.10VÐ0.30V
<50ns
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Preliminary
180
Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
Table 79
Sym Parameter
ADC0/Small Range*
Min
Typ
Max
Units
U
Clamping voltage at ADC0
Input voltage for level 0
Input voltage for level 1
Input voltage for level 2
Input voltage for level 3
Input voltage for level 4
Input voltage for level 5
Input voltage for level 6
Input voltage for level 7
Input voltage for level 8
Input voltage for level 9
Input voltage for level A
Input voltage for level B
Input voltage for level C
Input voltage for level D
Input voltage for level E
Input voltage for level F
1.0
1.5
2.0
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
RÐ
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
ADC
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
Ð(U +U )/15
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
U
+(U ÐU )/15
R+ RÐ
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
RÐ
RÐ
RÐ
RÐ
RÐ
RÐ
RÐ
RÐ
RÐ
RÐ
RÐ
RÐ
RÐ
RÐ
RÐ
R+
RÐ
RÐ
RÐ
RÐ
RÐ
RÐ
RÐ
RÐ
RÐ
RÐ
RÐ
RÐ
RÐ
RÐ
RÐ
RÐ
RÐ
RÐ
RÐ
RÐ
RÐ
RÐ
RÐ
RÐ
RÐ
RÐ
RÐ
RÐ
RÐ
RÐ
RÐ
+(U ÐU )/15
+2(U ÐU )/15
R+ RÐ
R+
RÐ
+(U ÐU )/15
+2(U ÐU )/15
+3(U ÐU )/15
R+ RÐ
R+
RÐ
R+
RÐ
+2(U ÐU )/15
+3(U ÐU )/15
+4(U ÐU )/15
R+ RÐ
R+
RÐ
R+
RÐ
+3(U ÐU )/15
+4(U ÐU )/15
+5(U ÐU )/15
R+ RÐ
R+
RÐ
R+
RÐ
+4(U ÐU )/15
+5(U ÐU )/15
+6(U ÐU )/15
R+ RÐ
R+
RÐ
R+
RÐ
+5(U ÐU )/15
+6(U ÐU )/15
+7(U ÐU )/15
R+ RÐ
R+
RÐ
R+
RÐ
+6(U ÐU )/15
+7(U ÐU )/15
+8(U ÐU )/15
R+ RÐ
R+
RÐ
R+
RÐ
+7(U ÐU )/15
+8(U ÐU )/15
+9(U ÐU )/15
R+ RÐ
R+
RÐ
R+
RÐ
+8(U ÐU )/15
+9(U ÐU )/15
+10(U ÐU )/15
R+ RÐ
R+
RÐ
R+
RÐ
+9(U ÐU )/15
+10(U ÐU )/15
+11(U ÐU )/15
R+ RÐ
R+
RÐ
R+
RÐ
+10(U ÐU )/15
+11(U ÐU )/15
+12(U ÐU )/15
R+ RÐ
R+
RÐ
R+
RÐ
+11(U ÐU )/15
+12(U ÐU )/15
+13(U ÐU )/15
R+ RÐ
R+
RÐ
R+
RÐ
+12(U ÐU )/15
+13(U ÐU )/15
+14(U ÐU )/15
R+ RÐ
R+
RÐ
R+
RÐ
+13(U ÐU )/15
+14(U ÐU )/15
+15(U ÐU )/15
R+ RÐ
R+
RÐ
R+
RÐ
ADC
U
+14(U ÐU )/15
U
U
+16(U ÐU )/15
RÐ R+ RÐ
F
RÐ
R+
RÐ
R+
R
Input impedance
1.0
MΩ
IN
Note: *The Input voltage level indicated in the table is a switch point from one ADC level to another. To be in the middle of
the level half, LSB ((U –U )/(15*2)) must be added. The Input voltage must be prorated accordingly if V is changed
R+
R–
CC
Note: 1.5–2.0V; TA = 0ºC to 70ºC; VCC = 4.75V to 5.25V
Table 80
ADC1-ADC4/Full range
Data
from
ADC
Input
voltage
(volts)
Data
from
ADC
Input
voltage
(volts)
Data
from
ADC
Input
voltage
(volts)
Data
from
ADC
Input
voltage
(volts)
0000
0001
0010
0011
0.000 ± 0.15
0.312 ± 0.15
0.625 ± 0.15
0.934 ± 0.15
0100
0101
0110
0111
1.250 ± 0.15
1.563 ± 0.15
1.875 ± 0.15
2.188 ± 0.15
1000
1001
1010
1011
2.500 ± 0.15
2.813 ± 0.15
3.125 ± 0.15
3.438 ± 0.15
> 1.0 MΩ
1100
1101
1110
1111
3.750 ± 0.15
4.063 ± 0.15
4.375 ± 0.15
4.688 ± 0.15
Input impedance
Note: 0-5.0V; Vcc = 5.0V; Temp=0-70C
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181
Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
5.2
AC Characteristics
Table 81 lists the AC characteristics.
Table 81
AC Characteristics
Sym
Parameter
Min
Typ
Max
Units
T
T
Input clock period
16
32
12
100
µS
ns
S
PC
, T
Clock input Rise and Fall
Power on reset delay
RC FC
TD
0.8
1.2
POR
TW
Power on reset minimum width
HSYNC incoming signal width
VSYNC incoming signal width
5 TPC
15
µS
µS
µS
µS
RES
HS
TD
TD
TD
1
1
10
200
0
10000
+12
VS
Time delay between leading edge of
VSYNC and HSYNC in EVEN Þeld
Ð12
ES
TD
Time delay between leading edge of
VSYNC and HSYNC in ODD Þeld
20
32
44
µS
µS
OS
TW
HSYNC/VSYNC edge width
0.5
2.0
HVS
2
2
Note: *All timing of the I C bus interface are defined by related specifications of the I C bus interface.
Note: T = 0˚C to 70˚C;V =4.75V to 5.25V;F =32,768Hz
A
CC
OSC
5.3
ANALOG RGB
The RGB outputs in analog mode are controlled current sources with an internal load.
These outputs display gamma-corrected, V prorated characteristics. See Table 82,
CC
Table 83, and Figure 29.
Table 82
RGB Voltage SpeciÞcation
Parameter
Min
Typical
Max
Units
Supply voltage
4.5
5.0
5.5
V
V
V
V
V
Full scale voltage
2/3 scale voltage
1/3 scale voltage
Zero scale voltage
1.8V
1.5V
1.125V
Ñ
2.00V (0.40 * V
1.65V (0.33 * V
1.25V (0.25 * V
0.00V (0.00 * V
)
)
)
)
2.2V
CC
CC
CC
CC
1.815V
1.375V
+0.1 V
PS005600-TVC1299
Preliminary
182
Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
Table 82
RGB Voltage SpeciÞcation (Continued)
Min Typical
Parameter
Max
Units
Note: *Measured with 3.9 kΩ load.
Table 83
RGB Time SpeciÞcation
Parameter
Min
Typical
Max
Units
Output rise time
Output fall time
50
50
65
65
ns
ns
Note: *Measured with 3.9 kΩ resistor in parallel with 30 pF capacitor load.
R1
R, G, B
R2
R1 + R2 = 3.9K
V
= 2 * R2/3.9
OUT
Figure 29 Recommended Application Schematics
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64 KWord Television Controller with OSD
6
SYSTEM DESIGN CONSIDERATIONS
The Z90376 provides the ability to
•
•
•
•
•
decode closed-caption transmissions
display characters on the screen
manipulate analog and digital control circuits
monitor keypad and infrared signals directly
generate OSD if the Z90376 receives vertical and horizontal synchronization signals
In a typical system, normal transmission is received and demodulated. The signals
received from the color decoder and deflection unit control the CRT display. To display
characters generated by the Z90376 requires a video multiplexor which enables the CRT
display’s RGB signals and synchronization to be controlled by the video outputs from the
processor. When the controller has to display a character on the screen, the multiplexor is
switched, and the processor’s video signals appear on the display.
The band-limited, A/C-coupled composite video signal is clamped internally to the
negative reference voltage (REF–) during the back porch interval. It is then passed to the
analog-to-digital converter through a 6:1 multiplexor. The digital signal is then decoded to
extract the closed-caption text embedded in the video signal. The characters received are
generated as video signals and are then passed to the display.
When a detectable composite video signal is received, the SYNC separator extracts the
horizontal and vertical synchronization signals and passes them to the deflection module
of the television. The FLYBACK signals from the deflection coils are fed back to the
Z90376. The controller uses these signals to align its video signals with those of the
normal display. If the composite video signal is not present, video synchronization is
provided by the controller. In this case, the SYNC signal pins are set to be outputs. The
pins then feed to the deflection unit which controls the display. The SYNC generators can
be configured to provide either HSYNC and VSYNC, or H-FLYBACK and V-FLYBACK.
Analog functions such as volume and color controls can be controlled by pulse width
modulated outputs from the Z90376. Additional digital controls like channel fine tuning
2
are controlled via the serial I C bus.
An infrared remote control receiver can be directly decoded through the capture register,
and keypad input can be scanned by directly controlling I/O pins as keyscan ports.
The processor clock is available by referencing an internal phase locked loop to an
external 32.768 KHz crystal oscillator. The oscillator minimizes EMI emissions from the
clock circuitry. The internal system clock frequency can be selected as 12.058 MHz in
normal operation or 32.768 KHz in low power consumption SLEEP mode (usually used if
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Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
there is a general system power failure). The Z90376’s STOP mode suspends processor
clocking for a power-down.
Program, display, and character graphics memory are on the chip, eliminating the
requirement for external memory components. Characters can be displayed as two or three
times normal size. Smoothing and fringing circuits enhance display appearance.
Figure 30 diagrams a typical application of the Z90376 Television Controller as an
embedded controller in a television.
L
FM Audio
Audio
R
RGB
Color
Decoder
RGB
RGB
output
stages
MUX
CRT
SYNC/
Flyback
Composite
Video
Television
Tuner, IF
H & V Deflection
VBlank
Deflection
Unit
OSD
SYNC/
Flyback
Tuning
Control
Control
I2C Bus
Z90376 Television Controller
Keypad
I/R
Detector
Figure 30 System Block Diagram
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Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
7
PACKAGING
Figure 31 and Table 84 indicate the controlling dimensions.
26
1
E1
27
52
D
Detail A
Q1
A2
A1
L
S
e
B
B1
Controlling dimension in inches
E
Optional end lead config
Detail A
C
eA
Figure 31 52-Pin SDIP Package Dimensions
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Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
Table 84
Controlling Dimensions
Millimeter
Inch
Symbol
Min
Max
Min
Max
A1
A2
B
0.51
3.25
0.38
0.89
0.23
Ñ
Ñ
0.020
0.128
0.015
0.035
0.009
Ñ
Ñ
3.94
0.53
1.14
0.38
47.50
15.75
14.10
0.155
0.021
0.045
0.015
1.870
0.620
0.555
B1
C
D
E
15.24
13.72
0.600
0.540
E1
1.778 TYP
0.070 TYP
e
eA
L
15.49
3.05
1.52
0.64
16.76
3.68
1.91
1.78
0.610
0.660
0.145
0.075
0.070
0.120
0.060
0.025
Q1
S
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Z90376 ROM and Z90371 OTP
64 KWord Television Controller with OSD
Customer Feedback Form
Z90376 Product SpeciÞcation
If there are any problems while operating this product, or any inaccuracies in the specification,
please copy and complete this form, then mail or fax it to ZiLOG. Suggestions welcome!
Customer Information
Name
Country
Phone
Fax
Company
Address
City/State/Zip
E-Mail
Product Information
Serial # or Board Fab #/Rev. #
Software Version
Document Number
Host Computer Description/Type
Return Information
ZiLOG
System Test/Customer Support
910 E. Hamilton Avenue, Suite 110, MS 4–3
Campbell, CA 95008
Fax: (408) 558-8536
Email: tools@zilog.com
Problem Description or Suggestion
Provide a complete description of the problem or suggestion. For specific problems,
include all steps leading up to the occurrence of the problem. Attach additional pages as
necessary.
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