ZGR323LAS2832C [ZILOG]
IC 8-BIT, OTPROM, 8 MHz, MICROCONTROLLER, PDSO28, SOIC-28, Microcontroller;
| 型号： | ZGR323LAS2832C |
| 厂家： | 
ZILOG, INC. |
| 描述： | IC 8-BIT, OTPROM, 8 MHz, MICROCONTROLLER, PDSO28, SOIC-28, Microcontroller 可编程只读存储器 微控制器 光电二极管 |
| 文件： | 总104页 (文件大小：1665K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TM
Z8 GP Microcontrollers
ZGR323L ROM MCU
Family
Product Specification
PS023904-0605
ZiLOG Worldwide Headquarters • 532 Race Street • San Jose, CA 95126-3432
Telephone: 408.558.8500 • Fax: 408.558.8300 • www.ZiLOG.com
This publication is subject to replacement by a later edition. To determine whether a later edition
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Telephone: 408.558.8500
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www.zilog.com
ZiLOG is a registered trademark of ZiLOG Inc. in the United States and in other countries. All other products and/or
service names mentioned herein may be trademarks of the companies with which they are associated.
Document Disclaimer
©2005 by ZiLOG, Inc. All rights reserved. Information in this publication concerning the devices, applications, or
technology described is intended to suggest possible uses and may be superseded. ZiLOG, INC. DOES NOT
ASSUME LIABILITY FOR OR PROVIDE A REPRESENTATION OF ACCURACY OF THE INFORMATION, DEVICES,
OR TECHNOLOGY DESCRIBED IN THIS DOCUMENT. ZiLOG ALSO DOES NOT ASSUME LIABILITY FOR
INTELLECTUAL PROPERTY INFRINGEMENT RELATED IN ANY MANNER TO USE OF INFORMATION, DEVICES,
OR TECHNOLOGY DESCRIBED HEREIN OR OTHERWISE. Devices sold by ZiLOG, Inc. are covered by warranty
and limitation of liability provisions appearing in the ZiLOG, Inc. Terms and Conditions of Sale. ZiLOG, Inc. makes no
warranty of merchantability or fitness for any purpose. Except with the express written approval of ZiLOG, use of
information, devices, or technology as critical components of life support systems is not authorized. No licenses are
conveyed, implicitly or otherwise, by this document under any intellectual property rights.
Disclaimer
PS023904-0605
ZGR323L
Product Specification
iii
Revision History
Each instance in the Revision History table reflects a change to this document
from its previous revision. To see more detail, click the appropriate link in the
table.
Revision
Page
Date
Level
Description
#
January
2005
02
Made minor change to Figure 50, bits D1 and D2.
74
Added characterization data, modified Tables 6 and and added two new 1,2,10,
tables 9 and 10 for the GR323LE and 323GRLA.
11,12,
13,14
Removed Preliminary designation
Minor change to Ordering Section
All
89
03
04
Deleted duplicate part numbers, added 4K part numbers, and changed
emulator/programmer part number in “Ordering Information” on page 87.
PS023904-0605
Revision History
ZGR323L
Product Specification
iv
Table of Contents
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii
Development Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Standard Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
XTAL1 Crystal 1 (Time-Based Input) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
XTAL2 Crystal 2 (Time-Based Output) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Port 0 (P07–P00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Port 1 (P17–P10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Port 2 (P27–P20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Port 3 (P37–P30) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
RESET (Input, Active Low) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Expanded Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Stack . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Counter/Timer Functional Blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Power-On Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Expanded Register File Control Registers (0D) . . . . . . . . . . . . . . . . . . . . . . . . 64
Expanded Register File Control Registers (0F) . . . . . . . . . . . . . . . . . . . . . . . . . 70
Standard Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
PS023904-0605
ZGR323L
Product Specification
vi
List of Figures
Figure 1. Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Figure 2. Counter/Timers Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Figure 3. 20-Pin PDIP/SOIC/SSOP Pin Configuration . . . . . . . . . . . . . . . . . . . 5
Figure 4. 28-Pin PDIP/SOIC/SSOP Pin Configuration . . . . . . . . . . . . . . . . . . . 6
Figure 5. 40-Pin PDIP Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Figure 6. 48-Pin SSOP Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Figure 7. Test Load Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Figure 8. AC Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure 9. Port 0 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure 10. Port 1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 11. Port 2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure 12. Port 3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure 13. Port 3 Counter/Timer Output Configuration . . . . . . . . . . . . . . . . . . . 23
Figure 14. Program Memory Map (32K OTP) . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 15. Expanded Register File Architecture . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 16. Register Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 17. Register Pointer—Detail . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure 18. Glitch Filter Circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 19. Transmit Mode Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Figure 20. 8-Bit Counter/Timer Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure 21. T8_OUT in Single-Pass Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 22. T8_OUT in Modulo-N Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Figure 23. Demodulation Mode Count Capture Flowchart . . . . . . . . . . . . . . . . 43
Figure 24. Demodulation Mode Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Figure 25. 16-Bit Counter/Timer Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Figure 26. T16_OUT in Single-Pass Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 27. T16_OUT in Modulo-N Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Figure 28. Ping-Pong Mode Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 29. Output Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Figure 30. Interrupt Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Figure 31. Oscillator Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Figure 32. Port Configuration Register (PCON) (Write Only) . . . . . . . . . . . . . . 54
Figure 33. STOP Mode Recovery Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 56
PS023904-0605
ZGR323L
Product Specification
vii
Figure 34. SCLK Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
Figure 35. Stop Mode Recovery Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Figure 36. Stop Mode Recovery Register 2 ((0F)DH:D2–D4,
D6 Write Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Figure 37. WATCH-DOG TIMER Mode Register (Write Only) . . . . . . . . . . . . . 61
Figure 38. Resets and WDT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Figure 39. TC8 Control Register ((0D)O0H: Read/Write
Except Where Noted) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Figure 40. T8 and T16 Common Control Functions ((0D)01H:
Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 41. T16 Control Register ((0D) 2H: Read/Write
Except Where Noted) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 42. T8/T16 Control Register (0D)03H: Read/Write
(Except Where Noted) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Figure 43. Voltage Detection Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
Figure 44. Port Configuration Register (PCON)(0F)00H: Write Only) . . . . . . . 71
Figure 45. Stop Mode Recovery Register ((0F)0BH: D6–D0=Write Only,
D7=Read Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Figure 46. Stop Mode Recovery Register 2 ((0F)0DH:D2–D4,
D6 Write Only) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Figure 47. Watch-Dog Timer Register ((0F) 0FH: Write Only) . . . . . . . . . . . . . 74
Figure 48. Port 2 Mode Register (F6H: Write Only) . . . . . . . . . . . . . . . . . . . . . 74
Figure 49. Port 3 Mode Register (F7H: Write Only) . . . . . . . . . . . . . . . . . . . . . 75
Figure 50. Port 0 and 1 Mode Register (F8H: Write Only) . . . . . . . . . . . . . . . . 76
Figure 51. Interrupt Priority Register (F9H: Write Only) . . . . . . . . . . . . . . . . . . 77
Figure 52. Interrupt Request Register (FAH: Read/Write) . . . . . . . . . . . . . . . . 78
Figure 53. Interrupt Mask Register (FBH: Read/Write) . . . . . . . . . . . . . . . . . . . 78
Figure 54. Flag Register (FCH: Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 55. Register Pointer (FDH: Read/Write) . . . . . . . . . . . . . . . . . . . . . . . . 79
Figure 56. Stack Pointer High (FEH: Read/Write) . . . . . . . . . . . . . . . . . . . . . . 80
Figure 57. Stack Pointer Low (FFH: Read/Write) . . . . . . . . . . . . . . . . . . . . . . . 80
Figure 58. 20-Pin PDIP Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 59. 20-Pin SOIC Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 60. 20-Pin SSOP Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 61. 28-Pin SOIC Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 62. 28-Pin PDIP Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84
Figure 63. 28-Pin SSOP Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
PS023904-0605
ZGR323L
Product Specification
viii
Figure 64. 40-Pin PDIP Package Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Figure 65. 48-Pin SSOP Package Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
PS023904-0605
ZGR323L
Product Specification
viii
List of Tables
Table 1. Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table 2. Power Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Table 3. 20-Pin PDIP/SOIC/SSOP Pin Identification . . . . . . . . . . . . . . . . . . . . 5
Table 4. 28-Pin PDIP/SOIC/SSOP Pin Identification . . . . . . . . . . . . . . . . . . . . 6
Table 5. 40- and 48-Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table 6. Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table 7. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 8. GR323LS DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Table 9. GR323LE DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table 10. GR323LA DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Table 11. AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table 12. Port 3 Pin Function Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 13. CTR0(D)00h Counter/Timer8 Control Register . . . . . . . . . . . . . . . . 32
Table 14. CTR1(0D)01h T8 and T16 Common Functions . . . . . . . . . . . . . . . . 34
Table 15. CTR2(D)02h: Counter/Timer16 Control Register . . . . . . . . . . . . . . 37
Table 16. CTR3 (D)03h: T8/T16 Control Register . . . . . . . . . . . . . . . . . . . . . . 38
Table 17. Interrupt Types, Sources, and Vectors . . . . . . . . . . . . . . . . . . . . . . 51
Table 18. IRQ Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
Table 19. SMR2(F)0Dh:Stop Mode Recovery Register 2* . . . . . . . . . . . . . . . 57
Table 20. Stop Mode Recovery Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
Table 21. Watch-Dog Timer Time Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 22. Selectable Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
PS023904-0605
ZGR323L
Product Specification
1
Development Features
Table 1 lists the features of ZiLOG®’s ZGR323L members.
Table 1. Features
Device
OTP(KB) RAM* (Bytes) I/O Lines Voltage Range
ZGR323L ROM MCU 8, 16, 32
237
32, 24 or 16
2.0V–3.6V
Note: *General purpose
•
•
Low power consumption–5mW (typical)
T = Temperature
S = Standard 0° to +70°C
E = Extended -40° to +105°C
A = Automotive -40° to +125°C
•
•
Three standby modes:
–
–
–
STOP—1.4µA (typical)
HALT—0.5mA (typical)
Low voltage reset
Special architecture to automate both generation and reception of complex pulses
or signals:
–
–
–
One programmable 8-bit counter/timer with two capture registers and two
load registers
One programmable 16-bit counter/timer with one 16-bit capture register
pair and one 16-bit load register pair
Programmable input glitch filter for pulse reception
•
Six priority interrupts
–
–
–
Three external
Two assigned to counter/timers
One low-voltage detection interrupt
•
•
•
•
Low voltage detection and high voltage detection flags
Programmable Watch-Dog Timer/Power-On Reset (WDT/POR) circuits
Two independent comparators with programmable interrupt polarity
Programmable EPROM options
–
Port 0: 0–3 pull-up transistors
–
Port 0: 4–7 pull-up transistors
PS023904-0605
Development Features
ZGR323L
Product Specification
2
–
–
–
–
Port 1: 0–3 pull-up transistors
Port 1: 4–7 pull-up transistors
Port 2: 0–7 pull-up transistors
WDT enabled at POR
General Description
The ZGR323L is an OTP-based member of the MCU family of infrared microcon-
trollers. With 237B of general-purpose RAM and 8KB to 32KB of OTP, ZiLOG®’s
CMOS microcontrollers offer fast-executing, efficient use of memory, sophisti-
cated interrupts, input/output bit manipulation capabilities, automated pulse gen-
eration/reception, and internal key-scan pull-up transistors.
The ZGR323L architecture (Figure 1) is based on ZiLOG’s 8-bit microcontroller
core with an Expanded Register File allowing access to register-mapped peripher-
als, input/output (I/O) circuits, and powerful counter/timer circuitry. The Z8 CPU
offers a flexible I/O scheme, an efficient register and address space structure, and
a number of ancillary features that are useful in many consumer, automotive,
computer peripheral, and battery-operated hand-held applications.
There are three basic address spaces available to support a wide range of config-
urations: Program Memory, Register File and Expanded Register File. The regis-
ter file is composed of 256 Bytes (B) of RAM. It includes 4 I/O port registers, 16
control and status registers, and 236 general-purpose registers. The Expanded
Register File consists of two additional register groups (F and D).
To unburden the program from coping with such real-time problems as generating
complex waveforms or receiving and demodulating complex waveform/pulses, the
ZGR323L offers a new intelligent counter/timer architecture with 8-bit and 16-bit
counter/timers (see Figure 2). Also included are a large number of user-selectable
modes and two on-board comparators to process analog signals with separate
reference voltages.
Note: All signals with an overline, “ ”, are active Low. For example,
B/W, in which WORD is active Low, and B/W, in which BYTE is
active Low.
Power connections use the conventional descriptions listed in Table 2.
Table 2. Power Connections
Connection
Power
Circuit
Device
V
V
V
CC
DD
SS
Ground
GND
PS023904-0605
General Description
ZGR323L
Product Specification
3
P00
P01
P02
P03
Register File
256 x 8-Bit
Pref1/P30
P31
4
4
P32
P33
I/O Nibble
Port 0
Port 1
Port 2
Port 3
P34
Programmable
P04
P05
P06
P07
Register Bus
P35
P36
P37
Internal
Address Bus
ROM
®
Z8Core
Up to 32K x 8
Internal
P10
P11
P12
P13
P14
P15
P16
P17
Data Bus
8
XTAL
I/O Byte
Programmable
Machine
Expanded
Register Bus
Timing &
RESET
Expanded
Instruction
Register
File
Control
P20
P21
P22
P23
P24
P25
P26
P27
V
DD
SS
Power
V
I/O Bit
Programmable
Power-On
Reset
Counter/Timer 16
16-Bit
High Voltage
Detection
Watch-Dog
Timer
Counter/Timer 8
8-Bit
2-Comparators
Low Voltage
Detection
Note: Refer to the specific package for available pins.
Figure 1. Functional Block Diagram
PS023904-0605
General Description
ZGR323L
Product Specification
4
HI16
8
LO16
8
16-Bit
T16
Timer 16
16
2
1
4 8
8
8
SCLK
Clock
TC16H
TC16L
Divider
And/Or
Logic
Timer 8/16
Timer 8
HI8
8
LO8
8
Edge
Input
Glitch
Filter
Detect
Circuit
8-Bit
T8
8
8
TC8H
TC8L
Figure 2. Counter/Timers Diagram
Pin Description
The pin configuration for the 20-pin PDIP/SOIC/SSOP is illustrated in Figure 3
and described in Table 3. The pin configuration for the 28-pin PDIP/SOIC/SSOP
are depicted in Figure 4 and described in Table 4. The pin configurations for the
40-pin PDIP and 48-pin SSOP versions are illustrated in Figure 5, Figure 6, and
described in Table 5.
PS023904-0605
Pin Description
ZGR323L
Product Specification
5
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
P25
P26
P24
P23
P27
P22
20-Pin
PDIP
SOIC
SSOP
P07
VDD
P21
P20
XTAL2
XTAL1
P31
VSS
P01
P00/Pref1/P30
P36
P32
P33
P34
Figure 3. 20-Pin PDIP/SOIC/SSOP Pin Configuration
Table 3. 20-Pin PDIP/SOIC/SSOP Pin Identification
Pin #
1–3
4
Symbol
P25–P27
P07
Function
Direction
Port 2, Bits 5,6,7
Port 0, Bit 7
Input/Output
Input/Output
5
V
Power Supply
DD
6
XTAL2
Crystal Oscillator Clock
Crystal Oscillator Clock
Port 3, Bits 1,2,3
Port 3, Bits 4,6
Output
Input
7
XTAL1
8–10
11,12
13
P31–P33
P34, P36
Input
Output
P00/Pref1/P30 Port 0, Bit 0/Analog reference input Input/Output for P00
Port 3 Bit 0
Input for Pref1/P30
Input/Output
14
P01
Port 0, Bit 1
Ground
15
V
SS
16–20
P20–P24
Port 2, Bits 0,1,2,3,4
Input/Output
PS023904-0605
Pin Description
ZGR323L
Product Specification
6
1
P25
P26
28
27
26
25
24
23
22
21
20
19
18
17
16
15
P24
2
P23
3
P27
P22
4
P04
P21
5
P05
P20
6
28-Pin
PDIP
P06
P03
7
P07
VSS
SOIC
SSOP
8
VDD
P02
9
XTAL2
XTAL1
P31
P01
10
11
12
13
14
P00
Pref1/P30
P36
P32
P33
P37
P35
P34
Figure 4. 28-Pin PDIP/SOIC/SSOP Pin Configuration
Table 4. 28-Pin PDIP/SOIC/SSOP Pin Identification
Pin
1-3
4-7
8
Symbol
P25-P27
P04-P07
Direction
Description
Input/Output Port 2, Bits 5, 6, 7
Input/Output Port 0, Bits 4, 5, 6, 7
Power supply
V
DD
9
XTAL2
XTAL1
P31-P33
P34
P35
P37
Output
Input
Input
Output
Output
Output
Output
Input
Crystal, oscillator clock
10
11-13
14
15
16
17
18
Crystal, oscillator clock
Port 3, Bits 1, 2, 3
Port 3, Bit 4
Port 3, Bit 5
Port 3, Bit 7
Port 3, Bit 6
Analog ref input; connect to V
Input for Pref1/P30
P36
Pref1/P30
if not used
CC
Port 3 Bit 0
19-21
22
P00-P02
Input/Output Port 0, Bits 0, 1, 2
Ground
V
SS
23
24-28
P03
P20-P24
Input/Output Port 0, Bit 3
Input/Output Port 2, Bits 0–4
PS023904-0605
Pin Description
ZGR323L
Product Specification
7
40
39
38
37
36
35
34
33
32
31
30
39
28
27
26
25
24
23
22
21
1
2
NC
P25
NC
P24
3
P26
P23
4
P27
P22
5
P04
P21
6
P05
P20
P06
7
P03
P14
8
P13
P15
9
P12
40-Pin
PDIP
P07
10
11
12
13
14
15
16
17
18
19
20
VSS
P02
VDD
P16
P11
P17
P10
XTAL2
XTAL1
P31
P01
P00
Pref1/P30
P36
P32
P33
P37
P34
P35
NC
RESET
Figure 5. 40-Pin PDIP Pin Configuration
PS023904-0605
Pin Description
ZGR323L
Product Specification
8
1
2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
NC
P25
P26
P27
P04
N/C
P05
P06
P14
P15
P07
VDD
VDD
N/C
NC
NC
3
P24
4
P23
5
P22
6
P21
7
P20
8
P03
P13
9
P12
10
11
12
13
14
15
16
17
18
19
20
21
VSS
VSS
N/C
48-Pin
SSOP
P02
P16
P17
XTAL2
XTAL1
P31
P32
P33
P34
NC
P11
P10
P01
P00
N/C
PREF1/P30
P36
P37
P35
RESET
22
23
24
VSS
Figure 6. 48-Pin SSOP Pin Configuration
Table 5. 40- and 48-Pin Configuration
40-Pin PDIP # 48-Pin SSOP # Symbol
26
27
30
34
5
6
7
10
28
29
32
31
32
35
41
5
7
8
11
33
34
39
P00
P01
P02
P03
P04
P05
P06
P07
P10
P11
P12
PS023904-0605
Pin Description
ZGR323L
Product Specification
9
Table 5. 40- and 48-Pin Configuration (Continued)
40-Pin PDIP # 48-Pin SSOP # Symbol
33
8
9
40
9
P13
P14
P15
P16
P17
P20
P21
P22
P23
P24
P25
P26
P27
P31
P32
P33
P34
P35
P36
P37
NC
10
15
16
42
43
44
45
46
2
12
13
35
36
37
38
39
2
3
4
3
4
16
17
18
19
22
24
23
20
40
1
19
20
21
22
26
28
27
23
47
1
NC
NC
21
15
14
11
31
25
25
18
17
12, 13
24, 37, 38
29
48
6
RESET
XTAL1
XTAL2
V
V
DD
SS
Pref1/P30
NC
NC
14
30
36
NC
NC
NC
PS023904-0605
Pin Description
ZGR323L
Product Specification
10
Absolute Maximum Ratings
Stresses greater than those listed in Table 7 might cause permanent damage to
the device. This rating is a stress rating only. Functional operation of the device at
any condition above those indicated in the operational sections of these specifica-
tions is not implied. Exposure to absolute maximum rating conditions for an
extended period might affect device reliability.
Table 6. Absolute Maximum Ratings
Parameter
Minimum Maximum Units
Notes
Ambient temperature under bias
Storage temperature
–40
–65
–0.3
–0.3
–5
+125
+150
+5.5
+3.6
+5
C
C
Voltage on any pin with respect to V
V
1
SS
Voltage on V pin with respect to V
V
DD
SS
Maximum current on input and/or inactive output pin
Maximum output current from active output pin
µA
mA
mA
–25
+25
75
Maximum current into V or out of V
DD
SS
Notes:
1. This voltage applies to all pins except the following: VDD, P32, P33 and RESET.
Standard Test Conditions
The characteristics listed in this product specification apply for standard test con-
ditions as noted. All voltages are referenced to GND. Positive current flows into
the referenced pin (see Figure 7).
From Output
Under Test
150pF
Figure 7. Test Load Diagram
PS023904-0605
Absolute Maximum Ratings
ZGR323L
Product Specification
11
Capacitance
Table 7 lists the capacitances.
Table 7. Capacitance
Parameter
Maximum
12pF
Input capacitance
Output capacitance
I/O capacitance
12pF
12pF
Note: TA = 25° C, VCC = GND = 0 V, f = 1.0 MHz, unmeasured pins returned to GND
DC Characteristics
Table 8. GR323LS DC Characteristics
TA= 0°C to +70°C
Symbol Parameter
VCC
Min
Typ(7)
Max Units Conditions
Notes
VCC
VCH
Supply Voltage
Clock Input High
Voltage
Clock Input Low
Voltage
2.0
0.8 VCC
3.6
VCC+0.3 V
V
See Notes
Driven by External
Clock Generator
Driven by External
Clock Generator
5
2.0-3.6
2.0-3.6
VCL
V
–0.3
SS
0.5
V
VIH
VIL
VOH1
VOH2
Input High Voltage
Input Low Voltage
Output High Voltage
Output High Voltage
(P36, P37, P00, P01)
2.0-3.6
2.0-3.6
2.0-3.6
2.0-3.6
0.7 VCC
VSS–0.3
VCC–0.4
VCC–0.8
VCC+0.3 V
0.2 VCC
V
V
V
IOH = –0.5mA
IOH = –7mA
VOL1
VOL2
Output Low Voltage
Output Low Voltage
(P00, P01, P36, P37)
2.0-3.6
2.0-3.6
0.4
0.8
V
V
IOL = 4.0mA
IOL = 10mA
VOFFSET Comparator Input
Offset Voltage
2.0-3.6
2.0-3.6
25
mV
V
VREF
Comparator
Reference
Voltage
0
VDD
-1.75
I
Input Leakage
2.0-3.6
–1
1
µA
V
= 0V, V
IL
IN CC
Pull-ups disabled
RPU
Pull-Up Resistance
2.0V
3.6V
2.0-3.6
2.0
3.6
225
75
–1
675
275
1
3
5
K Ω
K Ω
µA
mA
mA
VIN = 0V; Pullups selected by mask
option
I
I
Output Leakage
Supply Current
V
= 0V, V
OL
CC
IN CC
1.2
2.2
at 8.0 MHz
1, 2
1, 2
at 8.0 MHz
PS023904-0605
DC Characteristics
ZGR323L
Product Specification
12
Table 8. GR323LS DC Characteristics (Continued)
TA= 0°C to +70°C
Symbol Parameter
ICC1 Standby Current
(HALT Mode)
VCC
2.0
3.6
Min
Typ(7)
0.5
0.8
Max Units Conditions
Notes
1, 2, 6
1, 2, 6
1.6
mA
mA
VIN = 0V, V
at 8.0MHz
CC
2.0
Same as above
ICC2
Standby Current (Stop 2.0
1.5
2.1
4.7
7.4
8
µA
µA
µA
µA
V
= 0 V, V
WDT is not Running 3
IN
CC
Mode)
3.6
2.0
3.6
10
20
30
Same as above
3
3
3
VIN = 0 V, VCC WDT is Running
Same as above
ILV
Standby Current
(Low Voltage)
VCC Low Voltage
Protection
Vcc Low Voltage
Detection
Vcc High Voltage
Detection
1.0
1.8
2.4
2.7
6
µA
Measured at 1.3V
4
VBO
2.0
V
8MHz maximum
Ext. CLK Freq.
VLVD
VHVD
Notes:
V
V
1. All outputs unloaded, inputs at rail.
2. CL1 = CL2 = 100 pF.
3. Oscillator stopped.
4. Oscillator stops when VCC falls below VBO limit.
5. It is strongly recommended to add a filter capacitor (minimum 0.1µF), physically close to VDD and VSS pins if operating
voltage fluctuations are anticpated, such as those resulting from driving an infrared LED.
6. Comparator and Timers are on. Interrupt disabled.
7. Typical values shown are at 25 degrees C.
Table 9. GR323LE DC Characteristics
TA= –40°C to +105°C
Symbol Parameter
VCC
Min
Typ(7)
Max Units Conditions
Notes
VCC
VCH
Supply Voltage
Clock Input High
Voltage
Clock Input Low
Voltage
2.0
0.8 VCC
3.6
VCC+0.3 V
V
See Notes
Driven by External
Clock Generator
Driven by External
Clock Generator
5
2.0-3.6
2.0-3.6
VCL
V
–0.3
SS
0.5
V
VIH
VIL
VOH1
VOH2
Input High Voltage
Input Low Voltage
Output High Voltage
Output High Voltage
(P36, P37, P00, P01)
2.0-3.6
2.0-3.6
2.0-3.6
2.0-3.6
0.7 VCC
VSS–0.3
VCC–0.4
VCC–0.8
IOH = –0.5mA
IOH = –7mA
VOL1
VOL2
Output Low Voltage
Output Low Voltage
(P00, P01, P36, P37)
2.0-3.6
2.0-3.6
0.4
0.8
V
V
IOL = 4.0mA
IOL = 8mA
VOFFSET Comparator Input
Offset Voltage
2.0-3.6
25
mV
PS023904-0605
DC Characteristics
ZGR323L
Product Specification
13
Table 9. GR323LE DC Characteristics (Continued)
TA= –40°C to +105°C
Symbol Parameter
VCC
Min
Typ(7)
Max Units Conditions
Notes
VREF
Comparator
Reference
Voltage
2.0-3.6
0
VDD
-1.75
V
I
Input Leakage
2.0-3.6
–1
1
µA
V
= 0V, V
IL
IN CC
Pull-ups disabled
RPU
Pull-Up Resistance
2.0V
3.6V
2.0-3.6
2.0
3.6
2.0
3.6
200
50
–1
700
300
1
3
5
1.6
2.0
12
15
30
40
K Ω
K Ω
µA
mA
mA
mA
mA
µA
µA
µA
µA
VIN = 0V; Pullups selected by mask
option
I
I
Output Leakage
Supply Current
V
= 0V, V
OL
CC
IN
CC
CC
1.2
2.2
0.5
0.8
1.5
2.1
4.7
7.4
at 8.0 MHz
at 8.0 MHz
VIN = 0V, V
Same as above
1, 2
1, 2
1, 2, 6
1, 2, 6
ICC1
ICC2
Standby Current
(HALT Mode)
Standby Current (Stop 2.0
Mode)
at 8.0MHz
V
= 0 V, V
WDT is not Running 3
IN
CC
3.6
2.0
3.6
Same as above
3
3
3
VIN = 0 V, VCC WDT is Running
Same as above
ILV
Standby Current
(Low Voltage)
VCC Low Voltage
Protection
Vcc Low Voltage
Detection
Vcc High Voltage
Detection
1.0
1.8
2.4
2.7
6
µA
Measured at 1.3V
4
VBO
2.15
V
8MHz maximum
Ext. CLK Freq.
VLVD
VHVD
Notes:
V
V
1. All outputs unloaded, inputs at rail.
2. CL1 = CL2 = 100 pF.
3. Oscillator stopped.
4. Oscillator stops when VCC falls below VBO limit.
5. It is strongly recommended to add a filter capacitor (minimum 0.1µF), physically close to VDD and VSS pins if operating
voltage fluctuations are anticpated, such as those resulting from driving an infrared LED.
6. Comparator and Timers are on. Interrupt disabled.
7. Typical values shown are at 25 degrees C.
Table 10.GR323LA DC Characteristics
TA= –40°C to +125°C
Symbol Parameter
VCC
Min
Typ(7)
Max Units Conditions
Notes
VCC
VCH
Supply Voltage
Clock Input High
Voltage
Clock Input Low
Voltage
Input High Voltage
2.0
0.8 VCC
3.6
VCC+0.3 V
V
See Notes
Driven by External
Clock Generator
Driven by External
Clock Generator
5
2.0-3.6
2.0-3.6
2.0-3.6
VCL
VIH
V
–0.3
SS
0.5
V
0.7 VCC
VCC+0.3 V
PS023904-0605
DC Characteristics
ZGR323L
Product Specification
14
Table 10.GR323LA DC Characteristics (Continued)
TA= –40°C to +125°C
Symbol Parameter
VCC
Min
Typ(7)
Max Units Conditions
Notes
VIL
VOH1
VOH2
Input Low Voltage
Output High Voltage
Output High Voltage
(P36, P37, P00, P01)
2.0-3.6
2.0-3.6
2.0-3.6
VSS–0.3
VCC–0.4
VCC–0.8
0.2 VCC
V
V
V
IOH = –0.5mA
IOH = –7mA
VOL1
VOL2
Output Low Voltage
Output Low Voltage
(P00, P01, P36, P37)
2.0-3.6
2.0-3.6
0.4
0.8
V
V
IOL = 4.0mA
IOL = 8mA
VOFFSET Comparator Input
Offset Voltage
2.0-3.6
2.0-3.6
25
mV
V
VREF
Comparator
Reference
Voltage
0
VDD
-1.75
I
Input Leakage
2.0-3.6
–1
1
µA
V
= 0V, V
IL
IN CC
Pull-ups disabled
RPU
Pull-Up Resistance
2.0V
3.6V
2.0-3.6
2.0
3.6
2.0
3.6
200
50
–1
700
300
1
3
5
1.6
2.0
15
20
30
40
K Ω
K Ω
µA
mA
mA
mA
mA
µA
µA
µA
µA
VIN = 0V; Pullups selected by mask
option
I
I
Output Leakage
Supply Current
V
= 0V, V
OL
CC
IN
CC
CC
1.2
2.2
0.5
0.8
1.5
2.1
4.7
7.4
at 8.0 MHz
at 8.0 MHz
VIN = 0V, V
Same as above
1, 2
1, 2
1, 2, 6
1, 2, 6
ICC1
ICC2
Standby Current
(HALT Mode)
Standby Current (Stop 2.0
Mode)
at 8.0MHz
V
= 0 V, V
WDT is not Running 3
IN
CC
3.6
2.0
3.6
Same as above
3
3
3
VIN = 0 V, VCC WDT is Running
Same as above
ILV
Standby Current
(Low Voltage)
VCC Low Voltage
Protection
Vcc Low Voltage
Detection
Vcc High Voltage
Detection
1.0
1.8
2.4
2.7
6
µA
Measured at 1.3V
4
VBO
2.15
V
8MHz maximum
Ext. CLK Freq.
VLVD
VHVD
Notes:
V
V
1. All outputs unloaded, inputs at rail.
2. CL1 = CL2 = 100 pF.
3. Oscillator stopped.
4. Oscillator stops when VCC falls below VBO limit.
5. It is strongly recommended to add a filter capacitor (minimum 0.1µF), physically close to VDD and VSS pins if operating
voltage fluctuations are anticpated, such as those resulting from driving an infrared LED.
6. Comparator and Timers are on. Interrupt disabled.
7. Typical values shown are at 25 degrees C.
PS023904-0605
DC Characteristics
ZGR323L
Product Specification
15
AC Characteristics
Figure 8 and Table 11 describe the Alternating Current (AC) characteristics.
1
3
Clock
2
2
3
7
4
7
T
IN
5
6
IRQ
N
8
9
Clock
Setup
11
Stop
Mode
Recovery
Source
10
Figure 8. AC Timing Diagram
PS023904-0605
AC Characteristics
ZGR323L
Product Specification
16
Table 11. AC Characteristics
T =0°C to +70°C (S)
A
Watch-Dog
Timer
–40°C to +105°C (E)
–40°C to +125°C (A)
8.0MHz
Mode
Register
No Symbol
Parameter
V
Minimum Maximum Units Notes (D1, D0)
CC
1
2
TpC
Input Clock Period
2.0–3.6
121
DC
25
ns
ns
1
1
TrC,TfC
Clock Input Rise and 2.0–3.6
Fall Times
3
4
TwC
Input Clock Width
2.0–3.6
37
ns
ns
1
1
TwTinL
Timer Input
Low Width
2.0
3.6
100
70
5
TwTinH
Timer Input High
Width
2.0–3.6
3TpC
1
6
7
TpTin
Timer Input Period
2.0–3.6
8TpC
1
1
TrTin,TfTin Timer Input Rise and 2.0–3.6
Fall Timers
100
ns
ns
8
9
TwIL
Interrupt Request
Low Time
2.0
3.6
100
70
1, 2
1, 2
3
TwIH
Interrupt Request
Input High Time
2.0–3.6
5TpC
10 Twsm
Stop-Mode
Recovery Width
Spec
2.0–3.6
12
ns
10TpC
4
4
11 Tost
12 Twdt
Oscillator
2.0–3.6
5TpC
10
Start-Up Time
Watch-Dog Timer
Delay Time
2.0–3.6
2.0–3.6
2.0–3.6
2.0–3.6
5
ms
ms
ms
ms
0, 0
0, 1
1, 0
1, 1
10
20
80
13 T
Power-On Reset
2.0–3.6
2.5
ms
POR
Notes:
1. Timing Reference uses 0.9 V for a logic 1 and 0.1 V for a logic 0.
CC
CC
2. Interrupt request through Port 3 (P33–P31).
3. SMR – D5 = 1.
4. SMR – D5 = 0.
PS023904-0605
AC Characteristics
ZGR323L
Product Specification
17
Pin Functions
XTAL1 Crystal 1 (Time-Based Input)
This pin connects a parallel-resonant crystal or ceramic resonator to the on-chip
oscillator input. Additionally, an optional external single-phase clock can be coded
to the on-chip oscillator input.
XTAL2 Crystal 2 (Time-Based Output)
This pin connects a parallel-resonant crystal or ceramic resonant to the on-chip
oscillator output.
Port 0 (P07–P00)
Port 0 is an 8-bit, bidirectional, CMOS-compatible port. These eight I/O lines are
configured under software control as a nibble I/O port. The output drivers are
push-pull or open-drain controlled by bit D2 in the PCON register.
If one or both nibbles are needed for I/O operation, they must be configured by
writing to the Port 01 mode register (P01M). After a hardware reset or Stop Mode
recovery, Port 0 is configured as an input port.
An optional pull-up transistor is available as a OTP option bit on all Port 0 bits with
nibble select.
Notes: Internal pull-ups are disabled on any given pin or group of port
pins when programmed into output mode.
The Port 0 direction is reset to be input following an SMR.
PS023904-0605
Pin Functions
ZGR323L
Product Specification
18
4
4
Port 0 (I/O)
Z8 OTP
V
CC
OTP Programming
Option
Open-Drain
I/O
Resistive
Transistor
Pull-up
Pad
Out
In
Figure 9. Port 0 Configuration
Port 1 (P17–P10)
Port 1 (see Figure 10) Port 1 can be configured for standard port input or output
mode. After POR or stop mode recovery, Port 1 is configured as an input port. The
output drivers are either push-pull or open-drain and are controlled by bit D1 in the
PCON register.
Note:
The Port 1 direction is reset to be input following an SMR.
PS023904-0605
Pin Functions
ZGR323L
Product Specification
19
Z8 OTP
8
Port 1 (I/O)
V
CC
OTP Programming
Option
Open-Drain
OEN
Resistive
Transistor
Pull-up
Pad
Out
In
Figure 10. Port 1 Configuration
Port 2 (P27–P20)
Port 2 is an 8-bit, bidirectional, CMOS-compatible I/O port (see Figure 11). These
eight I/O lines can be independently configured under software control as inputs
or outputs. Port 2 is always available for I/O operation. A EPROM option bit is
available to connect eight pull-up transistors on this port. Bits programmed as out-
puts are globally programmed as either push-pull or open-drain. The POR resets
with the eight bits of Port 2 configured as inputs.
Port 2 also has an 8-bit input OR and AND gate, which can be used to wake up
the part. P20 can be programmed to access the edge-detection circuitry in
demodulation mode.
PS023904-0605
Pin Functions
ZGR323L
Product Specification
20
Port 2 (I/O)
Z8 OTP
V
CC
OTP Programming
Option
Open-Drain
I/O
Resistive
Transistor
Pull-up
Pad
Out
In
Figure 11. Port 2 Configuration
Port 3 (P37–P30)
Port 3 is a 8-bit, CMOS-compatible fixed I/O port (see Figure 12). Port 3 consists
of four fixed input (P33–P30) and four fixed output (P37–P34), which can be con-
figured under software control for interrupt and as output from the counter/timers.
P30, P31, P32, and P33 are standard CMOS inputs; P34, P35, P36, and P37 are
push-pull outputs.
PS023904-0605
Pin Functions
ZGR323L
Product Specification
21
Pref1/P30
P31
P32
P33
Port 3 (I/O)
Z8 OTP
P34
P35
P36
P37
R247 = P3M
1 = Analog
0 = Digital
D1
Dig.
An.
P31 (AN1)
Pref1
IRQ2, P31 Data Latch
IRQ0, P32 Data Latch
Comp1
Comp2
+
-
P32 (AN2)
+
-
P33 (REF2)
IRQ1, P33 Data Latch
From Stop Mode Recovery Source of SMR
Figure 12. Port 3 Configuration
Two on-board comparators process analog signals on P31 and P32, with refer-
ence to the voltage on Pref1 and P33. The analog function is enabled by program-
ming the Port 3 Mode Register (bit 1). P31 and P32 are programmable as rising,
falling, or both edge triggered interrupts (IRQ register bits 6 and 7). Pref1 and P33
are the comparator reference voltage inputs. Access to the Counter Timer edge-
detection circuit is through P31 or P20 (see “T8 and T16 Common Functions—
PS023904-0605
Pin Functions
ZGR323L
Product Specification
22
CTR1(0D)01h” on page 34). Other edge detect and IRQ modes are described in
Table 12.
Note:
Comparators are powered down by entering Stop Mode. For
P31–P33 to be used in a Stop Mode Recovery (SMR) source,
these inputs must be placed into digital mode.
2
Table 12.Port 3 Pin Function Summary
Pin
I/O
Counter/Timers Comparator Interrupt
Pref1/P30 IN
RF1
P31
P32
P33
P34
P35
P36
P37
P20
IN
IN
AN1
AN2
RF2
AO1
IRQ2
IRQ0
IRQ1
IN
IN
OUT
OUT
OUT
OUT
I/O
T8
T16
T8/16
AO2
IN
Port 3 also provides output for each of the counter/timers and the AND/OR Logic
(see Figure 13). Control is performed by programming bits D5–D4 of CTR1, bit 0
of CTR0, and bit 0 of CTR2.
PS023904-0605
Pin Functions
ZGR323L
Product Specification
23
CTR0, D0
MUX
PCON, D0
MUX
P34 data
T8_Out
V
DD
Pad
P34
P3M D1
Comp1
P31
P31
+
-
P30 (Pref1)
CTR2, D0
MUX
V
DD
Out 35
T16_Out
Pad
P35
CTR1, D6
MUX
V
DD
Out 36
T8/T16_Out
Pad
P36
PCON, D0
MUX
V
DD
P37 data
P3M D1
Pad
P37
P32
P32
P33
+
-
Comp2
Figure 13. Port 3 Counter/Timer Output Configuration
PS023904-0605
Pin Functions
ZGR323L
Product Specification
24
Comparator Inputs
In analog mode, P31 and P32 have a comparator front end. The comparator refer-
ence is supplied to P33 and Pref1. In this mode, the P33 internal data latch and its
corresponding IRQ1 are diverted to the SMR sources (excluding P31, P32, and
P33) as indicated in Figure 12 on page 21. In digital mode, P33 is used as D3 of
the Port 3 input register, which then generates IRQ1.
Note: Comparators are powered down by entering Stop Mode. For
P31–P33 to be used in a Stop Mode Recovery source, these
inputs must be placed into digital mode.
Comparator Outputs
These channels can be programmed to be output on P34 and P37 through the
PCON register.
RESET (Input, Active Low)
Reset initializes the MCU and is accomplished either through Power-On, Watch-
Dog Timer, Stop Mode Recovery, Low-Voltage detection, or external reset. During
Power-On Reset and Watch-Dog Timer Reset, the internally generated reset
drives the reset pin Low for the POR time. Any devices driving the external reset
line must be open-drain to avoid damage from a possible conflict during reset con-
ditions. Pull-up is provided internally.
When the Z8 GP ROM MCU asserts (Low) the RESET pin, the internal pull-up is
disabled. The Z8 GP ROM MCU does not assert the RESET pin when under
VBO.
Note:
The external Reset does not initiate an exit from STOP mode.
Functional Description
This device incorporates special functions to enhance the Z8®’ functionality in
consumer and battery-operated applications.
Program Memory
This device addresses up to 32KB of OTP memory. The first 12 Bytes are
reserved for interrupt vectors. These locations contain the six 16-bit vectors that
correspond to the six available interrupts. See Figure 14.
RAM
This device features 256B of RAM.
PS023904-0605
Functional Description
ZGR323L
Product Specification
25
Not Accessible
Location of
first Byte of
instruction
executed
32768
On-Chip
ROM
after RESET
Reset Start Address
IRQ5
12
11
IRQ5
IRQ4
10
9
IRQ4
8
7
IRQ3
IRQ3
Interrupt Vector
(Lower Byte)
6
5
4
IRQ2
IRQ2
IRQ1
Interrupt Vector
(Upper Byte)
3
2
1
IRQ1
IRQ0
IRQ0
0
Figure 14. Program Memory Map (32K OTP)
Expanded Register File
The register file has been expanded to allow for additional system control regis-
ters and for mapping of additional peripheral devices into the register address
area. The Z8 register address space (R0 through R15) has been implemented
as 16 banks, with 16 registers per bank. These register groups are known as the
PS023904-0605
Functional Description
ZGR323L
Product Specification
26
ERF (Expanded Register File). Bits 7–4 of register RP select the working register
group. Bits 3–0 of register RP select the expanded register file bank.
Note: An expanded register bank is also referred to as an expanded
register group (see Figure 15).
PS023904-0605
Functional Description
ZGR323L
Product Specification
27
Reset Condition
®
Z8 Standard Control Registers
D7 D6 D5 D4 D3 D2 D1 D0
Expanded Reg. Bank 0/Group 15**
FF
FE
FD
FC
FB
FA
F9
F8
F7
F6
F5
F4
F3
F2
F1
F0
SPL
SPH
RP
FLAGS
IMR
IRQ
IPR
P01M
P3M
U
U
0
U
U
0
U
1
0
1
U
U
U
U
U
U
U
U
0
U
U
0
U
1
0
1
U
U
U
U
U
U
U
U
0
U
U
0
U
0
0
1
U
U
U
U
U
U
U
U
0
U
U
0
U
0
0
1
U
U
U
U
U
U
U
U
0
U
U
0
U
1
0
1
U
U
U
U
U
U
U
U
0
U
U
0
U
1
0
1
U
U
U
U
U
U
U
U
0
U
U
0
U
1
0
1
U
U
U
U
U
U
U
U
0
U
U
0
U
1
0
1
U
U
U
U
U
U
Register Pointer
7
6 5 4 3 2 1 0
Working Register
Group Pointer
Expanded Register
Bank Pointer
*
*
P2M
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Register File (Bank 0)**
FF
F0
Expanded Reg. Bank F/Group 0**
(F) 0F WDTMR
(F) 0E Reserved
(F) 0D SMR2
*
U
0
U
0
0
0
0
0
1
0
1
0
0
0
1
0
*
(F) 0C Reserved
(F) 0B SMR
U
0 1 0 0 0 U 0
↑
7F
(F) 0A Reserved
(F) 09 Reserved
(F) 08 Reserved
(F) 07 Reserved
(F) 06 Reserved
(F) 05 Reserved
(F) 04 Reserved
(F) 03 Reserved
(F) 02 Reserved
(F) 01 Reserved
(F) 00 PCON
0F
00
*
1
1 1 1 1 1 1 0
Expanded Reg. Bank 0/Group (0)
Expanded Reg. Bank D/Group 0
(0) 03 P3
(0) 02 P2
(0) 01 P1
(0) 00 P0
0
U
(D) 0C
(D) 0B
(D) 0A
(D) 09
(D) 08
(D) 07
(D) 06
(D) 05
(D) 04
LVD
HI8
LO8
HI16
LO16
TC16H
TC16L
TC8H
TC8L
U
0
0
0
0
0
0
U
0
0
0
0
0
0
U
0
0
0
0
0
0
U
0
0
0
0
0
0
U
0
0
0
0
0
0
U
0
0
0
0
0
0
U
0
0
0
0
0
0
0
0
0
0
0
0
0
U
U
*
*
*
*
*
*
*
U
U = Unknown
* Is not reset with a Stop-Mode Recovery
** All addresses are in hexadecimal
↑ Is not reset with a Stop-Mode Recovery, except Bit 0
↑↑ Bit 5 Is not reset with a Stop-Mode Recovery
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
1
0
0
1
0
0
1
*
*
(D) 03 CTR3
↑↑
↑↑↑
0
0
0
0
0
0
0
0
(D) 02
(D) 01
(D) 00
CTR2
CTR1
CTR0
↑↑↑ Bits 5,4,3,2 not reset with a Stop-Mode Recovery
↑↑↑↑ Bits 5 and 4 not reset with a Stop-Mode Recovery
↑↑↑↑↑ Bits 5,4,3,2,1 not reset with a Stop-Mode Recovery
↑↑↑↑
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
↑↑↑↑↑
Figure 15. Expanded Register File Architecture
PS023904-0605
Functional Description
ZGR323L
Product Specification
28
The upper nibble of the register pointer (see Figure 16) selects which working reg-
ister group, of 16 bytes in the register file, is accessed out of the possible 256. The
lower nibble selects the expanded register file bank and, in the case of the Z8 GP
ROM MCU family, banks 0, F, and D are implemented. A 0hin the lower nibble
allows the normal register file (bank 0) to be addressed. Any other value from 1h
to Fhexchanges the lower 16 registers to an expanded register bank.
R253 RP
D7 D6 D5 D4 D3 D2 D1 D0
Expanded Register
File Pointer
Working Register
Pointer
Default Setting After Reset = 0000 0000
Figure 16. Register Pointer
Example: Z8 GP ROM MCU: (See Figure 15 on page 27)
R253 RP = 00h
R0 = Port 0
R1 = Port 1
R2 = Port 2
R3 = Port 3
But if:
R253 RP = 0Dh
R0 = CTR0
R1 = CTR1
R2 = CTR2
R3 = CTR3
PS023904-0605
Functional Description
ZGR323L
Product Specification
29
The counter/timers are mapped into ERF group D. Access is easily performed
using the following:
LD
RP, #0Dh
; Select ERF D
; (working
for access to bank D
register group 0)
LD
LD
LD
R0,#xx
1, #xx
R1, 2
; load CTR0
; load CTR1
; CTR2→CTR1
LD
RP, #0Dh
; Select ERF D
; (working
for access to bank D
register group 0)
LD
RP, #7Dh
; Select
expanded register bank D and working
group 7 of bank 0 for access.
; register
LD
71h, 2
; CTRL2→register 71h
LD
R1, 2
; CTRL2→register 71h
Register File
The register file (bank 0) consists of 4 I/O port registers, 237 general-purpose reg-
isters, 16 control and status registers (R0–R3, R4–R239, and R240–R255,
respectively), and two expanded registers groups in Banks D (see Table 13) and
F. Instructions can access registers directly or indirectly through an 8-bit address
field, thereby allowing a short, 4-bit register address to use the Register Pointer
(Figure 17). In the 4-bit mode, the register file is divided into 16 working register
groups, each occupying 16 continuous locations. The Register Pointer addresses
the starting location of the active working register group.
Note:
Working register group E0–EF can only be accessed through
working registers and indirect addressing modes.
PS023904-0605
Functional Description
ZGR323L
Product Specification
30
R253
R
R7 R6 R5 R4 R3 R2 R1
The upper nibble of the register file address
provided by the register pointer specifies the
active working-register group.
FF
F0
EF
E0
DF
D0
The lower nibble of the
40
3F
register file address provided
by the instruction points to
the specified register.
Specified Working
Register Group
30
2F
Register Group 2
20
1F
R15 to R0
R15 to R4 *
R3 to R0 *
Register Group 1
10
0F
Register Group 0
I/O Ports
00
* RP = 00: Selects Register Bank 0, Working Register Group 0
Figure 17. Register Pointer—Detail
Stack
The internal register file is used for the stack. An 8-bit Stack Pointer SPL (R255) is
used for the internal stack that resides in the general-purpose registers (R4–
R239). SPH (R254) can be used as a general-purpose register.
PS023904-0605
Functional Description
ZGR323L
Product Specification
31
Timers
T8_Capture_HI—HI8(D)0Bh
This register holds the captured data from the output of the 8-bit Counter/Timer0.
Typically, this register holds the number of counts when the input signal is 1.
Field
Bit Position
Description
T8_Capture_HI [7:0]
R/W Captured Data - No Effect
T8_Capture_LO—L08(D)0Ah
This register holds the captured data from the output of the 8-bit Counter/Timer0.
Typically, this register holds the number of counts when the input signal is 0.
Field
Bit Position
Description
T8_Capture_L0 [7:0]
R/W Captured Data - No Effect
T16_Capture_HI—HI16(D)09h
This register holds the captured data from the output of the 16-bit Counter/
Timer16. This register holds the MS-Byte of the data.
Field
Bit Position
Description
T16_Capture_HI [7:0]
R/W Captured Data - No Effect
T16_Capture_LO—L016(D)08h
This register holds the captured data from the output of the 16-bit Counter/
Timer16. This register holds the LS-Byte of the data.
Field
Bit Position
Description
T16_Capture_LO [7:0]
R/W Captured Data - No Effect
Counter/Timer2 MS-Byte Hold Register—TC16H(D)07h
Field
Bit Position
Description
R/W Data
T16_Data_HI
[7:0]
PS023904-0605
Functional Description
ZGR323L
Product Specification
32
Counter/Timer2 LS-Byte Hold Register—TC16L(D)06h
Field
Bit Position
Description
R/W Data
T16_Data_LO
[7:0]
Counter/Timer8 High Hold Register—TC8H(D)05h
Field
Bit Position
Description
R/W Data
T8_Level_HI
[7:0]
Counter/Timer8 Low Hold Register—TC8L(D)04h
Field
Bit Position
Description
R/W Data
T8_Level_LO
[7:0]
CTR0 Counter/Timer8 Control Register—CTR0(D)00h
Table 13 lists and briefly describes the fields for this register.
Table 13.CTR0(D)00h Counter/Timer8 Control Register
Field
Bit Position
Value
Description
T8_Enable
7-------
R/W
0*
1
Counter Disabled
Counter Enabled
Stop Counter
0
1
Enable Counter
Single/Modulo-N
Time_Out
-6-------
--5------
R/W
R/W
0*
1
Modulo-N
Single Pass
0**
1
No Counter Time-Out
Counter Time-Out Occurred
No Effect
0
1
Reset Flag to 0
T8 _Clock
---43---
-----2--
R/W
R/W
0 0**
0 1
SCLK
SCLK/2
SCLK/4
SCLK/8
1 0
1 1
Capture_INT_Mask
0**
1
Disable Data Capture Interrupt
Enable Data Capture Interrupt
PS023904-0605
Functional Description
ZGR323L
Product Specification
33
Table 13.CTR0(D)00h Counter/Timer8 Control Register (Continued)
Field
Bit Position
Value
Description
Counter_INT_Mask
------1-
R/W
R/W
0**
1
Disable Time-Out Interrupt
Enable Time-Out Interrupt
P34_Out
-------0
0*
1
P34 as Port Output
T8 Output on P34
Note:
*
Indicates the value upon Power-On Reset.
*
* Indicates the value upon Power -On Reset. Not reset with a Stop Mode recovery.
T8 Enable
This field enables T8 when set (written) to 1.
Single/Modulo-N
When set to 0 (Modulo-N), the counter reloads the initial value when the terminal
count is reached. When set to 1 (single-pass), the counter stops when the termi-
nal count is reached.
Timeout
This bit is set when T8 times out (terminal count reached). To reset this bit, write a
1 to its location.
Caution: Writing a 1 is the only way to reset the Terminal Count
status condition. Reset this bit before using/enabling the
counter/timers.
The first clock of T8 might not have complete clock width
and can occur any time when enabled.
Note: Take care when using the OR or AND commands to manipulate
CTR0, bit 5 and CTR1, bits 0 and 1 (Demodulation Mode).
These instructions use a Read-Modify-Write sequence in which
the current status from the CTR0 and CTR1 registers is ORed
or ANDed with the designated value and then written back into
the registers.
T8 Clock
These bits define the frequency of the input signal to T8.
PS023904-0605
Functional Description
ZGR323L
Product Specification
34
Capture_INT_Mask
Set this bit to allow an interrupt when data is captured into either LO8 or HI8 upon
a positive or negative edge detection in demodulation mode.
Counter_INT_Mask
Set this bit to allow an interrupt when T8 has a timeout.
P34_Out
This bit defines whether P34 is used as a normal output pin or the T8 output.
T8 and T16 Common Functions—CTR1(0D)01h
This register controls the functions in common with the T8 and T16.
Table 14 lists and briefly describes the fields for this register.
Table 14.CTR1(0D)01h T8 and T16 Common Functions
Field
Bit Position
Value
Description
Mode
7-------
R/W
R/W
0*
Transmit Mode
1
Demodulation Mode
P36_Out/
-6------
Transmit Mode
Port Output
T8/T16 Output
Demodulation Mode
P31
Demodulator_Input
0*
1
0*
1
P20
T8/T16_Logic/
Edge _Detect
--54----
R/W
Transmit Mode
00**
01
AND
OR
10
NOR
11
NAND
Demodulation Mode
Falling Edge
Rising Edge
Both Edges
Reserved
00**
01
10
11
PS023904-0605
Functional Description
ZGR323L
Product Specification
35
Table 14.CTR1(0D)01h T8 and T16 Common Functions (Continued)
Field
Bit Position
----32--
Value
Description
Transmit_Submode/
R/W
Transmit Mode
Normal Operation
Ping-Pong Mode
T16_Out = 0
Glitch_Filter
00*
01
10
11
T16_Out = 1
Demodulation Mode
No Filter
00*
01
10
11
4 SCLK Cycle
8 SCLK Cycle
Reserved
Initial_T8_Out/
Rising Edge
------1-
-------0
Transmit Mode
R/W
0*
1
T8_OUT is 0 Initially
T8_OUT is 1 Initially
Demodulation Mode
No Rising Edge
R
0*
1
Rising Edge Detected
No Effect
W
0
1
Reset Flag to 0
Initial_T16_Out/
Falling_Edge
Transmit Mode
R/W
0*
1
T16_OUT is 0 Initially
T16_OUT is 1 Initially
Demodulation Mode
No Falling Edge
R
0*
1
Falling Edge Detected
No Effect
W
0
1
Reset Flag to 0
Note:
*Default at Power-On Reset
**Default at Power-On Reset. Not reset with a Stop Mode recovery.
Mode
If the result is 0, the counter/timers are in TRANSMIT mode; otherwise, they are in
DEMODULATION mode.
P36_Out/Demodulator_Input
In TRANSMIT Mode, this bit defines whether P36 is used as a normal output pin
or the combined output of T8 and T16.
In DEMODULATION Mode, this bit defines whether the input signal to the
Counter/Timers is from P20 or P31.
If the input signal is from Port 31, a capture event may also generate an IRQ2
interrupt. To prevent generating an IRQ2, either disable the IRQ2 interrupt by
clearing its IMR bit D2 or use P20 as the input.
PS023904-0605
Functional Description
ZGR323L
Product Specification
36
T8/T16_Logic/Edge _Detect
In TRANSMIT Mode, this field defines how the outputs of T8 and T16 are com-
bined (AND, OR, NOR, NAND).
In DEMODULATION Mode, this field defines which edge should be detected by
the edge detector.
Transmit_Submode/Glitch Filter
In Transmit Mode, this field defines whether T8 and T16 are in the PING-PONG
mode or in independent normal operation mode. Setting this field to “NORMAL
OPERATION Mode” terminates the “PING-PONG Mode” operation. When set to
10, T16 is immediately forced to a 0; a setting of 11 forces T16 to output a 1.
In DEMODULATION Mode, this field defines the width of the glitch that must be fil-
tered out.
Initial_T8_Out/Rising_Edge
In TRANSMIT Mode, if 0, the output of T8 is set to 0 when it starts to count. If 1,
the output of T8 is set to 1 when it starts to count. When the counter is not enabled
and this bit is set to 1 or 0, T8_OUT is set to the opposite state of this bit. This
ensures that when the clock is enabled, a transition occurs to the initial state set
by CTR1, D1.
In DEMODULATION Mode, this bit is set to 1 when a rising edge is detected in the
input signal. In order to reset the mode, a 1 should be written to this location.
Initial_T16 Out/Falling _Edge
In TRANSMIT Mode, if it is 0, the output of T16 is set to 0 when it starts to count. If
it is 1, the output of T16 is set to 1 when it starts to count. This bit is effective only
in Normal or PING-PONG Mode (CTR1, D3; D2). When the counter is not enabled
and this bit is set, T16_OUT is set to the opposite state of this bit. This ensures
that when the clock is enabled, a transition occurs to the initial state set by CTR1,
D0.
In DEMODULATION Mode, this bit is set to 1 when a falling edge is detected in
the input signal. In order to reset it, a 1 should be written to this location.
Note: Modifying CTR1 (D1 or D0) while the counters are enabled
causes unpredictable output from T8/16_OUT.
CTR2 Counter/Timer 16 Control Register—CTR2(D)02h
Table 15 lists and briefly describes the fields for this register.
PS023904-0605
Functional Description
ZGR323L
Product Specification
37
Table 15.CTR2(D)02h: Counter/Timer16 Control Register
Field
Bit Position
Value
Description
T16_Enable
7-------
R
0*
1
Counter Disabled
Counter Enabled
Stop Counter
W
0
1
Enable Counter
Single/Modulo-N
-6------
R/W
Transmit Mode
Modulo-N
0*
1
Single Pass
Demodulation Mode
T16 Recognizes Edge
T16 Does Not Recognize
Edge
0
1
Time_Out
--5-----
---43---
R
0*
1
No Counter Timeout
Counter Timeout
Occurred
W
0
1
No Effect
Reset Flag to 0
T16 _Clock
R/W
00**
01
SCLK
SCLK/2
SCLK/4
SCLK/8
10
11
Capture_INT_Mask
Counter_INT_Mask
P35_Out
-----2--
------1-
-------0
R/W
R/W
R/W
0**
1
Disable Data Capture Int.
Enable Data Capture Int.
0
1
Disable Timeout Int.
Enable Timeout Int.
0*
1
P35 as Port Output
T16 Output on P35
Note:
*Indicates the value upon Power-On Reset.
**Indicates the value upon Power-On Reset. Not reset with a Stop Mode recovery.
T16_Enable
This field enables T16 when set to 1.
Single/Modulo-N
In TRANSMIT Mode, when set to 0, the counter reloads the initial value when it
reaches the terminal count. When set to 1, the counter stops when the terminal
count is reached.
PS023904-0605
Functional Description
ZGR323L
Product Specification
38
In Demodulation Mode, when set to 0, T16 captures and reloads on detection of
all the edges. When set to 1, T16 captures and detects on the first edge but
ignores the subsequent edges. For details, see the description of T16 Demodula-
tion Mode on page 46.
Time_Out
This bit is set when T16 times out (terminal count reached). To reset the bit, write
a 1 to this location.
T16_Clock
This bit defines the frequency of the input signal to Counter/Timer16.
Capture_INT_Mask
This bit is set to allow an interrupt when data is captured into LO16 and HI16.
Counter_INT_Mask
Set this bit to allow an interrupt when T16 times out.
P35_Out
This bit defines whether P35 is used as a normal output pin or T16 output.
CTR3 T8/T16 Control Register—CTR3(D)03h
Table 16 lists and briefly describes the fields for this register. This register allows
the T8 and T16 counters to be synchronized.
Table 16.CTR3 (D)03h: T8/T16 Control Register
Field
Enable
Bit Position
Value
Description
T
7-------
R
0*
1
Counter Disabled
Counter Enabled
Stop Counter
16
R
W
W
0
1
Enable Counter
T Enable
-6------
--5-----
R
0*
1
Counter Disabled
Counter Enabled
Stop Counter
8
R
W
W
0
1
Enable Counter
Sync Mode
R/W
0**
1
Disable Sync Mode
Enable Sync Mode
PS023904-0605
Functional Description
ZGR323L
Product Specification
39
Table 16.CTR3 (D)03h: T8/T16 Control Register (Continued)
Field
Bit Position
Value
Description
Reserved
---43210
R
1
x
Always reads 11111
W
No Effect
Note: *Indicates the value upon Power-On Reset.
**Indicates the value upon Power-On Reset. Not reset with a Stop Mode recovery.
Counter/Timer Functional Blocks
Input Circuit
The edge detector monitors the input signal on P31 or P20. Based on CTR1 D5–
D4, a pulse is generated at the Pos Edge or Neg Edge line when an edge is
detected. Glitches in the input signal that have a width less than specified (CTR1
D3, D2) are filtered out (see Figure 18).
CTR1
D5,D4
Pos
P31
P20
Edge
MUX
Glitch
Filter
Edge
Neg
Detector
Edge
CTR1
CTR1
D6
D3, D2
Figure 18. Glitch Filter Circuitry
T8 Transmit Mode
Before T8 is enabled, the output of T8 depends on CTR1, D1. If it is 0, T8_OUT is
1; if it is 1, T8_OUT is 0. See Figure 19.
PS023904-0605
Functional Description
ZGR323L
Product Specification
40
T8 (8-Bit)
Transmit Mode
No
T8_Enable Bit Set
CTR0, D7
Yes
Reset T8_Enable Bit
1
0
CTR1, D1
Value
Load TC8H
Set T8_OUT
Load TC8L
Reset T8_OUT
Set Timeout Status Bit
(CTR0 D5) and Generate
Timeout_Int if Enabled
Enable T8
No
T8_Timeout
Yes
Single Pass
Single
Pass?
Modulo-N
1
0
T8_OUT Value
Load TC8L
Load TC8H
Set T8_OUT
Reset T8_OUT
Enable T8
Set Timeout Status Bit
(CTR0 D5) and Generate
Timeout_Int if Enabled
No
T8_Timeout
Yes
Figure 19. Transmit Mode Flowchart
PS023904-0605
Functional Description
ZGR323L
Product Specification
41
When T8 is enabled, the output T8_OUT switches to the initial value (CTR1, D1).
If the initial value (CTR1, D1) is 0, TC8L is loaded; otherwise, TC8H is loaded into
the counter. In SINGLE-PASS Mode (CTR0, D6), T8 counts down to 0 and stops,
T8_OUT toggles, the timeout status bit (CTR0, D5) is set, and a timeout interrupt
can be generated if it is enabled (CTR0, D1). In Modulo-N Mode, upon reaching
terminal count, T8_OUT is toggled, but no interrupt is generated. From that point,
T8 loads a new count (if the T8_OUT level now is 0), TC8L is loaded; if it is 1,
TC8H is loaded. T8 counts down to 0, toggles T8_OUT, and sets the timeout sta-
tus bit (CTR0, D5), thereby generating an interrupt if enabled (CTR0, D1). One
cycle is thus completed. T8 then loads from TC8H or TC8L according to the
T8_OUT level and repeats the cycle. See Figure 20.
®
CTR0 D2
Z8 Data Bus
Positive Edge
Negative Edge
IRQ4
HI8
LO8
CTR0 D1
CTR0 D4, D3
SCLK
Clock
Clock
Select
8-Bit
Counter T8
T8_OUT
TC8H
TC8L
®
Z8 Data Bus
Figure 20. 8-Bit Counter/Timer Circuits
You can modify the values in TC8H or TC8L at any time. The new values take
effect when they are loaded.
Caution: To ensure known operation do not write these registers at
the time the values are to be loaded into the counter/timer.
An initial count of 1 is not allowed (a non-function occurs). An
initial count of 0 causes TC8 to count from 0 to FFhto FEh.
PS023904-0605
Functional Description
ZGR323L
Product Specification
42
The letter hdenotes hexadecimal values.
Note:
Transition from 0 to FFhis not a timeout condition.
Caution: Using the same instructions for stopping the counter/timers
and setting the status bits is not recommended.
Two successive commands are necessary. First, the counter/timers must be
stopped. Second, the status bits must be reset. These commands are required
because it takes one counter/timer clock interval for the initiated event to actually
occur. See Figure 21 and Figure 22.
TC8H
Counts
Counter Enable Command;
T8_OUT Switches to Its
Initial Value (CTR1 D1)
T8_OUT Toggles;
Timeout Interrupt
Figure 21. T8_OUT in Single-Pass Mode
T8_OUT Toggles
. . .
T8_OUT
TC8L
TC8H
TC8L
TC8H
TC8L
Counter Enable Command;
T8_OUT Switches to Its
Initial Value (CTR1 D1)
Timeout
Interrupt
Timeout
Interrupt
Figure 22. T8_OUT in Modulo-N Mode
T8 Demodulation Mode
The user must program TC8L and TC8H to FFh. After T8 is enabled, when the first
edge (rising, falling, or both depending on CTR1, D5; D4) is detected, it starts to
count down. When a subsequent edge (rising, falling, or both depending on
CTR1, D5; D4) is detected during counting, the current value of T8 is comple-
mented and put into one of the capture registers. If it is a positive edge, data is put
PS023904-0605
Functional Description
ZGR323L
Product Specification
43
into LO8; if it is a negative edge, data is put into HI8. From that point, one of the
edge detect status bits (CTR1, D1; D0) is set, and an interrupt can be generated if
enabled (CTR0, D2). Meanwhile, T8 is loaded with FFhand starts counting again.
If T8 reaches 0, the timeout status bit (CTR0, D5) is set, and an interrupt can be
generated if enabled (CTR0, D1). T8 then continues counting from FFh(see
Figure 23 and Figure 24).
T8 (8-Bit)
Count Capture
T8 Enable
(Set by User)
Yes
No
No
Edge Present
Yes
What Kind
of Edge
Positive
Negative
T8 LO8
T8 HI8
FFhT8
Figure 23. Demodulation Mode Count Capture Flowchart
PS023904-0605
Functional Description
ZGR323L
Product Specification
44
T8 (8-Bit)
Demodulation Mode
T8 Enable
CTR0, D7
No
No
Yes
FFh→ TC8
First
Edge Present
Yes
Enable TC8
Disable TC8
T8_Enable
Bit Set
No
Yes
No
Edge Present
Yes
No
T8 Timeout
Yes
Set Edge Present Status
Bit and Trigger Data
Capture Int. If Enabled
Set Timeout Status
Bit and Trigger
Timeout Int. If Enabled
Continue Counting
Figure 24. Demodulation Mode Flowchart
PS023904-0605
Functional Description
ZGR323L
Product Specification
45
T16 Transmit Mode
In NORMAL or PING-PONG mode, the output of T16 when not enabled, is depen-
dent on CTR1, D0. If it is a 0, T16_OUT is a 1; if it is a 1, T16_OUT is 0. You can
force the output of T16 to either a 0 or 1 whether it is enabled or not by program-
ming CTR1 D3; D2 to a 10 or 11.
When T16 is enabled, TC16H * 256 + TC16L is loaded, and T16_OUT is switched
to its initial value (CTR1, D0). When T16 counts down to 0, T16_OUT is toggled
(in NORMAL or PING-PONG mode), an interrupt (CTR2, D1) is generated (if
enabled), and a status bit (CTR2, D5) is set. See Figure 25.
®
CTR2 D2
Z8 Data Bus
Positive Edge
Negative Edge
IRQ3
HI16
LO16
CTR2 D1
CTR2 D4, D3
SCLK
Clock
Clock
16-Bit
Select
Counter T16
T16_OUT
TC16H
TC16L
®
Z8 Data Bus
Figure 25. 16-Bit Counter/Timer Circuits
Note: Global interrupts override this function as described in
“Interrupts” on page 49.
If T16 is in SINGLE-PASS mode, it is stopped at this point (see Figure 26). If it is
in Modulo-N Mode, it is loaded with TC16H * 256 + TC16L, and the counting con-
tinues (see Figure 27).
You can modify the values in TC16H and TC16L at any time. The new values take
effect when they are loaded.
PS023904-0605
Functional Description
ZGR323L
Product Specification
46
Do not load these registers at the time the values are to be
Caution:
loaded into the counter/timer to ensure known operation.
An initial count of 1 is not allowed. An initial count of 0
causes T16 to count from 0 to FFFFhto FFFEh. Transition
from 0 to FFFFhis not a timeout condition.
TC16H*256+TC16L Counts
“Counter Enable” Command
T16_OUT Toggles,
Timeout Interrupt
T16_OUT Switches to Its
Initial Value (CTR1 D0)
Figure 26. T16_OUT in Single-Pass Mode
TC16H*256+TC16L
TC16H*256+TC16L
. . .
TC16_OUT
TC16H*256+TC16L
“Counter Enable” Command,
T16_OUT Toggles,
Timeout Interrupt
T16_OUT Toggles,
Timeout Interrupt
T16_OUT Switches to Its
Initial Value (CTR1 D0)
Figure 27. T16_OUT in Modulo-N Mode
T16 DEMODULATION Mode
The user must program TC16L and TC16H to FFh. After T16 is enabled, and the
first edge (rising, falling, or both depending on CTR1 D5; D4) is detected, T16
captures HI16 and LO16, reloads, and begins counting.
If D6 of CTR2 Is 0
When a subsequent edge (rising, falling, or both depending on CTR1, D5; D4) is
detected during counting, the current count in T16 is complemented and put into
HI16 and LO16. When data is captured, one of the edge detect status bits (CTR1,
D1; D0) is set, and an interrupt is generated if enabled (CTR2, D2). T16 is loaded
with FFFFhand starts again.
This T16 mode is generally used to measure space time, the length of time
between bursts of carrier signal (marks).
PS023904-0605
Functional Description
ZGR323L
Product Specification
47
If D6 of CTR2 Is 1
T16 ignores the subsequent edges in the input signal and continues counting
down. A timeout of T8 causes T16 to capture its current value and generate an
interrupt if enabled (CTR2, D2). In this case, T16 does not reload and continues
counting. If the D6 bit of CTR2 is toggled (by writing a 0 then a 1 to it), T16 cap-
tures and reloads on the next edge (rising, falling, or both depending on CTR1,
D5; D4), continuing to ignore subsequent edges.
This T16 mode generally measures mark time, the length of an active carrier sig-
nal burst.
If T16 reaches 0, T16 continues counting from FFFFh. Meanwhile, a status bit
(CTR2 D5) is set, and an interrupt timeout can be generated if enabled (CTR2
D1).
Ping-Pong Mode
This operation mode is only valid in TRANSMIT Mode. T8 and T16 must be pro-
grammed in Single-Pass mode (CTR0, D6; CTR2, D6), and Ping-Pong mode
must be programmed in CTR1, D3; D2. The user can begin the operation by
enabling either T8 or T16 (CTR0, D7 or CTR2, D7). For example, if T8 is enabled,
T8_OUT is set to this initial value (CTR1, D1). According to T8_OUT's level,
TC8H or TC8L is loaded into T8. After the terminal count is reached, T8 is dis-
abled, and T16 is enabled. T16_OUT then switches to its initial value (CTR1, D0),
data from TC16H and TC16L is loaded, and T16 starts to count. After T16 reaches
the terminal count, it stops, T8 is enabled again, repeating the entire cycle. Inter-
rupts can be allowed when T8 or T16 reaches terminal control (CTR0, D1; CTR2,
D1). To stop the ping-pong operation, write 00 to bits D3 and D2 of CTR1. See
Figure 28.
Note: Enabling ping-pong operation while the counter/timers are
running might cause intermittent counter/timer function. Disable
the counter/timers and reset the status flags before instituting
this operation.
PS023904-0605
Functional Description
ZGR323L
Product Specification
48
Enable
Enable
TC8
Timeout
Ping-Pong
CTR1 D3,D2
TC16
Timeout
Figure 28. Ping-Pong Mode Diagram
Initiating PING-PONG Mode
First, make sure both counter/timers are not running. Set T8 into Single-Pass
mode (CTR0, D6), set T16 into SINGLE-PASS mode (CTR2, D6), and set the
Ping-Pong mode (CTR1, D2; D3). These instructions can be in random order.
Finally, start PING-PONG mode by enabling either T8 (CTR0, D7) or T16 (CTR2,
D7). See Figure 28.
P34_Internal
MUX
P34
CTR0 D0
MUX
P36_Internal
P35_Internal
T8_OUT
MUX
P36
P35
AND/OR/NOR/NAND
Logic
T16_OUT
CTR1, D2
CTR1 D6
MUX
CTR1 D5, D4
CTR1 D3
CTR2 D0
Figure 29. Output Circuit
The initial value of T8 or T16 must not be 1. If you stop the timer and restart the
timer, reload the initial value to avoid an unknown previous value.
PS023904-0605
Functional Description
ZGR323L
Product Specification
49
During PING-PONG Mode
The enable bits of T8 and T16 (CTR0, D7; CTR2, D7) are set and cleared alter-
nately by hardware. The timeout bits (CTR0, D5; CTR2, D5) are set every time the
counter/timers reach the terminal count.
Timer Output
The output logic for the timers is illustrated in Figure 29. P34 is used to output T8-
OUT when D0 of CTR0 is set. P35 is used to output the value of TI6-OUT when
D0 of CTR2 is set. When D6 of CTR1 is set, P36 outputs the logic combination of
T8-OUT and T16-OUT determined by D5 and D4 of CTR1.
Interrupts
The Z8 GP ROM MCU features six different interrupts (Table 17). The interrupts
are maskable and prioritized (Figure 30). The six sources are divided as follows:
three sources are claimed by Port 3 lines P33–P31, two by the counter/timers
(Table 17) and one for low voltage detection. The Interrupt Mask Register (globally
or individually) enables or disables the six interrupt requests.
The source for IRQ is determined by bit 1 of the Port 3 mode register (P3M).
When in digital mode, Pin P33 is the source. When in analog mode the output of
the Stop mode recovery source logic is used as the source for the interrupt. See
Figure 35, Stop Mode Recovery Source, on page 58.
PS023904-0605
Functional Description
ZGR323L
Product Specification
50
Stop Mode Recovery Source
P33
0
1
D1 of P3M Register
P31
P32
IRQ Register
D6, D7
Low-Voltage
Detection
Interrupt Edge
Select
Timer 8
Timer 16
IRQ1 IRQ3
IRQ2
IRQ0
IRQ4
IRQ5
IRQ
IMR
IPR
5
Global
Interrupt
Enable
Interrupt
Request
Priority
Logic
Vector Select
Figure 30. Interrupt Block Diagram
PS023904-0605
Functional Description
ZGR323L
Product Specification
51
Table 17.Interrupt Types, Sources, and Vectors
Name
IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
Source Vector Location Comments
P32
P33
P31, T
T16
T8
0,1
External (P32), Rising, Falling Edge Triggered
2,3
External (P33), Falling Edge Triggered
4,5
External (P31), Rising, Falling Edge Triggered
IN
6,7
Internal
Internal
Internal
8,9
LVD
10,11
When more than one interrupt is pending, priorities are resolved by a programma-
ble priority encoder controlled by the Interrupt Priority Register. An interrupt
machine cycle activates when an interrupt request is granted. As a result, all sub-
sequent interrupts are disabled, and the Program Counter and Status Flags are
saved. The cycle then branches to the program memory vector location reserved
for that interrupt. All Z8 GP ROM MCU interrupts are vectored through locations in
the program memory. This memory location and the next byte contain the 16-bit
address of the interrupt service routine for that particular interrupt request. To
accommodate polled interrupt systems, interrupt inputs are masked, and the Inter-
rupt Request register is polled to determine which of the interrupt requests require
service.
An interrupt resulting from AN1 is mapped into IRQ2, and an interrupt from AN2 is
mapped into IRQ0. Interrupts IRQ2 and IRQ0 can be rising, falling, or both edge
triggered. These interrupts are programmable by the user. The software can poll
to identify the state of the pin.
Programming bits for the Interrupt Edge Select are located in the IRQ Register
(R250), bits D7 and D6. The configuration is indicated in Table 18.
Table 18.IRQ Register
IRQ
D6
Interrupt Edge
IRQ2 (P31) IRQ0 (P32)
D7
0
0
1
0
1
F
F
0
F
R
1
R
F
1
R/F
R/F
Note: F = Falling Edge; R = Rising Edge
PS023904-0605
Functional Description
ZGR323L
Product Specification
52
Clock
The device’s on-chip oscillator has a high-gain, parallel-resonant amplifier, for
connection to a crystal, ceramic resonator, or any suitable external clock source
(XTAL1 = Input, XTAL2 = Output). The crystal must be AT cut, 1 MHz to 8 MHz
maximum, with a series resistance (RS) less than or equal to 100 Ω. The on-chip
oscillator can be driven with a suitable external clock source.
The crystal must be connected across XTAL1 and XTAL2 using the recommended
capacitors (capacitance greater than or equal to 22 pF) from each pin to ground.
XTAL1
XTAL1
C1
C2
XTAL2
XTAL2
Crystal
External Clock
C1, C2 =33pF TYP*
f = 8 MHz
XTAL1
XTAL2
* Preliminary value including pin parasitics
Ceramic Resonator
f = 8 MHz
Figure 31. Oscillator Configuration
Power-On Reset
A timer circuit clocked by a dedicated on-board RC-oscillator is used for the
Power-On Reset (POR) timer function. The POR time allows VDD and the oscilla-
tor circuit to stabilize before instruction execution begins.
The POR timer circuit is a one-shot timer triggered by one of three conditions:
•
•
•
Power Fail to Power OK status, including Waking up from VBO Standby
Stop-Mode Recovery (if D5 of SMR = 1)
WDT Timeout
PS023904-0605
Functional Description
ZGR323L
Product Specification
53
The POR timer is 2.5 ms minimum. Bit 5 of the Stop-Mode Register determines
whether the POR timer is bypassed after Stop-Mode Recovery (typical for external
clock).
HALT Mode
This instruction turns off the internal CPU clock, but not the XTAL oscillation. The
counter/timers and external interrupts IRQ0, IRQ1, IRQ2, IRQ3, IRQ4, and IRQ5
remain active. The devices are recovered by interrupts, either externally or inter-
nally generated. An interrupt request must be executed (enabled) to exit HALT
Mode. After the interrupt service routine, the program continues from the instruc-
tion after HALT Mode.
STOP Mode
This instruction turns off the internal clock and external crystal oscillation, reduc-
ing the standby current to 10 µA or less. STOP Mode is terminated only by a
reset, such as WDT timeout, POR or SMR. This condition causes the processor to
restart the application program at address 000Ch. To enter STOP (or HALT) mode,
first flush the instruction pipeline to avoid suspending execution in mid-instruction.
Execute a NOP (Opcode = FFh) immediately before the appropriate sleep instruc-
tion, as follows:
PS023904-0605
Functional Description
ZGR323L
Product Specification
54
FF
6F
NOP
STOP
; clear the pipeline
; enter Stop Mode
or
FF
7F
NOP
HALT
; clear the pipeline
; enter HALT Mode
Port Configuration Register
The Port Configuration (PCON) register (Figure 32) configures the comparator
output on Port 3. It is located in the expanded register 2 at Bank F, location 00.
PCON(FH)00h
D7 D6 D5 D4 D3 D2 D1 D0
Comparator Output Port 3
0 P34, P37 Standard Output*
1 P34, P37 Comparator Output
Port 1
0: Open-Drain
1: Push-Pull*
Port 0
0: Open-Drain
1: Push-Pull*
Reserved (Must be 1)
* Default setting after reset
Figure 32. Port Configuration Register (PCON) (Write Only)
Comparator Output Port 3 (D0)
Bit 0 controls the comparator used in Port 3. A 1 in this location brings the compar-
ator outputs to P34 and P37, and a 0 releases the Port to its standard I/O configu-
ration.
Port 1 Output Mode (D1)
Bit 1 controls the output mode of port 1. A 1 in this location sets the output to
push-pull, and a 0 sets the output to open-drain.
PS023904-0605
Functional Description
ZGR323L
Product Specification
55
Port 0 Output Mode (D2)
Bit 2 controls the output mode of port 0. A 1 in this location sets the output to
push-pull, and a 0 sets the output to open-drain.
Stop-Mode Recovery Register (SMR)
This register selects the clock divide value and determines the mode of Stop
Mode Recovery (Figure 33). All bits are write only except bit 7, which is read only.
Bit 7 is a flag bit that is hardware set on the condition of Stop recovery and reset
by a power-on cycle. Bit 6 controls whether a low level or a high level at the XOR-
gate input (Figure 35 on page 58) is required from the recovery source. Bit 5 con-
trols the reset delay after recovery. Bits D2, D3, and D4 of the SMR register spec-
ify the source of the Stop-Mode Recovery signal. Bits D0 determines if SCLK/
TCLK are divided by 16 or not. The SMR is located in Bank F of the Expanded
Register Group at address 0Bh.
PS023904-0605
Functional Description
ZGR323L
Product Specification
56
SMR(0F)0Bh
D7 D6 D5 D4 D3 D2 D1 D0
SCLK/TCLK Divide-by-16
0 OFF * *
1 ON
Reserved (Must be 0)
Stop-Mode Recovery Source
000 POR Only *
001 Reserved
010 P31
011 P32
100 P33
101 P27
110 P2 NOR 0-3
111 P2 NOR 0-7
Stop Delay
0 OFF
1 ON * * * *
Stop Recovery Level * * *
0 Low *
1 High
Stop Flag
0 POR *
1 Stop Recovery * *
* Default after Power On Reset or Watch-Dog Reset
* * Default setting after Reset and Stop Mode recovery.
* * * At the XOR gate input
* * * * Default setting after reset. Must be 1 if using a crystal or resonator clock source.
Figure 33. STOP Mode Recovery Register
SCLK/TCLK Divide-by-16 Select (D0)
D0 of the SMR controls a divide-by-16 prescaler of SCLK/TCLK (Figure 34). This
control selectively reduces device power consumption during normal processor
execution (SCLK control) and/or Halt Mode (where TCLK sources interrupt logic).
After Stop Mode Recovery, this bit is set to a 0.
PS023904-0605
Functional Description
ZGR323L
Product Specification
57
OSC
÷ 2
SCLK
TCLK
÷ 16
SMR, D0
Figure 34. SCLK Circuit
Stop-Mode Recovery Source (D2, D3, and D4)
These three bits of the SMR specify the wake-up source of the Stop recovery
(Figure 35 and Table 20).
Stop-Mode Recovery Register 2—SMR2(F)0Dh
Table 19 lists and briefly describes the fields for this register.
Table 19.SMR2(F)0Dh:Stop Mode Recovery Register 2*
Field
Bit Position
7-------
-6------
Value
Description
Reserved
Recovery Level
0
Reserved (Must be 0)
†
W
W
0
Low
1
0
High
Reserved
Source
--5-----
---432--
Reserved (Must be 0)
†
000
A. POR Only
001
010
011
100
101
110
111
B. NAND of P23–P20
C. NAND of P27–P20
D. NOR of P33–P31
E. NAND of P33–P31
F. NOR of P33–P31, P00, P07
G. NAND of P33–P31, P00, P07
H. NAND of P33–P31, P22–P20
Reserved
------10
00
Reserved (Must be 0)
Notes:
* Port pins configured as outputs are ignored as an SMR recovery source.
†
Indicates the value upon Power-On Reset
PS023904-0605
Functional Description
ZGR323L
Product Specification
58
SMR D4 D3 D2
0 0
SMR2 D4 D3 D2
0
0
0 0
VCC
SMR2 D4 D3 D2
0 1
VCC
SMR D4 D3 D2
0
0
1 0
P20
P23
P31
P32
SMR2 D4 D3 D2
1 0
SMR D4 D3 D2
1 1
0
P20
P27
0
SMR2 D4 D3 D2
1 1
SMR D4 D3 D2
0 0
0
1
P31
P32
P33
P33
P27
SMR2 D4 D3 D2
0 0
SMR D4 D3 D2
0 1
1
P31
P32
P33
1
SMR2 D4 D3 D2
0 1
SMR D4 D3 D2
1 0
P31
P32
P33
P00
P07
1
1
P20
P23
SMR2 D4 D3 D2
1 0
SMR D4 D3 D2
1 1
P31
P32
P33
P00
P07
1
1
P20
P27
SMR2 D4 D3 D2
1 1
SMR D6
P31
P32
P33
P20
P21
1
SMR2 D6
To RESET and WDT
Circuitry (Active Low)
Figure 35. Stop Mode Recovery Source
PS023904-0605
Functional Description
ZGR323L
Product Specification
59
Table 20.Stop Mode Recovery Source
SMR:432
Operation
D4
0
D3
0
D2
0
Description of Action
POR and/or external reset recovery
Reserved
0
0
1
0
1
0
P31 transition
0
1
1
P32 transition
1
0
0
P33 transition
1
0
1
P27 transition
1
1
0
Logical NOR of P20 through P23
Logical NOR of P20 through P27
1
1
1
Note: Any Port 2 bit defined as an output drives the corresponding
input to the default state. For example, if the NOR of P23-P20
is selected as the recovery source and P20 is configured as an
output, the remaining SMR pins (P23-P21) form the NOR
equation. This condition allows the remaining inputs to control
the AND/OR function. Refer to SMR2 register on page 60 for
other recover sources.
Stop Mode Recovery Delay Select (D5)
This bit, if low, disables the TPOR delay after Stop Mode Recovery. The default
configuration of this bit is 1. If the “fast” wake up is selected, the Stop-Mode
Recovery source must be kept active for at least 10 TpC.
Note:
This bit must be set to 1 if using a crystal or resonator clock
source. The TPOR delay allows the clock source to stabilize
before executing instructions.
Stop Mode Recovery Edge Select (D6)
A 1 in this bit position indicates that a High level on any one of the recovery
sources wakes the Z8 GP ROM MCU from Stop Mode. A 0 indicates Low level
recovery. The default is 0 on POR.
Cold or Warm Start (D7)
This bit is read only. It is set to 1 when the device is recovered from Stop Mode.
The bit is set to 0 when the device reset is other than Stop Mode Recovery (SMR).
PS023904-0605
Functional Description
ZGR323L
Product Specification
60
Stop Mode Recovery Register 2 (SMR2)
This register determines the mode of Stop Mode Recovery for SMR2 (Figure 36).
SMR2(0F)Dh
D7 D6 D5 D4 D3 D2 D1 D0
Reserved (Must be 0)
Reserved (Must be 0)
Stop-Mode Recovery Source 2
000 POR Only *
001 NAND P20, P21, P22, P23
010 NAND P20, P21, P22, P23, P24, P25, P26, P27
011 NOR P31, P32, P33
100 NAND P31, P32, P33
101 NOR P31, P32, P33, P00, P07
110 NAND P31, P32, P33, P00, P07
111 NAND P31, P32, P33, P20, P21, P22
Reserved (Must be 0)
Recovery Level * *
0 Low *
1 High
Reserved (Must be 0)
Note: If used in conjunction with SMR, either of the two specified events causes a Stop-Mode Recovery.
* Default setting after reset
* * At the XOR gate input
Figure 36. Stop Mode Recovery Register 2 ((0F)DH:D2–D4, D6 Write Only)
If SMR2 is used in conjunction with SMR, either of the specified events causes a
Stop Mode Recovery.
Note: Port pins configured as outputs are ignored as an SMR or
SMR2 recovery source. For example, if the NAND or P23–P20
is selected as the recovery source and P20 is configured as an
output, the remaining SMR pins (P23–P21) form the NAND
equation.
PS023904-0605
Functional Description
ZGR323L
Product Specification
61
Watch-Dog Timer Mode Register (WDTMR)
The Watch-Dog Timer (WDT) is a retriggerable one-shot timer that resets the Z8
if it reaches its terminal count. The WDT must initially be enabled by executing the
WDT instruction. On subsequent executions of the WDT instruction, the WDT is
refreshed. The WDT circuit is driven by an on-board RC-oscillator. The WDT
instruction affects the Zero (Z), Sign (S), and Overflow (V) flags.
The POR clock source the internal RC-oscillator. Bits 0 and 1 of the WDT register
control a tap circuit that determines the minimum timeout period. Bit 2 determines
whether the WDT is active during HALT, and Bit 3 determines WDT activity during
Stop. Bits 4 through 7 are reserved (Figure 37). This register is accessible only
during the first 60 processor cycles (120 XTAL clocks) from the execution of the
first instruction after Power-On-Reset, Watch-Dog Reset, or a Stop-Mode
Recovery (Figure 36). After this point, the register cannot be modified by any
means (intentional or otherwise). The WDTMR cannot be read. The register is
located in Bank F of the Expanded Register Group at address location 0Fh. It is
organized as shown in Figure 37.
WDTMR(0F)0Fh
D7 D6 D5 D4 D3 D2 D1 D0
WDT TAP INT RC OSC
00
01*
10
11
5 ms min.
10 ms min.
20 ms min.
80 ms min.
WDT During HALT
0 OFF
1 ON *
WDT During Stop
0 OFF
1 ON *
Reserved (Must be 0)
* Default setting after reset
Figure 37. WATCH-DOG TIMER Mode Register (Write Only)
WDT Time Select (D0, D1)
This bit selects the WDT time period. It is configured as indicated in Table 21.
PS023904-0605
Functional Description
ZGR323L
Product Specification
62
Table 21.Watch-Dog Timer Time Select
D1
0
D0
0
Timeout of Internal RC-Oscillator
5ms min.
0
1
10ms min.
20ms min.
80ms min.
1
0
1
1
WDTMR During Halt (D2)
This bit determines whether or not the WDT is active during HALT Mode. A 1 indi-
cates active during HALT. The default is 1. See Figure 38.
*CLR2
CLK
18 Clock RESET
Generator
5 Clock Filter
RESET
Internal
RESET
Active
High
WDT
TAP SELECT
XTAL
POR 5 ms 10 ms 20 ms 80 ms
CLK
*CLR1
Internal
RC
WDT/POR Counter Chain
Oscillator.
Low Operating
Voltage Det.
V
+
-
DD
VBO
WDT
V
DD
From Stop
Mode
12-ns Glitch Filter
Recovery
Source
Stop Delay
Select (SMR)
* CLR1 and CLR2 enable the WDT/POR and 18 Clock Reset timers respectively upon a Low-to-High
input translation.
PS023904-0605
Functional Description
ZGR323L
Product Specification
63
Figure 38. Resets and WDT
WDTMR During STOP (D3)
This bit determines whether or not the WDT is active during STOP Mode. A 1
indicates active during Stop. The default is 1.
Selectable Options
There are six Selectable Options to choose from based on ROM code require-
ments. These are listed in Table 22.
Table 22.Selectable Options
Port 00–03 Pull-Ups
Port 04–07 Pull-Ups
Port 10–13 Pull-Ups
Port 14–17 Pull-Ups
Port 20–27 Pull-Ups
On/Off
On/Off
On/Off
On/Off
On/Off
Watch-Dog Timer at Power-On Reset On/Off
Voltage Brown-Out/Standby
An on-chip Voltage Comparator checks that the VDD is at the required level for
correct operation of the device. Reset is globally driven when VDD falls below VBO
A small drop in VDD causes the XTAL1 and XTAL2 circuitry to stop the crystal or
.
resonator clock. If the VDD is allowed to stay above VRAM, the RAM content is pre-
served. When the power level is returned to above VBO, the device performs a
POR and functions normally.
PS023904-0605
Functional Description
ZGR323L
Product Specification
64
Low-Voltage Detection Register—LVD(D)0Ch
Note:
Voltage detection does not work at Stop mode. It must be
disabled during Stop mode in order to reduce current.
Field
Bit Position
Description
LVD
76543---
Reserved
No Effect
-----2--
------1-
-------0
R
1
HVD flag set
0*
HVD flag reset
R
1
LVD flag set
0*
LVD flag reset
R/W
1
Enable VD
Disable VD
0*
*Default after POR
Note:
Do not modify register P01M while checking a low-voltage
condition. Switching noise of both ports 0 and 1 together might
trigger the LVD flag.
Voltage Detection and Flags
The Voltage Detection register (LVD, register 0Chat the expanded register bank
0Dh) offers an option of monitoring the VCC voltage. The Voltage Detection is
enabled when bit 0 of LVD register is set. Once Voltage Detection is enabled, the
the VCC level is monitored in real time. The HVD flag (bit 2 of the LVD register) is
set only if VCC is higher than VHVD. The LVD flag (bit 1 of the LVD register) is set
only if VCC is lower than the VLVD. When Voltage Detection is enabled, the LVD
flag also triggers IRQ5. The IRQ bit 5 latches the low voltage condition until it is
cleared by instructions or reset. The IRQ5 interrupt is served if it is enabled in the
IMR register. Otherwise, bit 5 of IRQ register is latched as a flag only.
Note:
If it is necessary to receive an LVD interrupt upon power-up at
an operating voltage lower than the low battery detect
threshold, enable interrupts using the Enable Interrupt
instruction (EI) prior to enabling the voltage detection.
Expanded Register File Control Registers (0D)
The expanded register file control registers (0D) are depicted in Figure 39 through
Figure 43.
PS023904-0605
Expanded Register File Control Registers (0D)
ZGR323L
Product Specification
65
CTR0(0D)00H
D7 D6 D5 D4 D3 D2 D1 D0
0 P34 as Port Output *
1 Timer8 Output
0 Disable T8 Timeout Interrupt**
1 Enable T8 Timeout Interrupt
0 Disable T8 Data Capture Interrupt**
1 Enable T8 Data Capture Interrupt
00 SCLK on T8**
01 SCLK/2 on T8
10 SCLK/4 on T8
11 SCLK/8 on T8
R 0 No T8 Counter Timeout**
R 1 T8 Counter Timeout Occurred
W 0 No Effect
W 1 Reset Flag to 0
0 Modulo-N*
1 Single Pass
R 0 T8 Disabled *
R 1 T8 Enabled
W 0 Stop T8
W 1 Enable T8
* Default setting after reset.
** Default setting after reset. Not reset with a Stop Mode recovery.
Figure 39. TC8 Control Register ((0D)O0H: Read/Write Except Where Noted)
PS023904-0605
Expanded Register File Control Registers (0D)
ZGR323L
Product Specification
66
CTR1(0D)01H
D7
D6
D5
D4
D3
D2
D1
D0
Transmit Mode*
R/W
0
1
T16_OUT is 0 initially*
T16_OUT is 1 initially
Demodulation Mode
R
R
0
1
No Falling Edge Detection
Falling Edge Detection
W
W
0
1
No Effect
Reset Flag to 0
Transmit Mode*
R/W
0
1
T8_OUT is 0 initially*
T8_OUT is 1 initially
Demodulation Mode
R
R
0
1
No Rising Edge Detection
Rising Edge Detection
W
W
0
1
No Effect
Reset Flag to 0
Transmit Mode*
0
0
1
1
0
1
0
1
Normal Operation*
Ping-Pong Mode
T16_OUT = 0
T16_OUT = 1
Demodulation Mode
0
0
1
1
0
1
0
1
No Filter
4 SCLK Cycle Filter
8 SCLK Cycle Filter
Reserved
Transmit Mode/T8/T16 Logic
0
0
1
1
0
1
0
1
AND**
OR
NOR
NAND
Demodulation Mode
0
0
1
1
0
1
0
1
Falling Edge Detection
Rising Edge Detection
Both Edge Detection
Reserved
Transmit Mode
0
1
P36 as Port Output *
P36 as T8/T16_OUT
Demodulation Mode
0
1
P31 as Demodulator Input
P20 as Demodulator Input
Transmit/Demodulation Mode
0
1
Transmit Mode *
Demodulation Mode
* Default setting after reset
**Default setting after Reset. Not reset with a Stop Mode
recovery.
Figure 40. T8 and T16 Common Control Functions ((0D)01H: Read/Write)
PS023904-0605
Expanded Register File Control Registers (0D)
ZGR323L
Product Specification
67
Notes:
Take care in differentiating the Transmit Mode from
Demodulation Mode. Depending on which of these two modes
is operating, the CTR1 bit has different functions.
Changing from one mode to another cannot be performed
without disabling the counter/timers.
PS023904-0605
Expanded Register File Control Registers (0D)
ZGR323L
Product Specification
68
CTR2(0D)02H
D7 D6 D5 D4 D3 D2 D1 D0
0 P35 is Port Output *
1 P35 is TC16 Output
0 Disable T16 Timeout Interrupt*
1 Enable T16 Timeout Interrupt
0 Disable T16 Data Capture Interrupt**
1 Enable T16 Data Capture Interrupt
0 0 SCLK on T16**
0 1 SCLK/2 on T16
1 0 SCLK/4 on T16
1 1 SCLK/8 on T16
R 0 No T16 Timeout**
R 1 T16 Timeout Occurs
W 0 No Effect
W 1 Reset Flag to 0
Transmit Mode
0 Modulo-N for T16*
1 Single Pass for T16
Demodulator Mode
0 T16 Recognizes Edge
1 T16 Does Not Recognize Edge
R 0 T16 Disabled *
R 1 T16 Enabled
W 0 Stop T16
* Default setting after reset
W 1 Enable T16
** Default setting after reset. Not reset with a Stop
Mode recovery.
Figure 41. T16 Control Register ((0D) 2H: Read/Write Except Where Noted)
PS023904-0605
Expanded Register File Control Registers (0D)
ZGR323L
Product Specification
69
CTR3(0D)03H
D7 D6 D5 D4 D3 D2 D1 D0
Reserved
No effect when written
Always reads 11111
Sync Mode
0* Disable Sync Mode**
1 Enable Sync Mode
T Enable
8
R 0* T Disabled
8
R 1 T Enabled
8
W0 Stop T
8
W1 Enable T
8
T
Enable
16
16
16
R 0* T Disabled
R 1 T Enabled
W 0 Stop T
16
W 1 Enable T
16
* Default setting after reset.
** Default setting after reset. Not reset with a Stop
Mode recovery.
Figure 42. T8/T16 Control Register (0D)03H: Read/Write (Except Where Noted)
Note:
If Sync Mode is enabled, the first pulse of T8 carrier is always
synchronized with T16 (demodulated signal). It can always
provide a full carrier pulse.
PS023904-0605
Expanded Register File Control Registers (0D)
ZGR323L
Product Specification
70
LVD(0D)0CH
D7 D6 D5 D4 D3 D2 D1 D0
Voltage Detection
0: Disable *
1: Enable
LVD Flag (Read only)
0: LVD flag reset *
1: LVD flag set
HVD Flag (Read only)
0: HVD flag reset *
1: HVD flag set
Reserved (Must be 0)
* Default setting after reset.
Figure 43. Voltage Detection Register
Note:
Do not modify register P01M while checking a low-voltage
condition. Switching noise of both ports 0 and 1 together might
trigger the LVD flag.
Expanded Register File Control Registers (0F)
The expanded register file control registers (0F) are depicted in Figures 44
through Figure 57.
PS023904-0605
Expanded Register File Control Registers (0F)
ZGR323L
Product Specification
71
PCON(0F)00H
D7 D6 D5 D4 D3 D2 D1 D0
Comparator Output Port 3
0 P34, P37 Standard Output *
1 P34, P37 Comparator Output
Port 1
0: Open-Drain
1: Push-Pull*
Port 0
0: Open-Drain
1: Push-Pull *
Reserved (Must be 1)
* Default setting after reset
Figure 44. Port Configuration Register (PCON)(0F)00H: Write Only)
PS023904-0605
Expanded Register File Control Registers (0F)
ZGR323L
Product Specification
72
SMR(0F)0BH
D7 D6 D5 D4 D3 D2 D1 D0
SCLK/TCLK Divide-by-16
0 OFF *
1 ON
Reserved (Must be 0)
Stop-Mode Recovery Source
000 POR Only *
001 Reserved
010 P31
011 P32
100 P33
101 P27
110 P2 NOR 0–3
111 P2 NOR 0–7
Stop Delay
0 OFF
1 ON * * * *
Stop Recovery Level * * *
0 Low *
1 High
Stop Flag
0 POR * * * * *
1 Stop Recovery * *
* Default setting after Reset
* * Set after STOP Mode Recovery
* * * At the XOR gate input
* * * * Default setting after Reset. Must be 1 if using a crystal or resonator clock source.
* * * * * Default setting after Power On Reset. Not Reset with a Stop Mode recovery.
Figure 45. Stop Mode Recovery Register ((0F)0BH: D6–D0=Write Only, D7=Read
Only)
PS023904-0605
Expanded Register File Control Registers (0F)
ZGR323L
Product Specification
73
SMR2(0F)0DH
D7 D6 D5 D4 D3 D2 D1 D0
Reserved (Must be 0)
Reserved (Must be 0)
Stop-Mode Recovery Source 2
000 POR Only *
001 NAND P20, P21, P22, P23
010 NAND P20, P21, P22, P23, P24, P25, P26, P27
011 NOR P31, P32, P33
100 NAND P31, P32, P33
101 NOR P31, P32, P33, P00, P07
110 NAND P31, P32, P33, P00, P07
111 NAND P31, P32, P33, P20, P21, P22
Reserved (Must be 0)
Recovery Level * *
0 Low
1 High
Reserved (Must be 0)
Note: If used in conjunction with SMR, either of the two specified events causes a Stop-Mode Recovery.
* Default setting after reset. Not Reset with a Stop Mode recovery.
* * At the XOR gate input
Figure 46. Stop Mode Recovery Register 2 ((0F)0DH:D2–D4, D6 Write Only)
PS023904-0605
Expanded Register File Control Registers (0F)
ZGR323L
Product Specification
74
WDTMR(0F)0FH
D7 D6 D5 D4 D3 D2 D1 D0
WDT TAP INT RC OSC
00
01*
10
11
5 ms min.
10 ms min.
20 ms min.
80 ms min.
WDT During HALT
0 OFF
1 ON *
WDT During Stop
0 OFF
1 ON *
Reserved (Must be 0)
* Default setting after reset. Not Reset with a Stop Mode recovery.
Figure 47. Watch-Dog Timer Register ((0F) 0FH: Write Only)
Standard Control Registers
R246 P2M(F6H)
D7 D6 D5 D4 D3 D2 D1 D0
P27–P20 I/O Definition
0 Defines bit as OUTPUT
1 Defines bit as INPUT *
* Default setting after reset. Not Reset with a Stop Mode recovery.
Figure 48. Port 2 Mode Register (F6H: Write Only)
PS023904-0605
Standard Control Registers
ZGR323L
Product Specification
75
R247 P3M(F7H)
D7 D6 D5 D4 D3 D2 D1 D0
0: Port 2 Open Drain *
1: Port 2 Push-Pull
0= P31, P32 Digital Mode*
1= P31, P32 Analog Mode
Reserved (Must be 0)
* Default setting after reset. Not Reset with a Stop Mode recovery.
Figure 49. Port 3 Mode Register (F7H: Write Only)
PS023904-0605
Standard Control Registers
ZGR323L
Product Specification
76
R248 P01M(F8H)
D7 D6 D5 D4 D3 D2 D1 D0
P00–P03 Mode
0: Output
1: Input *
Reserved (Must be 0)
Reserved (Must be 1)
P17–P10 Mode
0: Byte Output
1: Byte Input*
Reserved (Must be 0)
P07–P04 Mode
0: Output
1: Input *
Reserved (Must be 0)
* Default setting after reset; only P00, P01 and P07 are available on 20-pin
configurations.
Figure 50. Port 0 and 1 Mode Register (F8H: Write Only)
PS023904-0605
Standard Control Registers
ZGR323L
Product Specification
77
R249 IPR(F9H)
D7 D6 D5 D4 D3 D2 D1 D0
Interrupt Group Priority
000 Reserved
001 C > A > B
010 A > B >C
011 A > C > B
100 B > C > A
101 C > B > A
110 B > A > C
111 Reserved
IRQ1, IRQ4, Priority
(Group C)
0: IRQ1 > IRQ4
1: IRQ4 > IRQ1
IRQ0, IRQ2, Priority
(Group B)
0: IRQ2 > IRQ0
1: IRQ0 > IRQ2
IRQ3, IRQ5, Priority
(Group A)
0: IRQ5 > IRQ3
1: IRQ3 > IRQ5
Reserved; must be 0
Figure 51. Interrupt Priority Register (F9H: Write Only)
PS023904-0605
Standard Control Registers
ZGR323L
Product Specification
78
R250 IRQ(FAH)
D7 D6 D5 D4 D3 D2 D1 D0
IRQ0 = P32 Input
IRQ1 = P33 Input
IRQ2 = P31 Input
IRQ3 = T16
IRQ4 = T8
IRQ5 = LVD
Inter Edge
P31↓
P31↓
P31↑
P32↓ = 00
P32↑ = 01
P32↓ = 10
P31↑↓ P32↑↓ = 11
Figure 52. Interrupt Request Register (FAH: Read/Write)
R251 IMR(FBH)
D7 D6 D5 D4 D3 D2 D1 D0
1 Enables IRQ5–IRQ0
(D0 = IRQ0)
Reserved (Must be 0)
0 Master Interrupt Disable *
1 Master Interrupt Enable * *
* Default setting after reset
* * Only by using EI, DI instruction; DI is required before changing the IMR register
Figure 53. Interrupt Mask Register (FBH: Read/Write)
PS023904-0605
Standard Control Registers
ZGR323L
Product Specification
79
R252 Flags(FCH)
D7 D6 D5 D4 D3 D2 D1 D0
User Flag F1
User Flag F2
Half Carry Flag
Decimal Adjust Flag
Overflow Flag
Sign Tag
Zero Flag
Carry Flag
Figure 54. Flag Register (FCH: Read/Write)
R253 RP(FDH)
D7 D6 D5 D4 D3 D2 D1 D0
Expanded Register Bank Pointer
Working Register Pointer
Default setting after reset = 0000 0000
Figure 55. Register Pointer (FDH: Read/Write)
PS023904-0605
Standard Control Registers
ZGR323L
Product Specification
80
R254 SPH(FEH)
D7 D6 D5 D4 D3 D2 D1 D0
General-Purpose Register
Figure 56. Stack Pointer High (FEH: Read/Write)
R255 SPL(FFH)
D7 D6 D5 D4 D3 D2 D1 D0
Stack Pointer Low
Byte (SP7–SP0)
Figure 57. Stack Pointer Low (FFH: Read/Write)
Package Information
Package information for all versions of Z8 GP ROM MCU is depicted in
Figures 58 through Figure 65.
PS023904-0605
Package Information
ZGR323L
Product Specification
81
Figure 58. 20-Pin PDIP Package Diagram
Figure 59. 20-Pin SOIC Package Diagram
PS023904-0605
Package Information
ZGR323L
Product Specification
82
Figure 60. 20-Pin SSOP Package Diagram
PS023904-0605
Package Information
ZGR323L
Product Specification
83
Figure 61. 28-Pin SOIC Package Diagram
PS023904-0605
Package Information
ZGR323L
Product Specification
84
Figure 62. 28-Pin PDIP Package Diagram
PS023904-0605
Package Information
ZGR323L
Product Specification
85
D
C
28
15
MILLIMETER
NOM
INCH
SYMBOL
MIN
1.73
0.05
1.68
0.25
0.09
MAX
1.99
0.21
1.78
0.38
0.20
MIN
NOM
0.073
0.005
0.068
MAX
0.078
0.008
0.070
0.015
0.008
A
1.86
0.068
0.002
0.066
0.010
0.004
A1
A2
B
0.13
H
E
1.73
C
0.006
1
14
D
E
e
10.07
5.20
10.20
5.30
10.33
5.38
0.397
0.205
0.402
0.407
0.212
DETAIL A
0.209
0.65 TYP
0.0256 TYP
H
L
7.65
0.63
7.80
0.75
7.90
0.95
0.301
0.025
0.307
0.030
0.311
0.037
A2
A
B
e
SEATING PLANE
CONTROLLING DIMENSIONS: MM
LEADS ARE COPLANAR WITHIN .004 INCHES.
L
0 - 8
DETAIL 'A'
Figure 63. 28-Pin SSOP Package Diagram
Figure 64. 40-Pin PDIP Package Diagram
PS023904-0605
Package Information
ZGR323L
Product Specification
86
c
D
48
25
E
H
1
24
Detail
A
A2
A
CONTROLLING DIMENSIONS
: MM
LEADS ARE COPLANAR WITHIN .004 INCH
A1
SEATING PLANE
e
b
L
0-8˚
Detail
A
Figure 65. 48-Pin SSOP Package Design
Note:
Please check with ZiLOG on the actual bonding diagram and
coordinate for chip-on-board assembly.
PS023904-0605
Package Information
ZGR323L
Product Specification
87
Ordering Information
32KB Standard Temperature: 0° to +70°C
Part Number
Description
Part Number
Description
ZGR323LSH4832C 48-pin SSOP 32K ROM ZGR323LSS2832C 28-pin SOIC 32K ROM
ZGR323LSP4032C 40-pin PDIP 32K ROM ZGR323LSH2032C 20-pin SSOP 32K ROM
ZGR323LSH2832C 28-pin SSOP 32K ROM ZGR323LSP2032C 20-pin PDIP 32K ROM
ZGR323LSP2832C 28-pin PDIP 32K ROM ZGR323LSS2032C 20-pin SOIC 32K ROM
32KB Extended Temperature: -40° to +105°C
Part Number
Description
Part Number
Description
ZGR323LEH4832C 48-pin SSOP 32K ROM ZGR323LES2832C 28-pin SOIC 32K ROM
ZGR323LEP4032C 40-pin PDIP 32K ROM ZGR323LEH2032C 20-pin SSOP 32K ROM
ZGR323LEH2832C 28-pin SSOP 32K ROM ZGR323LEP2032C 20-pin PDIP 32K ROM
ZGR323LEP2832C 28-pin PDIP 32K ROM ZGR323LES2032C 20-pin SOIC 32K ROM
32KB Automotive Temperature: -40° to +125°C
Part Number
Description
Part Number
Description
ZGR323LAH4832C 48-pin SSOP 32K ROM ZGR323LAS2832C 28-pin SOIC 32K ROM
ZGR323LAP4032C 40-pin PDIP 32K ROM ZGR323LAH2032C 20-pin SSOP 32K ROM
ZGR323LAH2832C 28-pin SSOP 32K ROM ZGR323LAP2032C 20-pin PDIP 32K ROM
ZGR323LAP2832C 28-pin PDIP 32K ROM ZGR323LAS2032C 20-pin SOIC 32K ROM
Note: Replace C with G for Lead-Free Packaging
PS023904-0605
Ordering Information
ZGR323L
Product Specification
88
16KB Standard Temperature: 0° to +70°C
Part Number Description
ZGR323LSH4816C 48-pin SSOP 16K ROM
ZGR323LSP4016C 40-pin PDIP 16K ROM
16KB Extended Temperature: -40° to +105°C
Part Number
Description
ZGR323LEH4816C 48-pin SSOP 16K ROM
ZGR323LEP4016C 40-pin PDIP 16K ROM
16KB Automotive Temperature: -40° to +125°C
Part Number
Description
ZGR323LAH4816C 48-pin SSOP 16K ROM
ZGR323LAP4016C 40-pin PDIP 16K ROM
Note: Replace C with G for Lead-Free Packaging
PS023904-0605
Ordering Information
ZGR323L
Product Specification
89
8KB Standard Temperature: 0° to +70°C
Part Number Description
ZGR323LSH4808C 48-pin SSOP 8K ROM
ZGR323LSP4008C 40-pin PDIP 8K ROM
8KB Extended Temperature: -40° to +105°C
Part Number
Description
ZGR323LEH4808C 48-pin SSOP 8K ROM
ZGR323LEP4008C 40-pin PDIP 8K ROM
8KB Automotive Temperature: -40° to +125°C
Part Number
Description
ZGR323LAH4808C 48-pin SSOP 8K ROM
ZGR323LAP4008C 40-pin PDIP 8K ROM
Note: Replace C with G for Lead-Free Packaging
PS023904-0605
Ordering Information
ZGR323L
Product Specification
90
4KB Standard Temperature: 0° to +70°C
Part Number Description
ZGR323LSH4804C 48-pin SSOP 4K ROM
ZGR323LSP4004C 40-pin PDIP 4K ROM
4KB Extended Temperature: -40° to +105°C
Part Number
Description
ZGR323LEH4804C 48-pin SSOP 4K ROM
ZGR323LEP4004C 40-pin PDIP 4K ROM
4KB Automotive Temperature: -40° to +125°C
Part Number
Description
ZGR323LAH4804C 48-pin SSOP 4K ROM
ZGR323LAP4004C 40-pin PDIP 4K ROM
Note: Replace C with G for Lead-Free Packaging
Additional Components
Part Number
Description
Part Number
Description
ZGP323ICE15ZEM Emulator/programmer
ZGP32300100ZPR Programming system
(Ethernet)
(For 3.6V Emulation
only)
ZGP32300200ZPR Programming system
(USB)
PS023904-0605
Ordering Information
ZGR323L
Product Specification
91
For fast results, contact your local ZiLOG sales office for assistance in ordering
the part desired.
Codes
ZG = ZiLOG General Purpose Family
R = ROM
323L = Family Designation
Temperature
S = Standard 0° to 70° C
E = Extended -40° to 105° C
A = Automotive -40° to 125° C
P = Package Type:
P = Plastic DIP
H = SSOP
S = SOIC
## = Number of Pins
CC = Memory Size
M = Molding Compound
C = Standard Plastic Molding Compound
G = “Green” Plastic Molding Compound
PS023904-0605
Ordering Information
ZGR323L
Product Specification
92
Example
ZG
R
323L
S
P
48 32
C
Molding Compound
Memory Size
Number of Pins
Package Type
Temperature
Family Designation
ROM
ZiLOG General Purpose Family
PS023904-0605
Ordering Information
ZGR323L
Product Specification
93
Index
counter/timer
16-bit circuits 45
Numerics
16-bit counter/timer circuits 45
20-pin DIP package diagram 81
20-pin SSOP package diagram 82
28-pin DIP package diagram 84
28-pin SOICpackage diagram 83
28-pin SSOP package diagram 85
40-pin DIP package diagram 85
48-pin SSOP package diagram 86
8-bit counter/timer circuits 41
8-bit circuits 41
brown-out voltage/standby 63
clock 52
demodulation mode count capture flow-
chart 43
demodulation mode flowchart 44
EPROM selectable options 63
glitch filter circuitry 39
halt instruction 53
input circuit 39
interrupt block diagram 50
interrupt types, sources and vectors 51
oscillator configuration 52
output circuit 48
A
absolute maximum ratings 10
AC
characteristics 15
timing diagram 15
address spaces, basic 2
architecture 2
ping-pong mode 47
port configuration register 54
resets and WDT 63
SCLK circuit 57
expanded register file 27
stop instruction 53
stop mode recovery register 56
stop mode recovery register 2 60
stop mode recovery source 58
T16 demodulation mode 46
T16 transmit mode 45
B
basic address spaces 2
block diagram, ZLP32300 functional 3
T16_OUT in modulo-N mode 46
T16_OUT in single-pass mode 46
T8 demodulation mode 42
T8 transmit mode 39
C
capacitance 11
characteristics
AC 15
T8_OUT in modulo-N mode 42
T8_OUT in single-pass mode 42
transmit mode flowchart 40
voltage detection and flags 64
watch-dog timer mode register 61
watch-dog timer time select 62
CTR(D)01h T8 and T16 Common Functions 34
DC 11
clock 52
comparator inputs/outputs 24
configuration
port 0 18
port 1 19
port 2 20
port 3 21
port 3 counter/timer 23
PS023904-0605
Index
ZGR323L
Product Specification
94
functional description
D
counter/timer functional blocks 39
CTR(D)01h register 34
CTR0(D)00h register 32
CTR2(D)02h register 36
CTR3(D)03h register 38
expanded register file 25
expanded register file architecture 27
HI16(D)09h register 31
HI8(D)0Bh register 31
L08(D)0Ah register 31
L0I6(D)08h register 31
program memory map 25
RAM 24
DC characteristics 11
demodulation mode
count capture flowchart 43
flowchart 44
T16 46
T8 42
description
functional 24
general 2
pin 4
E
register description 64
register file 29
EPROM
selectable options 63
register pointer 28
expanded register file 25
expanded register file architecture 27
expanded register file control registers 70
flag 79
register pointer detail 30
SMR2(F)0D1h register 39
stack 30
TC16H(D)07h register 31
TC16L(D)06h register 32
TC8H(D)05h register 32
TC8L(D)04h register 32
interrupt mask register 78
interrupt priority register 77
interrupt request register 78
port 0 and 1 mode register 76
port 2 configuration register 74
port 3 mode register 75
G
port configuration register 74
register pointer 79
glitch filter circuitry 39
stack pointer high register 80
stack pointer low register 80
stop-mode recovery register 72
stop-mode recovery register 2 73
T16 control register 68
H
halt instruction, counter/timer 53
T8 and T16 common control functions reg-
ister 66
I
T8/T16 control register 69
TC8 control register 64
input circuit 39
interrupt block diagram, counter/timer 50
interrupt types, sources and vectors 51
watch-dog timer register 74
F
L
features
low-voltage detection register 64
standby modes 1
PS023904-0605
Index
ZGR323L
Product Specification
95
port 1 configuration 19
port 1 pin function 18
port 2 configuration 20
port 2 pin function 19
port 3 configuration 21
port 3 pin function 20
M
memory, program 24
modulo-N mode
T16_OUT 46
T8_OUT 42
port 3counter/timer configuration 23
port configuration register 54
power connections 2
power supply 5
O
oscillator configuration 52
output circuit, counter/timer 48
program memory 24
map 25
P
package information
R
20-pin DIP package diagram 81
20-pin SSOP package diagram 82
28-pin DIP package diagram 84
28-pin SOIC package diagram 83
28-pin SSOP package diagram 85
40-pin DIP package diagram 85
48-pin SSOP package diagram 86
pin configuration
ratings, absolute maximum 10
register 60
CTR(D)01h 34
CTR0(D)00h 32
CTR2(D)02h 36
CTR3(D)03h 38
flag 79
HI16(D)09h 31
20-pin DIP/SOIC/SSOP 5
28-pin DIP/SOIC/SSOP 6
40- and 48-pin 8
HI8(D)0Bh 31
interrupt priority 77
interrupt request 78
interruptmask 78
L016(D)08h 31
40-pin DIP 7
48-pin SSOP 8
pin functions
L08(D)0Ah 31
port 0 (P07 - P00) 17
LVD(D)0Ch 64
port 0 (P17 - P10) 18
pointer 79
port 0 configuration 18
port 1 configuration 19
port 2 (P27 - P20) 19
port 0 and 1 76
port 2 configuration 74
port 3 mode 75
port 2 (P37 - P30) 20
port configuration 54, 74
SMR2(F)0Dh 39
port 2 configuration 20
port 3 configuration 21
port 3 counter/timer configuration 23
reset) 24
stack pointer high 80
stack pointer low 80
stop mode recovery 56
stop mode recovery 2 60
stop-mode recovery 72
stop-mode recovery 2 73
T16 control 68
XTAL1 (time-based input 17
XTAL2 (time-based output) 17
ping-pong mode 47
port 0 configuration 18
port 0 pin function 17
T8 and T16 common control functions 66
PS023904-0605
Index
ZGR323L
Product Specification
96
T8/T16 control 69
TC16H(D)07h 31
T
T16 transmit mode 45
T16_Capture_HI 31
T8 transmit mode 39
T8_Capture_HI 31
TC16L(D)06h 32
TC8 control 64
TC8H(D)05h 32
TC8L(D)04h 32
test conditions, standard 10
test load diagram 10
voltage detection 70
watch-dog timer 74
timing diagram, AC 15
transmit mode flowchart 40
register description
Counter/Timer2 LS-Byte Hold 32
Counter/Timer2 MS-Byte Hold 31
Counter/Timer8 Control 32
Counter/Timer8 High Hold 32
Counter/Timer8 Low Hold 32
CTR2 Counter/Timer 16 Control 36
CTR3 T8/T16 Control 38
Stop Mode Recovery2 39
T16_Capture_LO 31
T8 and T16 Common functions 34
T8_Capture_HI 31
V
VCC 5
voltage
brown-out/standby 63
detection and flags 64
voltage detection register 70
W
T8_Capture_LO 31
watch-dog timer
register file 29
mode registerwatch-dog timer mode regis-
expanded 25
ter 61
register pointer 28
time select 62
detail 30
reset pin function 24
resets and WDT 63
X
XTAL1 5
XTAL1 pin function 17
XTAL2 5
S
SCLK circuit 57
XTAL2 pin function 17
single-pass mode
T16_OUT 46
T8_OUT 42
stack 30
standard test conditions 10
standby modes 1
stop instruction, counter/timer 53
stop mode recovery
2 register 60
source 58
stop mode recovery 2 60
stop mode recovery register 56
PS023904-0605
Index
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