U6264AS1A07 [ZMD]
Automotive 8K x 8 SRAM; 汽车8K ×8 SRAM
| 型号： | U6264AS1A07 |
| 厂家： | 
Zentrum Mikroelektronik Dresden AG |
| 描述： | Automotive 8K x 8 SRAM |
| 文件： | 总8页 (文件大小：167K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
U6264ASA07
Automotive 8K x 8 SRAM
change, the data outputs go High-Z
until the new read information is
Features
Description
available. The full CMOS data out-
puts have no preferred state. If the
memory is driven by CMOS levels
in the active state, and if there is no
change of the address, data input
and control signals W or G, the ope-
rating current (at IO = 0 mA) drops
to the value of the operating current
in the Standby mode. The Read
cycle is finished by the falling edge
of E2 or W, or by the rising edge of
E1, respectively.
8192 x 8 bit static CMOS RAM
70 ns Access Time
Common data inputs and outputs
Three-state outputs
Typ. operating supply current:
30 mA
The U6264ASA07 is a static RAM
manufactured using a CMOS pro-
cess technology with the following
operating modes:
- Read
- Write
- Standby
- Data Retention
TTL/CMOS-compatible
Automatic reduction of power
dissipation in long Read or Write
cycles
Power supply voltage 5 V
Operating temperature ranges
-40 to 125 °C
Quality assessment according to
CECC 90000, CECC 90100 and
CECC 90111
ESD protection > 2000 V
(MIL STD 883C M3015.7)
Latch-up immunity > 100 mA
Packages: SOP28 (300 mil)
SOP28 (330 mil)
The memory array is based on a
6-transistor cell.
The circuit is activated by the rising
edge of E2 (at E1 = L), or the falling
edge of E1 (at E2 = H). The
address and control inputs open
simultaneously. According to the Data retention is guaranteed down
information of W and G, the data to 2 V. With the exception of E2, all
inputs, or outputs, are active. inputs consist of NOR gates, so that
During the active state (E1 = L and no pull-up/pull-down resistors are
E2 = H), each address change required. This gate circuit allows to
leads to a new Read or Write cycle. achieve low power standby require-
In a Read cycle, the data outputs ments by activation with TTL-levels
are activated by the falling edge of too.
G, afterwards the data word read If the circuit is inactivated by E2 = L,
will be available at the outputs
the standby current (TTL) drops to
DQ0 DQ7. After the address 150 µA typ.
-
Pin Description
Pin Configuration
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
n.c.
A12
A7
VCC
2
W (WE)
E2 (CE2)
A8
3
Signal Name Signal Description
4
A6
5
A5
A9
A0 - A12
Address Inputs
Data In/Outputs
Chip Enable 1
Chip Enable 2
Output Enable
Read/Write Enable
Power Supply Voltage
Ground
6
A4
A11
DQ0 - DQ7
7
A3
G (OE)
A10
E1
SOP
8
A2
E2
9
A1
E1 (CE1)
DQ7
G
10
11
12
13
14
A0
W
DQ0
DQ1
DQ2
VSS
DQ6
VCC
VSS
DQ5
DQ4
not connected
n.c.
DQ3
Top View
December 12, 1997
1
U6264ASA07
Block Diagram
A4
Memory Cell
Array
A5
A6
A7
A8
256 Rows x
256 Columns
A9
A11
A12
A0
A1
A2
A3
A10
DQ0
DQ1
DQ2
Sense Amplifier/
Write Control Logic
DQ3
DQ4
DQ5
Address
Change
Detector
Clock
Generator
DQ6
DQ7
E2
E1
VSS
W
G
VCC
1
Truth Table
Operating Mode
E1
E2
W
G
DQ0 - DQ7
*
H
L
L
L
L
*
*
*
*
*
High-Z
High-Z
Standby/not
selected
Internal Read
Read
H
H
H
H
H
L
H
L
*
High-Z
Data Outputs, Low-Z
Data Inputs, High-Z
Write
H or L
*
Characteristics
All voltages are referenced to VSS = 0 V (ground).
All characteristics are valid in the power supply voltage range and in the operating temperature range specified.
Dynamic measurements are based on a rise and fall time of ≤ 5 ns, measured between 10 % and 90 % of VI, as well as
input levels of VIL = 0 V and VIH = 3 V. The timing reference level of all input and output signals is 1.5 V,
with the exception of the tdis-times, in which cases transition is measured ± 200 mV from steady-state voltage.
Maximum Ratings
Symbol
Min.
Max.
Unit
Power Supply Voltage
Input Voltage
VCC
VI
-0.3
-0.3
-0.3
7
VCC + 0.5
VCC + 0.5
1
V
V
Output Voltage
VO
PD
Ta
V
Power Dissipation
Operating Temperature
Storage Temperature
W
°C
°C
-40
-65
125
Tstg
150
2
December 12, 1997
U6264ASA07
Recommended
Symbol
Conditions
Min.
Max.
Unit
Operating Conditions
Power Supply Voltage
Data Retention Voltage
VCC
4.5
2.0
5.5
V
V
VCC(DR)
-
Input Low Voltage*
VIL
VIH
-0.3
2.2
0.8
V
V
Input High Voltage
VCC+0.3
* -2 V at Pulse Width 10 ns
Electrical Characteristics
Symbol
Conditions
Min.
Max.
Unit
Supply Current - Operating Mode
ICC(OP)
VCC
VIL
VIH
tcW
= 5.5 V
= 0.8 V
= 2.2 V
55
mA
=
70 ns
Supply Current - Standby Mode
(TTL level)
ICC(SB)1
VCC
= 5.5 V
3
mA
VE1 = VE2 = 2.2 V
or VE2
= 0.8 V
Output High Voltage
VCC
IOH
= 4.5 V
= -1.0 mA
TTL compatible
CMOS compatible
VOH
VOH
2.4
-
-
V
V
0.85 VCC
*
Output Low Voltage
VOL
VCC
IOL
= 4.5 V
= 3.2 mA
-
0.4
V
Output High Current
Output Low Current
IOH
IOL
VCC
VOH
VCC
VOL
= 4.5 V
= 2.4 V
= 4.5 V
= 0.4 V
-
-1
-
mA
mA
3.2
Supply Current - Standby Mode
(CMOS level)
ICC(SB)
VCC
= 5.5 V
30
10
µA
µA
VE1 = VE2 = VCC-0.2V
or VE2
= 0.2 V
Supply Current - Data Retention
Mode
ICC(DR)
VCC(DR)
VE1 = VE2 = VCC(DR)
=
3 V
-
or
0.2 V
VE2
= 0.2 V
Input High Leakage Current
Input Low Leakage Current
IIH
IIL
VCC
VIH
VCC
VIL
= 5.5 V
= 5.5 V
= 5.5 V
-
2
-
µA
µA
-2
=
0 V
Output Leakage Current
High at Three-State Outputs
IOHZ
IOLZ
VCC
VOH
VCC
VOL
= 5.5 V
= 5.5 V
= 5.5 V
-
2
-
µA
µA
Low at Three-State Outputs
-2
=
0 V
December 12, 1997
3
U6264ASA07
Symbol
Switching Characteristics
Min.
Max.
Unit
Alt.
IEC
Time to Output in Low-Z
tLZ
tt(QX)
5
10
ns
Cycle Time
Write Cycle Time
Read Cycle Time
tWC
tRC
tcW
tcR
70
70
-
-
ns
ns
Access Time
E1 LOW or E2 HIGH to Data Valid
G LOW to Data Valid
Address to Data Valid
tACE
tOE
tAA
ta(E)
ta(G)
ta(A)
-
-
-
70
40
70
ns
ns
ns
Pulse Widths
Write Pulse Width
Chip Enable to End of Write
tWP
tCW
tw(W)
tw(E)
50
65
-
-
ns
ns
Setup Times
Address Setup Time
Chip Enable to End of Write
Write Pulse Width
Data Setup Time
tAS
tCW
tWP
tDS
tsu(A)
tsu(E)
tsu(W)
0
-
-
-
-
ns
ns
ns
ns
65
50
35
tsu(D
)
Data Hold Time
Address Hold from End of Write
tDH
tAH
th(D)
th(A)
0
0
-
-
ns
ns
Output Hold Time from Address
Change
tOH
tv(A)
5
-
ns
E1 HIGH or E2 LOW to Output in
High-Z
tHZCE
tdis(E)
0
25
ns
W LOW to Output in High-Z
G HIGH to Output in High-Z
tHZWE
tHZOE
tdis(W)
tdis(G)
0
0
30
25
ns
ns
Data Retention Mode E2-Controlled
Data Retention Mode E1-Controlled
VCC
VCC
E2
4.5 V
4.5 V
VCC(DR) ≥ 2 V
V
CC(DR) ≥ 2 V
Data Retention
E2(DR) ≤ 0.2 V
2.2 V
2.2 V
E1
trec
tDR
trec
tDR
Data Retention
V
0.8 V
0.8 V
0 V
0 V
V
E2(DR) ≥ VCC(DR) - 0.2 V or VE2(DR) ≤ 0.2 V
VCC(DR) - 0.2 V ≤ VE1(DR) ≤ VCC(DR) + 0.3 V
Chip Deselect to Data Retention Time
Operating Recovery Time
tDR
:
min 0 ns
min tcR
trec
:
4
December 12, 1997
U6264ASA07
Test Configuration for Functional Check
(for TTL output levels)
5 V
VCC
A0
A1
A2
A3
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
A4
960
A5
VIH
A6
A7
A8
A9
A10
A11
A12
VIL
VO
30 pF1)
E1
E2
W
G
510
VSS
1) In measurement of tdis(E), tdis(W), tdis(G) the capacitance is 5 pF.
Capacitance
Conditions
Symbol
Min.
Max.
Unit
V
CC = 5.0 V
Input Capacitance
CI
8
pF
VI = VSS
f
= 1 MHz
Output Capacitance
CO
10
pF
Ta = 25 °C
All pins not under test must be connected with ground by capacitors.
IC Code Numbers
Example
U6264A
S
A
07
Type
Package
S1 = SOP28 (300 mil)
Internal Code
S
= SOP28 (330 mil)
Operating Temperature Range
Access Time
07 = 70 ns
A = -40 to 125 °C
The date of manufacture is given by the last 4 digits of the mark, the first 2 digits indicating the year, and the last
2 digits the calendar week.
December 12, 1997
5
U6264ASA07
Read Cycle 1 (during Read cycle: E1 = G = VIL, E2 = W = VIH)
tcR
Ai
Addresses Valid
ta(A)
Previous
Data Valid
tv(A)
Output Data
Valid
DQi
Output
Read Cycle 2 (during Read cycle: W = VIH)
tcR
Ai
Addresses Valid
ta(E)
tsu(A)
tt(QX)
tdis(E)
tdis(E)
E1
ta(E)
tsu(A)
tt(QX)
E2
ta(G)
tdis(G)
G
tt(QX)
DQi
Output
High-Z
Output Data
Valid
Write Cycle 1 (W-controlled)
tcW
Addresses Valid
tsu(E)
Ai
th(A)
E1
tsu(E)
E2
tsu(A)
tw(W)
W
tsu(D)
th(D)
DQi
Input
Input Data
Valid
tdis(W)
tt(QX)
DQi
Output
High-Z
G
6
December 12, 1997
U6264ASA07
Write Cycle 2 (E1-controlled)
tcW
Addresses Valid
tw(E)
Ai
tsu(A)
th(A)
E1
E2
tsu(E)
tsu(W)
W
th(D)
tsu(D)
DQi
Input
Input Data
Valid
tdis(W)
tt(QX)
DQi
Output
High-Z
G
Write Cycle 3 (E2-controlled)
tcW
Addresses Valid
tsu(E)
Ai
th(A)
E1
E2
tsu(A)
tw(E)
tsu(W)
W
tsu(D)
th(D)
DQi
Input
Input Data
Valid
tdis(W)
tt(QX)
DQi
Output
High-Z
G
L- or H-level
undefined
December 12, 1997
7
Memory Products 1998
Automotive 8K x 8 SRAM U6264ASA07
LIFE SUPPORT POLICY
ZMD products are not designed, intended, or authorized for use as components in
systems intend for surgical implant into the body, or other applications intended to
support or sustain life, or for any other application in which the failure of the ZMD
product could create a situation where personal injury or death may occur.
Components used in life-support devices or systems must be expressly authorized
by ZMD for such purpose.
The information describes the type of component and shall not be considered as
assured characteristics.
Terms of delivery and rights to change design reserved.
Zentrum Mikroelektronik Dresden GmbH
Grenzstraße 28 • D-01109 Dresden• P. O.B. 800134 •D-01101 Dresden•Germany
Phone: +49 351 88 22-3 06 • Fax: +49 351 88 22-3 37 • Email: sales@zmd.de
Internet Web Site: http://www.zmd.de
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