U6264BDK07G1 [ZMD]
STANDARD 5K X 8 SRAM; 标准5K ×8 SRAM
| 型号： | U6264BDK07G1 |
| 厂家： | 
Zentrum Mikroelektronik Dresden AG |
| 描述： | STANDARD 5K X 8 SRAM |
| 文件： | 总9页 (文件大小：163K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
U6264B
Standard 8K x 8 SRAM
Features
Description
! 8192 x 8 bit static CMOS RAM
! 70 ns Access Times
! Common data inputs and
outputs
The U6264B is a static RAM manu-
factured using a CMOS process
technology with the following ope-
rating modes:
address, data input and control
signals W or G, the operating cur-
rent (at IO = 0 mA) drops to the
value of the operating current in the
Standby mode. The Read cycle is
finished by the falling edge of E2 or
W, or by the rising edge of E1,
respectively.
! Three-state outputs
! Typ. operating supply current
70 ns: 10 mA
- Read
- Write
- Standby
- Data Retention
The memory array is based on a
6-transistor cell.
! Standby current:
< 2 µA at T ≤ 70 °C
The circuit is activated by the rising
edge of E2 (at E1 = L), or the falling
edge of E1 (at E2 = H). The
address and control inputs open
simultaneously. According to the
information of W and G, the data
inputs, or outputs, are active. In a
Read cycle, the data outputs are
activated by the falling edge of G,
afterwards the data word read will
be available at the outputs DQ0 -
DQ7. After the address change, the
data outputs go High-Z until the
new read information is available.
The data outputs have no preferred
state. If the memory is driven by
CMOS levels in the active state,
and if there is no change of the
Data retention is guaranteed down
to 2 V. With the exception of E2, all
inputs consist of NOR gates, so
that no pull-up/pull-down resistors
are required. This gate circuit
allows to achieve low power
standby requirements by activation
with TTL-levels too.
a
! Data retention current at 2 V:
< 1 µA at T ≤ 70 °C
a
! TTL/CMOS-compatible
! Automatic reduction of power
dissipation in long Read or Write
cycles
! Power supply voltage 5 V
! Operating temperature ranges:
0 to 70 °C
If the circuit is inactivated by
E2 = L, the standby current (TTL)
drops to 150 µA typ.
-40 to 85 °C
-40 to 125 °C
! QS 9000 Quality Standard
! ESD protection > 2000 V
(MIL STD 883C M3015.7)
! Latch-up immunity > 100 mA
! Packages: PDIP28 (600 mil)
SOP28 (330 mil)
Pin Configuration
Pin Description
Signal Name Signal Description
n.c.
A12
A7
A6
A5
A4
A3
A2
A1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
VCC
A0 - A12
Address Inputs
Data In/Out
W (WE)
E2 (CE2)
A8
A9
A11
G (OE)
A10
E1 (CE1)
DQ7
DQ6
DQ5
DQ0 - DQ7
Chip Enable 1
Chip Enable 2
Output Enable
Write Enable
Power Supply Voltage
Ground
E1
E2
PDIP
SOP
G
9
W
A0
10
11
12
13
14
DQ0
DQ1
DQ2
VSS
VCC
VSS
DQ4
DQ3
not connected
n.c.
Top View
April 20, 2004
1
U6264B
Block Diagram
A4
A5
A6
A7
A8
A9
Memory Cell
Array
256 Rows x
256 Columns
A11
A12
A0
A1
A2
A3
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
Sense Amplifier/
Write Control Logic
A10
Address
Change
Detector
Clock
DQ6
DQ7
Generator
E2
E1
VSS
W
G
VCC
1
Truth Table
Operating Mode
E1
E2
W
G
DQ0 - DQ7
*
H
L
L
L
L
*
*
*
*
*
High-Z
High-Z
High-Z
Standby/not selected
Internal Read
Read
H
H
H
H
H
L
H
L
*
Data Outputs Low-Z
Data Inputs High-Z
Write
H or L
*
April 20, 2004
2
U6264B
Characteristics
All voltages are referenced to VSS = 0 V (ground).
All characteristics are valid in the power supply voltage range and in the operating temperature range specified.
Dynamic measurements are based on a rise and fall time of ≤ 5 ns, measured between 10 % and 90 % of VI, as well as
input levels of VIL = 0 V and VIH = 3 V. The timing reference level of all input and output signals is 1.5 V,
with the exception of the tdis-times, in which cases transition is measured ± 200 mV from steady-state voltage.
a
Absolute Maximum Ratings
Symbol
Min.
Max.
Unit
Power Supply Voltage
Input Voltage
VCC
VI
-0.3
-0.3
-0.3
-
7
VCC + 0.5
VCC + 0.5
1
V
V
b
b
Output Voltage
VO
PD
Ta
V
Power Dissipation
Operating Temperature
W
C-Type
K-Type
A-Type
0
70
85
°C
°C
°C
-40
-40
125
Storage Temperature
C/K-Type
A-Type
Tstg
-55
-65
125
150
°C
°C
Output Short-Circuit Current
at VCC = 5 V and VO = 0 V c
| IOS
|
100
mA
a
Stresses greater than those listed under „Absolute Maximum Ratings“ may cause permanent damage to the device. This is a stress rating
only, and functional operation of the device at condition above those indicated in the operational sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability
b
c
Maximum voltage is 7 V
Not more than 1 output should be shorted at the same time. Duration of the short circuit should not exceed 30 s.
Recommended
Symbol
Conditions
Min.
Max.
Unit
Operating Conditions
Power Supply Voltage
Data Retention Voltage
VCC
4.5
2.0
5.5
V
V
VCC(DR)
Input Low Voltage d
Input High Voltage
VIL
-0.3
2.2
0.8
V
V
VIH
VCC + 0.3
d
-2 V at Pulse Width 10 ns
April 20, 2004
3
U6264B
Electrical Characteristics
Symbol
Conditions
Min.
Max.
Unit
Supply Current - Operating Mode
ICC(OP) VCC
= 5.5 V
= 0.8 V
= 2.2 V
= 70 ns
55
mA
VIL
VIH
tcW
Supply Current - Standby Mode
(CMOS level)
ICC(SB) VCC
= 5.5 V
VE1 = VE2 = VCC - 0.2 V
or VE2
= 0.2 V
C-Type
K-Type
A-Type
2
5
µA
µA
µA
100
Supply Current - Standby Mode
(TTL level)
ICC(SB)1 VCC
= 5.5 V
3
mA
VE1 = VE2 = 2.2 V
or VE2
= 0.8 V
Supply Current - Data Retention
Mode
ICC(DR) VCC(DR)
=
2 V
VE1 = VE2 = VCC(DR) - 0.2 V
or VE2
= 0.2 V
C-Type
K-Type
A-Type
1
3
µA
µA
µA
50
Output High Voltage
Output Low Voltage
VOH
VOL
VCC
IOH
= 4.5 V
2.4
3.2
V
V
= -1.0 mA
= 4.5 V
VCC
IOL
0.4
-1
= 3.2 mA
Output High Current
Output Low Current
IOH
IOL
VCC
VOH
VCC
VOL
= 4.5 V
= 2.4 V
= 4.5 V
= 0.4 V
mA
mA
Input Leakage Current
High
IIH
VCC
= 5.5 V
= 5.5 V
VIH
C/K-Type
A-Type
-
-
1
2
µA
µA
VCC
= 5.5 V
Low
IIL
VIL
=
0 V
C/K-Type
A-Type
-1
-2
-
-
µA
µA
Output Leakage Current
High at Three-State Outputs
IOHZ
VCC
= 5.5 V
= 5.5 V
VOH
C/K-Type
A-Type
-
-
1
2
µA
µA
VCC
= 5.5 V
Low at Three-State Outputs
IOLZ
VOL
=
0 V
C/K-Type
A-Type
-1
-2
-
-
µA
µA
April 20, 2004
4
U6264B
Symbol
Switching Characteristics
Min.
Max.
Unit
Alt.
IEC
Time to Output in Low-Z
tLZ
tt(QX)
5
10
ns
Cycle Time
Write Cycle Time
Read Cycle Time
tWC
tRC
tcW
tcR
70
70
ns
ns
Access Time
E1 LOW or E2 HIGH to Data Valid
G LOW to Data Valid
Address to Data Valid
tACE
ta(E)
ta(G)
ta(A)
-
-
-
70
40
70
ns
ns
ns
tOE
tAA
Pulse Widths
Write Pulse Width
Chip Enable to End of Write
tWP
tCW
tw(W)
tw(E)
50
65
ns
ns
Setup Times
Address Setup Time
Chip Enable to End of Write
Write Pulse Width
Data Setup Time
tAS
tCW
tWP
tDS
tsu(A)
tsu(E)
tsu(W)
tsu(D)
0
ns
ns
ns
ns
65
50
35
Data Hold Time
t
t
th(D)
th(A)
0
0
ns
ns
DH
AH
Address Hold from End of Write
Output Hold Time from Address Change
tOH
tv(A)
5
0
ns
ns
E1 HIGH or E2 LOW to Output in High-Z
W LOW to Output in High-Z
tHZCE
tdis(E)
25
G HIGH to Output in High-Z
tHZWE
tHZOE
tdis(W)
tdis(G)
0
0
30
25
ns
ns
Data Retention Mode E1-Controlled
Data Retention Mode E2-Controlled
VCC
VCC
4.5 V
4.5 V
0 V
V
CC(DR) ≥ 2 V
V
CC(DR) ≥ 2 V
Data Retention
E2(DR) ≤ 0.2 V
E2
2.2 V
E1
2.2 V
0 V
trec
tDR
tDR
trec
0.8 V
Data Retention
0.8 V
V
V
V
E2(DR) ≥ VCC(DR) - 0.2 V or VE2(DR) ≤ 0.2 V
CC(DR) - 0.2 V ≤ VE1(DR) ≤ VCC(DR) + 0.3 V
Chip Deselect to Data Retention Time tDR
Operating Recovery Time trec
:
:
min 0 ns
min tcR
April 20, 2004
5
U6264B
Test Configuration for Functional Check
5 V
VCC
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
960
VIH
VIL
VO
30 pFe
E1
E2
W
510
VSS
G
e In measurement of tdis(E), tdis(W), tdis(G) the capacitance is 5 pF.
Capacitance
Conditions
VCC = 5.0 V
Symbol
Min.
Max.
Unit
Input Capacitance
CI
8
pF
VI = VSS
f
= 1 MHz
Output Capacitance
CO
10
pF
Ta = 25 °C
All pins not under test must be connected with ground by capacitors.
Ordering Code
Example
Type
U6264B S2
K
07 LL
Leadfree Option
blank= Standard Package
Package
G1 = Leadfree Green Package f
D = PDIP28 (600 mil, only C/K-Type)
S = SOP28 (330 mil) Type 1
S2 = SOP28 (330 mil) Type 2
Power Consumption
blank= Standard (only A-Type)
LL
= Very Low Power (C/K-Type)
Operating Temperature Range
C = 0 to 70 °C
Access Time
07 = 70 ns
K = -40 to 85 °C
A = -40 to 125 °C
f on special request
Device Marking (example)
ZMD
Product specification
Date of manufacture
U6264BS2K
07LL C 0425
(The first 2 digits indicating
the year, and the last 2
digits the calendar week.)
Assembly location and
trace code
1 ZZ
G1
Internal Code
Leadfree Green Package
April 20, 2004
6
U6264B
Read Cycle 1 (during Read cycle: E1 = G = VIL, E2 = W = VIH)
tcR
Ai
Addresses Valid
ta(A)
DQi
Previous Data Valid
tv(A)
Output Data Valid
Output
Read Cycle 2 (during Read cycle: W = VIH)
tcR
Ai
Addresses Valid
ta(E)
tt(QX)
tsu(A)
E1
tdis(E)
tdis(E)
tsu(A)
ta(E)
tt(QX)
E2
G
ta(G)
tdis(G)
tt(QX)
DQi
High-Z
Output Data Valid
Output
Write Cycle 1 (W-controlled)
tcW
Ai
Addresses Valid
tsu(E)
th(A)
E1
E2
tsu(E)
tw(W)
tsu(A)
W
tsu(D)
th(D)
DQi
Input Data Valid
Input
tdis(W)
tt(QX)
DQi
High-Z
Output
G
April 20, 2004
7
U6264B
Write Cycle 2 (E1-controlled)
tcW
Ai
Addresses Valid
tw(E)
tsu(A)
th(A)
E1
E2
W
tsu(E)
tsu(W)
th(D)
tsu(D)
DQi
Input Data Valid
Input
tdis(W)
tt(QX)
High-Z
DQi
Output
G
Write Cycle 3 (E2-controlled)
tcW
Ai
Addresses Valid
tsu(E)
th(A)
E1
tsu(A)
tw(E)
E2
W
tsu(W)
tsu(D)
th(D)
DQi
Input Data Valid
Input
tdis(W)
tt(QX)
DQi
High-Z
Output
G
L- or H-level
undefined
The information describes the type of component and shall not be considered as assured characteristic. Terms of
delivery and rights to change design reserved.
April 20, 2004
8
U6264B
LIFE SUPPORT POLICY
ZMD products are not designed, intended, or authorized for use as components in systems intended for surgical
implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the ZMD product could create a situation where personal injury or death may occur.
Components used in life-support devices or systems must be expressly authorized by ZMD for such purpose.
LIMITED WARRANTY
The information in this document has been carefully checked and is believed to be reliable. However Zentrum
Mikroelektronik Dresden AG (ZMD) makes no guarantee or warranty concerning the accuracy of said information
and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon it.
The information in this document describes the type of component and shall not be considered as assured charac-
teristics.
ZMD does not guarantee that the use of any information contained herein will not infringe upon the patent, trade-
mark, copyright, mask work right or other rights of third parties, and no patent or licence is implied hereby. This
document does not in any way extent ZMD’s warranty on any product beyond that set forth in its standard terms and
conditions of sale.
ZMD reserves terms of delivery and reserves the right to make changes in the products or specifications, or both,
presented in this publication at any time and without notice.
Zentrum Mikroelektronik Dresden AG
April 20, 2004
Grenzstraße 28 • D-01109 Dresden •P. O. B. 80 01 34 • D-01101 Dresden • Germany
Phone: +49 351 8822 306 • Fax: +49 351 8822 337 • Email: memory@zmd.de • http://www.zmd.de
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