QL12X16B-PQ208M [ETC]

Military 5.0V pASIC 1 Family - Very-High-Speed CMOS FPGA; 军事5.0V pASIC 1家庭 - 非常高速的CMOS FPGA
QL12X16B-PQ208M
元器件型号: QL12X16B-PQ208M
生产厂家: ETC    ETC
描述和应用:

Military 5.0V pASIC 1 Family - Very-High-Speed CMOS FPGA
军事5.0V pASIC 1家庭 - 非常高速的CMOS FPGA

军事
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Military 5.0V pASIC 1 Family
Military 5.0V pASIC 1 Family - Very-High-Speed CMOS FPGA
Military 5.0V pASIC 1 Family
D
EVICE
H
IGHLIGHTS
Device Highlights
Features
s
F
EATURES
Total of 180 I/O pins
s
s
s
Very High Speed
s
ViaLink“ metal-to-metal programmable technol-
ogy, allows counter speeds over 150 MHz and
logic cell delays of under 2 ns at 5V, and over 80
MHz at 3.3V operation.
-172 Bidirectional Input/Output pins
-6 Dedicated Input/High-Drive pins
-2 Clock/Dedicated input pins with fanout-
independent, low-skew clock networks
-PCI 2.1 Compliant I/Os
High Usable Density
s
s
s
s
s
Up to a 24-by-32 array of 768 logic cells provides
22,000 usable PLD gates in 208-pin PQFP and
208-pin CQFP packages.
Input + logic cell + output delays under 6 ns
Chip-to-chip operating frequencies up to 110 MHz
Internal state machine frequencies up to 150 MHz
Clock skew < 0.5 ns
Input hysteresis provides high noise immunity
Built-in scan path permits 100% factory testing of
logic and I/O cells and functional testing with Auto-
matic Test Vector Generation (ATVG) software
after programming
208 pin PQFP pin for pin compatible with the
208 CQFP
0.65µ CMOS process with ViaLink programming
technology
PCI-Output Drive
s
s
s
s
Fully PCI 2.1 compliant input/output capability.
(including drive current)
s
s
Device
ASIC
Gates
PLD
Gates
Package
Max
I/O
Qualification
Level
SMD
5962-
QL8x12B
QL12x16B
QL16x24B
QL24x32B
1,000
2,000
4,000
8,000
2,000
4,000
7,000
14,000
68CPGA
84CPGA
144CPGA
160 CQFP
208CQFP
208PQFP
64
76
122
122
180
180
M
M, /883
M, /883
M, /883
M, /883
M
96836
95599
95599
96837
M = Military Temperature (-55 to +125 degrees C)
/883 = MIL-STD-883 qualified
TABLE 1: Selector Table
Rev B
8-7
Military 5.0V pASIC 1 Family
P
RODUCT
S
UMMARY
Product Summary
The pASIC 1 Family is a very-high-speed CMOS
user-programmable ASIC devices. The 768 logic cell
field-programmable gate array (FPGA) features
22,000 usable PLD gates of high-performance gen-
eral-purpose logic in a 208-pin PQFP and CQFP
package.
Low-impedance, metal-to-metal, ViaLink intercon-
nect technology provides nonvolatile custom logic
capable of operating above 150 MHz. Logic cell
delays under 2 ns, combined with input delays of
under 1.5 ns and output delays under 3 ns, permit
high-density programmable devices to be used with
today’s fastest microprocessors and DSPs.
Designs can be entered using QuickLogic’s Quick-
Works Toolkit or most popular third-party CAE tools.
QuickWorks combines Verilog/VHDL design entry
and simulation tools with device-specific place &
route and programming software. Ample on-chip
routing channels allow fast, fully automatic place and
route of designs using up to 100% of the logic and I/
O cells, while maintaining fixed pin-outs.
P
INOUT
D
IAGRAM
68-P
IN
CPGA
Pinout Diagram 68-Pin CPGA
PIN
B10
A10
B9
A9
B8
A8
B7
A7
B6
A6
B5
A5
B4
A4
B3
A3
A2
FUNC
IO
IO
IO
IO
IO
IO
I/(SCLK)
I/CLK/(SM)
VCC
I
I
IO
IO
IO
IO
IO
IO
PIN
B2
B1
C2
C1
D2
D1
E2
E1
F2
F1
G2
G1
H2
H1
J2
J1
K1
FUNC
IO
IO
IO
IO
IO
IO
IO
IO
GND
IO
IO
IO
IO
IO
IO
IO
IO
PIN
K2
L2
K3
L3
K4
L4
K5
L5
K6
L6
K7
L7
K8
L8
K9
L9
L10
FUNC
IO
IO
IO
IO
IO
IO
I/(SI)
I/CLK
VCC
I
I/(SO)
IO
IO
IO
IO
IO
IO
PIN
K10
K11
J10
J11
H10
H11
G10
G11
F10
F11
E10
E11
D10
D11
C10
C11
B11
FUNC
IO
IO
IO
IO
IO
IO
IO
IO
GND
IO
IO
IO
IO
IO
IO
IO
IO
TABLE 2: CPGA 68 Function/Connector Pin Table
8-8
8
Preliminary
Military 5.0V pASIC 1 Family
P
INOUT
D
IAGRAM
84-P
IN
CPGA
Pinout Diagram 84-pin CPGA
PIN
B10
B9
A10
A9
B8
A8
A7
C7
A6
B7
C6
B6
B5
C5
A5
A4
B4
A3
A2
B3
A1
FUNC
IO
IO
IO
IO
IO
IO
IO
GND
IO
I/(SCLK)
I/CLK/(SM)
I(P)
I
VCC
IO
IO
IO
IO
IO
IO
IO
PIN
B2
C2
B1
C1
D2
D1
E1
E3
E2
F1
F2
F3
G1
G3
G2
H1
H2
J1
K1
J2
L1
FUNC
IO
IO
IO
IO
IO
IO
IO
GND
IO
IO
IO
IO
IO
VCC
IO
IO
IO
IO
IO
IO
IO
PIN
K2
K3
L2
L3
K4
L4
L5
J5
L6
K5
J6
K6
K7
J7
L7
L8
K8
L9
L10
K9
L11
FUNC
IO
IO
IO
IO
IO
IO
IO
GND
IO
I/(SI)
I/CLK
I
I/(SO)
VCC
IO
IO
IO
IO
IO
IO
IO
PIN
K10
J10
K11
J11
H10
H11
G11
G9
G10
F11
F10
F9
E11
E9
E10
D11
D10
C11
B11
C10
A11
FUNC
IO
IO
IO
IO
IO
IO
IO
GND
IO
IO
IO
IO
IO
VCC
IO
IO
IO
IO
IO
IO
IO
TABLE 3: CPGA 84 Function/Connector Pin Table
8-9
Military 5.0V pASIC 1 Family
P
INOUT
D
IAGRAM
144-P
IN
CPGA
Pinout Diagram 144-pin CPGA
PIN
A2
B3
C4
A3
B4
A4
C3
B5
A5
C6
B6
A6
A7
B7
C5
A8
B8
C8
C7
A9
B9
C11
A10
A11
B10
FUNC
IO
IO
IO
IO
IO
IO
VCC
IO
IO
IO
IO
IO
IO
IO
GND
IO
I/(SCLK)
I/CLK/(SM)
VCC
I/(P)
I
VCC
IO
IO
IO
PIN
B15
C14
D13
C15
D14
E13
D15
E14
E15
F13
F14
F15
G15
C13
G14
H15
H14
G13
H13
J15
J14
J13
K15
L15
K14
FUNC
IO
IO
IO
IO
IO
VCC
IO
IO
IO
IO
IO
IO
IO
GND
IO
IO
IO
GND
IO
IO
IO
VCC
IO
IO
IO
PIN
R14
P13
N12
R13
P12
R12
N13
P11
R11
N10
P10
R10
R9
P9
N11
R8
P8
N8
N9
R7
P7
N5
R6
R5
P6
FUNC
IO
IO
IO
IO
IO
IO
VCC
IO
IO
IO
IO
IO
IO
IO
GND
IO
I/(SI)
I/CLK
VCC
I
I/(SO)
VCC
IO
IO
IO
PIN
P1
N2
M3
N1
M2
L3
M1
L2
L1
K3
K2
K1
J1
N3
J2
H1
H2
J3
H3
G1
G2
G3
F1
E1
F2
FUNC
IO
IO
IO
IO
IO
VCC
IO
IO
IO
IO
IO
IO
IO
GND
IO
IO
IO
GND
IO
IO
IO
VCC
IO
IO
IO
TABLE 4: CPGA 144 Function/Connector Table
(Cont’d on next page)
8-10
10
Preliminary
Military 5.0V pASIC 1 Family
CPGA 144 Function/Connector Table (Cont’d)
A12
B11
C10
A13
C9
B12
A14
B13
C12
A15
B14
IO
IO
IO
IO
GND
IO
IO
IO
IO
IO
IO
M15
L14
K13
N15
L13
M14
P15
N14
M13
R15
P14
IO
IO
IO
IO
GND
IO
IO
IO
IO
IO
nc
R4
P5
N6
R3
N7
P4
R2
P3
N4
R1
P2
IO
IO
IO
IO
GND
IO
IO
IO
IO
IO
IO
D1
E2
F3
C1
E3
D2
B1
C2
D3
A1
B2
IO
IO
IO
IO
GND
IO
IO
IO
IO
IO
nc
P
INOUT
D
IAGRAM
160-P
IN
CPGA
QL16x24B-1CF160M
8-11
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