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ADS8401IBPFBR

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描述：16-BIT, 1.25 MSPS, UNIPOLAR INPUT, MICRO POWER SAMPLING ANALOG-TODIGITAL CONVERTER WITH PARALLEL INTERFACE AND REFERENCE

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ADS8401IBPFBR 概述

16-BIT, 1.25 MSPS, UNIPOLAR INPUT, MICRO POWER SAMPLING ANALOG-TODIGITAL CONVERTER WITH PARALLEL INTERFACE AND REFERENCE 16位， 1.25 MSPS ，单极性输入，微功耗采样模数，并行接口和引用转换器

ADS8401IBPFBR 数据手册

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ADS8401  
SLAS376B – DECEMBER 2002 – REVISED APRIL 2003  
16-BIT, 1.25 MSPS, UNIPOLAR INPUT, MICRO POWER SAMPLING ANALOG-TO-  
DIGITAL CONVERTER WITH PARALLEL INTERFACE AND REFERENCE  
FEATURES  
APPLICATIONS  
D
D
D
D
D
D
DWDM  
D
D
D
D
1.25-MHz Sample Rate  
Instrumentation  
16-Bit NMC Ensured Over Temperature  
Zero Latency  
High-Speed, High-Resolution, Zero Latency  
Data Acquisition Systems  
Transducer Interface  
Medical Instruments  
Communication  
Unipolar Single-Ended Input Range: 0 V to  
V
ref  
D
D
D
D
D
D
D
Onboard Reference  
DESCRIPTION  
Onboard Reference Buffer  
High-Speed Parallel Interface  
Power Dissipation: 155 mW at 1.25 MHz Typ  
Wide Digital Supply  
The ADS8401 is a 16-bit, 1.25 MHz A/D converter with an  
internal 4.096-V reference. The device includes a 16-bit  
capacitor-based SAR A/D converter with inherent sample  
and hold. The ADS8401 offers a full 16-bit interface and an  
8-bit option where data is read using two 8-bit read cycles.  
The ADS8401 has a unipolar single-ended input. It is  
available in a 48-lead TQFP package and is characterized  
over the industrial –40°C to 85°C temperature range.  
8-/16-Bit Bus Transfer  
48-Pin TQFP Package  
Output  
Latches  
and  
3-State  
Drivers  
BYTE  
SAR  
16-/8-Bit  
Parallel DATA  
Output Bus  
+
_
+IN  
–IN  
CDAC  
Comparator  
Clock  
RESET  
REFIN  
CONVST  
Conversion  
and  
Control Logic  
BUSY  
CS  
4.096-V  
Internal  
Reference  
REFOUT  
RD  
Pleasebe aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments  
semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date. Products  
conform to specifications per the terms of Texas Instruments standard warranty.  
Production processing does not necessarily include testing of all parameters.  
Copyright 2002–2003, Texas Instruments Incorporated  
ADS8401  
www.ti.com  
SLAS376B – DECEMBER 2002 – REVISED APRIL 2003  
Thesedeviceshavelimitedbuilt-inESDprotection.Theleadsshouldbeshortedtogetherorthedeviceplacedinconductivefoamduring  
storageor handling to prevent electrostatic damage to the MOS gates.  
ORDERING INFORMATION  
NO  
MISSING  
CODES  
RESOLU-  
TION (BIT)  
MAXIMUM  
INTEGRAL DIFFERENTIAL  
LINEARITY  
(LSB)  
MAXIMUM  
TRANS-  
PORT  
MEDIA  
TEMPER-  
ATURE  
RANGE  
PACKAGE  
TYPE  
PACKAGE  
DESIGNATOR  
ORDERING  
INFORMATION  
MODEL  
LINEARITY  
(LSB)  
QUANTITY  
Tape and  
reel 250  
ADS8401IPFBT  
ADS8401IPFBR  
ADS8401IBPFBT  
ADS8401IBPFBR  
48 Pin  
TQFP  
–40°C to  
85°C  
ADS8401I  
±6  
–2~3  
–1~2  
15  
16  
PFB  
PFB  
Tape and  
reel1000  
Tape and  
reel 250  
48 Pin  
TQFP  
–40°C to  
85°C  
ADS8401IB  
±3.5  
Tape and  
reel1000  
NOTE:  
For the most current specifications and package information, refer to our website at www.ti.com.  
ABSOLUTE MAXIMUM RATINGS  
overoperating free-air temperature range unless otherwise noted  
(1)  
UNIT  
+IN to AGND  
+VA + 0.1 V  
0.5 V  
Voltage  
–IN to AGND  
+VA to AGND  
–0.3 V to 7 V  
–0.3 V to 7 V  
+VBD to BDGND  
+VA to +VBD  
Voltagerange  
–0.3 V to 2.5 V  
–0.3 V to +VBD + 0.3 V  
–0.3 V to +VBD + 0.3 V  
–40°C to 85°C  
Digital input voltage to BDGND  
Digital output voltage to BDGND  
Operating free-air temperature range, T  
A
Storage temperature range, T  
stg  
–65°C to 150°C  
150°C  
Junctiontemperature(T max)  
J
Powerdissipation  
thermalimpedance  
(T Max – T )/θ  
J
A
JA  
TQFP package  
θ
86°C/W  
JA  
Vapor phase (60 sec)  
Infrared (15 sec)  
215°C  
220°C  
Leadtemperature,soldering  
(1)  
Stressesbeyondthoselistedunder“absolutemaximumratings”maycausepermanentdamagetothedevice. Thesearestressratingsonly,and  
functionaloperation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not  
implied.Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
2
ADS8401  
www.ti.com  
SLAS376B– DECEMBER 2002 – REVISED APRIL 2003  
SPECIFICATIONS  
A
T
= –40°C to 85°C, +VA = 5 V, +VBD = 3 V or 5 V, V = 4.096 V, f  
= 1.25 MHz (unless otherwise noted)  
ref  
SAMPLE  
TEST CONDITIONS  
PARAMETER  
MIN  
TYP  
MAX  
UNIT  
Analog Input  
Full-scale input voltage (see Note 1)  
+IN – –IN  
0
–0.2  
–0.2  
V
V
V
ref  
+IN  
V
ref  
+ 0.2  
0.2  
Absoluteinputvoltage  
–IN  
Inputcapacitance  
Input leakage current  
SystemPerformance  
Resolution  
25  
pF  
nA  
0.5  
16  
Bits  
Bits  
ADS8401I  
ADS8401IB  
ADS8401I  
ADS8401IB  
ADS8401I  
ADS8401IB  
ADS8401I  
ADS8401IB  
ADS8401I  
ADS8401IB  
15  
16  
No missing codes  
–6  
±2.5  
±2  
6
3.5  
Integral linearity (see Notes 2 and 3)  
Differentiallinearity  
LSB  
LSB  
–3.5  
–2  
±1  
3
–1 ±0.75  
2
–1.5  
±0.5  
–0.75 ±0.25  
–0.15  
1.5  
mV  
mV  
Offset error (see Note 4)  
0.75  
0.15  
0.098  
Gain error (see Notes 4 and 5)  
Noise  
%FS  
–0.098  
60  
µV RMS  
At FFFFh output code,  
+VA = 4.75 V to 5.25 V,  
Vref = 4.096 V, See Note 4  
DC Power supply rejection ratio  
2
LSB  
SamplingDynamics  
Conversiontime  
Acquisitiontime  
Throughputrate  
Aperturedelay  
610  
ns  
ns  
150  
1.25  
MHz  
ns  
2
25  
Aperturejitter  
ps  
Stepresponse  
100  
100  
ns  
Overvoltagerecovery  
ns  
(1)  
Ideal input span, does not include gain or offset error.  
LSB means least significant bit  
This is endpoint INL, not best fit.  
Measured relative to an ideal full-scale input (+IN – –IN) of 4.096 V  
This specification does not include the internal reference voltage error and drift.  
(2)  
(3)  
(4)  
(5)  
3
ADS8401  
www.ti.com  
SLAS376B – DECEMBER 2002 – REVISED APRIL 2003  
SPECIFICATIONS (CONTINUED)  
A
T
= –40°C to 85°C, +VA = +5 V, +VBD = 3 V or 5 V, V = 4.096 V, f  
= 1.25 MHz (unless otherwise noted)  
ref  
SAMPLE  
TEST CONDITIONS  
PARAMETER  
MIN  
TYP  
MAX  
UNIT  
DynamicCharacteristics  
Total harmonic distortion (THD) (see Note 1)  
Signal-to-noiseratio(SNR)  
V
IN  
V
IN  
V
IN  
V
IN  
= 4 V at 100 kHz  
pp  
–93  
86  
85  
93  
5
dB  
dB  
= 4 V at 100 kHz  
pp  
Signal-to-noise + distortion (SINAD)  
Spurious free dynamic range (SFDR)  
–3dB Small signal bandwidth  
= 4 V at 100 kHz  
pp  
dB  
= 4 V at 100 kHz  
pp  
dB  
MHz  
External Voltage Reference Input  
Reference voltage at REFIN, V  
ref  
2.5  
4.096  
500  
4.2  
V
Reference resistance (see Note 2)  
kΩ  
Internal Reference Output  
from 95% (+VA), with 1 µF storage  
capacitor  
Internal reference start-up time  
120  
ms  
V
range  
IOUT = 0  
4.065  
4.096  
4.13  
10  
V
µA  
ref  
Source Current  
LineRegulation  
Drift  
Static load  
+VA = 4.75 ~ 5.25 V  
IOUT = 0  
0.6  
36  
mV  
PPM/C  
DigitalInput/Output  
Logicfamily  
CMOS  
V
I
I
I
I
= 5 µA  
= 5 µA  
+VBD–1  
–0.3  
+VBD + 0.3  
0.8  
IH  
IH  
V
V
V
IL  
IL  
Logic level  
V
= 2 TTL loads  
= 2 TTL loads  
+VBD – 0.6  
0
+VBD  
0.4  
OH  
OL  
OH  
OL  
Straight  
Binary  
Dataformat  
PowerSupplyRequirements  
+VBD (see Notes 3 and 4)  
+VA (see Note 4)  
2.95  
4.75  
3.3  
5
5.25  
5.25  
34  
V
V
Power supply  
voltage  
+VA Supply current (see Note 5)  
Power dissipation (see Note 5)  
TemperatureRange  
f = 1.25 MHz  
31  
mA  
mW  
s
f = 1.25 MHz  
s
155  
Operatingfree-air  
–40  
85  
°C  
(1)  
Calculated on the first nine harmonics of the input frequency  
(2)  
(3)  
(4)  
(5)  
Can vary ±20%  
The difference between +VA and +VBD should not be less than 2.3 V, i.e., if +VA is 5.25 V, +VBD should be minimum of 2.95 V.  
+VBD ≥ +VA – 2.3 V  
This includes only VA+ current. +VBD current is typically 1 mA with 5 pF load capacitance on output pins.  
4
ADS8401  
www.ti.com  
SLAS376B – DECEMBER 2002 – REVISED APRIL 2003  
TIMING CHARACTERISTICS  
All specifications typical at –40°C to 85°C, +VA = +VBD = 5 V (see Notes 1, 2, and 3)  
PARAMETER  
MIN  
TYP  
MAX  
UNIT  
ns  
t
t
t
t
t
t
t
Conversiontime  
600  
610  
CONV  
ACQ  
pd1  
pd2  
w1  
Acquisitiontime  
150  
ns  
CONVST low to conversion started (BUSY high)  
Propagation delay time, End of conversion to BUSY low  
Pulse duration, CONVST low  
35  
20  
ns  
ns  
20  
0
ns  
Setup time, CS low to CONVST low  
Pulse duration, CONVST high  
CONVST falling edge jitter  
ns  
su1  
20  
ns  
w2  
10  
ps  
t
t
Pulse duration, BUSY signal low  
Pulse duration, BUSY signal high  
Min(t  
ACQ  
)
ns  
w3  
630  
ns  
w4  
Hold time, First data bus data transition (RD low, or CS low for read cycle, or BYTE input  
changes) after CONVST low  
t
h1  
40  
ns  
t
t
t
t
t
t
t
t
t
t
t
Delay time, CS low to RD low  
0
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
d1  
Setup time, RD high to CS high  
su2  
w5  
en  
Pulse duration, RD low time  
50  
Enable time, RD low (or CS low for read cycle) to data valid  
Delay time, data hold from RD high  
20  
20  
0
2
d2  
Delay time, BYTE rising edge or falling edge to data valid  
RD high  
d3  
20  
50  
w6  
h2  
Hold time, last RD (or CS for read cycle ) rising edge to CONVST falling edge  
Propagation delay time, BUSY falling edge to next RD (or CS for read cycle) falling edge  
Setup time, BYTE rising edge to RD falling edge  
Hold time, BYTE falling edge to RD falling edge  
Max(t  
)
d5  
pd4  
su3  
h3  
0
0
t
t
t
Disable time, RD High (CS high for read cycle) to 3-stated data bus  
Delay time, BUSY low to MSB data valid  
20  
0
ns  
ns  
ns  
dis  
d5  
Setup time, BYTE change before BUSY falling edge  
2
20  
su4  
(1)  
(2)  
(3)  
All input signals are specified with t = t = 5 ns (10% to 90% of +VBD) and timed from a voltage level of (V + V )/2.  
Seetimingdiagrams.  
All timings are measured with 20 pF equivalent loads on all data bits and BUSY pins.  
r
f
IL IH  
5
ADS8401  
www.ti.com  
SLAS376B– DECEMBER 2002 – REVISED APRIL 2003  
TIMING CHARACTERISTICS  
All specifications typical at –40°C to 85°C, +VA = 5 V, +VBD = 3 V (see Notes 1, 2, and 3)  
PARAMETER  
MIN  
TYP  
MAX  
UNIT  
t
t
t
t
t
t
t
Conversiontime  
600  
610  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ps  
ns  
ns  
CONV  
ACQ  
pd1  
pd2  
w1  
Acquisitiontime  
150  
CONVST low to conversion started (BUSY high)  
Propagation delay time, end of conversion to BUSY low  
Pulse duration, CONVST low  
40  
20  
20  
0
Setup time, CS low to CONVST low  
Pulse duration, CONVST high  
CONVST falling edge jitter  
su1  
20  
w2  
10  
t
t
Pulse duration, BUSY signal low  
Pulse duration, BUSY signal high  
Min(t )  
ACQ  
w3  
630  
w4  
Hold time, first data bus transition (RD low, or CS low for read cycle, or BYTE or BUS  
16/16input changes) after CONVST low  
t
h1  
40  
ns  
t
t
t
t
t
t
t
t
t
t
t
Delay time, CS low to RD low  
0
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
d1  
Setup time, RD high to CS high  
su2  
w5  
en  
Pulse duration, RD low  
50  
Enable time, RD low (or CS low for read cycle) to data valid  
Delay time, data hold from RD high  
30  
30  
0
2
d2  
Delay time, BUS16/16 or BYTE rising edge or falling edge to data valid  
Pulse duration, RD high time  
d3  
20  
50  
w6  
h2  
Hold time, last RD (or CS for read cycle ) rising edge to CONVST falling edge  
Propagation delay time, BUSY falling edge to next RD (or CS for read cycle) falling edge  
Setup time, BYTE rising edge to RD falling edge  
Hold time, BYTE falling edge to RD falling edge  
Max(td5)  
pd4  
su3  
h3  
0
0
t
t
t
Disable time, RD High (CS high for read cycle) to 3-stated data bus  
Delay time, BUSY low to MSB data valid delay time  
30  
0
ns  
ns  
ns  
dis  
d5  
Setup time, BYTE change before BUSY falling edge  
2
30  
su4  
(1)  
(2)  
(3)  
All input signals are specified with t = t = 5 ns (10% to 90% of +VBD) and timed from a voltage level of (V + V )/2.  
Seetimingdiagrams.  
All timings are measured with 10 pF equivalent loads on all data bits and BUSY pins.  
r
f
IL IH  
6
ADS8401  
www.ti.com  
SLAS376B– DECEMBER 2002 – REVISED APRIL 2003  
PIN ASSIGNMENTS  
PFB PACKAGE  
(TOP VIEW)  
36 35 34 33 32 31 30 29 28 27 26 25  
+VBD  
RESET  
BYTE  
CONVST  
RD  
+VBD  
DB8  
DB9  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
DB10  
DB11  
DB12  
DB13  
DB14  
DB15  
AGND  
AGND  
+VA  
CS  
+VA  
AGND  
AGND  
+VA  
REFM  
REFM  
1
2
3
4
5
6
7
8
9 10 11 12  
NC – No connection  
7
ADS8401  
www.ti.com  
SLAS376B– DECEMBER 2002 – REVISED APRIL 2003  
TERMINAL FUNCTIONS  
NAME  
AGND  
NO.  
I/O  
DESCRIPTION  
5, 8, 11, 12,  
–
Analogground  
14, 15, 44, 45  
BDGND  
BUSY  
BYTE  
25, 35  
36  
–
O
I
Digital ground for bus interface digital supply  
Status output. High when a conversion is in progress.  
39  
Byte select input. Used for 8-bit bus reading.  
0: No fold back  
1: Low byte D[7:0] of the 16 most significant bits is folded back to high byte of the 16 most significant  
pinsDB[15:8].  
CONVST  
CS  
40  
42  
I
I
Convert start  
Chip select  
8-Bit Bus  
16-Bit Bus  
BYTE = 0  
Data Bus  
BYTE = 0  
BYTE = 1  
DB15  
DB14  
DB13  
DB12  
DB11  
DB10  
DB9  
16  
17  
18  
19  
20  
21  
22  
23  
26  
27  
28  
29  
30  
31  
32  
33  
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
D15 (MSB)  
D14  
D13  
D12  
D11  
D10  
D9  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D15 (MSB)  
D14  
D13  
D12  
D11  
D10  
D9  
DB8  
D8  
D0 (LSB)  
D8  
DB7  
D7  
All ones  
All ones  
All ones  
All ones  
All ones  
All ones  
All ones  
All ones  
D7  
DB6  
D6  
D6  
DB5  
D5  
D5  
DB4  
D4  
D4  
DB3  
D3  
D3  
DB2  
D2  
D2  
DB1  
D1  
D1  
DB0  
D0 (LSB)  
D0 (LSB)  
–IN  
7
I
I
Invertinginputchannel  
Non inverting input channel  
Noconnection  
+IN  
6
NC  
3
–
I
REFIN  
REFM  
REFOUT  
1
47, 48  
2
Referenceinput  
I
Referenceground  
O
Reference output. Add 1 µF capacitor between the REFOUT pin and REFM pin when internal reference  
is used.  
RESET  
38  
41  
I
Current conversion is aborted and output latches are cleared (set to zeros) when this pin is asserted low.  
RESET works independantly of CS.  
RD  
I
Synchronization pulse for the parallel output.  
Analog power supplies, 5-V dc  
+VA  
4, 9, 10, 13,  
43, 46  
–
+VBD  
24, 34, 37  
–
Digital power supply for bus  
8
ADS8401  
www.ti.com  
SLAS376B – DECEMBER 2002 – REVISED APRIL 2003  
TIMING DIAGRAMS  
t
t
w2  
w1  
CONVST  
t
t
pd2  
pd1  
t
w4  
t
w3  
BUSY  
t
su1  
CS  
†
CONVERT  
t
(CONV)  
t
(CONV)  
†
SAMPLING  
(When CS Toggle)  
t
(ACQ)  
BYTE  
t
h1  
t
su2  
t
pd4  
t
h2  
t
d1  
RD  
t
t
en  
dis  
Hi–Z  
Hi–Z  
Hi–Z  
Hi–Z  
DB[15:8]  
DB[7:0]  
D [7:0]  
D [15:8]  
D [7:0]  
†
Signal internal to device  
Figure 1. Timing for Conversion and Acquisition Cycles With CS and RD Toggling  
9
ADS8401  
www.ti.com  
SLAS376B– DECEMBER 2002 – REVISED APRIL 2003  
t
w1  
t
w2  
CONVST  
t
t
pd2  
pd1  
t
w4  
t
w3  
BUSY  
t
su1  
CS  
†
CONVERT  
t
(CONV)  
t
(CONV)  
†
SAMPLING  
(When CS Toggle)  
t
(ACQ)  
BYTE  
t
h1  
t
pd4  
t
h2  
RD = 0  
t
en  
t
dis  
Hi–Z  
Hi–Z  
Hi–Z  
Hi–Z  
DB[15:8]  
D [15:8]  
D [7:0]  
D [7:0]  
DB[7:0]  
†
Signal internal to device  
Figure 2. Timing for Conversion and Acquisition Cycles With CS Toggling, RD Tied to BDGND  
10  
ADS8401  
www.ti.com  
CONVST  
SLAS376B– DECEMBER 2002 – REVISED APRIL 2003  
t
w1  
t
w2  
t
t
pd2  
pd1  
t
w4  
t
w3  
BUSY  
CS = 0  
†
CONVERT  
t
(CONV)  
t
(CONV)  
t
(ACQ)  
†
SAMPLING  
(When CS = 0)  
BYTE  
t
h1  
t
pd4  
t
h2  
RD  
t
t
en  
dis  
Hi–Z  
Hi–Z  
Hi–Z  
Hi–Z  
DB[15:8]  
D [15:8]  
D [7:0]  
D [7:0]  
DB[7:0]  
†
Signal internal to device  
Figure 3. Timing for Conversion and Acquisition Cycles With CS Tied to BDGND, RD Toggling  
11  
ADS8401  
www.ti.com  
SLAS376B– DECEMBER 2002 – REVISED APRIL 2003  
t
w2  
t
w1  
CONVST  
t
t
pd2  
pd1  
t
w4  
t
w3  
BUSY  
CS = 0  
†
CONVERT  
t
t
(CONV)  
(CONV)  
t
(ACQ)  
†
SAMPLING  
(When CS = 0)  
BYTE  
t
h1  
t
h1  
t
dis  
RD = 0  
t
d3  
t
d5  
DB[15:8]  
DB[7:0]  
Next D [15:8]  
Next D [7:0]  
Previous D [7:0]  
D [7:0]  
D [15:8]  
D [7:0]  
†
Signal internal to device  
Figure 4. Timing for Conversion and Acquisition Cycles With CS and RD Tied to BDGND—Auto Read  
CS  
RD  
BYTE  
t
en  
t
d3  
t
t
t
en  
dis  
dis  
Hi–Z  
Hi–Z  
Hi–Z  
Valid  
Valid  
Valid  
DB[15:0]  
Figure 5. Detailed Timing for Read Cycles  
12  
ADS8401  
www.ti.com  
SLAS376B– DECEMBER 2002 – REVISED APRIL 2003  
TYPICAL CHARACTERISTICS†  
SIGNAL-TO-NOISE RATIO  
vs  
FREE-AIR TEMPERATURE  
HISTOGRAM (DC Code Spread)  
NEAR FULL SCALE 98304 CONVERSIONS  
86.4  
86.2  
86  
40000  
35000  
30000  
25000  
20000  
15000  
10000  
5000  
f = 100 kHz  
i
+V = 5 V,  
A
Code = 65260  
(+IN– –IN) = Full Scale  
85.8  
85.6  
85.4  
85.2  
85  
0
–10  
5
20  
35  
50  
65  
80  
T
A
– Free-Air Temperature – °C  
Figure 6  
Figure 7  
SIGNAL-TO-NOISE PLUS DISTORTION  
SPURIOUS FREE-DYNAMIC RANGE  
vs  
vs  
FREE-AIR TEMPERATURE  
FREE-AIR TEMPERATURE  
85.4  
93.3  
93.2  
93.1  
93  
f = 100 kHz  
i
f = 100 kHz  
i
(+IN– –IN) = Full Scale  
(+IN– –IN) = Full Scale  
85.2  
85  
92.9  
92.8  
92.7  
84.8  
84.6  
92.6  
92.5  
92.4  
92.3  
92.2  
84.4  
84.2  
–10  
5
20  
35  
50  
65  
80  
–40  
–20  
0
20  
40  
60  
80  
T
A
– Free-Air Temperature – °C  
T
A
– Free-Air Temperature – °C  
Figure 8  
Figure 9  
†
At –40°C to 85°C, +VA = 5 V, +VBD = 5 V, REFIN = 4.096 V (internal reference used) and f  
= 1.25 MHz (unless otherwise noted)  
sample  
13  
ADS8401  
www.ti.com  
SLAS376B– DECEMBER 2002 – REVISED APRIL 2003  
SIGNAL-TO-NOISE RATIO  
vs  
TOTAL HARMONIC DISTORTION  
vs  
INPUT FREQUENCY  
FREE-AIR TEMPERATURE  
87.2  
87  
–92.2  
T
= 25°C  
f = 100 kHz  
(+IN– –IN) = Full Scale  
A
i
–92.3  
–92.4  
(+IN– –IN) = Full Scale  
–92.5  
–92.6  
86.8  
86.6  
–92.7  
–92.8  
86.4  
86.2  
–92.9  
–93  
–93.1  
86  
–93.2  
–93.3  
85.8  
0
20  
40  
60  
80  
100  
–40  
–10  
5
–25  
20  
35  
50  
65  
80  
f – Input Frequency – kHz  
i
T
A
– Free-Air Temperature – °C  
Figure 10  
Figure 11  
ENOB  
vs  
INPUT FREQUENCY  
SIGNAL-TO-NOISE PLUS DISTORTION  
vs  
INPUT FREQUENCY  
14.2  
14.15  
14.1  
87  
86.8  
86.6  
86.4  
T
= 25°C  
A
(+IN– –IN) = Full Scale  
14.05  
14  
86.2  
86  
85.8  
13.95  
13.9  
85.6  
85.4  
13.85  
13.8  
85.2  
85  
0
20  
40  
60  
80  
100  
0
20  
40  
60  
80  
100  
f – Input Frequency – kHz  
i
f – Input Frequency – kHz  
i
Figure 12  
Figure 13  
†
At –40°C to 85°C, +VA = 5 V, +VBD = 5 V, REFIN = 4.096 V (internal reference used) and f  
= 1.25 MHz (unless otherwise noted)  
sample  
14  
ADS8401  
www.ti.com  
SLAS376B– DECEMBER 2002 – REVISED APRIL 2003  
TOTAL HARMONIC DISTORTION  
SPURIOUS FREE-DYNAMIC RANGE  
vs  
vs  
INPUT FREQUENCY  
INPUT FREQUENCY  
–92  
–94  
–96  
–98  
106  
T
= 25°C  
A
(+IN– –IN) = Full Scale  
104  
102  
100  
98  
–100  
–102  
96  
T
A
= 25°C  
(+IN– –IN) = Full Scale  
–104  
–106  
94  
92  
0
20  
40  
60  
80  
100  
0
20  
40  
60  
80  
100  
f – Input Frequency – kHz  
i
f – Input Frequency – kHz  
i
Figure 15  
Figure 14  
GAIN ERROR  
vs  
SUPPLY CURRENT  
vs  
SUPPLY VOLTAGE  
SAMPLE RATE  
31.5  
T
A
= 25°C  
0.022  
0.019  
0.017  
Current of +VA only  
31  
30.5  
30  
29.5  
29  
28.5  
0.014  
0.012  
28  
T
= 25°C  
A
External Reference = 4.096 V (REFIN)  
27.5  
27  
4.75  
4.85  
4.95  
5.05  
5.15  
5.25  
250  
500  
750  
1000  
1250  
+V – Supply Voltage – V  
A
Sample Rate – KSPS  
Figure 16  
Figure 17  
†
At –40°C to 85°C, +VA = 5 V, +VBD = 5 V, REFIN = 4.096 V (internal reference used) and f  
= 1.25 MHz (unless otherwise noted)  
sample  
15  
ADS8401  
www.ti.com  
SLAS376B– DECEMBER 2002 – REVISED APRIL 2003  
INTERNAL REFERENCE VOLTAGE  
OFFSET ERROR  
vs  
SUPPLY VOLTAGE  
vs  
FREE-AIR TEMPERATURE  
4.104  
4.100  
4.096  
4.092  
0.14  
0.12  
0.10  
0.08  
0.06  
0.04  
T
= 25°C  
4.088  
4.084  
A
External Reference = 4.096 V (REFIN)  
0.02  
0
–40 –25 –10  
5
20  
35  
50  
65  
80  
4.75  
4.85  
4.95  
5.05  
5.15  
5.25  
T
– Free-Air Temperature – °C  
A
+V – Supply Voltage – V  
A
Figure 19  
Figure 18  
OFFSET ERROR  
vs  
GAIN ERROR  
vs  
FREE-AIR TEMPERATURE  
FREE-AIR TEMPERATURE  
0.028  
0.024  
0.019  
0.014  
0.009  
0.004  
0
0.30  
0.25  
0.20  
0.15  
0.10  
External Reference = 4.096 V (REFIN)  
External Reference = 4.096 V (REFIN)  
0.05  
0
–40 –25 –10  
5
20  
35  
50  
65  
80  
–40 –25 –10  
5
20  
35  
50  
65  
80  
T
A
– Free-Air Temperature – °C  
T
A
– Free-Air Temperature – °C  
Figure 20  
Figure 21  
†
At –40°C to 85°C, +VA = 5 V, +VBD = 5 V, REFIN = 4.096 V (internal reference used) and f  
= 1.25 MHz (unless otherwise noted)  
sample  
16  
ADS8401  
www.ti.com  
SLAS376B– DECEMBER 2002 – REVISED APRIL 2003  
DIFFERENTIAL NONLINEARITY (MAX)  
SUPPLY CURRENT  
vs  
FREE-AIR TEMPERATURE  
vs  
FREE-AIR TEMPERATURE  
1.24  
1.20  
1.16  
1.12  
1.08  
1.04  
1
31.4  
31.2  
31.0  
30.8  
External Reference = 4.096 V (REFIN)  
External Reference = 4.096 V (REFIN)  
Current of +VA Only  
30.6  
–40 –25 –10  
–40 –25 –10  
5
20  
35  
50  
65  
80  
5
20  
35  
50  
65  
80  
T
A
– Free-Air Temperature – °C  
T
A
– Free-Air Temperature – °C  
Figure 22  
Figure 23  
DIFFERENTIAL NONLINEARITY (MIN)  
INTEGRAL NONLINEARITY (MAX)  
vs  
vs  
FREE-AIR TEMPERATURE  
FREE-AIR TEMPERATURE  
2
1.6  
1.2  
0.8  
–0.72  
–0.76  
–0.80  
–0.84  
–0.88  
0.4  
0
External Reference = 4.096 V (REFIN)  
External Reference = 4.096 V (REFIN)  
–40 –25 –10  
5
20  
35  
50  
65  
80  
–40 –25 –10  
5
20  
35  
50  
65  
80  
T
A
– Free-Air Temperature – °C  
T
A
– Free-Air Temperature – °C  
Figure 24  
Figure 25  
†
At –40°C to 85°C, +VA = 5 V, +VBD = 5 V, REFIN = 4.096 V (internal reference used) and f  
= 1.25 MHz (unless otherwise noted)  
sample  
17  
ADS8401  
www.ti.com  
SLAS376B– DECEMBER 2002 – REVISED APRIL 2003  
INTEGRAL NONLINEARITY (MIN)  
vs  
INTEGRAL NONLINEARITY  
vs  
REFERENCE VOLTAGE  
FREE-AIR TEMPERATURE  
5
4
–2  
–2.4  
–2.8  
–3.2  
+V = +V  
= 5 V,  
A
BD  
T
= 25°C  
A
3
Max  
2
1
0
–1  
–2  
–3  
–4  
Min  
–3.6  
External Reference = 4.096 V (REFIN)  
–4  
–40 –25 –10  
5
20  
35  
50  
65  
80  
2.0  
2.5  
3.0  
3.5  
4.0  
4.5  
T
A
– Free-Air Temperature – °C  
V
ref  
– Reference Voltage – V  
Figure 26  
Figure 27  
DIFFERENTIAL NONLINEARITY  
vs  
REFERENCE VOLTAGE  
3.0  
2.5  
+V = +V  
= 5 V,  
A
BD  
T
= 25°C  
A
2.0  
Max  
1.5  
1.0  
0.5  
0.0  
Min  
–0.5  
–1.0  
2.0  
2.5  
3.0  
3.5  
4.0  
4.5  
V
ref  
– Reference Voltage – V  
Figure 28  
†
At –40°C to 85°C, +VA = 5 V, +VBD = 5 V, REFIN = 4.096 V (internal reference used) and f  
= 1.25 MHz (unless otherwise noted)  
sample  
18  
ADS8401  
www.ti.com  
SLAS376B– DECEMBER 2002 – REVISED APRIL 2003  
DNL  
1.2  
1
0.8  
0.6  
0.4  
0.2  
0
–0.2  
–0.4  
–0.6  
–0.8  
–1  
–1.2  
16384  
32768  
Code  
65536  
49152  
0
T
A
= 25°C, External Reference = 4.096 V (REFIN)  
Figure 29  
INL  
2.5  
2
1.5  
1
0.5  
0
–0.5  
–1  
–1.5  
–2  
–2.5  
16384  
0
32768  
Code  
49152  
65536  
T
A
= 25°C, External Reference = 4.096 V (REFIN)  
Figure 30  
FFT SPECTRUM RESPONSE  
0
–20  
–40  
–60  
–80  
–100  
–120  
–140  
–160  
–180  
–200  
300  
200  
400  
500  
600  
0
100  
Frequency – kHz  
32768Points, f = 1.25 MHz,  
S
Internal Reference = 4.096 V (REFIN),  
= 25°C, f = 100 kHz, (+IN– –IN) = Full Scale  
T
A
i
Figure 31  
†
At –40°C to 85°C, +VA = 5 V, +VBD = 5 V, REFIN = 4.096 V (internal reference used) and f  
= 1.25 MHz (unless otherwise noted)  
sample  
19  
ADS8401  
www.ti.com  
SLAS376B– DECEMBER 2002 – REVISED APRIL 2003  
APPLICATION INFORMATION  
MICROCONTROLLER INTERFACING  
ADS8401 to 8-Bit Microcontroller Interface  
Figure 32 shows a parallel interface between the ADS8401 and a typical microcontroller using the 8-bit data  
bus.  
The BUSY signal is used as a falling-edge interrupt to the microcontroller.  
Analog 5 V  
0.1 µF  
AGND  
10 µF  
Ext Ref Input  
0.1 µF  
1 µF  
Analog Input  
Micro  
Controller  
Digital 3 V  
ADS8401  
GPIO  
CS  
0.1 µF  
GPIO  
P[7:0]  
BYTE  
BDGND  
DB[15:8]  
RD  
CONVST  
BUSY  
BDGND  
RD  
GPIO  
INT  
+VBD  
Figure 32. ADS8401 Application Circuitry (using external reference)  
Analog 5 V  
AGND  
0.1 µF  
10 µF  
0.1 µF  
1 µF  
AGND  
ADS8401  
Figure 33. Use Internal Reference  
20  
ADS8401  
www.ti.com  
SLAS376B– DECEMBER 2002 – REVISED APRIL 2003  
PRINCIPLES OF OPERATION  
The ADS8401 is a high-speed successive approximation register (SAR) analog-to-digital converter (ADC). The  
architecture is based on charge redistribution, which inherently includes a sample/hold function. See Figure 32 for  
the application circuit for the ADS8401.  
The conversion clock is generated internally. The conversion time of 610 ns is capable of sustaining a 1.25-MHz  
throughput.  
The analog input is provided to two input pins: +IN and –IN. When a conversion is initiated, the differential input on  
these pins is sampled on the internal capacitor array. While a conversion is in progress, both inputs are disconnected  
from any internal function.  
REFERENCE  
The ADS8401 can operate with an external reference with a range from 2.5 V to 4.2 V. A 4.096-V internal reference  
is included. When internal reference is used, pin 2 (REFOUT) should be connected to pin 1 (REFIN) with an 0.1 µF  
decoupling capacitor and 1 µF storage capacitor between pin 2 (REFOUT) and pins 47 and 48 (REFM) (see Figure  
33). The internal reference of the converter is double buffered. If an external reference is used, the second buffer  
provides isolation between the external reference and the CDAC. This buffer is also used to recharge all of the  
capacitors of the CDAC during conversion. Pin 2 (REFOUT) can be left unconnected (floating) if external reference  
is used.  
ANALOG INPUT  
When the converter enters the hold mode, the voltage difference between the +IN and –IN inputs is captured on the  
internal capacitor array. The voltage on the –IN input is limited between –0.2 V and 0.2 V, allowing the input to reject  
small signals which are common to both the +IN and –IN inputs. The +IN input has a range of –0.2 V to V + 0.2  
ref  
V. The input span (+IN – (–IN)) is limited to 0 V to V  
.
ref  
The input current on the analog inputs depends upon a number of factors: sample rate, input voltage, and source  
impedance. Essentially, the current into the ADS8401 charges the internal capacitor array during the sample period.  
After this capacitance has been fully charged, there is no further input current. The source of the analog input voltage  
must be able to charge the input capacitance (25 pF) to an 16-bit settling level within the acquisition time (150 ns)  
of the device. When the converter goes into the hold mode, the input impedance is greater than 1 GΩ.  
Care must be taken regarding the absolute analog input voltage. To maintain the linearity of the converter, the +IN  
and –IN inputs and the span (+IN – (–IN)) should be within the limits specified. Outside of these ranges, the  
converter’s linearity may not meet specifications. To minimize noise, low bandwidth input signals with low-pass filters  
should be used.  
Care should be taken to ensure that the output impedance of the sources driving +IN and –IN inputs are matched.  
If this is not observed, the two inputs could have different setting time. This may result in offset error, gain error and  
linearity error which varies with temperature and input voltage.  
DIGITAL INTERFACE  
Timing And Control  
Seethetimingdiagramsinthespecificationssectionfordetailedinformationontimingsignalsandtheirrequirements.  
The ADS8401 uses an internal oscillator generated clock which controls the conversion rate and in turn the  
throughput of the converter. No external clock input is required.  
Conversions are initiated by bringing the CONVST pin low for a minimum of 20 ns (after the 20 ns minimum  
requirement has been met, the CONVST pin can be brought high), while CS is low. The ADS8401 switches from the  
sample to the hold mode on the falling edge of the CONVST command. A clean and low jitter falling edge of this signal  
is important to the performance of the converter. The BUSY output is brought high after CONVST goes low. BUSY  
stays high throughout the conversion process and returns low when the conversion has ended.  
21  
ADS8401  
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SLAS376B– DECEMBER 2002 – REVISED APRIL 2003  
Sampling starts with the falling edge of the BUSY signal when CS is tied low or starts with the falling edge of CS when  
BUSY is low.  
Both RD and CS can be high during and before a conversion with one exception (CS must be low when CONVST  
goes low to initiate a conversion). Both the RD and CS pins are brought low in order to enable the parallel output bus  
with the conversion.  
Reading Data  
The ADS8401outputsfullparalleldatainstraightbinaryformatasshowninTable 1. The parallel output is activewhen  
CS and RD are both low. There is a minimal quiet zone requirement around the falling edge of CONVST. This is 100  
ns prior to the falling edge of CONVST and 40 ns after the falling edge. No data read should be attempted within this  
zone. Any other combination of CS and RD sets the parallel output to 3-state. BYTE is used for multiword read  
operations. BYTE is used whenever lower bits of the converter result are output on the higher byte of the bus. Refer  
to Table 1 for ideal output codes.  
Table 1. Ideal Input Voltages and Output Codes  
DESCRIPTION  
FULL SCALE RANGE  
Least significant bit (LSB)  
Full scale  
ANALOG VALUE  
DIGITAL OUTPUT STRAIGHT BINARY  
V
ref  
V
/65536  
– 1 LSB  
/2  
BINARY CODE  
HEX CODE  
FFFF  
ref  
V
1111 1111 1111 1111  
1000 0000 0000 0000  
0111 1111 1111 1111  
0000 0000 0000 0000  
ref  
Midscale  
V
8000  
ref  
Midscale – 1 LSB  
Zero  
V
/2 – 1 LSB  
ref  
0 V  
7FFF  
0000  
The output data is a full 16-bit word (D15–D0) on DB15–DB0 pins (MSB–LSB) if BYTE is low.  
The result may also be read on an 8-bit bus for convenience. This is done by using only pins DB15–DB8. In this case  
two reads are necessary: the first as before, leaving BYTE low and reading the 8 most significant bits on pins  
DB15–DB8, then bringing BYTE high. When BYTE is high, the low bits (D7–D0) appear on pins DB15–D8.  
These multiword read operations can be done with multiple active RD (toggling) or with RD tied low for simplicity.  
DATA READ OUT  
BYTE  
DB15–DB8  
D7–D0  
DB7–DB0  
All one’s  
D7–D0  
High  
Low  
D15–D8  
RESET  
RESET is an asynchronous active low input signal (that works independently of CS). Minimum RESET low time is  
20 ns. Current conversion will be aborted no later than 50 ns after the converter is in the reset mode. In addition, all  
output latches are cleared (set to zero’s) after RESET. The converter goes back to normal operation mode no later  
than 20 ns after RESET input is brought high.  
The converter starts the first sampling period 20 ns after the rising edge of RESET. Any sampling period except for  
the one immediately after a RESET is started with the falling edge of the previous BUSY signal or the falling edge  
of CS, whichever is later.  
POWER-ON INITIALIZATION  
One RESET pulse followed by three conversion cycles must be given to the converter after powerup to ensure proper  
operation. The next pulse can be issued once both +VA and +VBD reach 95% of the minimum required value.  
22  
ADS8401  
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SLAS376B– DECEMBER 2002 – REVISED APRIL 2003  
LAYOUT  
For optimum performance, care should be taken with the physical layout of the ADS8401 circuitry.  
As the ADS8401 offers single-supply operation, it is often used in close proximity with digital logic, microcontrollers,  
microprocessors, and digital signal processors. The more digital logic present in the design and the higher the  
switching speed, the more difficult it is to achieve good performance from the converter.  
The basic SAR architecture is sensitive to glitches or sudden changes on the power supply, reference, ground  
connections and digital inputs that occur just prior to latching the output of the analog comparator. Thus, driving any  
single conversion for an n-bit SAR converter, there are at least n windows in which large external transient voltages  
can affect the conversion result. Such glitches might originate from switching power supplies, nearby digital logic,  
or high power devices.  
The degree of error in the digital output depends on the reference voltage, layout, and the exact timing of the external  
event.  
On average, the ADS8401 draws very little current from an external reference, as the reference voltage is internally  
buffered. If the reference voltage is external and originates from an op amp, make sure that it can drive the bypass  
capacitor or capacitors without oscillation. A 0.1-µF bypass capacitor and a1-µFstoragecapacitorarerecommended  
from pin 1 (REFIN) directly to pin 48 (REFM). REFM and AGND should be shorted on the same ground plane under  
the device.  
The AGND and BDGND pins should be connected to a clean ground point. In all cases, this should be the analog  
ground. Avoid connections which are close to the grounding point of a microcontroller or digital signal processor. If  
required, run a ground trace directly from the converter to the power supply entry point. The ideal layout consists of  
an analog ground plane dedicated to the converter and associated analog circuitry.  
As with the AGND connections, +VA should be connected to a 5-V power supply plane or trace that is separate from  
the connection for digital logic until they are connected at the power entry point. Power to the ADS8401 should be  
clean and well bypassed. A 0.1-µF ceramic bypass capacitor should be placed as close to the device as possible.  
See Table 2 for the placement of the capacitor. In addition, a 1-µF to 10-µF capacitor is recommended. In some  
situations, additional bypassing may be required, such as a 100-µF electrolytic capacitor or even a Pi filter made up  
of inductors and capacitors—all designed to essentially low-pass filter the 5-V supply, removing the high frequency  
noise.  
Table 2. Power Supply Decoupling Capacitor Placement  
POWER SUPPLY PLANE  
CONVERTER ANALOG SIDE  
CONVERTER DIGITAL SIDE  
SUPPLY PINS  
Pin pairs that require shortest path to decoupling capacitors  
Pins that require no decoupling  
(4,5), (8,9), (10,11), (13,15),  
(43,44),(45,46)  
(24,25), (34, 35)  
37  
12, 14  
23  
MECHANICAL DATA  
MTQF019A – JANUARY 1995 – REVISED JANUARY 1998  
PFB (S-PQFP-G48)  
PLASTIC QUAD FLATPACK  
0,27  
0,17  
0,50  
M
0,08  
36  
25  
37  
24  
48  
13  
0,13 NOM  
1
12  
5,50 TYP  
7,20  
SQ  
Gage Plane  
6,80  
9,20  
SQ  
8,80  
0,25  
0,05 MIN  
0°–7°  
1,05  
0,95  
0,75  
0,45  
Seating Plane  
0,08  
1,20 MAX  
4073176/B 10/96  
NOTES: A. All linear dimensions are in millimeters.  
B. This drawing is subject to change without notice.  
C. Falls within JEDEC MS-026  
1
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ADS8401IBPFBR 相关器件

型号 制造商 描述 价格 文档
ADS8401IBPFBRG4 TI 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, PARALLEL ACCESS, PQFP48, GREEN, PLASTIC, TQFP-48 获取价格
ADS8401IBPFBT BB 16-BIT, 1.25 MSPS, UNIPOLAR INPUT, MICRO POWER SAMPLING ANALOG-TODIGITAL CONVERTER WITH PARALLEL INTERFACE AND REFERENCE 获取价格
ADS8401IBPFBT TI 最高分辨率:16;最大数据速率:1.25M;元器件封装:48-TQFP; 获取价格
ADS8401IBPFBTG4 TI 16 Bit 1.25MSPS Parallel ADC W Ref 48-TQFP -40 to 85 获取价格
ADS8401IPFBR BB 16-BIT, 1.25 MSPS, UNIPOLAR INPUT, MICRO POWER SAMPLING ANALOG-TODIGITAL CONVERTER WITH PARALLEL INTERFACE AND REFERENCE 获取价格
ADS8401IPFBR TI 16 Bit 1.25MSPS Parallel ADC W Ref 48-TQFP -40 to 85 获取价格
ADS8401IPFBT BB 16-BIT, 1.25 MSPS, UNIPOLAR INPUT, MICRO POWER SAMPLING ANALOG-TODIGITAL CONVERTER WITH PARALLEL INTERFACE AND REFERENCE 获取价格
ADS8401IPFBT TI 16 Bit 1.25MSPS Parallel ADC W Ref 48-TQFP -40 to 85 获取价格
ADS8401IPFBTG4 TI 16 Bit 1.25MSPS Parallel ADC W Ref 48-TQFP -40 to 85 获取价格
ADS8402 BB 16-BIT, 1.25 MSPS, UNIPOLAR DIFFERENTIAL INPUT, MICRO POWER SAMPLING ANALOG-TO-DIGITAL CONVERTER WITH PARALLEL INTERFACE AND REFERENCE 获取价格

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