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CAT24WC66XA-1.8REVC

更新时间：2025-07-13 00:37:17

品牌：CATALYST

描述：EEPROM, 8KX8, Serial, CMOS, PDSO8, LEAD FREE AND HALOGEN FREE, EIAJ, SOIC-8

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CAT24WC66XA-1.8REVC 概述

EEPROM, 8KX8, Serial, CMOS, PDSO8, LEAD FREE AND HALOGEN FREE, EIAJ, SOIC-8

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CAT24WC66

64K-Bit I²C Serial CMOS EEPROM

FEATURES

■ 400 kHz I²C bus compatible*

■ Commercial, industrial and automotive

temperature ranges

■ 1.8 to 6 volt read and write operation

■ Cascadable for up to eight devices

■ 32-byte page write buffer

■ Write protection

–Top 1/4 array protected when WP at V_IH

■ 1,000,000 program/erase cycles

■ 100 year data retention

■ Self-timed write cycle with auto-clear

■ Schmitt trigger inputs for noise protection

■ 8-pin DIP or 8-pin SOIC packages

DESCRIPTION

The CAT24WC66 is a 64K-bit Serial CMOS EEPROM

internally organized as 8192 words of 8 bits each.

Catalyst’s advanced CMOS technology substantially

reduces device power requirements. The

CAT24WC66 features a 32-byte page write buffer. The

device operates via the I²C bus serial interface and is

available in 8-pin DIP or 8-pin SOIC packages.

PIN CONFIGURATION

BLOCK DIAGRAM

DIP Package (P, L)

EXTERNAL LOAD

SENSE AMPS

SHIFT REGISTERS

OUT

ACK

SCL

SDA

WORD ADDRESS

BUFFERS

COLUMN

DECODERS

256

START/STOP

SOIC Package (J, K, W, X)

SDA

LOGIC

EEPROM

256 X 256

XDEC 256

SCL

SDA

CONTROL

LOGIC

PIN FUNCTIONS

Pin Name

Function

DATA IN STORAGE

A0, A1, A2

SDA

Device Address Inputs

Serial Data/Address

Serial Clock

HIGH VOLTAGE/

TIMING CONTROL

SCL

STATE COUNTERS

Write Protect

V_CC

+1.8V to +6V Power Supply

Ground

SLAVE

ADDRESS

COMPARATORS

V_SS

* Catalyst Semiconductor is licensed by Philips Corporation to carry the I C Bus Protocol.

Doc. No. 1037, Rev. H

Characteristics subject to change without notice

CAT24WC66

Lead Soldering Temperature (10 secs) ............ 300°C

ABSOLUTE MAXIMUM RATINGS*

Output Short Circuit Current⁽²⁾........................ 100mA

Temperature Under Bias ................. –55°C to +125°C

Storage Temperature....................... –65°C to +150°C

*COMMENT

Voltage on Any Pin with

Stresses above those listed under “Absolute Maximum Ratings” may

cause permanent damage to the device. These are stress ratings only,

and functional operation of the device at these or any other conditions

outsideofthoselistedintheoperationalsectionsofthisspecificationisnot

implied. Exposure to any absolute maximum rating for extended periods

may affect device performance and reliability.

Respect to Ground⁽¹⁾........... –2.0V to +V_CC+ 2.0V

V_CCwith Respect to Ground ............... –2.0V to +7.0V

Package Power Dissipation

Capability (T_A= 25°C) ................................... 1.0W

RELIABILITY CHARACTERISTICS

Symbol

NEND⁽³⁾

TDR⁽³⁾

Parameter

Reference Test Method

MIL-STD-883, Test Method 1033

MIL-STD-883, Test Method 1008

MIL-STD-883, Test Method 3015

JEDEC Standard 17

Min

1,000,000

100

Max

Units

Cycles/Byte

Years

Endurance

Data Retention

ESD Susceptibility

Latch-up

VZAP⁽³⁾

ILTH⁽³⁾⁽⁴⁾

2000

Volts

100

D.C. OPERATING CHARACTERISTICS

= +1.8V to +6.0V, unless otherwise specified.

Symbol

Parameter

Test Conditions

f_SCL= 100 kHz

Min

Typ

Max

Units

µA

I_CC

Power Supply Current

Standby Current (VCC = 5V)

Input Leakage Current

Output Leakage Current

Input Low Voltage

(5)

I_SB

V_IN= GND or V_CC

V_IN= GND to V_CC

V_OUT= GND to V_CC

I_LI

I_LO

V_IL

V_IH

-1

V_CCx 0.3

V_CC+ 0.5

Input High Voltage

V_CCx 0.7

Output Low Voltage

(V_CC= +3.0V)

V_OL1

V_OL2

I_OL= 3.0 mA

I_OL= 1.5 mA

0.4

0.5

Output Low Voltage

(V_CC= +1.8V)

CAPACITANCE T = 25°C, f = 1.0 MHz, V

= 5V

Symbol

Parameter

Conditions

Min

Typ

Max

Units

Input/Output Capacitance

(SDA)

(3)

C_I/O

V_I/O= 0V

Input Capacitance

(A0, A1, A2, SCL, WP)

(3)

C_IN

V_IN= 0V

Note:

(1) The minimum DC input voltage is –0.5V. During transitions, inputs may undershoot to –2.0V for periods of less than 20 ns. Maximum DC

voltage on output pins is V +0.5V, which may overshoot to V + 2.0V for periods of less than 20ns.

(2) Output shorted for no more than one second. No more than one output shorted at a time.

(3) This parameter is tested initially and after a design or process change that affects the parameter.

(4) Latch-up protection is provided for stresses up to 100 mA on address and data pins from –1V to V +1V.

(5) Maximum standby current (I ) = 10µA for the Automotive and Extended Automotive temperature range.

Doc. No. 1037, Rev. H

CAT24WC66

A.C. CHARACTERISTICS

= +1.8V to +6V, unless otherwise specified

Output Load is 1 TTL Gate and 100pF

Read & Write Cycle Limits

1.8V - 2.5V

4.5V - 5.5V

Symbol

Parameter

Units

Min

Max

Min

Max

FSCL

T_I⁽¹⁾

Clock Frequency

100

200

400

200

kHz

Noise Suppression Time Constant at

SCL, SDA Inputs

SCL Low to SDA Data Out and

ACK Out

t_AA

3.5

µs

Time the Bus Must be Free Before a

New Transmission Can Start

(1)

t_BUF

4.7

1.2

t_HD:STA

t_LOW

Start Condition Hold Time

Clock Low Period

4.7

0.6

1.2

0.6

µs

t_HIGH

Clock High Period

Start Condition Setup Time (for a

Repeated Start Condition)

t_SU:STA

4.7

0.6

µs

t_HD:DAT

t_SU:DAT

Data In Hold Time

µs

Data In Setup Time

(1)

t_R

SDA and SCL Rise Time

SDA and SCL Fall Time

Stop Condition Setup Time

0.3

(1)

t_F

300

t_SU:STO

t_DH

0.6

Data Out Hold Time

100

(1)(2)

Power-Up Timing

Symbol

t_PUR

Parameter

Min

Typ

Max

Units

Power-Up to Read Operation

Power-Up to Write Operation

t_PUW

Note:

(1) This parameter is tested initially and after a design or process change that affects the parameter.

(2) t and t are the delays required from the time V is stable until the specified operation can be initiated.

PUR

PUW

Write Cycle Limits

Symbol

Parameter

Min

Typ

Max

Units

t_WR

Write Cycle Time

The write cycle time is the time from a valid stop

condition of a write sequence to the end of the internal

program/erase cycle. During the write cycle, the bus

interface circuits are disabled, SDA is allowed to remain

high, and the device does not respond to its slave

address.

Doc. No. 1037, Rev. H

CAT24WC66

FUNCTIONAL DESCRIPTION

TheCAT24WC66supportstheI²CBusdatatransmission

protocol.ThisInter-IntegratedCircuitBusprotocoldefines

any device that sends data to the bus to be a transmitter

and any device receiving data to be a receiver. The

transfer is controlled by the Master device which

generates the serial clock and all START and STOP

conditions for bus access. The CAT24WC66 operates

as a Slave device. Both the Master device and Slave

device can operate as either transmitter or receiver, but

the Master device controls which mode is activated.

transfer all data into and out of the device. The SDA pin

is an open drain output and can be wire-ORed with other

open drain or open collector outputs.

A0, A1, A2: Device Address Inputs

These pins are hardwired or left unconnected (for

hardware compatibility with CAT24WC16). When

hardwired, up to eight CAT24WC66 devices may be

addressed on a single bus system (refer to Device

Addressing ). When the pins are left unconnected, the

default values are zeros.

WP: Write Protect

PIN DESCRIPTIONS

This input, when tied to GND, allows write operations to

the entire memory. When this pin is tied to Vcc, the top

1/4 array of memory is write protected. When left

floating, memory is unprotected.

SCL: Serial Clock

The serial clock input clocks all data transferred into or

out of the device.

SDA: Serial Data/Address

The bidirectional serial data/address pin is used to

HIGH

Figure 1. Bus Timing

LOW

SCL

HD:DAT

SU:STA

HD:STA

SU:DAT

SU:STO

BUF

SDA IN

SDA OUT

Figure 2. Write Cycle Timing

SCL

SDA

8TH BIT

BYTE n

ACK

STOP

CONDITION

START

CONDITION

ADDRESS

Figure 3. Start/Stop Timing

SDA

SCL

START BIT

STOP BIT

Doc. No. 1037, Rev. H

CAT24WC66

I²C BUS PROTOCOL

to the hardwired input pins, A2, A1 and A0. The last bit

of the slave address specifies whether a Read or Write

operation is to be performed. When this bit is set to 1, a

Read operation is selected, and when set to 0, a Write

operation is selected.

The features of the I²C bus protocol are defined as

follows:

(1) Data transfer may be initiated only when the bus is

not busy.

After the Master sends a START condition and the slave

address byte, the CAT24WC66 monitors the bus and

responds with an acknowledge (on the SDA line) when

its address matches the transmitted slave address. The

CAT24WC66 then performs a Read or Write operation

depending on the state of the R/W bit.

(2) During a data transfer, the data line must remain

stablewhenevertheclocklineishigh.Anychanges

in the data line while the clock line is high will be

interpreted as a START or STOP condition.

START Condition

Acknowledge

The START Condition precedes all commands to the

device, and is defined as a HIGH to LOW transition of

SDAwhenSCLisHIGH. TheCAT24WC66monitorsthe

SDA and SCL lines and will not respond until this

condition is met.

Afterasuccessfuldatatransfer, eachreceivingdeviceis

requiredtogenerateanacknowledge.TheAcknowledg-

ing device pulls down the SDA line during the ninth clock

cycle, signaling that it received the 8 bits of data.

The CAT24WC66 responds with an acknowledge after

receivingaSTARTconditionanditsslaveaddress. Ifthe

device has been selected along with a write operation,

it responds with an acknowledge after receiving each 8-

bit byte.

STOP Condition

A LOW to HIGH transition of SDA when SCL is HIGH

determinestheSTOPcondition.Alloperationsmustend

with a STOP condition.

When the CAT24WC66 begins a READ mode it trans-

mits 8 bits of data, releases the SDA line, and monitors

the line for an acknowledge. Once it receives this ac-

knowledge, the CAT24WC66 will continue to transmit

data. IfnoacknowledgeissentbytheMaster, thedevice

terminates data transmission and waits for a STOP

condition. The master must then issue a stop condition

to return the CAT24WC66 to the standby power mode

and place the device in a known state.

DEVICE ADDRESSING

The bus Master begins a transmission by sending a

START condition. The Master sends the address of the

particular slave device it is requesting. The four most

significant bits of the 8-bit slave address are fixed as

1010 (Fig. 5). The next three bits (A2, A1, A0) are the

device address bits; up to eight 64K devices may to be

connected to the same bus. These bits must compare

Figure 4. Acknowledge Timing

SCL FROM

MASTER

DATA OUTPUT

FROM TRANSMITTER

DATA OUTPUT

FROM RECEIVER

START

ACKNOWLEDGE

Figure 5. Slave Address Bits

A0 R/W

Doc. No. 1037, Rev. H

CAT24WC66

IftheMastertransmitsmorethan32bytesbeforesending

the STOP condition, the address counter ‘wraps around’,

and previously transmitted data will be overwritten.

WRITE OPERATIONS

Byte Write

In the Byte Write mode, the Master device sends the

START condition and the slave address information

(with the R/W bit set to zero) to the Slave device. After

the Slave generates an acknowledge, the Master sends

two 8-bit address words that are to be written into the

address pointers of the CAT24WC66. After receiving

another acknowledge from the Slave, the Master device

transmits the data to be written into the addressed

memorylocation.TheCAT24WC66acknowledgesonce

more and the Master generates the STOP condition. At

this time, the device begins an internal programming

cycle to nonvolatile memory. While the cycle is in

progress, thedevicewillnotrespondtoanyrequestfrom

the Master device.

When all 32 bytes are received, and the STOP condition

has been sent by the Master, the internal programming

cycle begins. At this point, all received data is written to

the CAT24WC66 in a single write cycle.

Acknowledge Polling

Disabling of the inputs can be used to take advantage of

the typical write cycle time. Once the stop condition is

issued to indicate the end of the host's write operation,

CAT24WC66 initiates the internal write cycle. ACK

pollingcanbeinitiatedimmediately.Thisinvolvesissuing

the start condition followed by the slave address for a

writeoperation. IfCAT24WC66isstillbusywiththewrite

operation, no ACK will be returned. If

CAT24WC66 has completed the write operation, an

ACK will be returned and the host can then proceed with

the next read or write operation.

Page Write

The CAT24WC66 writes up to 32 bytes of data, in a

single write cycle, using the Page Write operation. The

page write operation is initiated in the same manner as

the byte write operation, however instead of terminating

after the initial byte is transmitted, the Master is allowed

to send up to 31 additional bytes. After each byte has

been transmitted, CAT24WC66 will respond with an

acknowledge,andinternallyincrementthefiveloworder

address bits by one. The high order bits remain

unchanged.

WRITE PROTECTION

The Write Protection feature allows the user to protect

against inadvertent programming of the memory array.

If the WP pin is tied to V_CC, the top 1/4 of the memory

array (locations 1800H to 1FFF) is protected and

Figure 6. Byte Write Timing

BUS ACTIVITY:

MASTER

SLAVE

ADDRESS

BYTE ADDRESS

–A

A –A

DATA

SDA LINE

X X X

Figure 7. Page Write Timing

BUS ACTIVITY:

MASTER

SLAVE

ADDRESS

BYTE ADDRESS

–A A –A

DATA

DATA n

DATA n+31

SDA LINE

X X X

* = Don't care bit for 24WC33

X= Don't care bit

Doc. No. 1037, Rev. H

CAT24WC66

becomes read only. The CAT24WC66 will accept both

slave and byte addresses, but the memory location

accessedisprotectedfromprogrammingbythedevice’s

failuretosendanacknowledgeafterthefirstbyteofdata

is received.

tion, slave address and byte addresses of the location it

wishes to read. After CAT24WC66 acknowledges, the

MasterdevicesendstheSTARTconditionandtheslave

address again, this time with the R/W bit set to one. The

CAT24WC66 then responds with its acknowledge and

sends the 8-bit byte requested. The master device does

not send an acknowledge but will generate a STOP

condition.

READ OPERATIONS

The READ operation for the CAT24WC66 is initiated in

the same manner as the write operation with one excep-

tion, that R/W bit is set to one. Three different READ

operations are possible: Immediate/Current Address

READ,Selective/RandomREADandSequentialREAD.

Sequential Read

The Sequential READ operation can be initiated by

either the Immediate Address READ or Selective READ

operations. After the CAT24WC66 sends the initial 8-bit

byte requested, the Master will respond with an ac-

knowledge which tells the device it requires more data.

TheCAT24WC66willcontinuetooutputan8-bitbytefor

each acknowledge sent by the Master. The operation

will terminate when the Master fails to respond with an

acknowledge, thus sending the STOP condition.

Immediate/Current Address Read

The CAT24WC66’s address counter contains the ad-

dress of the last byte accessed, incremented by one. In

other words, if the last READ or WRITE access was to

address N, the READ immediately following would ac-

cess data from address N+1. If N=E (where E=8191),

then the counter will ‘wrap around’ to address 0 and

continue to clock out data. After the CAT24WC66 re-

ceivesitsslaveaddressinformation(withtheR/W bitset

to one), it issues an acknowledge, then transmits the 8

bit byte requested. The master device does not send an

acknowledge, but will generate a STOP condition.

The data being transmitted from CAT24WC66 is output-

ted sequentially with data from address N followed by

data from address N+1. The READ operation address

counter increments all of the CAT24WC66 address bits

so that the entire memory array can be read during one

operation. IfmorethanE(whereE=8191)bytesareread

out, the counter will ‘wrap around’ and continue to clock

out data bytes.

Selective/Random Read

Selective/Random READ operations allow the Master

device to select at random any memory location for a

READ operation. The Master device first performs a

‘dummy’ write operation by sending the START condi-

Figure 8. Immediate Address Read Timing

BUS ACTIVITY:

MASTER

SLAVE

ADDRESS

DATA

SDA LINE

SCL

SDA

8TH BIT

DATA OUT

NO ACK

STOP

Doc. No. 1037, Rev. H

CAT24WC66

Figure 9. Selective Read Timing

BUS ACTIVITY:

MASTER

SLAVE

ADDRESS

BYTE ADDRESS

SLAVE

ADDRESS

–A

A –A

DATA

SDA LINE

X X X

X= Don't care bit

Figure 10. Sequential Read Timing

BUS ACTIVITY:

MASTER

SLAVE

ADDRESS

DATA n

DATA n+1

DATA n+2

DATA n+x

SDA LINE

Doc. No. 1037, Rev. H

CAT24WC66

ORDERING INFORMATION

Prefix

Device #

Suffix

Rev C⁽²⁾

-1.8

TE13

CAT

24WC66

Temperature Range

Blank = Commercial (0˚ to 70˚C)

Product

Number

Tape & Reel

Optional

Company ID

I = Industrial (-40˚ to 85˚C)

A = Automotive (-40˚ to 105˚C)

E = Extended Automotive (-40˚ to 125˚C)

Die Revision

Package

Operating Voltage

Blank: 2.5V - 6.0V

1.8: 1.8V - 6.0V

P: PDIP

K: SOIC (EIAJ)

J: SOIC (JEDEC)

L: PDIP (Lead free, Halogen free)

W: SOIC (JEDEC, Lead free, Halogen free)

X: SOIC (EIAJ, Lead free, Halogen free)

Notes:

(1) The device used in the above example is a 24WC66JI-1.8TE13 (SOIC, Industrial Temperature, 1.8 Volt to 6 Volt Operating

Voltage, Tape & Reel)

(2) Product die revision letter is marked on top of the package as a suffix to the production date code (e.g. AYWWC). For additional

information, please contact your Catalyst sales office.

Doc. No. 1037, Rev. H

REVISION HISTORY

Date

Rev.

Reason

3/4/2004

04/03/04

Added Commercial temp range in all areas

Update Pin Configuration

Update Ordering Information

Eliminate data sheet designation

7/22/2004

8/3/2004

Added Die Revision to Ordering Information

Update Features

Update DC Operating Characteristics table & notes

03/10/2005

Update Ordering Information

Copyrights, Trademarks and Patents

Trademarks and registered trademarks of Catalyst Semiconductor include each of the following:

DPP ™

AE ™

Catalyst Semiconductor has been issued U.S. and foreign patents and has patent applications pending that protect its products. For a complete list of patents

issued to Catalyst Semiconductor contact the Company’s corporate office at 408.542.1000.

CATALYST SEMICONDUCTOR MAKES NO WARRANTY, REPRESENTATION OR GUARANTEE, EXPRESS OR IMPLIED, REGARDING THE SUITABILITY OF ITS

PRODUCTS FOR ANY PARTICULAR PURPOSE, NOR THAT THE USE OF ITS PRODUCTS WILL NOT INFRINGE ITS INTELLECTUAL PROPERTY RIGHTS OR THE

RIGHTS OF THIRD PARTIES WITH RESPECT TO ANY PARTICULAR USE OR APPLICATION AND SPECIFICALLY DISCLAIMS ANY AND ALL LIABILITY ARISING

OUT OF ANY SUCH USE OR APPLICATION, INCLUDING BUT NOT LIMITED TO, CONSEQUENTIAL OR INCIDENTAL DAMAGES.

Catalyst Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or

other applications intended to support or sustain life, or for any other application in which the failure of the Catalyst Semiconductor product could create a

situation where personal injury or death may occur.

Catalyst Semiconductor reserves the right to make changes to or discontinue any product or service described herein without notice. Products with data sheets

labeled "Advance Information" or "Preliminary" and other products described herein may not be in production or offered for sale.

Catalyst Semiconductor advises customers to obtain the current version of the relevant product information before placing orders. Circuit diagrams illustrate

typical semiconductor applications and may not be complete.

Catalyst Semiconductor, Inc.

Corporate Headquarters

1250 Borregas Avenue

Sunnyvale, CA 94089

Publication #: 1037

Phone: 408.542.1000

Revison:

Fax: 408.542.1200

Issue date:

03/10/05

www.catalyst-semiconductor.com

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