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B9688AYB

更新时间：2025-07-05 18:57:35
品牌：CYPRESS
描述：Low Skew Clock Driver, 18 True Output(s), 0 Inverted Output(s), PDSO48, SSOP-48

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免费 PCB/SMT

B9688AYB 概述

Low Skew Clock Driver, 18 True Output(s), 0 Inverted Output(s), PDSO48, SSOP-48 时钟驱动器

B9688AYB 规格参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：SSOP
包装说明：SSOP, SSOP48,.4针数：48
Reach Compliance Code：compliantHTS代码：8542.39.00.01
风险等级：5.92输入调节：STANDARD
JESD-30 代码：R-PDSO-G48JESD-609代码：e0
长度：15.875 mm逻辑集成电路类型：LOW SKEW CLOCK DRIVER
湿度敏感等级：1功能数量：1
反相输出次数：端子数量：48
实输出次数：18最高工作温度：70 °C
最低工作温度：输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：SSOP
封装等效代码：SSOP48,.4封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, SHRINK PITCH峰值回流温度（摄氏度）：220
电源：3.3 VProp。Delay @ Nom-Sup：5 ns
认证状态：Not QualifiedSame Edge Skew-Max（tskwd）：0.25 ns
座面最大高度：2.794 mm子类别：Clock Drivers
最大供电电压 (Vsup)：3.465 V最小供电电压 (Vsup)：3.135 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子节距：0.635 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：7.5 mm最小 fmax：100 MHz
Base Number Matches：1

B9688AYB 数据手册

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B9688  
SMBUS System Clock Buffer  
Product Features  
Product Description  
The B9688 is a high fanout system clock buffer. Loads  
of up to 30 pF are supported. One of the chief  
applications of this component is where long traces are  
used to transport clocks from their generating devices  
to their loads. The creation of EMI and the degradation  
of waveform rise and fall times are greatly reduced by  
running a single reference clock trace to this device and  
then using it to regenerate the clock that drives shorter  
traces. Using these devices, the EMI is therefore  
minimized, and board real estate is saved.  
§
§
18 output buffer for high clock fanout applications  
Each output can be disabled through SMBUS for  
reductions of EMI/power consumption  
§
§
§
§
§
3.3 volts operation  
Output frequency range 10 Mhz to 100 MHz  
< 250ps skew between output clocks  
48-pin SSOP package  
Single Clock Enable pin for testability  
Pin Configuration  
Block Diagram  
IMIB9688  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
VDD  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
CLK[1:2]  
CLK[3:4]  
NC  
NC  
1
NC  
2
NC  
VDD  
3
VDD  
CLK18  
CLK17  
VSS  
REFIN  
CLK1  
CLK2  
VSS  
4
CLK[5:6]  
5
6
CLK[7:8]  
VDD  
7
VDD  
CLK16  
CLK3  
CLK4  
VSS  
8
CLK[9:10]  
CLK[11:12]  
CLK[13:14]  
CLK[15:16]  
9
CLK15  
VSS  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
OE  
REFIN  
VDD  
OE  
Control  
Logic  
SDATA  
SCLK  
VDD  
CLK5  
CLK6  
VSS  
CLK14  
CLK13  
VSS  
CLK[17,18]  
VDD  
VDD  
CLK7  
CLK8  
VSS  
CLK12  
CLK11  
VSS  
VDD  
VDD  
CLK10  
CLK9  
VSS  
VSS  
VDD  
VSS  
SDATA  
SCLOCK  
Cypress Semiconductor Corporation  
525 Los Coches St.  
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571  
http://www.cypress.com  
Document#: 38-07075 Rev. **  
05/09/01  
Page 1 of 10  
APPROVED PRODUCT  
B9688  
SMBUS System Clock Buffer  
Pin Description  
PIN  
No.  
11  
Pin  
PWR  
VDD  
VDD  
I/O  
I
TYPE  
PAD  
Description  
Name  
REFIN  
This pin is connected to the input reference clock. This clock  
must be in the range of 10.0 to 100.0 Mhz.  
4,5,  
O
BUF1 Low skew output clock  
CLK(1:18)  
8,9,13,14,  
17,18,21,  
28, 31, 32,  
35,36,40,  
41,44,45  
38  
-
I
PAD  
Buffer Output Enable pin. When driven to a logic low level this  
OE  
pin is used to place all output clocks (CLK1: 18) in a tri state  
condition. This feature facilitates in production board level  
testing to be easily implemented for the clocks that this device  
produces. Has internal pull-up resistor.  
24  
25  
-
-
I/O  
I
PAD  
PAD  
-
Serial data of SMBUS 2-wire control interface. Has internal pull-  
up resistor.  
Serial clock of SMBUS 2-wire control interface. Has internal  
pull-up resistor.  
Ground pins for clock output buffers. These pins must be  
returned to the same potential to reduce output clock skew.  
SDATA  
SDCLK  
Vss  
6, 10, 15,  
19, 22, 30,  
34, 39, 43  
3, 7, 12,  
PWR  
-
PWR  
-
Power for output clock buffers.  
Vdd  
16, 20, 33,  
37, 42, 46  
23, 29  
-
-
PWR  
PWR  
-
-
Power for core logic.  
Vdd  
Vss  
26, 27  
Ground supply pins for internal core logic pins.  
Cypress Semiconductor Corporation  
525 Los Coches St.  
Document#: 38-07075 Rev. **  
05/09/01  
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571  
http://www.cypress.com  
Page 2 of 10  
APPROVED PRODUCT  
B9688  
SMBUS System Clock Buffer  
2-Wire SMBUS Control Interface  
The 2-wire control interface implements a write only slave interface. The device cannot be read back. Sub addressing is  
not supported, thus all preceding bytes must be sent in order to change one of the control bytes. The 2-wire control  
interface allows each clock output to be individually enabled or disabled.  
During normal data transfer, the SDATA signal only changes when the SDCLK signal is low, and is stable when SDCLK  
is high. There are two exceptions to this. A high to low transition on SDATA while SDCLK is high is used to indicate the  
start of a data transfer cycle. A low to high transition on SDATA while SDCLK is high indicates the end of a data transfer  
cycle. Data is always sent as complete 8-bit bytes, after which an acknowledge is generated. The first byte of a  
transfer cycle is a 7-bit address with a Read/Write bit as the LSB. Data is transferred MSB first.  
The device will respond to writes to 10 bytes (max) of data to address D2 by generating the acknowledge (low) signal on  
the SDATA wire following reception of each byte. The device will not respond to any other control interface conditions.  
Previously set control registers are retained.  
Serial Control Registers  
NOTE: The Pin# column lists the affected pin number where applicable. The @Pup column gives the state at true  
power up. Bytes are set to the values shown only on true power up, and not when the PWR_DWN# pin is activated.  
Following the acknowledge of the Address Byte (D2), two additional bytes must be sent:  
1) “Command Code “ byte, and  
2) “Byte Count” byte.  
Although the data (bits) in these two bytes are considered “don’t care”; they must be sent and will be acknowledged.  
After the Command Code and the Count bytes have been acknowledged, the below described sequence (Byte 0, Byte 1,  
Byte 2...) will be valid and acknowledged.  
Byte 0: Function Select Register (1 = enable, 0 = Stopped, Default = FF)  
Bit  
7
6
5
4
3
2
1
0
@Pup  
Pin#  
18  
17  
14  
13  
9
8
5
4
Description  
1
1
1
1
1
1
1
1
CLK8 (Active = 1, Forced low = 0)  
CLK7 (Active = 1, Forced low = 0)  
CLK6 (Active = 1, Forced low = 0)  
CLK5 (Active = 1, Forced low = 0)  
CLK4 (Active = 1, Forced low = 0)  
CLK3 (Active = 1, Forced low = 0)  
CLK2 (Active = 1, Forced low = 0)  
CLK1 (Active = 1, Forced low = 0)  
Cypress Semiconductor Corporation  
525 Los Coches St.  
Document#: 38-07075 Rev. **  
9/15/2000  
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571  
http://www.cypress.com  
Page 3 of 10  
APPROVED PRODUCT  
B9688  
SMBUS System Clock Buffer  
Byte 1: Clock Register (1 = enable, 0 = Stopped, Default = FF)  
Bit  
7
6
5
4
3
2
1
0
@Pup  
Pin#  
45  
44  
41  
40  
36  
35  
32  
31  
Description  
1
1
1
1
1
1
1
1
CLK18 (Active = 1, Forced low = 0)  
CLK17(Active = 1, Forced low = 0)  
CLK16 (Active = 1, Forced low = 0)  
CLK15 (Active = 1, Forced low = 0)  
CLK14 (Active = 1, Forced low = 0)  
CLK13(Active = 1, Forced low = 0)  
CLK12 (Active = 1, Forced low = 0)  
CLK11 (Active = 1, Forced low = 0)  
Byte 2: Clock Register (1 = enable, 0 = Stopped, Default = C0)  
Bit  
7
6
5
4
3
2
1
0
@Pup  
Pin#  
Description  
CLK10 (Active = 1, Forced low = 0)  
CLK9 (Active = 1, Forced low = 0)  
Not Used  
Not Used  
Not Used  
Not Used  
Not Used  
Not Used  
1
1
0
0
0
0
0
0
28  
21  
-
-
-
-
-
-
Maximum Ratings  
This device contains circuitry to protect the inputs  
against damage due to high static voltages or electric  
field; however, precautions should be taken to avoid  
application of any voltage higher than the maximum  
rated voltages to this circuit. For proper operation, Vin  
and Vout should be constrained to the range:  
VSS<(Vin or Vout)<VDD  
Voltage Relative to VSS:  
Voltage Relative to VDD:  
Storage Temperature:  
Operating Temperature:  
Maximum Power Supply:  
-0.3V  
0.3V  
-65ºC to + 150ºC  
0ºC to +70ºC  
7V  
Unused inputs must always be tied to an appropriate  
logic voltage level (either VSS or VDD).  
Cypress Semiconductor Corporation  
525 Los Coches St.  
Document#: 38-07075 Rev. **  
9/15/2000  
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571  
http://www.cypress.com  
Page 4 of 10  
APPROVED PRODUCT  
B9688  
SMBUS System Clock Buffer  
DC Parameters  
Characteristic  
Symbol Min  
Typ  
Max  
0.8  
Units  
Vdc  
Vdc  
µA  
Conditions  
Input Low Voltage (OE)  
Input High Voltage (OE)  
Input Low Current  
VIL  
VIH  
IIL  
-
-
-
-
-
2.0  
-66  
-
-
Input High Current  
IIH  
66  
1.0  
-
µA  
Input Low Voltage (SMBUS)  
VILisc  
VIHisc  
-
-
-
Vdc  
Vdc  
Input High Voltage  
(SMBUS)  
2.2  
Tri-State leakage Current  
Dynamic Supply Current  
Ioz  
-
-
-
10  
µA  
Idd66  
9
160  
mA  
Input frequency = 66 MHz - All outputs  
on and at 30 pF load  
Dynamic Supply Current  
Idd100  
12  
-
220  
mA  
Input frequency 100 MHz - All outputs on  
and at 30 pF load  
Static Supply Current  
Input pin capacitance  
Pin Inductance  
Isdd  
Cin  
-
-
-
-
-
-
-
-
4
5
7
6
mA  
pF  
All outputs disabled no input clock  
Lpin  
Cout  
nH  
pF  
Output Capacitance  
VDD = 3.3V ±5%, , TA = 0ºC to +70ºC  
AC Parameters  
Characteristic  
Symbol  
-
Min  
45  
-
Typ  
50  
-
Max  
55  
Units  
%
Conditions  
Output Duty Cycle  
Measured at 1.5V (50/50 in)  
35 pF Load Measured at 1.5V  
Buffer out/out Skew All  
Buffer Outputs  
tSKEW  
250  
pS  
Buffer input to output Skew  
Jitter Cycle to Cycle*  
tDLY  
TJCC  
TJabs  
2.0  
0
5.0  
100  
150  
nS  
pS  
pS  
@ 30 pF loading  
@ 30 pF loading  
Jitter Absolute (Peak to  
Peak)*  
VDD = 3.3V ±5%, , TA = 0ºC to +70ºC  
*This jitter is additive to the input clock’s jitter.  
Cypress Semiconductor Corporation  
525 Los Coches St.  
Document#: 38-07075 Rev. **  
9/15/2000  
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571  
http://www.cypress.com  
Page 5 of 10  
APPROVED PRODUCT  
B9688  
SMBUS System Clock Buffer  
Buffer Characteristics (All Clock Outputs)  
Characteristic  
Symbol  
IOHmin  
IOHmax  
IOLmin  
IOLmax  
ZO  
Min  
30  
75  
30  
75  
8
Typ  
Max  
39  
Units  
mA  
Conditions  
Pull-Up Current Min  
Pull-Up Current Max  
Pull-Down Current Min  
Pull-Down Current Max  
Dynamic Output Impedance  
-
-
-
-
-
-
Vout = VDD - 0.5V  
Vout = 1.5V  
109  
40  
mA  
mA  
Vout = 0.4 V  
Vout = 1.2V  
103  
15  
mA  
Ohms  
nS  
66 - 100 MHz  
30 pF Load  
Rise/Fall Time Min  
TRFmin  
0.5  
1.33  
Between 0.4 V and 2.4 V  
Rise/Fall Time Max  
TRFmax  
0.5  
-
1.33  
nS  
30 pF Load  
Between 0.4 V and 2.4 V  
VDD = 3.3V ±5%, , TA = 0ºC to +70ºC  
Cypress Semiconductor Corporation  
525 Los Coches St.  
Document#: 38-07075 Rev. **  
9/15/2000  
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571  
http://www.cypress.com  
Page 6 of 10  
APPROVED PRODUCT  
B9688  
SMBUS System Clock Buffer  
PCB Layout Suggestion  
Via to VDD Plane  
Via to GND Plane  
Void (cut) in power plane  
1
2
3
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
48  
47  
46  
45  
C1  
C2  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
C11  
FB2  
VCC  
C10  
C9  
C12  
C3  
C4  
22uF  
C8  
C7  
C5  
C6  
This is only a layout recommendation for best performance and lower EMI. The designer may choose a different  
approach but C1, C2, C3, C4, C5, C6, C7, C8, C9, C10, and C11 (all are 0.1 µf) should always be used and placed  
as close to their VDD pins as is physically possible.  
Cypress Semiconductor Corporation  
525 Los Coches St.  
Document#: 38-07075 Rev. **  
9/15/2000  
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571  
http://www.cypress.com  
Page 7 of 10  
APPROVED PRODUCT  
B9688  
SMBUS System Clock Buffer  
Package Drawing and Dimensions  
48 Pin SSOP Outline Dimensions  
INCHES  
MILLIMETERS  
SYMBOL  
MIN  
NOM  
MAX  
MIN  
2.41  
0.20  
2.16  
NOM  
2.59  
0.31  
2.29  
MAX  
2.79  
0.41  
2.41  
C
A
A1  
A2  
B
0.095  
0.008  
0.085  
0.008  
0.005  
0.620  
0.291  
0.102  
0.012  
0.090  
0.010  
.008  
0.110  
0.016  
0.095  
0.0135  
0.010  
0.637  
0.299  
L
H
E
0.203 0.254 0.343  
0.127 0.20 0.254  
15.75 15.88 16.18  
c
D
E
0.625  
0.295  
0.0256 BSC  
0.408  
0.030  
4º  
D
a
7.39  
7.49  
7.59  
A2  
A
e
0.640 BSC  
H
L
0.395  
0.024  
0º  
0.420  
0.040  
8º  
10.03 10.36 10.67  
A1  
e
0.61  
0º  
0.76  
4º  
1.02  
8º  
B
a
Ordering Information  
Part Number  
Package Type  
Production Flow  
Commercial, 0ºC to +70ºC  
B9688AYB  
48 PIN SSOP  
Note:  
The ordering part number is formed by a combination of device number, device revision, package style, and  
screening as shown below.  
Marking: Example: Cypress  
B9688AYB  
Date Code, Lot #  
B9688AYB  
Flow  
B = Commercial, 0ºC to + 70ºC  
Package  
Y= SSOP  
Revision  
Device Number  
Cypress Semiconductor Corporation  
525 Los Coches St.  
Document#: 38-07075 Rev. **  
9/15/2000  
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571  
http://www.cypress.com  
Page 8 of 10  
APPROVED PRODUCT  
B9688  
SMBUS System Clock Buffer  
Notice  
Cypress Semiconductor Corporation reserves the right to make changes to its products in order to improve design,  
performance or reliability. Cypress Semiconductor Corporation assumes no responsibility for the use of its products in  
life supporting and medical applications where the failure or malfunction of the product could cause failure of the life  
supporting and medical systems. Products are not authorized for use in such applications unless a written approval is  
requested by the manufacturer and an approval is given in writing by Cypress Semiconductor Corporation for the use of  
its products in the life supporting and medical applications.  
Cypress Semiconductor Corporation  
525 Los Coches St.  
Document#: 38-07075 Rev. **  
9/15/2000  
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571  
http://www.cypress.com  
Page 9 of 10  
APPROVED PRODUCT  
B9688  
SMBUS System Clock Buffer  
Document Title: B9688 SMBus System Clock Buffer  
Document Number: 38-07075  
Rev. ECN  
NO.  
Issue  
Date  
Orig. of Description of Change  
Change  
**  
107111 06/05/01 IKA  
Convert from IMI to Cypress  
Cypress Semiconductor Corporation  
525 Los Coches St.  
Document#: 38-07075 Rev. **  
9/15/2000  
Milpitas, CA 95035. Tel: 408-263-6300, Fax: 408-263-6571  
http://www.cypress.com  
Page 10 of 10  

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