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CY14B101KA-SP25XCT

更新时间：2025-06-13 08:23:35
品牌：CYPRESS
描述：1 Mbit (128K x 8/64K x 16) nvSRAM with Real Time Clock

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CY14B101KA-SP25XCT 概述

1 Mbit (128K x 8/64K x 16) nvSRAM with Real Time Clock 1兆位（ 128K ×8 / 64K ×16 ）的nvSRAM与实时时钟 SRAM

CY14B101KA-SP25XCT 规格参数

生命周期：Obsolete零件包装代码：SSOP
包装说明：SSOP,针数：48
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.32.00.41风险等级：5.42
Is Samacsys：N最长访问时间：25 ns
JESD-30 代码：R-PDSO-G48长度：15.875 mm
内存密度：1048576 bit内存集成电路类型：NON-VOLATILE SRAM
内存宽度：8功能数量：1
端子数量：48字数：131072 words
字数代码：128000工作模式：ASYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：128KX8封装主体材料：PLASTIC/EPOXY
封装代码：SSOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, SHRINK PITCH并行/串行：PARALLEL
认证状态：Not Qualified座面最大高度：2.794 mm
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：2.7 V
标称供电电压 (Vsup)：3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子形式：GULL WING端子节距：0.635 mm
端子位置：DUAL宽度：7.5 mm
Base Number Matches：1

CY14B101KA-SP25XCT 数据手册

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PRELIMINARY  
CY14B101KA/CY14B101MA  
1 Mbit (128K x 8/64K x 16) nvSRAM with  
Real Time Clock  
■
Industry Standard Configurations  
Features  
❐
❐
❐
❐
Single 3V +20%, –10% operation  
■
1 Mbit nvSRAM  
Commercial and Industrial temperatures  
44-pin and 54-pin TSOP II and 48-pin SSOP packages  
Pb-free and RoHS compliance  
❐
20 ns, 25 ns, and 45 ns access times  
❐
Internally organized as 128K x 8 (CY14B101KA) or 64K x 16  
(CY14B101MA)  
❐
❐
❐
HandsoffautomaticSTOREon powerdown with onlyasmall  
Functional Description  
capacitor  
The Cypress CY14B101KA/CY14B101MA combines a 1 Mbit  
nonvolatile static RAM with a full featured real time clock in a  
monolithic integrated circuit. The embedded nonvolatile  
elements incorporate QuantumTrap technology producing the  
world’s most reliable nonvolatile memory. The SRAM is read and  
written an infinite number of times, while independent nonvolatile  
data resides in the nonvolatile elements.  
STORE to QuantumTrap nonvolatile elements is initiated by  
software, hardware, or AutoStore on power down  
RECALL to SRAM initiated on power up or by software  
■
■
High Reliability  
❐
❐
❐
Infinite Read, Write, and RECALL cycles  
200,000 STORE cycles to QuantumTrap  
20 year data retention  
The Real Time Clock function provides an accurate clock with  
leap year tracking and a programmable, high accuracy oscillator.  
The alarm function is programmable for periodic minutes, hours,  
days, or months alarms. There is also a programmable watchdog  
timer for process control.  
Real Time Clock  
❐
❐
Full featured Real Time Clock  
Watchdog timer  
Clock alarm with programmable interrupts  
Capacitor or battery backup for RTC  
Backup current of 300 nA  
❐
❐
❐
Logic Block Diagram[1, 2, 3]  
VCA  
P
VCC  
Quatrum  
Trap  
1024 X 1024  
VRTCbat  
VRTCcap  
POWER  
CONTROL  
R
O
W
A5  
A6  
A7  
STORE  
RECALL  
A8  
A9  
A12  
A13  
A14  
A15  
A16  
STORE/RECALL  
CONTROL  
D
E
C
O
D
E
R
HSB  
STATIC RAM  
ARRAY  
1024 X 1024  
SOFTWARE  
DETECT  
A14 - A2  
DQ0  
DQ1  
DQ2  
Xout  
Xin  
DQ3  
RTC  
DQ4  
DQ5  
DQ6  
I
INT  
N
P
U
T
B
U
F
F
E
R
S
DQ7  
COLUMN I/O  
MUX  
A16- A0  
DQ8  
DQ9  
DQ10  
OE  
COLUMN DEC  
WE  
DQ11  
DQ12  
DQ13  
DQ14  
CE  
BLE  
A0 A1 A2 A3 A4 A10 A11  
DQ15  
BHE  
Notes  
1. Address A - A for x8 configuration and Address A - A for x16 configuration.  
0
16  
0
15  
2. Data DQ - DQ for x8 configuration and Data DQ - DQ for x16 configuration.  
0
7
0
15  
3. BHE and BLE are applicable for x16 configuration only.  
Cypress Semiconductor Corporation  
Document #: 001-42880 Rev. *C  
•
198 Champion Court  
•
San Jose  
,
CA 95134-1709  
•
408-943-2600  
Revised July 09, 2009  
[+] Feedback  
CY14B101KA/CY14B101MA  
PRELIMINARY  
Pinouts  
Figure 1. Pin Diagram - 44-Pin, 54-Pin TSOP II, and 48-Pin SSOP  
VCAP  
INT  
[7]  
54  
53  
HSB  
1
2
3
INT  
48  
47  
V
CC  
1
2
3
1
44  
43  
42  
41  
HSB  
NC  
[6]  
[7  
NC  
NC  
NC  
NC  
A
16  
NC  
2
3
4
5
6
7
8
A
15  
[5]  
[4]  
[6]  
A
0
52  
51  
50  
49  
A
14  
A12  
A
7
A
46  
45  
44  
43  
42  
NC  
HSB  
WE  
A13  
A8  
0
A
1
4
[5]  
4
5
6
7
8
9
10  
11  
12  
13  
14  
A
NC  
NC  
1
A
2
A
15  
5
[4]  
A
2
A
3
40  
39  
OE  
BHE  
6
A
6
A
A
4
48  
47  
46  
45  
A
7
8
3
16  
A
5
INT  
A
4
A
9
CE  
DQ0  
DQ1  
BLE  
A
38  
37  
36  
35  
34  
A
4
15  
DQ15  
DQ14  
DQ13  
DQ12  
41  
40  
NC  
A
9
CE  
DQ0  
DQ1  
OE  
DQ7  
48 - SSOP  
(x8)  
54 - TSOP II  
(x16)  
10  
11  
12  
11  
44 - TSOP II  
(x8)  
9
10  
DQ2  
DQ3  
44  
43  
42  
41  
40  
39  
NC  
NC  
NC  
VSS  
39  
NC  
NC  
NC  
V
SS  
NC  
DQ6  
38  
37  
36  
Top View  
V
11  
12  
13  
14  
Top View  
V
CC  
V
CC  
V
Top View  
13  
14  
15  
16  
17  
18  
SS  
SS  
V
SS  
V
CC  
(not to scale)  
VSS  
DQ2  
DQ3  
V
33  
32  
31  
(not to scale)  
CC  
(not to scale)  
DQ4  
DQ5  
DQ 11  
DQ 10  
DQ9  
DQ5  
NC  
VRTCbat  
35  
DQ4  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
VRTCcap  
34  
33  
32  
31  
38  
37  
36  
35  
DQ6  
DQ7  
WE  
WE  
A
5
15  
16  
17  
18  
30  
29  
28  
27  
26  
25  
24  
23  
VCAP  
DQ0  
A
3
A
2
DQ6  
OE  
A10  
DQ8  
A
14  
VCAP  
A
14  
19  
20  
21  
22  
23  
24  
25  
26  
27  
A
6
A13  
A12  
A
5
A
7
34  
33  
32  
31  
30  
29  
28  
A
1
A
0
A
6
A
13  
30  
29  
28  
27  
26  
25  
CE  
DQ7  
A8  
19  
20  
21  
22  
A
A
7
A
8
12  
A
11  
A
11  
A
9
DQ1  
DQ2  
Xout  
Xin  
A10  
DQ5  
DQ4  
DQ3  
A
10  
A9  
Xout  
Xin  
VRTCcap  
VRTCbat  
NC  
Xout  
Xin  
NC  
VRTCcap  
VRTCbat  
V
CC  
Pin Definitions  
Pin Name  
A0 – A16  
I/O Type  
Description  
Address Inputs Used to Select one of the 131,072 Bytes of the nvSRAM for x8 Configuration.  
Address Inputs Used to Select one of the 65,536 Words of the nvSRAM for x16 Configuration.  
Input  
A0 – A15  
DQ0 – DQ7  
Bidirectional Data I/O Lines for x8 Configuration. Used as input or output lines depending on  
operation.  
Input/Output  
DQ0 – DQ15  
Bidirectional Data I/O Lines for x16 Configuration. Used as input or output lines depending on  
operation.  
NC  
No Connect No Connects. This pin is not connected to the die.  
Input  
Write Enable Input, Active LOW. When the chip is enabled and WE is LOW, data on the I/O pins is  
written to the specific address location.  
WE  
Input  
Input  
Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.  
CE  
OE  
Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read  
cycles. Deasserting OE HIGH causes the I/O pins to tristate.  
Input  
Input  
Byte High Enable, Active LOW. Controls DQ15 - DQ8.  
Byte Low Enable, Active LOW. Controls DQ7 - DQ0.  
Crystal Connection. Drives crystal on start up.  
Crystal Connection. For 32.768 kHz crystal.  
BHE  
BLE  
Xout  
Output  
Input  
Xin  
VRTCcap Power Supply Capacitor Supplied Backup RTC Supply Voltage. Left unconnected if VRTCbat is used.  
VRTCbat Power Supply Battery Supplied Backup RTC Supply Voltage. Left unconnected if VRTCcap is used.  
Notes  
4. Address expansion for 2 Mbit. NC pin not connected to die.  
5. Address expansion for 4 Mbit. NC pin not connected to die.  
6. Address expansion for 8 Mbit. NC pin not connected to die.  
7. Address expansion for 16 Mbit. NC pin not connected to die.  
Document #: 001-42880 Rev. *C  
Page 2 of 29  
[+] Feedback  
CY14B101KA/CY14B101MA  
PRELIMINARY  
Pin Definitions (continued)  
Pin Name  
I/O Type  
Description  
Output  
Interrupt Output. Programmable to respond to the clock alarm, the watchdog timer, and the power  
monitor. Also programmable to either active HIGH (push or pull) or LOW (open drain).  
INT  
VSS  
VCC  
Ground  
Ground for the Device. Must be connected to the ground of the system.  
Power Supply Power Supply Inputs to the Device. 3.0V +20%, –10%  
Input/Output Hardware STORE Busy (HSB). When LOW this output indicates that a Hardware STORE is in progress.  
When pulled LOW external to the chip, it initiates a nonvolatile STORE operation. A weak internal pull  
up resistor keeps this pin HIGH if not connected (connection optional). After each STORE operation,  
HSB is driven HIGH for short time with standard output high current.  
HSB  
VCAP  
Power Supply AutoStore Capacitor. Supplies power to the nvSRAM during power loss to store data from SRAM to  
nonvolatile elements.  
Device Operation  
AutoStore Operation  
The CY14B101KA/CY14B101MA nvSRAM is made up of two  
functional components paired in the same physical cell. These  
are a SRAM memory cell and a nonvolatile QuantumTrap cell.  
The SRAM memory cell operates as a standard fast static RAM.  
Data in the SRAM is transferred to the nonvolatile cell (the  
STORE operation), or from the nonvolatile cell to the SRAM (the  
RECALL operation). Using this unique architecture, all cells are  
stored and recalled in parallel. During the STORE and RECALL  
operations SRAM read and write operations are inhibited. The  
CY14B101KA/CY14B101MA supports infinite reads and writes  
similar to a typical SRAM. In addition, it provides infinite RECALL  
operations from the nonvolatile cells and up to 200K STORE  
operations. Refer the Truth Table For SRAM Operations on page  
23 for a complete description of read and write modes.  
The CY14B101KA/CY14B101MA stores data to the nvSRAM  
using one of three storage operations. These three operations  
are: Hardware STORE, activated by the HSB; Software STORE,  
activated by an address sequence; AutoStore, on device power  
down. The AutoStore operation is a unique feature of  
QuantumTrap technology and is enabled by default on the  
CY14B101KA/CY14B101MA.  
During normal operation, the device draws current from VCC to  
charge a capacitor connected to the VCAP pin. This stored  
charge is used by the chip to perform a single STORE operation.  
If the voltage on the VCC pin drops below VSWITCH, the part  
automatically disconnects the VCAP pin from VCC. A STORE  
operation is initiated with power provided by the VCAP capacitor.  
Note If the capacitor is not connected to VCAP pin, AutoStore  
must be disabled using the soft sequence specified in Preventing  
AutoStore on page 5. In case AutoStore is enabled without a  
capacitor on VCAP pin, the device attempts an AutoStore  
operation without sufficient charge to complete the Store. This  
may corrupt the data stored in nvSRAM.  
SRAM Read  
The CY14B101KA/CY14B101MA performs  
a read cycle  
whenever CE and OE are LOW, and WE and HSB are HIGH.  
The address specified on pins A0-16 or A0-15 determines which  
of the 131,072 data bytes or 65,536 words of 16 bits each are  
accessed. Byte enables (BHE, BLE) determine which bytes are  
enabled to the output, in the case of 16-bit words. When the read  
is initiated by an address transition, the outputs are valid after a  
delay of tAA (read cycle #1). If the read is initiated by CE or OE,  
the outputs are valid at tACE or at tDOE, whichever is later (read  
cycle #2). The data output repeatedly responds to address  
changes within the tAA access time without the need for transi-  
tions on any control input pins. This remains valid until another  
address change or until CE or OE is brought HIGH, or WE or  
HSB is brought LOW.  
Figure 2. AutoStore Mode  
Vcc  
0.1uF  
Vcc  
WE  
VCAP  
SRAM Write  
A write cycle is performed when CE and WE are LOW and HSB  
is HIGH. The address inputs must be stable before entering the  
write cycle and must remain stable until CE or WE goes HIGH at  
the end of the cycle. The data on the common I/O pins IO0-7 are  
written into the memory if it is valid tSD before the end of a  
WE-controlled write, or before the end of an CE-controlled write.  
The Byte Enable inputs (BHE, BLE) determine which bytes are  
written, in the case of 16-bit words. It is recommended that OE  
be kept HIGH during the entire write cycle to avoid data bus  
contention on common I/O lines. If OE is left LOW, internal  
circuitry turns off the output buffers tHZWE after WE goes LOW.  
VCAP  
VSS  
Figure 2 shows the proper connection of the storage capacitor  
(VCAP) for automatic STORE operation. Refer to DC Electrical  
Characteristics on page 15 for the size of the VCAP. The voltage  
on the VCAP pin is driven to VCC by a regulator on the chip. Place  
Document #: 001-42880 Rev. *C  
Page 3 of 29  
[+] Feedback  
CY14B101KA/CY14B101MA  
PRELIMINARY  
a pull up on WE to hold it inactive during power up. This pull up  
is only effective if the WE signal is tristate during power up. Many  
MPUs tristate their controls on power up. This must be Verified  
when using the pull up. When the nvSRAM comes out of  
power-on-recall, the MPU must be active or the WE held inactive  
until the MPU comes out of reset.  
Because a sequence of reads from specific addresses is used  
for STORE initiation, it is important that no other read or write  
accesses intervene in the sequence, or the sequence is aborted  
and no STORE or RECALL takes place.  
To initiate the Software STORE cycle, the following read  
sequence must be performed:  
To reduce unnecessary nonvolatile stores, AutoStore and  
Hardware STORE operations are ignored unless at least one  
write operation has taken place since the most recent STORE or  
RECALL cycle. Software initiated STORE cycles are performed  
regardless of whether a write operation has taken place.  
1. Read address 0x4E38 Valid READ  
2. Read address 0xB1C7 Valid READ  
3. Read address 0x83E0 Valid READ  
4. Read address 0x7C1F Valid READ  
5. Read address 0x703F Valid READ  
6. Read address 0x8FC0 Initiate STORE cycle  
The HSB signal is monitored by the system to detect if an  
AutoStore cycle is in progress.  
The software sequence may be clocked with CE controlled reads  
or OE controlled reads, with WE kept HIGH for all the six READ  
sequences. After the sixth address in the sequence is entered,  
the STORE cycle commences and the chip is disabled. HSB is  
driven LOW. After the tSTORE cycle time is fulfilled, the SRAM is  
activated again for the read and write operation.  
Hardware STORE (HSB) Operation  
The CY14B101KA/CY14B101MA provides the HSB pin to  
control and acknowledge the STORE operations. The HSB pin  
is used to request a Hardware STORE cycle. When the HSB pin  
is driven LOW, the CY14B101KA/CY14B101MA conditionally  
initiates a STORE operation after tDELAY. An actual STORE cycle  
begins only if a write to the SRAM has taken place since the last  
STORE or RECALL cycle. The HSB pin also acts as an open  
drain driver that is internally driven LOW to indicate a busy  
condition when the STORE (initiated by any means) is in  
progress.  
Software RECALL  
Data is transferred from nonvolatile memory to the SRAM by a  
software address sequence. A Software RECALL cycle is  
initiated with a sequence of read operations in a manner similar  
to the Software STORE initiation. To initiate the RECALL cycle,  
the following sequence of CE or OE controlled read operations  
must be performed:  
SRAM write operations that are in progress when HSB is driven  
LOW by any means are given time (tDELAY) to complete before  
the STORE operation is initiated. However, any SRAM write  
cycles requested after HSB goes LOW are inhibited until HSB  
returns HIGH. In case the write latch is not set, HSB is not driven  
LOW by the CY14B101KA/CY14B101MA. But any SRAM read  
and write cycles are inhibited until HSB is returned HIGH by MPU  
or other external source.  
1. Read address 0x4E38 Valid READ  
2. Read address 0xB1C7 Valid READ  
3. Read address 0x83E0 Valid READ  
4. Read address 0x7C1F Valid READ  
5. Read address 0x703F Valid READ  
6. Read address 0x4C63 Initiate RECALL cycle  
During any STORE operation, regardless of how it is initiated,  
the CY14B101KA/CY14B101MA continues to drive the HSB pin  
LOW, releasing it only when the STORE is complete. Upon  
Internally, RECALL is a two step procedure. First, the SRAM data  
is cleared. Next, the nonvolatile information is transferred into the  
SRAM cells. After the tRECALL cycle time, the SRAM is again  
ready for read and write operations. The RECALL operation  
does not alter the data in the nonvolatile elements.  
completion  
of  
the  
STORE  
operation,  
the  
CY14B101KA/CY14B101MA remains disabled until the HSB pin  
returns HIGH. Leave the HSB unconnected if it is not used.  
Hardware RECALL (Power Up)  
During power up or after any low power condition  
(VCC< VSWITCH), an internal RECALL request is latched. When  
VCC again exceeds the VSWITCH on powerup, a RECALL cycle  
is automatically initiated and takes tHRECALL to complete. During  
this time, the HSB pin is driven LOW by the HSB driver and all  
reads and writes to nvSRAM are inhibited.  
Software STORE  
Data is transferred from SRAM to the nonvolatile memory by a  
software address sequence. The CY14B101KA/CY14B101MA  
Software STORE cycle is initiated by executing sequential CE or  
OE controlled read cycles from six specific address locations in  
exact order. During the STORE cycle, an erase of the previous  
nonvolatile data is first performed, followed by a program of the  
nonvolatile elements. After a STORE cycle is initiated, further  
input and output are disabled until the cycle is completed.  
Document #: 001-42880 Rev. *C  
Page 4 of 29  
[+] Feedback  
CY14B101KA/CY14B101MA  
PRELIMINARY  
Table 1. Mode Selection  
[8]  
Mode  
I/O  
Power  
Standby  
Active  
A15 - A0  
CE  
H
WE  
OE, BHE, BLE[3]  
X
H
L
X
X
Not Selected  
Read SRAM  
Write SRAM  
Output High Z  
Output Data  
Input Data  
L
L
L
L
X
L
X
X
Active  
Active[9]  
H
0x4E38  
0xB1C7  
0x83E0  
0x7C1F  
0x703F  
0x8B45  
Read SRAM  
Read SRAM  
Read SRAM  
Read SRAM  
Read SRAM  
AutoStore  
Output Data  
Output Data  
Output Data  
Output Data  
Output Data  
Output Data  
Disable  
L
L
L
H
H
H
L
L
L
0x4E38  
0xB1C7  
0x83E0  
0x7C1F  
0x703F  
0x4B46  
Read SRAM  
Read SRAM  
Read SRAM  
Read SRAM  
Read SRAM  
AutoStore  
Output Data  
Output Data  
Output Data  
Output Data  
Output Data  
Output Data  
Active[9]  
Active ICC2  
Active[9]  
Enable  
[9]  
0x4E38  
0xB1C7  
0x83E0  
0x7C1F  
0x703F  
0x8FC0  
Read SRAM  
Read SRAM  
Read SRAM  
Read SRAM  
Read SRAM  
Nonvolatile  
STORE  
Output Data  
Output Data  
Output Data  
Output Data  
Output Data  
Output High Z  
0x4E38  
0xB1C7  
0x83E0  
0x7C1F  
0x703F  
0x4C63  
Read SRAM  
Read SRAM  
Read SRAM  
Read SRAM  
Read SRAM  
Nonvolatile  
Recall  
Output Data  
Output Data  
Output Data  
Output Data  
Output Data  
Output High Z  
To initiate the AutoStore enable sequence, the following  
sequence of CE or OE controlled read operations must be  
performed:  
Preventing AutoStore  
The AutoStore function is disabled by initiating an AutoStore  
disable sequence. A sequence of read operations is performed  
in a manner similar to the Software STORE initiation. To initiate  
the AutoStore disable sequence, the following sequence of CE  
or OE controlled read operations must be performed:  
1. Read address 0x4E38 Valid READ  
2. Read address 0xB1C7 Valid READ  
3. Read address 0x83E0 Valid READ  
4. Read address 0x7C1F Valid READ  
5. Read address 0x703F Valid READ  
6. Read address 0x4B46 AutoStore Enable  
1. Read address 0x4E38 Valid READ  
2. Read address 0xB1C7 Valid READ  
3. Read address 0x83E0 Valid READ  
4. Read address 0x7C1F Valid READ  
5. Read address 0x703F Valid READ  
6. Read address 0x8B45 AutoStore Disable  
If the AutoStore function is disabled or reenabled, a manual  
STORE operation (Hardware or Software) issued to save the  
AutoStore state through subsequent power down cycles. The  
part comes from the factory with AutoStore enabled.  
The AutoStore is reenabled by initiating an AutoStore enable  
sequence. A sequence of read operations is performed in a  
manner similar to the Software RECALL initiation.  
Notes  
8. While there are 17 address lines on the CY14B101KA (16 address lines on the CY14B101MA), only the 13 address lines (A - A ) are used to control software  
14  
2
modes. The remaining address lines are don’t care.  
9. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a nonvolatile cycle.  
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CY14B101KA/CY14B101MA  
PRELIMINARY  
or more random bytes) as part of the final system manufac-  
turing test to ensure these system routines work consistently.  
Best Practices  
nvSRAM products have been used effectively for over 15 years.  
While ease-of-use is one of the product’s main system values,  
experience gained working with hundreds of applications has  
resulted in the following suggestions as best practices:  
■
Power up boot firmware routines should rewrite the nvSRAM  
into the desired state (for example, autostore enabled). While  
the nvSRAM is shipped in a preset state, best practice is to  
again rewrite the nvSRAM into the desired state as a safeguard  
against events that might flip the bit inadvertently such as  
program bugs and incoming inspection routines.  
■
ThenonvolatilecellsinthisnvSRAMproductaredeliveredfrom  
Cypress with 0x00 written in all cells. Incoming inspection  
routines at customer or contract manufacturer’s sites  
■
The VCAP value specified in this data sheet includes a minimum  
and a maximum value size. Best practice is to meet this  
requirement and not exceed the maximum VCAP value because  
the nvSRAM internal algorithm calculates VCAP charge and  
discharge time based on this max VCAP value. Customers that  
want to use a larger VCAP value to make sure there is extra store  
charge and store time should discuss their VCAP size selection  
withCypresstounderstandanyimpactontheVCAP voltagelevel  
at the end of a tRECALL period.  
sometimes reprogram these values. Final NV patterns are  
typically repeating patterns of AA, 55, 00, FF, A5, or 5A. End  
product’s firmware should not assume an NV array is in a set  
programmed state. Routines that check memory content  
values to determine first time system configuration, cold or  
warm boot status, and so on should always program a unique  
NV pattern (that is, complex 4-byte pattern of 46 E6 49 53 hex  
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CY14B101KA/CY14B101MA  
PRELIMINARY  
Setting the Clock  
Data Protection  
Setting the write bit ‘W’ (in the flags register at 0x1FFF0) to a ‘1’  
stops updates to the time keeping registers and enables the time  
to be set. The correct day, date, and time is then written into the  
registers and must be in 24-hour BCD format. The time written  
is referred to as the “Base Time”. This value is stored in nonvol-  
atile registers and used in the calculation of the current time.  
Resetting the write bit to ‘0’ transfers the values of timekeeping  
registers to the actual clock counters, after which the clock  
resumes normal operation.  
The CY14B101KA/CY14B101MA protects data from corruption  
during low voltage conditions by inhibiting all externally initiated  
STORE and write operations. The low voltage condition is  
detected when VCC is less than VSWITCH  
.
If the  
CY14B101KA/CY14B101MA is in a write mode (both CE and  
WE are LOW) at power up, after a RECALL or STORE, the write  
is inhibited until the SRAM is enabled after tLZHSB (HSB to output  
active). This protects against inadvertent writes during power up  
or brown out conditions.  
If the time written to the timekeeping registers is not in the correct  
BCD format, each invalid nibble of the RTC registers continue  
counting to 0xF before rolling over to 0x0 after which RTC  
resumes normal operation.  
Noise Considerations  
Refer to CY application note AN1064.  
Real Time Clock Operation  
nvTIME Operation  
Note The values entered in the timekeeping, alarm, calibration,  
and interrupt registers need a STORE operation to be saved in  
nonvolatile memory. Therefore, while working in AutoStore  
disabled mode, the user must perform a STORE operation after  
writing into the RTC registers for the RTC to work correctly.  
The CY14B101KA/CY14B101MA offers internal registers that  
contain clock, alarm, watchdog, interrupt, and control functions.  
Internal double buffering of the clock and timer information  
registers prevents accessing transitional internal clock data  
during a read or write operation. Double buffering also  
circumvents disrupting normal timing counts or the clock  
accuracy of the internal clock when accessing clock data. Clock  
and alarm registers store data in BCD format.  
Backup Power  
The RTC in the CY14B101KA is intended for permanently  
powered operation. The VRTCcap or VRTCbat pin is connected  
depending on whether a capacitor or battery is chosen for the  
application. When the primary power, VCC, fails and drops below  
VSWITCH the device switches to the backup power supply.  
RTC functionality is described with respect to CY14B101KA in  
the following sections. The same description applies to  
CY14B101MA, except for the RTC register addresses. The RTC  
register addresses for CY14B101KA range from 0x1FFF0 to  
0x1FFFF, while those for CY14B101MA range from 0x0FFF0 to  
0x0FFFF. Refer to Table 3 on page 11 and Table 4 on page 12  
for a detailed Register Map description.  
The clock oscillator uses very little current, which maximizes the  
backup time available from the backup source. Regardless of the  
clock operation with the primary source removed, the data stored  
in the nvSRAM is secure, having been stored in the nonvolatile  
elements when power was lost.  
During backup operation, the CY14B101KA consumes a  
maximum of 300 nanoamps at room temperature. The user must  
choose capacitor or battery values according to the application.  
Clock Operations  
Backup time values based on maximum current specifications  
are shown in the following table. Nominal backup times are  
approximately two times longer.  
The clock registers maintain time up to 9,999 years in one  
second increments. The time can be set to any calendar time and  
the clock automatically keeps track of days of the week and  
month, leap years, and century transitions. There are eight  
registers dedicated to the clock functions, which are used to set  
time with a write cycle and to read time during a read cycle.  
These registers contain the time of day in BCD format. Bits  
defined as ‘0’ are currently not used and are reserved for future  
use by Cypress.  
Table 2. RTC Backup Time  
Capacitor Value  
Backup Time  
72 hours  
14 days  
0.1F  
0.47F  
1.0F  
30 days  
Reading the Clock  
The double buffered RTC register structure reduces the chance  
of reading incorrect data from the clock. Stop internal updates to  
the CY14B101KA time keeping registers before reading clock  
data, to prevent reading of data in transition. Stopping the  
register updates does not affect clock accuracy.  
Using a capacitor has the obvious advantage of recharging the  
backup source each time the system is powered up. If a battery  
is used, a 3V lithium is recommended and the CY14B101KA  
sources current only from the battery when the primary power is  
removed. However, the battery is not recharged at any time by  
the CY14B101KA. The battery capacity must be chosen for total  
anticipated cumulative down time required over the life of the  
system.  
The updating process is stopped by writing a ‘1’ to the read bit  
‘R’ (in the flags register at 0x1FFF0), and does not restart until a  
‘0’ is written to the read bit. The RTC registers are then read while  
the internal clock continues to run. After a ‘0’ is written to the read  
bit (‘R’), all RTC registers are simultaneously updated within  
20 ms.  
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CY14B101KA/CY14B101MA  
PRELIMINARY  
125,829,120 actual oscillator cycles, that is, 4.068 or –2.034 ppm  
of adjustment per calibration step in the Calibration register.  
Stopping and Starting the Oscillator  
The OSCEN bit in the calibration register at 0x1FFF8 controls  
the enable and disable of the oscillator. This bit is nonvolatile and  
is shipped to customers in the “enabled” (set to 0) state. To  
preserve the battery life when the system is in storage, OSCEN  
must be set to ‘1’. This turns off the oscillator circuit, extending  
the battery life. If the OSCEN bit goes from disabled to enabled,  
it takes approximately one second (two seconds maximum) for  
the oscillator to start.  
To determine the required calibration, the CAL bit in the Flags  
register (0x1FFF0) must be set to ‘1’. This causes the INT pin to  
toggle at a nominal frequency of 512 Hz. Any deviation  
measured from the 512 Hz indicates the degree and direction of  
the required correction. For example, a reading of 512.01024 Hz  
indicates a +20 ppm error. Hence, a decimal value of –10  
(001010b) must be loaded into the Calibration register to offset  
this error.  
While system power is off, If the voltage on the backup supply  
(VRTCcap or VRTCbat) falls below their respective minimum level,  
the oscillator may fail.The CY14B101KA has the ability to detect  
oscillator failure when system power is restored. This is recorded  
in the OSCF (Oscillator Failed bit) of the flags register at the  
address 0x1FFF0. When the device is powered on (VCC goes  
above VSWITCH) the OSCEN bit is checked for “enabled” status.  
If the OSCEN bit is enabled and the oscillator is not active within  
the first 5 ms, the OSCF bit is set to “1”. The system must check  
for this condition and then write ‘0’ to clear the flag. Note that in  
addition to setting the OSCF flag bit, the time registers are reset  
to the “Base Time” (see Setting the Clock on page 7), which is  
the value last written to the timekeeping registers. The control or  
calibration registers and the OSCEN bit are not affected by the  
‘oscillator failed’ condition.  
Note Setting or changing the Calibration register does not affect  
the test output frequency.  
To set or clear CAL, set the write bit “W” (in the flags register at  
0x1FFF0) to “1” to enable writes to the Flag register. Write a  
value to CAL, and then reset the write bit to “0” to disable writes.  
Alarm  
The alarm function compares user programmed values of alarm  
time and date (stored in the registers 0x1FFF1-5) with the corre-  
sponding time of day and date values. When a match occurs, the  
alarm internal flag (AF) is set and an interrupt is generated on  
INT pin if Alarm Interrupt Enable (AIE) bit is set.  
There are four alarm match fields - date, hours, minutes, and  
seconds. Each of these fields has a match bit that is used to  
determine if the field is used in the alarm match logic. Setting the  
match bit to ‘0’ indicates that the corresponding field is used in  
the match process. Depending on the match bits, the alarm  
occurs as specifically as once a month or as frequently as once  
every minute. Selecting none of the match bits (all 1s) indicates  
that no match is required and therefore, alarm is disabled.  
Selecting all match bits (all 0s) causes an exact time and date  
match.  
Reset the value of OSCF to ‘0’ when the time registers are written  
for the first time. This initializes the state of this bit which may  
have become set when the system was first powered on.  
To reset OSCF, set the write bit “W” (in the Flags register at  
0x1FFF0) to a “1” to enable writes to the Flag register. Write a  
“0” to the OSCF bit and reset the write bit to “0” to disable writes.  
Calibrating the Clock  
The RTC is driven by a quartz controlled crystal with a nominal  
frequency of 32.768 kHz. Clock accuracy depends on the quality  
of the crystal and calibration. The crystals available in market  
typically have an error of +20 ppm to +35 ppm. However,  
CY14B101KA employs a calibration circuit that improves the  
accuracy to +1/–2 ppm at 25°C. This implies an error of +2.5  
seconds to -5 seconds per month.  
There are two ways to detect an alarm event: by reading the AF  
flag or monitoring the INT pin. The AF flag in the flags register at  
0x1FFF0 indicates that a date or time match has occurred. The  
AF bit is set to “1” when a match occurs. Reading the flags  
register clears the alarm flag bit (and all others). A hardware  
interrupt pin may also be used to detect an alarm event.  
To set, clear or enable an alarm, set the ‘W’ bit (in Flags Register  
- 0x1FFF0) to ‘1’ to enable writes to Alarm Registers. After writing  
the alarm value, clear the ‘W’ bit back to “0” for the changes to  
take effect.  
The calibration circuit adds or subtracts counts from the oscillator  
divider circuit to achieve this accuracy. The number of pulses that  
are suppressed (subtracted, negative calibration) or split (added,  
positive calibration) depends upon the value loaded into the five  
calibration bits found in Calibration register at 0x1FFF8. The  
calibration bits occupy the five lower order bits in the Calibration  
register. These bits are set to represent any value between ‘0’  
and 31 in binary form. Bit D5 is a sign bit, where a ‘1’ indicates  
positive calibration and a ‘0’ indicates negative calibration.  
Adding counts speeds the clock up and subtracting counts slows  
the clock down. If a binary ‘1’ is loaded into the register, it corre-  
sponds to an adjustment of 4.068 or –2.034 ppm offset in oscil-  
lator error, depending on the sign.  
Note CY14B101KA requires the alarm match bit for seconds  
(0x1FFF2 - D7) to be set to ‘0’ for proper operation of Alarm Flag  
and Interrupt.  
Watchdog Timer  
The Watchdog Timer is a free running down counter that uses  
the 32 Hz clock (31.25 ms) derived from the crystal oscillator.  
The oscillator must be running for the watchdog to function. It  
begins counting down from the value loaded in the Watchdog  
Timer register.  
Calibration occurs within a 64-minute cycle. The first 62 minutes  
in the cycle may, once per minute, have one second shortened  
by 128 or lengthened by 256 oscillator cycles. If a binary ‘1’ is  
loaded into the register, only the first two minutes of the  
64-minute cycle are modified. If a binary 6 is loaded, the first 12  
are affected, and so on. Therefore, each calibration step has the  
effect of adding 512 or subtracting 256 oscillator cycles for every  
The timer consists of a loadable register and a free running  
counter. On power up, the watchdog time out value in register  
0x1FFF7 is loaded into the Counter Load register. Counting  
begins on power up and restarts from the loadable value any time  
the Watchdog Strobe (WDS) bit is set to ‘1’. The counter is  
compared to the terminal value of ‘0’. If the counter reaches this  
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CY14B101KA/CY14B101MA  
PRELIMINARY  
value, it causes an internal flag and an optional interrupt output.  
Interrupts  
You can prevent the time out interrupt by setting WDS bit to ‘1’  
prior to the counter reaching ‘0’. This causes the counter to  
reload with the watchdog time out value and to be restarted. As  
long as the user sets the WDS bit prior to the counter reaching  
the terminal value, the interrupt and WDT flag never occur.  
The CY14B101KA has Flags register, Interrupt register and  
Interrupt logic that can signal interrupt to the microcontroller.  
There are three potential sources for interrupt: watchdog timer,  
power monitor, and alarm timer. Each of these can be individually  
enabled to drive the INT pin by appropriate setting in the Interrupt  
register (0x1FFF6). In addition, each has an associated flag bit  
in the Flags register (0x1FFF0) that the host processor uses to  
determine the cause of the interrupt. The INT pin driver has two  
bits that specify its behavior when an interrupt occurs.  
New time out values are written by setting the watchdog write bit  
to ‘0’. When the WDW is ‘0’, new writes to the watchdog time out  
value bits D5-D0 are enabled to modify the time out value. When  
WDW is ‘1’, writes to bits D5-D0 are ignored. The WDW function  
enables a user to set the WDS bit without concern that the  
watchdog timer value is modified. A logical diagram of the  
watchdog timer is shown in Figure 3. Note that setting the  
watchdog time out value to ‘0’ disables the watchdog function.  
An Interrupt is raised only if both a flag is raised by one of the  
three sources and the respective interrupt enable bit in Interrupts  
register is enabled (set to ‘1’). After an interrupt source is active,  
two programmable bits, H/L and P/L, determine the behavior of  
the output pin driver on INT pin. These two bits are located in the  
Interrupt register and can be used to drive level or pulse mode  
output from the INT pin. In pulse mode, the pulse width is  
internally fixed at approximately 200 ms. This mode is intended  
to reset a host microcontroller. In the level mode, the pin goes to  
its active polarity until the Flags register is read by the user. This  
mode is used as an interrupt to a host microcontroller. The  
control bits are summarized in the following section.  
The output of the watchdog timer is the flag bit WDF that is set if  
the watchdog is allowed to time out. If the Watchdog Interrupt  
Enable (WIE) bit in the Interrupt register is set, a hardware  
interrupt on INT pin is also generated on watchdog timeout. The  
flag and the hardware interrupt are both cleared when user reads  
the Flags registers.  
.
Figure 3. Watchdog Timer Block Diagram  
Interrupts are only generated while working on normal power and  
are not triggered when system is running in backup power mode.  
Clock  
Oscillator  
1 Hz  
Divider  
32,768 KHz  
Note CY14B101KA generates valid interrupts only after the  
Powerup Recall sequence is completed. All events on INT pin  
must be ignored for tHRECALL duration after powerup.  
32 Hz  
Zero  
Compare  
WDF  
Counter  
Interrupt Register  
Watchdog Interrupt Enable - WIE. When set to ‘1’, the  
watchdog timer drives the INT pin and an internal flag when a  
watchdog time out occurs. When WIE is set to ‘0’, the watchdog  
timer only affects the WDF flag in Flags register.  
Load  
WDS  
Register  
Q
D
WDW  
Alarm Interrupt Enable - AIE. When set to ‘1’, the alarm match  
drives the INT pin and an internal flag. When AIE is set to ‘0’, the  
alarm match only affects the AF Flag in Flags register.  
Q
Watchdog  
Register  
write to  
Watchdog  
Register  
Power Fail Interrupt Enable - PFE. When set to ‘1’, the power  
fail monitor drives the pin and an internal flag. When PFE is set  
to ‘0’, the power fail monitor only affects the PF flag in Flags  
register.  
Power Monitor  
High/Low - H/L. When set to a ‘1’, the INT pin is active HIGH  
and the driver mode is push pull. The INT pin drives high only  
when VCC is greater than VSWITCH. When set to a ‘0’, the INT pin  
is active LOW and the drive mode is open drain. The INT pin  
must be pulled up to Vcc by a 10k resistor while using the  
interrupt in active LOW mode.  
The CY14B101KA provides a power management scheme with  
power fail interrupt capability. It also controls the internal switch  
to backup power for the clock and protects the memory from low  
V
CC access. The power monitor is based on an internal band gap  
reference circuit that compares the VCC voltage to VSWITCH  
threshold.  
Pulse/Level - P/L. When set to a ‘1’ and an interrupt occurs, the  
INT pin is driven for approximately 200 ms. When P/L is set to a  
‘0’, the INT pin is driven high or low (determined by H/L) until the  
Flags or Control register is read.  
As described in the AutoStore Operation on page 3, when  
VSWITCH is reached as VCC decays from power loss, a data  
STORE operation is initiated from SRAM to the nonvolatile  
elements, securing the last SRAM data state. Power is also  
switched from VCC to the backup supply (battery or capacitor) to  
operate the RTC oscillator.  
When an enabled interrupt source activates the INT pin, an  
external host reads the Flags registers to determine the cause.  
All flags are cleared when the register is read. If the INT pin is  
programmed for Level mode, then the condition clears and the  
INT pin returns to its inactive state. If the pin is programmed for  
Pulse mode, then reading the flag also clears the flag and the  
pin. The pulse does not complete its specified duration if the  
Flags register is read. If the INT pin is used as a host reset, then  
the Flags register is not read during a reset.  
When operating from the backup source, read and write opera-  
tions to nvSRAM are inhibited and the clock functions are not  
available to the user. The clock continues to operate in the  
background. The updated clock data is available to the user  
tHRECALL delay after VCC is restored to the device (see  
AutoStore/Power Up RECALL on page 20).  
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CY14B101KA/CY14B101MA  
PRELIMINARY  
ically reset when the register is read. The flags register is  
automatically loaded with the value 0x00 on power up (except for  
the OSCF bit; see Stopping and Starting the Oscillator on page  
8).  
Flags Register  
The Flag register has three flag bits: WDF, AF, and PF, which can  
be used to generate an interrupt. These flags are set by the  
watchdog timeout, alarm match, or power fail monitor respec-  
tively. The processor can either poll this register or enable inter-  
rupts to be informed when a flag is set. These flags are automat-  
Figure 4. RTC Recommended Component Configuration  
Recommended Values  
= 32.768 KHz (12.5 pF)  
Y
1
C1 = 10 pF  
C2 = 67 pF  
Note: The recommended values for C1 and C2 include  
board trace capacitance.  
C1  
C2  
X
out  
Y1  
X
in  
Figure 5. Interrupt Block Diagram  
WDF  
Watchdog  
Timer  
WDF - Watchdog Timer Flag  
WIE - Watchdog Interrupt  
Enable  
WIE  
PF  
V
CC  
P/L  
PF - Power Fail Flag  
PFE - Power Fail Enable  
Power  
Pin  
Monitor  
INT  
AF - Alarm Flag  
AIE - Alarm Interrupt Enable  
PFE  
Driver  
VINT  
P/L - Pulse Level  
H/L - High/Low  
H/L  
V
SS  
AF  
Clock  
Alarm  
AIE  
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CY14B101KA/CY14B101MA  
PRELIMINARY  
Table 3. RTC Register Map[10, 11, 12]  
Register  
BCD Format Data[11]  
Function/Range  
CY14B101KA CY14B101MA  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
Years  
D0  
0x1FFFF  
0x1FFFE  
0x0FFFF  
0x0FFFE  
10s Years  
Years: 00–99  
0
0
0
0
0
10s  
Months  
Months  
Months: 01–12  
0x1FFFD  
0x0FFFD  
10s Day of  
Month  
Day Of Month  
Day of Month: 01–31  
0x1FFFC  
0x1FFFB  
0x1FFFA  
0x1FFF9  
0x1FFF8  
0x0FFFC  
0x0FFFB  
0x0FFFA  
0x0FFF9  
0x0FFF8  
0
0
0
0
0
0
0
0
0
Day of Week  
Day of Week: 01–07  
Hours: 00–23  
10s Hours  
10s Minutes  
Hours  
Minutes  
Seconds  
Minutes: 00–59  
10s Seconds  
Seconds: 00–59  
Calibration Values [13]  
OSCEN  
(0)  
0
Cal  
Sign  
(0)  
Calibration (00000)  
0x1FFF7  
0x1FFF6  
0x1FFF5  
0x1FFF4  
0x0FFF7  
0x0FFF6  
0x0FFF5  
0x0FFF4  
WDS (0) WDW  
(0)  
WDT (000000)  
Watchdog [13]  
Interrupts [13]  
WIE (0)  
AIE  
(0)  
PFE  
(0)  
0
H/L (1) P/L  
(0)  
0
0
M (1)  
0
10s Alarm Date  
Alarm Day  
Alarm, Day of Month:  
01–31  
M (1)  
0
10s Alarm  
Hours  
Alarm Hours  
Alarm, Hours: 00–23  
0x1FFF3  
0x1FFF2  
0x1FFF1  
0x1FFF0  
0x0FFF3  
0x0FFF2  
0x0FFF1  
0x0FFF0  
M (1)  
M (1)  
10 Alarm Minutes  
10 Alarm Seconds  
10s Centuries  
Alarm Minutes  
Alarm, Seconds  
Centuries  
Alarm, Minutes: 00–59  
Alarm, Seconds: 00–59  
Centuries: 00–99  
Flags [13]  
WDF  
AF  
PF  
OSCF  
0
CAL W (0)  
(0)  
R (0)  
Notes  
10. Upper byte D15-D8 (CY14B101MA) of RTC registers are reserved for future use.  
11. The unused bits of RTC registers are reserved for future use and should be set to ‘0’.  
12. ( ) designates values shipped from the factory.  
13. This is a binary value, not a BCD value.  
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CY14B101KA/CY14B101MA  
PRELIMINARY  
Table 4. Register Map Detail  
Register  
Description  
CY14B101KA CY14B101MA  
Time Keeping - Years  
D4 D3  
0x1FFFF  
0x1FFFE  
0x1FFFD  
0x1FFFC  
0x1FFFB  
0x1FFFA  
0x1FFF9  
0x0FFFF  
0x0FFFE  
0x0FFFD  
0x0FFFC  
0x0FFFB  
0x0FFFA  
0x0FFF9  
D7  
D6  
D5  
10s Years  
D2  
D1  
D0  
Years  
Contains the lower two BCD digits of the year. Lower nibble (four bits) contains the value for years;  
upper nibble (four bits) contains the value for 10s of years. Each nibble operates from 0 to 9. The  
range for the register is 0–99.  
Time Keeping - Months  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
Months  
D0  
0
0
0
10s Month  
Contains the BCD digits of the month. Lower nibble (four bits) contains the lower digit and operates  
from 0 to 9; upper nibble (one bit) contains the upper digit and operates from 0 to 1. The range  
for the register is 1–12.  
Time Keeping - Date  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
0
0
10s Day of Month  
Day of Month  
Contains the BCD digits for the date of the month. Lower nibble (four bits) contains the lower digit  
and operates from 0 to 9; upper nibble (two bits) contains the 10s digit and operates from 0 to 3.  
The range for the register is 1–31. Leap years are automatically adjusted for.  
Time Keeping - Day  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
0
0
0
0
0
Day of Week  
Lower nibble (three bits) contains a value that correlates to day of the week. Day of the week is  
a ring counter that counts from 1 to 7 then returns to 1. The user must assign meaning to the day  
value, because the day is not integrated with the date.  
Time Keeping - Hours  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
0
0
10s Hours  
Hours  
Contains the BCD value of hours in 24 hour format. Lower nibble (four bits) contains the lower  
digit and operates from 0 to 9; upper nibble (two bits) contains the upper digit and operates from  
0 to 2. The range for the register is 0–23.  
Time Keeping - Minutes  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
Minutes  
D0  
0
10s Minutes  
Contains the BCD value of minutes. Lower nibble (four bits) contains the lower digit and operates  
from 0 to 9; upper nibble (three bits) contains the upper minutes digit and operates from 0 to 5.  
The range for the register is 0–59.  
Time Keeping - Seconds  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
Seconds  
D0  
0
10s Seconds  
Contains the BCD value of seconds. Lower nibble (four bits) contains the lower digit and operates  
from 0 to 9; upper nibble (three bits) contains the upper digit and operates from 0 to 5. The range  
for the register is 0–59.  
Document #: 001-42880 Rev. *C  
Page 12 of 29  
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CY14B101KA/CY14B101MA  
PRELIMINARY  
Table 4. Register Map Detail (continued)  
Register  
Description  
CY14B101KA CY14B101MA  
Calibration/Control  
D4 D3  
0x1FFF8  
0x0FFF8  
D7  
D6  
D5  
D2  
D1  
D0  
OSCEN  
0
Calibration  
Sign  
Calibration  
OSCEN  
Oscillator Enable. When set to 1, the oscillator is stopped. When set to 0, the oscillator runs.  
Disabling the oscillator saves battery or capacitor power during storage.  
Calibration  
Sign  
Determines if the calibration adjustment is applied as an addition (1) to or as a subtraction (0)  
from the time-base.  
Calibration  
These five bits control the calibration of the clock.  
WatchDog Timer  
0x1FFF7  
0x0FFF7  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
WDS  
WDW  
WDT  
WDS  
Watchdog Strobe. Setting this bit to 1 reloads and restarts the watchdog timer. Setting the bit to  
0 has no effect. The bit is cleared automatically after the watchdog timer is reset. The WDS bit is  
write only. Reading it always returns a 0.  
WDW  
Watchdog Write Enable. Setting this bit to 1 disables any WRITE to the watchdog timeout value  
(D5–D0). This allows the user to set the watchdog strobe bit without disturbing the timeout value.  
Setting this bit to 0 allows bits D5–D0 to be written to the watchdog register when the next write  
cycle is complete. This function is explained in more detail in Watchdog Timer on page 8.  
WDT  
Watchdog timeout selection. The watchdog timer interval is selected by the 6-bit value in this  
register. It represents a multiplier of the 32 Hz count (31.25 ms). The range of timeout value is  
31.25 ms (a setting of 1) to 2 seconds (setting of 3 Fh). Setting the watchdog timer register to 0  
disables the timer. These bits can be written only if the WDW bit was set to 0 on a previous cycle.  
Interrupt Status/Control  
0x1FFF6  
0x0FFF6  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
WIE  
AIE  
PFE  
0
H/L  
P/L  
0
0
WIE  
Watchdog Interrupt Enable. When set to 1 and a watchdog timeout occurs, the watchdog timer  
drives the INT pin and the WDF flag. When set to 0, the watchdog timeout affects only the WDF  
flag.  
AIE  
Alarm Interrupt Enable. When set to 1, the alarm match drives the INT pin and the AF flag. When  
set to 0, the alarm match only affects the AF flag.  
PFE  
Power Fail Enable. When set to 1, the power fail monitor drives the INT pin and the PF flag. When  
set to 0, the power fail monitor affects only the PF flag.  
0
Reserved for future use  
H/L  
High/Low. When set to 1, the INT pin is driven active HIGH. When set to 0, the INT pin is open  
drain, active LOW.  
P/L  
Pulse/Level. When set to 1, the INT pin is driven active (determined by H/L) by an interrupt source  
for approximately 200 ms. When set to 0, the INT pin is driven to an active level (as set by H/L)  
until the flags register is read.  
Alarm - Day  
0x1FFF5  
0x0FFF5  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
M
0
10s Alarm Date  
Alarm Date  
Contains the alarm value for the date of the month and the mask bit to select or deselect the date  
value.  
M
Match. When this bit is set to 0, the date value is used in the alarm match. Setting this bit to 1  
causes the match circuit to ignore the date value.  
Document #: 001-42880 Rev. *C  
Page 13 of 29  
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CY14B101KA/CY14B101MA  
PRELIMINARY  
Table 4. Register Map Detail (continued)  
Register  
Description  
CY14B101KA CY14B101MA  
Alarm - Hours  
D4 D3  
10s Alarm Hours  
0x1FFF4  
0x1FFF3  
0x1FFF2  
0x0FFF4  
0x0FFF3  
0x0FFF2  
D7  
D6  
D5  
D2  
D1  
D0  
M
0
Alarm Hours  
Contains the alarm value for the hours and the mask bit to select or deselect the hours value.  
M
M
M
Match. When this bit is set to 0, the hours value is used in the alarm match. Setting this bit to 1  
causes the match circuit to ignore the hours value.  
Alarm - Minutes  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
M
0
10s Alarm Minutes  
Alarm Minutes  
Contains the alarm value for the minutes and the mask bit to select or deselect the minutes value.  
Match. When this bit is set to 0, the minutes value is used in the alarm match. Setting this bit to  
1 causes the match circuit to ignore the minutes value.  
Alarm - Seconds  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
M
0
10s Alarm Seconds  
Alarm Seconds  
Contains the alarm value for the seconds and the mask bit to select or deselect the seconds’ value.  
Match. When this bit is set to 0, the seconds value is used in the alarm match. Setting this bit to  
1 causes the match circuit to ignore the seconds value.  
Time Keeping - Centuries  
0x1FFF1  
0x1FFF0  
0x0FFF1  
0x0FFF0  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
Centuries  
D0  
0
0
10s Centuries  
Contains the BCD value of centuries. Lower nibble (four bits) contains the lower digit and operates  
from 0 to 9; upper nibble (two bits) contains the upper digit and operates from 0 to 9. The range  
for the register is 0-99 centuries.  
Flags  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
WDF  
AF  
PF  
OSCF  
0
CAL  
W
R
WDF  
AF  
Watchdog Timer Flag. This read only bit is set to 1 when the watchdog timer is allowed to reach  
0 without being reset by the user. It is cleared to 0 when the Flags register is read or on power up  
Alarm Flag. This read only bit is set to 1 when the time and date match the values stored in the  
alarm registers with the match bits = 0. It is cleared when the Flags register is read or on power up.  
PF  
Power Fail Flag. This read only bit is set to 1 when power falls below the power fail threshold  
VSWITCH. It is cleared to 0 when the Flags register is read or on power up.  
OSCF  
Oscillator Fail Flag. Set to 1 on power up if the oscillator is enabled and not running in the first 5  
ms of operation. This indicates that RTC backup power failed and clock value is no longer valid.  
This bit survives power cycle and is never cleared internally by the chip. The user must check for  
this condition and write '0' to clear this flag.  
CAL  
W
Calibration Mode. When set to 1, a 512 Hz square wave is output on the INT pin. When set to 0,  
the INT pin resumes normal operation. This bit defaults to 0 (disabled) on power up.  
Write Enable: Setting the W bit to 1 freezes updates of the RTC registers. The user can then write  
to RTC registers, Alarm registers, Calibration register, Interrupt register and Flags register. Setting  
the W bit to 0 transfers the contents of the RTC registers to the time keeping counters if the time  
is changed (a new base time is loaded). This bit defaults to 0 on power up.  
R
Read Enable: Setting R bit to 1, stops clock updates to user RTC registers so that clock updates  
are not seen during the reading process. Set R bit to 0 to resume clock updates to the holding  
register. Setting this bit does not require W bit to be set to 1. This bit defaults to 0 on power up.  
Document #: 001-42880 Rev. *C  
Page 14 of 29  
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CY14B101KA/CY14B101MA  
PRELIMINARY  
Package Power Dissipation  
Capability (TA = 25°C) ................................................... 1.0W  
Maximum Ratings  
Exceeding maximum ratings may impair the useful life of the  
device. These user guidelines are not tested.  
Surface Mount Pb Soldering  
Temperature (3 Seconds).......................................... +260°C  
Storage Temperature ................................. –65°C to +150°C  
Maximum Accumulated Storage Time  
DC Output Current (1 output at a time, 1s duration).....15 mA  
Static Discharge Voltage.......................................... > 2001V  
(per MIL-STD-883, Method 3015)  
At 150°C Ambient Temperature........................ 1000h  
At 85°C Ambient Temperature..................... 20 Years  
Ambient Temperature with Power Applied.. –55°C to +150°C  
Supply Voltage on VCC Relative to GND ..........–0.5V to 4.1V  
Latch Up Current ................................................... > 200 mA  
Operating Range  
Voltage Applied to Outputs  
in High-Z State.......................................–0.5V to VCC + 0.5V  
Range  
Commercial  
Industrial  
Ambient Temperature  
0°C to +70°C  
VCC  
2.7V to 3.6V  
Input Voltage.............................................–0.5V to Vcc+0.5V  
–40°C to +85°C  
Transient Voltage (<20 ns) on  
Any Pin to Ground Potential ..................–2.0V to VCC + 2.0V  
DC Electrical Characteristics  
Over the Operating Range (VCC = 2.7V to 3.6V)  
Parameter  
VCC  
Description  
Test Conditions  
Min Typ[14] Max Unit  
Power Supply Voltage  
2.7  
3.0  
3.6  
V
ICC1  
Average Vcc Current tRC = 20 ns  
tRC = 25 ns  
Commercial  
Industrial  
65  
65  
50  
mA  
mA  
t
RC = 45 ns  
Values obtained without output loads (IOUT = 0 mA)  
70  
70  
52  
mA  
mA  
mA  
ICC2  
Average VCC Current All Inputs Don’t Care, VCC = Max.  
during STORE Average current for duration tSTORE  
Average VCC Current All I/P cycling at CMOS levels.  
10  
mA  
[14]  
35  
mA  
ICC3  
at tRC= 200 ns,  
VCC (Typ), 25°C  
Values obtained without output loads (IOUT = 0 mA).  
ICC4  
Average VCAP  
Current during  
AutoStore Cycle  
All Inputs Don’t Care, VCC = Max.  
Average current for duration tSTORE  
5
5
mA  
mA  
ISB  
VCC Standby Current CE > (VCC – 0.2V). VIN < 0.2V or > (VCC – 0.2V).  
Standby current level after nonvolatile cycle is complete.  
Inputs are static. f = 0 MHz.  
[15]  
Input Leakage  
Current (except HSB)  
VCC = Max, VSS < VIN < VCC  
–1  
–100  
–1  
+1  
+1  
+1  
µA  
µA  
µA  
IIX  
Input Leakage  
Current (for HSB)  
VCC = Max, VSS < VIN < VCC  
IOZ  
Off State Output  
Leakage Current  
VCC = Max, VSS < VOUT < VCC, CE or OE > VIH or BHE/BLE > VIH  
or WE < VIL  
VIH  
VIL  
Input HIGH Voltage  
2.0  
VCC  
0.5  
+
V
V
Input LOW Voltage  
VSS  
0.5  
–
0.8  
VOH  
VOL  
Output HIGH Voltage IOUT = –2 mA  
Output LOW Voltage IOUT = 4 mA  
2.4  
V
V
0.4  
Storage Capacitor  
Between VCAP pin and VSS, 5V Rated  
61  
68  
180  
µF  
VCAP  
Notes  
14. Typical values are at 25°C, V = V (Typ). Not 100% tested.  
CC  
CC  
15. The HSB pin has I  
= -2 uA for V of 2.4V when both active HIGH and low drivers are disabled. When they are enabled standard V and V are valid. This  
OUT  
O
H
O
H
O
L
parameter is characterized but not tested.  
Document #: 001-42880 Rev. *C  
Page 15 of 29  
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CY14B101KA/CY14B101MA  
PRELIMINARY  
Capacitance  
Parameter[16]  
Description  
Input Capacitance  
Output Capacitance  
Test Conditions  
TA = 25°C, f = 1 MHz,  
CC = VCC (Typ)  
Max  
7
Unit  
pF  
CIN  
V
COUT  
7
pF  
Thermal Resistance  
Parameter[16]  
Description  
Test Conditions  
48 SSOP 44 TSOP II 54 TSOP II Unit  
ΘJA  
Thermal Resistance  
(Junction to Ambient)  
Test conditions follow standard  
test methods and procedures for  
measuringthermalimpedance, in  
accordance with EIA/JESD51.  
TBD  
31.11  
30.73  
°C/W  
ΘJC  
Thermal Resistance  
(Junction to Case)  
TBD  
5.56  
6.08  
°C/W  
Figure 6. AC Test Loads  
577Ω  
577Ω  
R1  
3.0V  
3.0V  
OUTPUT  
R1  
OUTPUT  
R2  
789Ω  
R2  
789Ω  
5 pF  
30 pF  
AC Test Conditions  
Input Pulse Levels ....................................................0V to 3V  
Input Rise and Fall Times (10% - 90%)........................ <3 ns  
Input and Output Timing Reference Levels .................... 1.5V  
RTC Characteristics  
Parameters  
Description  
RTC Battery Pin Voltage  
Min  
Typ[14]  
Max  
Units  
V
VRTCbat  
1.8  
3.0  
3.3  
[17]  
IBAK  
RTC Backup Current  
TA (Min)  
350  
nA  
nA  
nA  
V
25°C  
350  
TA (Max)  
TA (Min)  
25°C  
500  
3.6  
3.6  
3.6  
2
[18]  
VRTCcap  
RTC Capacitor Pin Voltage  
RTC Oscillator Time to Start  
1.6  
1.5  
1.4  
3.0  
3.0  
3.0  
1
V
TA (Max)  
V
tOCS  
sec  
Ω
RBKCHG  
RTC Backup Capacitor Charge Current-Limiting  
Resistor  
450  
850  
Notes  
16. These parameters are guaranteed by design and are not tested.  
17. From either V or V  
RTCcap  
RTCbat.  
18. If V  
> 0.3V or if no capacitor is connected to V  
pin, the oscillator starts in tOCS time. If a backup capacitor is connected and vrtccap < 0.3V, the capacitor  
RTCcap  
RTCcap  
must be allowed to charge to 0.3V for oscillator to start.  
Document #: 001-42880 Rev. *C  
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CY14B101KA/CY14B101MA  
PRELIMINARY  
AC Switching Characteristics  
Parameters  
20 ns  
25 ns  
45 ns  
Description  
Unit  
Cypress  
Parameters  
Alt  
Min  
Max  
Min  
Max  
Min  
Max  
Parameters  
SRAM Read Cycle  
tACE  
tACS  
tRC  
Chip Enable Access Time  
20  
25  
45  
ns  
ns  
[19]  
Read Cycle Time  
20  
25  
45  
tRC  
[20]  
tAA  
tOE  
tOH  
tLZ  
Address Access Time  
20  
10  
25  
12  
45  
20  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tAA  
tDOE  
Output Enable to Data Valid  
Output Hold After Address Change  
Chip Enable to Output Active  
Chip Disable to Output Inactive  
Output Enable to Output Active  
Output Disable to Output Inactive  
Chip Enable to Power Active  
Chip Disable to Power Standby  
[20]  
3
3
3
3
3
3
tOHA  
[16, 21]  
[16, 21]  
[16, 21]  
[16, 21]  
tLZCE  
tHZCE  
tLZOE  
tHZOE  
tHZ  
tOLZ  
tOHZ  
tPA  
8
8
10  
10  
15  
15  
0
0
0
0
0
0
[16]  
tPU  
[16]  
tPS  
20  
10  
25  
12  
45  
20  
tPD  
tDBE  
-
-
-
Byte Enable to Data Valid  
ns  
ns  
ns  
[16]  
[16]  
tLZBE  
Byte Enable to Output Active  
Byte Disable to Output Inactive  
0
0
0
tHZBE  
8
10  
15  
SRAM Write Cycle  
tWC  
tPWE  
tSCE  
tSD  
tWC  
Write Cycle Time  
20  
15  
15  
8
25  
20  
20  
10  
0
45  
30  
30  
15  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
tWP  
tCW  
tDW  
tDH  
tAW  
tAS  
Write Pulse Width  
Chip Enable To End of Write  
Data Setup to End of Write  
Data Hold After End of Write  
Address Setup to End of Write  
Address Setup to Start of Write  
Address Hold After End of Write  
Write Enable to Output Disable  
tHD  
0
tAW  
tSA  
15  
0
20  
0
30  
0
tHA  
tWR  
tWZ  
tOW  
-
0
0
0
[16, 21, 22]  
[16, 21]  
8
10  
15  
tHZWE  
Output Active after End of Write  
Byte Enable to End of Write  
3
3
3
ns  
ns  
tLZWE  
tBW  
15  
20  
30  
Switching Waveforms  
Figure 7. SRAM Read Cycle #1: Address Controlled [19, 20, 23]  
tRC  
Address  
Address Valid  
tAA  
Output Data Valid  
Previous Data Valid  
tOHA  
Data Output  
Notes  
19. WE must be HIGH during SRAM read cycles.  
20. Device is continuously selected with CE, OE and BHE/BLE LOW.  
21. Measured ±200 mV from steady state output voltage.  
22. If WE is low when CE goes low, the outputs remain in the high impedance state.  
23. HSB must remain HIGH during Read and Write cycles.  
Document #: 001-42880 Rev. *C  
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CY14B101KA/CY14B101MA  
PRELIMINARY  
Figure 8. SRAM Read Cycle #2: CE Controlled [3, 19, 23]  
tWC  
Address Valid  
Address  
tSA  
tSCE  
tHA  
CE  
tBW  
BHE, BLE  
tPWE  
WE  
tHD  
tSD  
Input Data Valid  
Data Input  
High Impedance  
Data Output  
Figure 9. SRAM Write Cycle #1: WE Controlled [3, 22, 23, 24]  
tWC  
Address  
Address Valid  
tSCE  
tHA  
CE  
tBW  
BHE, BLE  
tAW  
tPWE  
WE  
Data Input  
Data Output  
tSA  
tHD  
tSD  
Input Data Valid  
tLZWE  
tHZWE  
High Impedance  
Previous Data  
Note  
24. CE or WE must be >V during address transitions.  
IH  
Document #: 001-42880 Rev. *C  
Page 18 of 29  
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CY14B101KA/CY14B101MA  
PRELIMINARY  
Figure 10. SRAM Write Cycle #2: CE Controlled [3, 22, 23, 24]  
tWC  
Address Valid  
Address  
tSA  
tSCE  
tHA  
CE  
tBW  
BHE, BLE  
tPWE  
WE  
tHD  
tSD  
Input Data Valid  
Data Input  
High Impedance  
Data Output  
Figure 11. SRAM Write Cycle #3: BHE and BLE Controlled [3, 22, 23, 24, 25]  
(Not applicable for RTC register writes)  
tWC  
Address  
CE  
Address Valid  
tSCE  
tSA  
tHA  
tBW  
BHE, BLE  
WE  
tAW  
tPWE  
tSD  
tHD  
Data Input  
Input Data Valid  
High Impedance  
Data Output  
Note  
25. Only CE and WE controlled writes to RTC registers are allowed. BLE pin must be held LOW before CE or WE pin goes LOW for writes to RTC register.  
Document #: 001-42880 Rev. *C  
Page 19 of 29  
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CY14B101KA/CY14B101MA  
PRELIMINARY  
AutoStore/Power Up RECALL  
20ns  
25ns  
45ns  
Parameters  
Description  
Unit  
Min  
Max  
Min  
Max  
Min  
Max  
[26]  
Power Up RECALL Duration  
STORE Cycle Duration  
20  
8
20  
20  
ms  
ms  
ns  
V
tHRECALL  
[27]  
8
8
tSTORE  
[28]  
Time Allowed to Complete SRAM Write Cycle  
Low Voltage Trigger Level  
VCC Rise Time  
20  
25  
25  
tDELAY  
2.65  
2.65  
2.65  
VSWITCH  
[16]  
150  
150  
150  
µs  
V
tVCCRISE  
[16]  
HSB Output Disable Voltage  
1.9  
1.9  
1.9  
VHDIS  
[16]  
tLZHSB  
HSB To Output Active Time  
HSB High Active Time  
5
5
5
µs  
ns  
[16]  
tHHHD  
500  
500  
500  
Switching Waveforms  
Figure 12. AutoStore or Power Up RECALL [29]  
VCC  
VSWITCH  
VHDIS  
27  
27  
VVCCRISE  
tSTORE  
tSTORE  
30  
Note  
Note  
Note  
tHHHD  
tHHHD  
HSB OUT  
AutoStore  
tDELAY  
tLZHSB  
tLZHSB  
tDELAY  
POWER-  
UP  
RECALL  
tHRECALL  
tHRECALL  
Read & Write  
Inhibited  
(RWI)  
Read & Write  
Read & Write  
POWER-UP  
RECALL  
BROWN  
OUT  
AutoStore  
POWER  
DOWN  
AutoStore  
POWER-UP  
RECALL  
Notes  
26. t  
starts from the time V rises above V  
SWITCH.  
HRECALL  
CC  
27. If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware STORE takes place  
28. On a Hardware Store and AutoStore initiation, SRAM write operation continues to be enabled for time t  
.
DELAY  
29. Read and Write cycles are ignored during STORE, RECALL, and while VCC is below V  
SWITCH.  
30. HSB pin is driven HIGH to VCC only by internal 100 kΩ resistor, HSB driver is disabled.  
Document #: 001-42880 Rev. *C  
Page 20 of 29  
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CY14B101KA/CY14B101MA  
PRELIMINARY  
Software Controlled STORE/RECALL Cycle  
20 ns  
25 ns  
45 ns  
Parameters[31, 32]  
Description  
Unit  
Min  
Max  
Min  
Max  
Min  
Max  
tRC  
tSA  
tCW  
tHA  
STORE/RECALL Initiation Cycle Time  
Address Setup Time  
Clock Pulse Width  
Address Hold Time  
RECALL Duration  
20  
0
15  
0
25  
0
20  
0
45  
0
30  
0
ns  
ns  
ns  
ns  
µs  
µs  
tRECALL  
200  
100  
200  
100  
200  
100  
[33, 34]  
Soft Sequence Processing Time  
tSS  
Switching Waveforms  
Figure 13. CE & OE Controlled Software STORE/RECALL Cycle [32]  
tRC  
tRC  
Address  
Address #1  
tCW  
Address #6  
tCW  
tSA  
CE  
tSA  
tHA  
tHA  
tHA  
tHA  
OE  
tHHHD  
tHZCE  
HSB (STORE only)  
DQ (DATA)  
35  
Note  
tDELAY  
tLZCE  
tLZHSB  
High Impedance  
tSTORE/tRECALL  
RWI  
Figure 14. AutoStore Enable/Disable Cycle  
tRC  
tRC  
Address  
Address #1  
Address #6  
tCW  
tSA  
tCW  
CE  
tSA  
tHA  
tHA  
tHA  
tHA  
OE  
tSS  
tHZCE  
35  
Note  
tLZCE  
tDELAY  
DQ (DATA)  
Notes  
31. The software sequence is clocked with CE controlled or OE controlled reads.  
32. The six consecutive addresses must be read in the order listed in Table 1. WE must be HIGH during all six consecutive cycles.  
33. This is the amount of time it takes to take action on a soft sequence command. Vcc power must remain HIGH to effectively register command.  
34. Commands such as STORE and RECALL lock out I/O until operation is complete which further increases this time. See the specific command.  
35. DQ output data at the sixth read may be invalid since the output is disabled at t  
time.  
DELAY  
Document #: 001-42880 Rev. *C  
Page 21 of 29  
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CY14B101KA/CY14B101MA  
PRELIMINARY  
Hardware STORE Cycle  
20ns  
25ns  
45ns  
Parameters  
Description  
Unit  
Min  
Max  
Min  
Max  
Min  
Max  
tDHSB  
tPHSB  
HSB To Output Active Time when write latch not set  
Hardware STORE Pulse Width  
20  
25  
25  
ns  
ns  
15  
15  
15  
Switching Waveforms  
Figure 15. Hardware STORE Cycle[27]  
Write latch set  
tPHSB  
HSB (IN)  
tSTORE  
tHHHD  
tDELAY  
HSB (OUT)  
DQ (Data Out)  
RWI  
tLZHSB  
Write latch not set  
tPHSB  
HSB pin is driven high to VCC only by Internal  
100kOhm resistor,  
HSB (IN)  
HSB driver is disabled  
SRAM is disabled as long as HSB (IN) is driven low.  
tDELAY  
tDHSB  
tDHSB  
HSB (OUT)  
RWI  
Figure 16. Soft Sequence Processing[33, 34]  
tSS  
tSS  
Soft Sequence  
Command  
Soft Sequence  
Command  
Address  
Address #1  
tSA  
Address #6  
tCW  
Address #1  
Address #6  
tCW  
CE  
VCC  
Document #: 001-42880 Rev. *C  
Page 22 of 29  
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CY14B101KA/CY14B101MA  
PRELIMINARY  
Truth Table For SRAM Operations  
HSB must remain HIGH for SRAM operations.  
Table 5. Truth Table for x8 Configuration  
CE  
H
L
WE  
X
OE  
X
Inputs/Outputs[2]  
Mode  
Deselect/Power down  
Power  
High Z  
Standby  
Active  
Active  
Active  
H
L
Data Out (DQ0–DQ7)  
High Z  
Read  
L
H
H
Output Disabled  
Write  
L
L
X
Data in (DQ0–DQ7)  
Table 6. Truth Table for x16 Configuration  
CE  
H
L
WE  
X
OE  
X
BHE[3] BLE[3]  
Inputs/Outputs[2]  
High-Z  
Mode  
Power  
X
H
L
X
H
L
Deselect/Power down  
Output Disabled  
Read  
Standby  
Active  
Active  
Active  
X
X
High-Z  
L
H
L
Data Out (DQ0–DQ15  
)
L
H
L
H
L
Data Out (DQ0–DQ7)  
DQ8–DQ15 in High-Z  
Read  
L
H
L
L
H
Data Out (DQ8–DQ15  
DQ0–DQ7 in High-Z  
)
Read  
Active  
L
L
L
L
L
H
H
H
L
H
H
H
X
X
L
H
L
L
L
H
L
L
High-Z  
High-Z  
High-Z  
Output Disabled  
Output Disabled  
Output Disabled  
Write  
Active  
Active  
Active  
Active  
Active  
L
Data In (DQ0–DQ15  
Data In (DQ0–DQ7)  
DQ8–DQ15 in High-Z  
)
L
H
Write  
L
L
X
L
H
Data In (DQ8–DQ15  
DQ0–DQ7 in High-Z  
)
Write  
Active  
Document #: 001-42880 Rev. *C  
Page 23 of 29  
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CY14B101KA/CY14B101MA  
PRELIMINARY  
Part Numbering Nomenclature  
CY 14 B 101 K A -ZS P 20 X C T  
Option:  
T - Tape and Reel  
Blank - Std.  
Temperature:  
C - Commercial (0 to 70°C)  
I - Industrial (–40 to 85°C)  
Speed:  
20 - 20 ns  
Pb-Free  
25 - 25 ns  
45 - 45 ns  
P - 54 Pin  
Blank - 44 Pin  
Package:  
ZS - TSOP II  
SP - TSSOP  
Die revision:  
Blank: No Rev  
A - 1st Rev  
Data Bus:  
K - x8 + RTC  
M - x16 + RTC  
Density:  
101 - 1 Mb  
Voltage:  
B - 3.0V  
nvSRAM  
14 - AutoStore + Software STORE + Hardware STORE  
Cypress  
Document #: 001-42880 Rev. *C  
Page 24 of 29  
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CY14B101KA/CY14B101MA  
PRELIMINARY  
Ordering Information  
Speed  
Package  
Operating  
Ordering Code  
Package Type  
(ns)  
Diagram  
51-85087  
51-85087  
51-85160  
51-85160  
51-85061  
51-85061  
51-85087  
51-85087  
51-85160  
51-85160  
51-85061  
51-85061  
51-85087  
51-85087  
51-85160  
51-85160  
51-85061  
51-85061  
51-85087  
51-85087  
51-85160  
51-85160  
51-85061  
51-85061  
51-85087  
51-85087  
51-85160  
51-85160  
51-85061  
51-85061  
51-85087  
51-85087  
51-85160  
51-85160  
51-85061  
51-85061  
Range  
20  
CY14B101KA-ZS20XCT  
CY14B101KA-ZS20XC  
CY14B101MA-ZSP20XCT  
CY14B101MA-ZSP20XC  
CY14B101KA-SP20XCT  
CY14B101KA-SP20XC  
CY14B101KA-ZS20XIT  
CY14B101KA-ZS20XI  
CY14B101MA-ZSP20XIT  
CY14B101MA-ZSP20XI  
CY14B101KA-SP20XIT  
CY14B101KA-SP20XI  
CY14B101KA-ZS25XCT  
CY14B101KA-ZS25XC  
CY14B101MA-ZSP25XCT  
CY14B101MA-ZSP25XC  
CY14B101KA-SP25XCT  
CY14B101KA-SP25XC  
CY14B101KA-ZS25XIT  
CY14B101KA-ZS25XI  
CY14B101MA-ZSP25XIT  
CY14B101MA-ZSP25XI  
CY14B101KA-SP25XIT  
CY14B101KA-SP25XI  
CY14B101KA-ZS45XCT  
CY14B101KA-ZS45XC  
CY14B101MA-ZSP45XCT  
CY14B101MA-ZSP45XC  
CY14B101KA-SP45XCT  
CY14B101KA-SP45XC  
CY14B101KA-ZS45XIT  
CY14B101KA-ZS45XI  
CY14B101MA-ZSP45XIT  
CY14B101MA-ZSP45XI  
CY14B101KA-SP45XIT  
CY14B101KA-SP45XI  
44-pin TSOPII  
44-pin TSOPII  
54-pin TSOPII  
54-pin TSOPII  
48-pin SSOP  
48-pin SSOP  
44-pin TSOPII  
44-pin TSOPII  
54-pin TSOPII  
54-pin TSOPII  
48-pin SSOP  
48-pin SSOP  
44-pin TSOPII  
44-pin TSOPII  
54-pin TSOPII  
54-pin TSOPII  
48-pin SSOP  
48-pin SSOP  
44-pin TSOPII  
44-pin TSOPII  
54-pin TSOPII  
54-pin TSOPII  
48-pin SSOP  
48-pin SSOP  
44-pin TSOPII  
44-pin TSOPII  
54-pin TSOPII  
54-pin TSOPII  
48-pin SSOP  
48-pin SSOP  
44-pin TSOPII  
44-pin TSOPII  
54-pin TSOPII  
54-pin TSOPII  
48-pin SSOP  
48-pin SSOP  
Commercial  
Industrial  
Commercial  
Industrial  
25  
45  
Commercial  
Industrial  
All parts are Pb-free. This table contains Preliminary information. Contact your local Cypress sales representative for availability of these parts.  
Document #: 001-42880 Rev. *C  
Page 25 of 29  
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CY14B101KA/CY14B101MA  
PRELIMINARY  
Package Diagrams  
Figure 17. 44-Pin TSOP II (51-85087)  
DIMENSION IN MM (INCH)  
MAX  
MIN.  
PIN 1 I.D.  
22  
1
R
O
E
K
A
X
S G  
EJECTOR PIN  
23  
44  
TOP VIEW  
BOTTOM VIEW  
10.262 (0.404)  
10.058 (0.396)  
0.400(0.016)  
0.300 (0.012)  
0.800 BSC  
(0.0315)  
BASE PLANE  
0.10 (.004)  
0.210 (0.0083)  
0.120 (0.0047)  
0°-5°  
18.517 (0.729)  
18.313 (0.721)  
0.597 (0.0235)  
0.406 (0.0160)  
SEATING  
PLANE  
51-85087-*A  
Figure 18. 54-Pin TSOP II (51-85160)  
51-85160-**  
Document #: 001-42880 Rev. *C  
Page 26 of 29  
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CY14B101KA/CY14B101MA  
PRELIMINARY  
Package Diagrams (continued)  
Figure 19. 48-Pin SSOP (51-85061)  
Document #: 001-42880 Rev. *C  
Page 27 of 29  
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CY14B101KA/CY14B101MA  
PRELIMINARY  
Document History Page  
Document Title: CY14B101KA/CY14B101MA 1 Mbit (128K x 8/64K x 16) nvSRAM with Real Time Clock  
Document Number: 001-42880  
Submission  
Date  
Orig. of  
Change  
Rev. ECN No.  
Description of Change  
**  
2050747  
See ECN  
UNC/PYRS New Data Sheet  
*A  
2607447 11/18/2008  
GVCH/AESA Removed 15 ns access speed, updated “Features”, added CY14B101MA (x16)  
part, changed title to “CY14B101KA/CY14B101MA 1 Mbit (128K x 8/64K x 16)  
nvSRAM with Real-Time-Clock”.  
Added 54-pinTSOP II package relatedinformation, updatedLogicblockdiagram,  
added footnote 1 and 2.  
Pin definition: Updated WE, HSB and NC pin description.  
Page 4: Updated SRAM READ, SRAM WRITE, Autostore operation description,  
Page 4: Updated Software store and software recall description  
Updated Figure 2, Page 4: Updated Hardware store operation and Hardware  
RECALL (Power up) description  
Footnote 1 and 10 referenced for Mode selection Table  
Added footnote 10, updated footnote 8 and 9  
Page 6: updated Data protection description  
Page 6: Updated starting and stopping the oscillator description  
Page 7: Updated Calibrating the clock description  
Page 8: Added Flags register  
Updated table 4, added footnote 12 and 13  
Updated Register map detail Table 5  
Maximum Ratings: Added Max. Accumulated storage time  
Changed Output short circuit current parameter name to DC output current  
Changed ICC2 from 6 mA to 10 mA  
Changed ICC3 from 15 mA to 35 mA  
Changed ICC4 from 6 mA to 5 mA  
Changed ISB from 3 mA to 5 mA  
Added IIX for HSB  
Updated ICC1, CC3, SB and IOZ Test conditions  
I
I
Changed VCAP voltage min value from 68uF to 61uF  
Added VCAP voltage max value to 180uF  
Updated footnote 14 and 15, added footnote 16  
Added Data retention and Endurance Table  
Added thermal resistance value to 44/54 TSOP II packages  
Updated Input Rise and Fall time in AC test Conditions  
Changed VRTCcap min value from 1.2 to 1.5V for industrial Commercial  
temperature  
Changed VRTCcap min value from 2.7 to 3.6V for industrial Commercial  
temperature  
Updated RTC recommended component configuration values  
Updated tOCS value for minimum and room temperature from 10 and 5sec to 2  
and 1sec resp.  
Referenced footnote 22 to tOHA parameter  
Updated All switching waveforms  
Updated footnote 22, added footnote 25  
Added Figure 11 (SRAM WRITE CYCLE:BHE and BLE controlled)  
Changed tSTORE max value from 15ms to 8ms  
Updated tDELAY value  
Added VHDIS, tHHHD and tLZHSB parameters  
Updated footnote 29, added footnote 31 and 32  
Software controlled STORE/RECALL Table: Changed tAS to tSA  
Changed tGHAX to tHA, changed tHA value from 1ns to 0ns  
Added Figure 14  
Added tDHSB parameter, changed tHLHX to tPHSB  
Updated tSS from 70 us to 100 us, added truth table for SRAM operations  
Updated ordering information and part numbering nomenclature  
Document #: 001-42880 Rev. *C  
Page 28 of 29  
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PRELIMINARY  
CY14B101KA/CY14B101MA  
Document Title: CY14B101KA/CY14B101MA 1 Mbit (128K x 8/64K x 16) nvSRAM with Real Time Clock  
Document Number: 001-42880  
Submission  
Date  
Orig. of  
Change  
Rev. ECN No.  
*B 2654484  
Description of Change  
02/05/09  
GVCH/PYRS Changed the data sheet from Advance information to Preliminary  
Changed X1, X2 pin names to Xout, Xin respectively  
Updated Real Time Clock operation description  
Added footnotes 11 and 12  
Added default values to RTC Register Map” table 3  
Updated flag register description in Register Map Detail” table 4  
Changed C1, C2 values to 21pF, 21pF respectively  
Changed IBAK value from 350 nA to 450 nA at hot temperature  
Changed VRTCcap typical value from 2.4V to 3.0V  
Referenced Note 15 to parameters tLZCE, tHZCE, tLZOE, HZOE, LZBE, LZWE, HZWE-  
t
t
t
t
and tHZBE  
Added footnote 24  
Updated Figure 13  
*C  
2733909  
07/09/09  
GVCH/AESA Page 3; Added note to AutoStore Operation description  
Page 4; Updated Hardware STORE (HSB) Operation description  
Page 4; Updated Software STORE Operation description  
Added best practices  
Changed C1, C2 values to 10pF, 67pF respectively  
Changed IBAK and VRTCcap parameter values  
Added RBKCHG parameter  
Updated VHDIS parameter description  
Updated tDELAY parameter description  
Updated footnote 28 and added footnote 35  
Sales, Solutions, and Legal Information  
Worldwide Sales and Design Support  
Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office  
closest to you, visit us at www.cypress.com/sales.  
Products  
PSoC  
psoc.cypress.com  
clocks.cypress.com  
wireless.cypress.com  
memory.cypress.com  
image.cypress.com  
Clocks & Buffers  
Wireless  
Memories  
Image Sensors  
© Cypress Semiconductor Corporation, 2008-2009. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of  
any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for  
medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as  
critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems  
application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
Any Source Code (software and/or firmware) is owned by Cypress Semiconductor Corporation (Cypress) and is protected by and subject to worldwide patent protection (United States and foreign),  
United States copyright laws and international treaty provisions. Cypress hereby grants to licensee a personal, non-exclusive, non-transferable license to copy, use, modify, create derivative works of,  
and compile the Cypress Source Code and derivative works for the sole purpose of creating custom software and or firmware in support of licensee product to be used only in conjunction with a Cypress  
integrated circuit as specified in the applicable agreement. Any reproduction, modification, translation, compilation, or representation of this Source Code except as specified above is prohibited without  
the express written permission of Cypress.  
Disclaimer: CYPRESS MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARD TO THIS MATERIAL, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES  
OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE. Cypress reserves the right to make changes without further notice to the materials described herein. Cypress does not  
assume any liability arising out of the application or use of any product or circuit described herein. Cypress does not authorize its products for use as critical components in life-support systems where  
a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress’ product in a life-support systems application implies that the manufacturer  
assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
Use may be limited by and subject to the applicable Cypress software license agreement.  
Document #: 001-42880 Rev. *C  
Revised July 09, 2009  
Page 29 of 29  
All products and company names mentioned in this document are the trademarks of their respective holders.  
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CY14B101KA-SP25XCT 相关器件

型号 制造商 描述 价格 文档
CY14B101KA-SP25XI CYPRESS 1 Mbit (128K x 8/64K x 16) nvSRAM with Real Time Clock 获取价格
CY14B101KA-SP25XI INFINEON nvSRAM (non-volatile SRAM) 获取价格
CY14B101KA-SP25XIT CYPRESS 1 Mbit (128K x 8/64K x 16) nvSRAM with Real Time Clock 获取价格
CY14B101KA-SP25XIT INFINEON nvSRAM (non-volatile SRAM) 获取价格
CY14B101KA-SP45XC CYPRESS 1 Mbit (128K x 8/64K x 16) nvSRAM with Real Time Clock 获取价格
CY14B101KA-SP45XCT CYPRESS 1 Mbit (128K x 8/64K x 16) nvSRAM with Real Time Clock 获取价格
CY14B101KA-SP45XI CYPRESS 1 Mbit (128K x 8/64K x 16) nvSRAM with Real Time Clock 获取价格
CY14B101KA-SP45XI INFINEON nvSRAM (non-volatile SRAM) 获取价格
CY14B101KA-SP45XIT CYPRESS 1 Mbit (128K x 8/64K x 16) nvSRAM with Real Time Clock 获取价格
CY14B101KA-SP45XIT INFINEON nvSRAM (non-volatile SRAM) 获取价格

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