MT55L512L18PB-7.5IT中文资料_数据手册_规格书

8Mb: 512K x 18, 256K x 32/36

PIPELINED ZBT SRAM

MT55L512L18P, MT55L512V18P,

MT55L256L32P, MT55L256V32P,

MT55L256L36P, MT55L256V36P

8Mb

ZBT^®SRAM

3.3V VDD, 3.3V or 2.5V I/O

FEATURES

1

100-PinTQFP

• High frequency and 100 percent bus utilization

• Fast cycle times: 6ns, 7.5ns and 10ns

• Single +3.3V 5ꢀ poꢁer supply ꢂV^DD)

• Separate +3.3V or +2.5V isolated output buffer

supply ꢂV^DDQ)

• Advanced control logic for minimum control

signal interface

• Individual BYTE WRITE controls may be tied LOW

• Single R/W# ꢂread/ꢁrite) control pin

• CKE# pin to enable clock and suspend operations

• Three chip enables for simple depth expansion

• Clock-controlled and registered addresses, data

I/Os and control signals

• Internally self-timed, fully coherent WRITE

• Internally self-timed, registered outputs to

eliminate the need to control OE#

• SNOOZE MODE for reduced-poꢁer standby

• Common data inputs and data outputs

• Linear or Interleaved Burst Modes

• Burst feature ꢂoptional)

165-PinFBGA

(Preliminary Package Data)

• Pin/function compatibility ꢁith 2Mb, 4Mb, and

18Mb ZBT SRAM

• Automatic poꢁer-doꢁn

• 100-pin TQFP package

• 165-pin FBGA package

• 119-pin BGA package

OPTIONS

MARKING*

• Timing ꢂAccess/Cycle/MHz)

3.5ns/6ns/166 MHz

4.2ns/7.5ns/133 MHz

5ns/10ns/100 MHz

2

-6

-7.5

-10

119-Pin BGA

• Configurations

3.3V I/O

512K x 18

256K x 32

256K x 36

2.5V I/O

MT55L512L18P

MT55L256L32P

MT55L256L36P

512K x 18

256K x 32

256K x 36

MT55L512V18P

MT55L256V32P

MT55L256V36P

NOTE: 1. JEDEC-standardMS-026BHA(LQFP).

2. JEDEC-standardMS-028BHA(PBGA).

• Package

100-pin TQFP

T

F

B

Part Number Example:

165-pin, 13mm x 15mm FBGA

119-pin, 14mm x 22mm BGA

MT55L256L32PT-7.5

• Operating Temperature Range

Commercial ꢂ0ºC to +70ºC)

Industrial ꢂ-40°C to +85°C)**

* A Part Marking Guide for the FBGA devices can be found on Micron’s

ꢁebsite—http://ꢁꢁꢁ.micron.com/support/index.html.

** Industrial temperature range offered in specific speed grades and

confgurations. Contact factory for more information.

None

IT

8Mb: 512K x 18, 256K x 32/36 Pipelined ZBT SRAM

MT55L512L18P_2.p65 – Rev. 6/01

MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.

1

8Mb: 512K x 18, 256K x 32/36

PIPELINED ZBT SRAM

FUNCTIONAL BLOCK DIAGRAM

512K x 18

17

19

ADDRESS

SA0, SA1, SA

REGISTER 0

SA1

SA0

SA1'

SA0'

D1

D0

Q1

Q0

BURST

LOGIC

MODE

K

ADV/LD#

K

CLK

CKE#

19

WRITE ADDRESS

REGISTER 1

WRITE ADDRESS

REGISTER 2

19

O

U

T

O

U

T

P

S

E

N

S

P

D

A

T

U

T

U

T

ADV/LD#

BWa#

512K x 9 x 2

WRITE REGISTRY

AND DATA COHERENCY

CONTROL LOGIC

A

R

E

G

I

E

B

U

F

18

DQs

WRITE

DRIVERS

S

T

E

R

I

A

M

P

MEMORY

ARRAY

F

S

T

E

R

S

E

R

S

BWb#

R/W#

S

N

G

E

18

INPUT

REGISTER 1

INPUT

REGISTER 0

18

E

OE#

CE#

READ LOGIC

CE2

CE2#

FUNCTIONAL BLOCK DIAGRAM

256K x 32/36

16

18

ADDRESS

REGISTER 0

SA0, SA1, SA

SA1

SA0

SA1'

SA0'

D1

D0

Q1

Q0

BURST

LOGIC

MODE

K

ADV/LD#

K

CLK

18

CKE#

WRITE ADDRESS

REGISTER 1

WRITE ADDRESS

REGISTER 2

18

O

U

T

O

U

T

P

S

E

N

S

P

D

A

T

U

T

ADV/LD#

BWa#

BWb#

BWc#

U

T

256K x 8 x 4

(x32)

WRITE REGISTRY

AND DATA COHERENCY

CONTROL LOGIC

A

R

E

G

I

DQs

E

B

U

F

36

256K x 9 x 4

(x36)

WRITE

DRIVERS

S

DQPa

DQPb

DQPc

DQPd

A

M

P

T

E

R

I

F

S

T

E

R

S

MEMORY

ARRAY

E

R

S

BWd#

R/W#

N

G

E

INPUT

REGISTER 1

36

INPUT

E

REGISTER 0

E

OE#

CE#

READ LOGIC

CE2

CE2#

NOTE: Functional block diagrams illustrate simplified device operation. See truth table, pin descriptions, and timing diagrams

for detailed information.

8Mb: 512K x 18, 256K x 32/36 Pipelined ZBT SRAM

MT55L512L18P_2.p65 – Rev. 6/01

MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.

2

8Mb: 512K x 18, 256K x 32/36

PIPELINED ZBT SRAM

GENERALDESCRIPTION

The Micron^®Zero Bus Turnaround^™ꢂZBT^®) SRAM

family employs high-speed, loꢁ-poꢁer CMOS designs

using an advanced CMOS process.

addresses can be internally generated as controlled by

the burst advance pin ꢂADV/LD#). Use of burst mode

is optional. It is alloꢁable to give an address for each

individual READ and WRITE cycle. BURST cycles ꢁrap

around after the fourth access from a base address.

To alloꢁ for continuous, 100 percent use of the data

bus, the pipelined ZBT SRAM uses a LATE LATE WRITE

cycle.Forexample,ifaWRITEcyclebeginsinclockcycle

one, the address is present on rising edge one. BYTE

WRITEs need to be asserted on the same cycle as the

address. Thedataassociatedꢁiththeaddressisrequired

tꢁocycleslater,orontherisingedgeofclockcyclethree.

Address and ꢁrite control are registered on-chip to

simplify WRITE cycles. This alloꢁs self-timed WRITE

cycles. Individualbyteenablesalloꢁindividualbytesto

be ꢁritten. During a BYTE WRITE cycle, BWa# controls

DQa pins; BWb# controls DQb pins; BWc# controls

DQc pins; and BWd# controls DQd pins. Cycle types

can only be defined ꢁhen an address is loaded, i.e.,

ꢁhen ADV/LD# is LOW. Parity/ECC bits are only

available on the x36 version.

Micron’s 8Mb ZBT SRAMs integrate a 512K x 18,

256K x 32, or 256K x 36 SRAM core ꢁith advanced

synchronous peripheral circuitry and a 2-bit burst

counter. These SRAMs are optimized for 100 percent

bus utilization, eliminating any turnaround cycles for

READ to WRITE, or WRITE to READ, transitions. All

synchronous inputs pass through registers controlled

by a positive-edge-triggered single clock input ꢂCLK).

The synchronous inputs include all addresses, all data

inputs, chip enable ꢂCE#), tꢁo additional chip enables

for easy depth expansion ꢂCE2, CE2#), cycle start input

ꢂADV/LD#), synchronous clock enable ꢂCKE#), byte

ꢁrite enables ꢂBWa#, BWb#, BWc#, and BWd#), and

read/ꢁrite ꢂR/W#).

Asynchronous inputs include the output enable

ꢂOE#, ꢁhich may be tied LOW for control signal mini-

mization), clock ꢂCLK), and snooze enable ꢂZZ, ꢁhich

may be tied LOW if unused). There is also a burst mode

pin ꢂMODE) that selects betꢁeen interleaved and linear

burst modes. MODE may be tied HIGH, LOW, or left

unconnected if burst is unused. The data-out ꢂQ),

enabled by OE#, is registered by the rising edge of CLK.

WRITE cycles can be from one to four bytes ꢁide as

controlled by the ꢁrite control inputs.

Micron’s 8Mb ZBT SRAMs operate from a +3.3V V^DD

poꢁer supply, and all inputs and outputs are LVTTL-

compatible. Users can choose either a 2.5V or 3.3V I/O

version. The device is ideally suited for systems requir-

ing high bandꢁidth and zero bus turnaround delays.

PleaserefertoMicron’sWebsiteꢂꢁꢁꢁ.micron.com/

datasheets) for the latest data sheet.

All READ, WRITE, and DESELECT cycles are initi-

ated by the ADV/LD# input. Subsequent burst

8Mb: 512K x 18, 256K x 32/36 Pipelined ZBT SRAM

MT55L512L18P_2.p65 – Rev. 6/01

MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.

3

8Mb: 512K x 18, 256K x 32/36

PIPELINED ZBT SRAM

TQFP PIN ASSIGNMENT TABLE

PIN #

1

2

3

4

5

6

7

8

x18

NC

x32

NF

DQc

VDDQ

VSS

x36

DQPc

DQc

PIN #

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

x18

x32

VSS

VDDQ

DQd DQd

NF

x36

PIN #

51

52

53

54

55

56

57

58

59

60

61

62

63

64

65

66

67

x18

NC

x32

NF

DQa DQa

VDDQ

x36

DQPa

PIN #

76

77

78

79

80

81

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

100

x18

x32

VSS

VDDQ

DQb DQb

x36

NC

SA

DQPd

VSS

NF

SA

DQPb

NC

DQc DQc

MODE(LBO#)

SA

NC

DQa DQa

DQa

VSS

VDDQ

DQa

ZZ

DQb DQc DQc

SA

2

9

10

11

NF

ADV/LD#

OE# (G#)

CKE#

R/W#

CLK

VSS

VDDQ

SA1

SA0

DNU

VSS

VDD

DNU

SA

12 DQb DQc DQc

13 DQb DQc DQc

14

15

16

17

18 DQb DQd DQd

19 DQb DQd DQd

20

21

VDD

VSS

VDD

CE2#

BWa#

BWb#

1

VDD

VSS

VDD

VSS

68 DQa DQb DQb

69 DQa DQb DQb

70

71

72 DQa DQb DQb

73 DQa DQb DQb

74 DQa DQb DQb

VDDQ

VSS

VDDQ

VSS

NC BWc# BWc#

NC BWd# BWd#

22 DQb DQd DQd

23 DQb DQd DQd

24 DQb DQd DQd

CE2

CE#

SA

25

NC

DQd DQd

75

NC

DQb DQb

SA

NOTE: 1. Pins 16 and 66 do not have to be connected directly to V^DDif the input voltage is ≥ VIH.

2. Pin 84 is reserved for expansion to 18Mb device.

8Mb: 512K x 18, 256K x 32/36 Pipelined ZBT SRAM

MT55L512L18P_2.p65 – Rev. 6/01

MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.

4

8Mb: 512K x 18, 256K x 32/36

PIPELINED ZBT SRAM

PIN ASSIGNMENT (TOP VIEW)

100-PIN TQFP

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

SA

81

50

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

SA

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

SA

2

NF

SA

ADV/LD#

OE# (G#)

CKE#

SA

R/W#

DNU

CLK

V

SS

DD

V

DD

SS

V

x18

CE2#

BWa#

BWb#

NC

DNU

SA0

SA1

SA

NC

CE2

CE#

SA

100

MODE

(LBO#)

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51

81 50

SA

82

83

84

85

86

87

88

89

90

91

92

93

94

95

96

97

98

99

49

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

SA

2

NF

SA

ADV/LD#

OE# (G#)

CKE#

SA

R/W#

DNU

CLK

V

SS

DD

V

DD

SS

V

x32/x36

CE2#

BWa#

BWb#

BWc#

BWd#

CE2

DNU

SA0

SA1

SA

CE#

SA

100

MODE

(LBO#)

1

2

3

4

5

6

7

8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30

NOTE: 1. Pins 16 and 66 do not have to be connected directly to VDD if the input voltage is ≥ VIH.

2. Pin 84 is reserved for expansion to 18Mb device.

3. NF for x32 version, DQPx for x36 version.

8Mb: 512K x 18, 256K x 32/36 Pipelined ZBT SRAM

MT55L512L18P_2.p65 – Rev. 6/01

MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.

5

8Mb: 512K x 18, 256K x 32/36

PIPELINED ZBT SRAM

TQFP PIN DESCRIPTIONS

x18

x32/x36

SYMBOL TYPE

DESCRIPTION

37

36

37

36

SA0

SA1

SA

Input Synchronous Address Inputs: These inputs are registered

and must meet the setup and hold times around the rising

edge of CLK. Pin 84 is reserved as an address bit for

32-35, 44-50,

80-83, 99, 100

32-35, 44-50,

81-83, 99, 100

higher-density 18Mb ZBT SRAMs. SA0 and SA1 are the

two least significant bits (LSB) of the address field and

set the internal burst counter if burst is desired.

93

94

–

93

94

95

96

BWa#

BWb#

BWc#

BWd#

Input Synchronous Byte Write Enables: These active LOW inputs

allow individual bytes to be written when a WRITE cycle is

active and must meet the setup and hold times around the

rising edge of CLK. BYTE WRITEs need to be asserted on

the same cycle as the address. BWs are associated with

addresses and apply to subsequent data. BWa# controls

DQa pins; BWb# controls DQb pins; BWc# controls DQc

pins; BWd# controls DQd pins.

–

89

CLK

Input Clock: This signal registers the address, data, chip enables,

byte write enables, and burst control inputs on its rising

edge. All synchronous inputs must meet setup and hold

times around the clock’s rising edge.

98

92

98

92

CE#

Input Synchronous Chip Enable: This active LOW input is used to

enable the device and is sampled only when a new

external address is loaded (ADV/LD# is LOW).

CE2#

Input Synchronous Chip Enable: This active LOW input is used to

enable the device and is sampled only when a new

external address is loaded (ADV/LD# is LOW). This

input can be used for memory depth expansion.

97

CE2

Input Synchronous Chip Enable: This active HIGH input is used to

enable the device and is sampled only when a new

external address is loaded (ADV/LD# is LOW). This

input can be used for memory depth expansion.

86

85

86

85

OE#

(G#)

Input Output Enable: This active LOW, asynchronous input

enables the data I/O output drivers. G# is the JEDEC-

standard term for OE#.

ADV/LD# Input Synchronous Address Advance/Load: When HIGH, this

input is used to advance the internal burst counter,

controlling burst access after the external address is

loaded. When ADV/LD# is HIGH, R/W# is ignored. A LOW

on ADV/LD# clocks a new address at the CLK rising edge.

87

64

87

64

CKE#

ZZ

Input Synchronous Clock Enable: This active LOW input permits

CLK to propagate throughout the device. When CKE# is

HIGH, the device ignores the CLK input and effectively

internally extends the previous CLK cycle. This input must

meet setup and hold times around the rising edge of CLK.

Input Snooze Enable: This active HIGH, asynchronous input

causes the device to enter a low-power standby mode in

which all data in the memory array is retained. When ZZ is

active, all other inputs are ignored.

(continued on next page)

8Mb: 512K x 18, 256K x 32/36 Pipelined ZBT SRAM

MT55L512L18P_2.p65 – Rev. 6/01

MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.

6

8Mb: 512K x 18, 256K x 32/36

PIPELINED ZBT SRAM

TQFP PIN DESCRIPTIONS (CONTINUED)

x18

x32/x36

SYMBOL TYPE

R/W#

DESCRIPTION

88

Input Read/Write: This input determines the cycle type when

ADV/LD# is LOW and is the only means for determining

READs and WRITEs. READ cycles may not be converted into

WRITEs (and vice versa) other than by loading a new

address. A LOW on this pin permits BYTE WRITE operations

and must meet the setup and hold times around the rising

edge of CLK. Full bus-width WRITEs occur if all byte write

enables are LOW.

31

MODE Input Mode: This input selects the burst sequence. A LOW on

(LBO#)

this pin selects linear burst. NC or HIGH on this pin selects

interleaved burst. Do not alter input state while device is

operating. LBO# is the JEDEC-standard term for MODE.

(a) 58, 59, 62, 63,

68, 69, 72-74

(b) 8, 9, 12, 13,

18, 19, 22-24

(a) 52, 53, 56-59,

62, 63

(b) 68, 69, 72-75,

78, 79

(c) 2, 3, 6-9,

12, 13

(d) 18, 19, 22-25,

28, 29

DQa

DQb

DQc

DQd

Input/ SRAM Data I/Os: Byte “a” is associated with DQa pins;

Output Byte “b” is associated with DQb pins; Byte “c” is

associated with DQc pins; Byte “d” is associated with

DQd pins. Input data must meet setup and hold times

around the rising edge of CLK.

n/a

51

80

1

NF/DQPa NF/

NF/DQPb I/O

NF/DQPc

No Function/Data Bits: On the x32 version, these pins are

No Function (NF) and can be left floating or connected to

GND to minimize thermal impedance. On the x36 version,

these bits are DQPs.

30

NF/DQPd

14, 15, 16, 41, 65, 14, 15, 16, 41, 65,

VDD

Supply Power Supply: See DC Electrical Characteristics and

Operating Conditions for range.

66, 91

4, 11, 20, 27,

54, 61, 70, 77

4, 11, 20, 27,

54, 61, 70, 77

V

DDQ

Supply Isolated Output Buffer Supply: See DC Electrical

Characteristics and Operating Conditions for range.

5, 10, 17, 21,

26, 40, 55, 60,

67, 71, 76, 90

5, 10, 17, 21,

26, 40, 55, 60,

67, 71, 76, 90

VSS

Supply Ground: GND.

1-3, 6, 7, 25,

28-30, 51-53, 56,

57, 75, 78, 79,

95, 96

n/a

NC

–

No Connect: These pins can be left floating or connected

to GND to minimize thermal impedance.

38, 39, 42, 43

84

DNU

NF

–

Do Not Use: These signals may either be unconnected or

wired to GND to minimize thermal impedance.

84

No Function: This pin is internally connected to the die and

will have the capacitance of an input pin. It is allowable to

leave this pin unconnected or driven by signals. Pin 84 is

reserved as an address pin for the 18Mb ZBT SRAM.

8Mb: 512K x 18, 256K x 32/36 Pipelined ZBT SRAM

MT55L512L18P_2.p65 – Rev. 6/01

MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.

7

8Mb: 512K x 18, 256K x 32/36

PIPELINED ZBT SRAM

PIN LAYOUT (TOP VIEW)

165-PIN FBGA

X18

X32/X36

1

2

3

4

5

6

7

8

9

10

11

1

2

3

4

5

6

7

8

9

10

11

A

B

C

D

E

A

B

C

D

E

A

B

C

D

E

A

B

C

D

E

NC

SA

CE# BWb#

NC

CE2# CKE# ADV/L D# SA

SA

NC

SA

CE# BWc# BWb# CE2# CKE# ADV/LD# SA

CE2 BWd# BWa# CLK R/W# OE# (G#) NC

SA

NC

CE2

NC

BWa# CLK R/W# OE# (G#) NC

NC

V

DD

Q

V

SS

VSS

V

SS

V

SS

V

SS

V

DD

Q

NC NF/DQPa

NF/DQPc NC

V

DD

Q

V

SS

V

SS

V

SS

V

SS

V

SS

V

DD

Q

NC NF/DQPb

DQb DQb

DQb

V

Q

VDD

NC

DQa

ZZ

DQc

V

DD

V

DD

F

NC

G

H

J

G

H

J

G

H

J

G

H

J

NC

V

DD

DQb

VDD

NC

V

DD

VDD

NC

ZZ

NC

V

DD

Q

V

DD

Q

DQa

NC

DQd DQd

NF/DQPd NC

V

DD

Q

V

DD

Q

DQa

K

L

K

L

K

L

K

L

V

Q

V

Q

NC

V

Q

V

Q

NC

M

N

P

M

N

P

M

N

P

M

N

P

NC

NF/DQPb NC

VSS

NC

SA1

SA0

VDD

VSS

NC

V

SS

NC

SA1

SA0

V

DD

V

SS

NC NF/DQPa

NC

SA

DNU

SA

NC

SA

DNU

SA

NC

SA

R

MODE NC

(LBO#)

SA

MODE NC

(LBO#)

TOP VIEW

*No Function (NF) is used on the x32 version. Parity (DQPx) is used on the x36 version.

NOTE: Pin 9B reserved for address pin expansion; 18Mb.

8Mb: 512K x 18, 256K x 32/36 Pipelined ZBT SRAM

MT55L512L18P_2.p65 – Rev. 6/01

MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.

8

8Mb: 512K x 18, 256K x 32/36

PIPELINED ZBT SRAM

FBGA PIN DESCRIPTIONS

x18

x32/x36

SYMBOL TYPE

DESCRIPTION

6R

6P

6R

6P

SA0

SA1

SA

Input Synchronous Address Inputs: These inputs are registered and

must meet the setup and hold times around the rising edge of

CLK.

2A, 9A, 10A, 2A, 9A, 10A,

11A, 2B, 10B,

3P, 4P, 8P,

2B, 10B,

3P, 4P, 8P,

9P, 10P, 3R, 9P, 10P, 3R,

4R, 8R, 9R,

10R, 11R

4R, 8R, 9R,

10R, 11R

5B

4A

–

5B

5A

4A

4B

BWa#

BWb#

BWc#

BWd#

Input Synchronous Byte Write Enables: These active LOW inputs allow

individual bytes to be written and must meet the setup and hold

times around the rising edge of CLK. A byte write enable is LOW

for a WRITE cycle and HIGH for a READ cycle. For the x18 version,

BWa# controls DQa’s and DQPa; BWb# controls DQb’s and DQPb.

For the x32 and x36 versions, BWa# controls DQa’s and DQPa;

BWb# controls DQb’s and DQPb; BWc# controls DQc’s and DQPc;

BWd# controls DQd’s and DQPd. Parity is only available on the

x18 and x36 versions.

–

7A

7B

7A

7B

CKE#

R/W#

Input Synchronous Clock Enable: This active LOW input permits CLK to

propogate throughout the device. When CKE# is HIGH, the

device ignores the CLK input and effectively internally extends

the previous CLK cycle. This input must meet the setup and hold

times around the rising edge of CLK.

Input Read/Write: This input determines the cycle type when ADV/LD#

is LOW and is the only means for determining READs and

WRITEs. READ cycles may not be converted into WRITEs (and vice

versa) other than by loading a new address. A LOW on this pin

permits BYTE WRITE operations to meet the setup and hold times

around the rising edge of CLK. Full bus-width WRITEs occur if all

byte write enables are LOW.

6B

CLK

Input Clock: This signal registers the address, data, chip enable, byte

write enables and burst control inputs on its rising edge. All

synchronous inputs must meet setup and hold times around the

clock’s rising edge.

3A

6A

3A

6A

CE#

CE2#

ZZ

Input Synchronous Chip Enable: This active LOW input is used to enable

the device. CE# is sampled only when a new external address is

loaded.

Input Synchronous Chip Enable: This active LOW input is used to enable

the device and is sampled only when a new external address is

loaded.

11H

Input Snooze Enable: This active HIGH, asynchronous input causes the

device to enter a low-power standby mode in which all data in

the memory array is retained. When ZZ is active, all other inputs

are ignored.

3B

CE2

Input Synchronous Chip Enable: This active HIGH input is used to

enable the device and is sampled only when a new external

address is loaded.

(continued on next page)

8Mb: 512K x 18, 256K x 32/36 Pipelined ZBT SRAM

MT55L512L18P_2.p65 – Rev. 6/01

MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.

9

8Mb: 512K x 18, 256K x 32/36

PIPELINED ZBT SRAM

FBGA PIN DESCRIPTIONS (CONTINUED)

x18

x32/x36

SYMBOL TYPE

DESCRIPTION

8B

OE#

(G#)

Input Output Enable: This active LOW, asynchronous input enables the

data I/O output drivers.

8A

1R

8A

1R

ADV/LD# Input Synchronous Address Advance/Load: When HIGH, this input is used

to advance the internal burst counter, controlling burst access after

the external address is loaded. When ADV/LD# is HIGH, R/W# is

ignored. A LOW on ADV/LD# clocks a new address at the CLK rising

edge.

MODE

(LBO#)

Input Mode: This input selects the burst sequence. A LOW on this input

selects “linear burst.” NC or HIGH on this input selects “interleaved

burst.” Do not alter input state while device is operating.

(a) 10J, 10K, (a) 10J, 10K,

10L, 10M, 11D 10L, 10M, 11J,

11E, 11F, 11G 11K, 11L, 11M

(b) 2D, 2E, 2F, (b) 10D, 10E,

2G, 1J, 1K, 10F, 10G, 11D,

DQa

DQb

DQc

DQd

Input/ SRAM Data I/Os: For the x18 version, Byte “a” is associated with

Output DQa’s; Byte “b” is associated with DQb’s. For the x32 and x36

versions, Byte “a” is associated with DQa’s; Byte “b” is associated

with DQb’s; Byte “c” is associated with DQc’s; Byte “d” is associated

with DQd’s. Input data must meet setup and hold times around the

rising edge of CLK.

1L, 1M

11E, 11F, 11G

(c) 1D, 1E, 1F,

1G, 2D, 2E,

2F, 2G,

(d) 1J, 1K, 1L,

1M, 2J, 2K,

2L, 2M

11C

1N

–

11N

11C

1C

NF/DQPa

NF/DQPb

NF/DQPc

NF/DQPd

NF/

I/O

No Function/Parity Data I/Os: On the x32 version, these are No

Function(NF). On the x18 version, Byte “a” parity is DQPa; Byte “b”

parity is DQPb. On the x36 version, Byte “a” parity is DQPa; Byte

“b” parity is DQPb; Byte “c” parity is DQPc; Byte “d” parity is DQPd.

–

1N

1H, 2H, 4D,

VDD

Supply Power Supply: See DC Electrical Characteristics and Operating

Conditions for range.

4E, 4F, 4G, 4H, 4E, 4F, 4G, 4H,

4J, 4K, 4L, 4M, 4J, 4K, 4L, 4M,

7N, 8D, 8E, 8F, 7N, 8D, 8E, 8F,

8G,8H, 8J,

8K, 8L, 8M

8G,8H, 8J,

8K, 8L, 8M

3C, 3D, 3E, 3F, 3C, 3D, 3E, 3F,

3G, 3J, 3K, 3L, 3G, 3J, 3K, 3L,

V

DDQ

Supply Isolated Output Buffer Supply: See DC Electrical Characteristics and

Operating Conditions for range.

3M, 3N, 9C,

9D, 9E, 9F,

9G, 9J, 9K,

9L, 9M, 9N

3M, 3N, 9C,

9D, 9E, 9F,

9G, 9J, 9K,

9L, 9M, 9N

(continued on next page)

8Mb: 512K x 18, 256K x 32/36 Pipelined ZBT SRAM

MT55L512L18P_2.p65 – Rev. 6/01

MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.

10

8Mb: 512K x 18, 256K x 32/36

PIPELINED ZBT SRAM

FBGA PIN DESCRIPTIONS (CONTINUED)

x18

x32/x36

SYMBOL TYPE

Supply Ground: GND.

DESCRIPTION

4C, 4N, 5C,

VSS

5D, 5E, 5F, 5G, 5D, 5E, 5F, 5G,

5H, 5J, 5K, 5L, 5H, 5J, 5K, 5L,

5M, 6C, 6D,

6E, 6F, 6G, 6H, 6E, 6F, 6G, 6H,

6J, 6K, 6L, 6M, 6J, 6K, 6L, 6M,

7C, 7D, 7E, 7F, 7C, 7D, 7E, 7F,

7G, 7H, 7J, 7K, 7G, 7H, 7J, 7K,

7L, 7M, 8C, 8N 7L, 7M, 8C, 8N

5P, 7P, 5R, 7R 5P, 7P, 5R, 7R

DNU

NC

–

Do Not Use: These signals may either be unconnected or wired to

GND to improve package heat dissipation.

1A, 1B, 1C, 1D, 1A, 1B, 1P,

No Connect: These signals are not internally connected and may be

connected to ground to improve package heat dissipation.

Pin 9B is reserved for address pin expansion; 16MB.

1E, 1F, 1G,

2C, 2N, 2P,

1P, 2C, 2J, 2K, 2R, 3H, 5N,

2L, 2M, 2N, 6N, 9B, 9H,

2P, 2R, 3H, 4B, 10C, 10H, 10N,

5A, 5N, 6N, 11A, 11B, 11P

9B, 9H, 10C,

10D, 10E, 10F,

10G, 10H, 10N,

11B, 11J, 11K,

11L, 11M,

11N, 11P

NF

—

No Function: These pins are internally connected to the die and

have the capacitance of an input pin. It is allowable to leave

these pins unconnected or driven by signals.

8Mb: 512K x 18, 256K x 32/36 Pipelined ZBT SRAM

MT55L512L18P_2.p65 – Rev. 6/01

MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.

11

8Mb: 512K x 18, 256K x 32/36

PIPELINED ZBT SRAM

PINLAYOUT(TOPVIEW)

119-PINBGA

x18

x32/x36

1

2

3

4

5

6

7

1

2

3

4

5

6

7

A

B

C

D

E

A

B

C

D

E

1

V

DD

Q

SA

CE2

SA

NF

SA

CE2#

SA

V

DDQ

V

DD

Q

SA

CE2

SA

NF

SA

CE2#

SA

V

DDQ

NC

SA ADV/LD# SA

NC

SA ADV/LD# SA

NC

SA

V

DD

SA

V

DD

SA

2

DQb

NC

V

SS

NC

VSS

DQPa

NC

DQc NC/DQPc

V

SS

NC

V

SS NC/DQPb DQb

DQb

NC

CE#

DQa

DQc

CE#

SS

DQb DQb

F

V

DD

Q

SS OE# (G#)

DQa

NC

V

DD

DQa

NC

Q

V

DD

Q

SS OE# (G#)

DQb

VDDQ

G

H

J

G

H

J

NC

DQb BWb#

SA

DQc

DQc BWc#

SA

BWb# DQb DQb

DQb

NC

V

SS

R/W#

DQa

DQc

V

SS

R/W#

VSS

DQb DQb

3

V

DD

Q

V

DD

DQb

NC

V

DD

V

DD

V

DD

V

DD

V

DD

DQa

NC

Q

V

DD

Q

V

DD

V

DD

V

DD

V

DD

V

DD

VDDQ

K

L

K

L

NC

V

SS

CLK

NC

V

SS

NC

DQd DQd

V

SS

CLK

NC

V

SS

DQa

DQb

V

BWa# DQa

DQd DQd BWd#

BWa# DQa

M

N

P

M

N

P

V

DD

DQb

NC

Q

DQb

NC

V

CKE#

SA1

SA0

V

SS

NC

DQa

NC

VDD

Q

V

DD

Q

DQd

V

SS

CKE#

SA1

SA0

V

SS

DQa

V

DDQ

NC

DQd DQd

SS

DQa

2

DQPb

DQa

NC

DQd NC/DQPd

SS NC/DQPa DQa

R

T

R

T

NC

SA MODE (LBO#)

VDD

V

DD³

SA

NC

SA MODE (LBO#)

V

DD

V

DD³

SA

NC

ZZ

NC

SA

NC

SA

ZZ

NC

SA

U

V

DD

Q

DNU DNU DNU DNU

NC

VDDQ

V

DD

Q

DNU DNU DNU DNU

VDDQ

TOP VIEW

NOTE: 1. Pin 4A is reserved for address expansion to 18Mb.

2. No Function (NF) is used on the x32 version. Parity (DQPx) is used on the x36 version.

3. Pin 3J, 5J, and 5R do not have to be connected directly to VDD if the input voltage is ≥ VIH.

8Mb: 512K x 18, 256K x 32/36 Pipelined ZBT SRAM

MT55L512L18P_2.p65 – Rev. 6/01

MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.

12

8Mb: 512K x 18, 256K x 32/36

PIPELINED ZBT SRAM

BGAPINDESCRIPTIONS

x18

x32/x36

SYMBOL TYPE

DESCRIPTION

4P

4N

4P

4N

SA0

SA1

S A

Input Synchronous Address Inputs: These inputs are registered and

must meet the setup and hold times around the rising edge

of CLK.

2A, 3A, 5A,

6A, 3B, 5B,

2C, 3C, 5C,

6C, 2R, 6R,

2T, 3T, 5T, 6T

2A, 2C, 2R,

3A, 3B, 3C,

3T, 4T, 5A,

5B, 5C, 5T,

6A, 6C, 6R

5L

3G

–

5L

5G

3G

3L

BWa#

BWb#

BWc#

BWd#

Input Synchronous Byte Write Enables: These active LOW inputs allow

individual bytes to be written and must meet the setup and hold

times around the rising edge of CLK. A byte write enable is LOW

for a WRITE cycle and HIGH for a READ cycle. For the x18 version,

BWa# controls DQa’s and DQPa; BWb# controls DQb’s and DQPb.

For the x32 and x36 versions, BWa# controls DQa’s and DQPa;

BWb# controls DQb’s and DQPb; BWc# controls DQc’s and DQPc;

BWd# controls DQd’s and DQPd. Parity is only available on the x18

and x36 versions.

–

4M

4H

4M

4H

CKE#

R/W#

Input Synchronous Clock Enable: This active LOW input permits CLK to

propagate throughout the device. When CKE# is HIGH, the

device ignores the CK input and effectively internally extends

the previous CLK cycle. This input must meet the setup and

hold times around the rising edge of CLK.

Input Read/Write: This input determines the cycle type when ADV/

LD# is lOW and is the only means for determining READs and

WRITEs. READ cycles may not be converted into WRITEs (and

vice versa) other than by loading a new address. A LOW on this

pin permits BYTE WRITE operations must meet the setup and

hold times around the rising edge of CLK. Full bus-width

WRITEs occur if all byte write enables are LOW.

4K

CLK

Input Clock: This signal registers the address, data, chip enable, byte write

enables and burst control inputs on its rising edge. All synchronous

inputs must meet setup and hold times around the clock’s rising

edge.

4E

6B

7T

4E

6B

7T

CE#

CE2#

ZZ

Input Synchronous Chip Enable: This active LOW input is used to enable

the device. CE# is sampled only when a new external address is

loaded.

Input Synchronous Chip Enable: This active LOW input is used to enable

the device and is sampled only when a new external address is

loaded.

Input Snooze Enable: This active HIGH, asynchronous input causes the

device to enter a low-power standby mode in which all data in the

memory array is retained. When ZZ is active, all other inputs are

ignored.

2B

CE2

Input Synchronous Chip Enable: This active HIGH input is used to enable

the device and is sampled only when a new external address is

loaded.

(continued on next page)

8Mb: 512K x 18, 256K x 32/36 Pipelined ZBT SRAM

MT55L512L18P_2.p65 – Rev. 6/01

MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.

13

8Mb: 512K x 18, 256K x 32/36

PIPELINED ZBT SRAM

BGA PIN DESCRIPTIONS (continued)

x18

x32/x36

SYMBOL TYPE

OE#

DESCRIPTION

4F

Input Output Enable: This active LOW, asynchronous input enables the

data I/O output drivers.

4B

ADV#/LD# Input Synchronous Address Advance/Load: When HIGH, this input is

used to advance the internal burst counter, controlling burst

access after the external addressis loaded. When ADV#/LD# is

HIGH, R/W# is ignored. A LOW on ADV#/LD# clocks a new

address at the CLK rising edge.

3R

4A

3R

4A

MODE

Input Mode: This input selects the burst sequence. A LOW on this

input selects “linear burst.” NC or HIGH on this input selects

“interleaved burst.” Do not alter input state while device is

operating.

N F

Input No Function: These pins are internally connected to the die and

will have the capacitance of input pins. It is allowable to leave

these pins unconnected or driven by signals. These pins are

reserved for address expansion; 4A becomes an SA at 16Mb

density.

(a) 6F, 6H, 6L, (a) 6K, 6L,

DQa

DQb

DQc

DQd

Input/ SRAM Data I/Os: For the x18 version, Byte “a” is DQa’s; Byte “b”

Output is DQb’s. For the x32 and x36 versions, Byte “a” is DQa’s;

Byte “b” is DQb’s; Byte “c” is DQc’s; Byte “d” is DQd’s. Input

data must meet setup and hold times around the rising edge of

CLK.

6N, 7E, 7G,

7K, 7P

6M, 6N, 7K,

7L, 7N, 7P

(b) 6E, 6F,

6G, 6H, 7D,

7E, 7G, 7H

(c) 1D, 1E,

1G, 1H, 2E,

2F, 2G, 2H

(d) 1K, 1L,

1N, 1P, 2K,

2L, 2M, 2N

(b) 1D, 1H,

1L, 1N, 2E,

2G, 2K, 2M

6D

2P

–

6P

6D

2D

2P

NF/DQPa

NF/DQPb

NF/DQPc

NF/DQPd

NF/

I/O

No Function/Parity Data I/Os: On the x32 version, these are No

Function (NF). On the x18 version, Byte “a” parity is DQPa; Byte

“b” parity is DQPb. On the x36 version, Byte “a” parity is DQPa;

Byte “b” parity is DQPb; Byte “c” parity is DQPc; Byte “d” parity

is DQPd.

–

2J, 4C, 4J,

4R, 5R, 6J

2J, 4C, 4J,

4R, 5R, 6J

V

DD

Supply Power Supply: See DC Electrical Characteristics and Operating

Conditions for range.

1A, 1F, 1J,

1M, 1U, 7A, 1M, 1U, 7A,

1A, 1F, 1J,

V

DD

Q

Supply Isolated Output Buffer Supply: See DC Electrical Characteristics

and Operating Conditions for range.

7F, 7J, 7M,

7U

7F, 7J, 7M,

7U

(continued on next page)

8Mb: 512K x 18, 256K x 32/36 Pipelined ZBT SRAM

MT55L512L18P_2.p65 – Rev. 6/01

MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.

14

8Mb: 512K x 18, 256K x 32/36

PIPELINED ZBT SRAM

BGA PIN DESCRIPTIONS (continued)

x18

x32/x36

SYMBOL TYPE

Supply Ground: GND.

DESCRIPTION

3D, 3E, 3F,

3H, 3K, 3L,

3M, 3N, 3P,

5D, 5E, 5F,

3D, 3E, 3F,

3H, 3K, 3M,

3N, 3P, 5D,

5E, 5F, 5H,

V

SS

5G, 5H, 5K, 5K, 5M, 5N,

5M, 5N, 5P 5P

2U, 3U, 4U, 2U, 3U, 4U,

DNU

NC

–

Do Not Use: These signals may either be unconnected or wired

to GND to improve package heat dissipation.

5U

1B, 1C, 1E,

1G, 1K, 1P,

1R, 1T, 2D,

2F, 2H, 2L,

2N, 3J, 4D,

4L, 4T, 5J,

6E, 6G, 6K,

6M, 6P, 6U,

7B, 7C, 7D,

7H, 7L, 7N,

7R

1B, 1C, 1R,

1T, 2T, 3J,

4D, 4L, 5J,

6T, 6U, 7B,

7C, 7R

No Connect: These signals are not internally connected and

may be connected to ground to improve package heat

dissipation.

NF

—

No Function: These pins are internally connected to the die and

have the capacitance of an input pin. It is allowable to leave

these pins unconnected or driven by signals.

8Mb: 512K x 18, 256K x 32/36 Pipelined ZBT SRAM

MT55L512L18P_2.p65 – Rev. 6/01

MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.

15

8Mb: 512K x 18, 256K x 32/36

PIPELINED ZBT SRAM

INTERLEAVED BURST ADDRESS TABLE (MODE = NC OR HIGH)

FIRST ADDRESS (EXTERNAL)

SECOND ADDRESS (INTERNAL)

THIRD ADDRESS (INTERNAL)

FOURTH ADDRESS (INTERNAL)

X...X00

X...X01

X...X10

X...X11

X...X01

X...X00

X...X11

X...X10

X...X11

X...X00

X...X01

X...X11

X...X10

X...X01

X...X00

LINEAR BURST ADDRESS TABLE (MODE = LOW)

FIRST ADDRESS (EXTERNAL)

SECOND ADDRESS (INTERNAL)

THIRD ADDRESS (INTERNAL)

FOURTH ADDRESS (INTERNAL)

X...X00

X...X01

X...X10

X...X11

X...X01

X...X10

X...X11

X...X00

X...X10

X...X11

X...X00

X...X01

X...X11

X...X00

X...X01

X...X10

PARTIAL TRUTH TABLE FOR READ/WRITE COMMANDS (x18)

FUNCTION

R/W#

BWa#

BWb#

READ

H

L

X

L

X

H

L

WRITE Byte “a”

WRITE Byte “b”

WRITE All Bytes

WRITE ABORT/NOP

H

L

H

NOTE: Using R/W# and byte write(s), any one or more bytes may be

written.

PARTIAL TRUTH TABLE FOR READ/WRITE COMMANDS (x32/x36)

FUNCTION

R/W#

BWa#

BWb#

BWc#

BWd#

READ

H

L

X

L

X

H

L

X

H

L

X

H

L

WRITE Byte “a”

WRITE Byte “b”

WRITE Byte “c”

WRITE Byte “d”

WRITE All Bytes

WRITE ABORT/NOP

H

L

H

L

H

L

H

NOTE: Using R/W# and byte write(s), any one or more bytes may be written.

8Mb: 512K x 18, 256K x 32/36 Pipelined ZBT SRAM

MT55L512L18P_2.p65 – Rev. 6/01

MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.

16

8Mb: 512K x 18, 256K x 32/36

PIPELINED ZBT SRAM

STATE DIAGRAM FOR ZBT SRAM

DS

BURST

DS

DESELECT

WRITE

READ

DS

WRITE

READ

BEGIN

READ

BEGIN

WRITE

BURST

READ

BURST

WRITE

READ

BURST

READ

BURST

WRITE

BURST

KEY:

COMMAND OPERATION

DS

DESELECT

READ

WRITE

BURST

New READ

New WRITE

BURST READ,

BURST WRITE or

CONTINUE DESELECT

NOTE: 1. A STALL or IGNORE CLOCK EDGE cycle is not shown in the above diagram. This is because CKE# HIGH only blocks the

clock (CLK) input and does not change the state of the device.

2. States change on the rising edge of the clock (CLK).

8Mb: 512K x 18, 256K x 32/36 Pipelined ZBT SRAM

MT55L512L18P_2.p65 – Rev. 6/01

MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.

17

8Mb: 512K x 18, 256K x 32/36

PIPELINED ZBT SRAM

TRUTH TABLE

(Notes 5-10)

ADDRESS

USED

ADV/

CE# CE2# CE2 Z Z L D # R/W# B W x OE# CKE# C L K

OPERATION

D Q

NOTES

DESELECT Cycle

CONTINUE DESELECT Cycle

None

H

X

L

X

H

X

L

X

L

X

H

X

L

L-H High-Z

None

L

None

X

H

L

1

READ Cycle

External

L-H

Q

(Begin Burst)

READ Cycle

(Continue Burst)

L

X

L

X

H

X

H

X

H

X

L

H

L

X

H

X

L

X

L

L-H

Q

1, 11

2

NOP/DUMMY READ

(Begin Burst)

H

X

L-H High-Z

DUMMY READ

(Continue Burst)

X

L

X

L

H

L

L-H High-Z 1, 2,

11

WRITE Cycle

(Begin Burst)

External

L-H

D

3

WRITE Cycle

(Continue Burst)

X

L

X

L

H

L

X

L

L-H

D

1, 3,

11

NOP/WRITE ABORT

(Begin Burst)

None

H

X

L

L-H High-Z 2, 3

WRITE ABORT

(Continue Burst)

X

H

X

L

L-H High-Z 1, 2,

3, 11

IGNORE CLOCK EDGE

(Stall)

Current

None

H

X

L-H

–

4

SNOOZE MODE

X

High-Z

NOTE: 1. CONTINUE BURST cycles, whether READ or WRITE, use the same control inputs. The type of cycle performed (READ or

WRITE) is chosen in the initial BEGIN BURST cycle. A CONTINUE DESELECT cycle can only be entered if a DESELECT cycle

is executed first.

2. DUMMY READ and WRITE ABORT cycles can be considered NOPs because the device performs no external operation.

A WRITE ABORT means a WRITE command is given, but no operation is performed.

3. OE# may be wired LOW to minimize the number of control signals to the SRAM. The device will automatically turn off

the output drivers during a WRITE cycle. OE# may be used when the bus turn-on and turn-off times do not meet an

application’s requirements.

4. If an IGNORE CLOCK EDGE command occurs during a READ operation, the DQ bus will remain active (Low-Z). If it

occurs during a WRITE cycle, the bus will remain in High-Z. No WRITE operations will be performed during the IGNORE

CLOCK EDGE cycle.

5. X means “Don’t Care.” H means logic HIGH. L means logic LOW. BWx = H means all byte write signals (BWa#, BWb#,

BWc# and BWd#) are HIGH. BWx = L means one or more byte write signals are LOW.

6. BWa# enables WRITEs to Byte “a” (DQa pins); BWb# enables WRITEs to Byte “b” (DQb pins); BWc# enables WRITEs to

Byte “c” (DQc pins); BWd# enables WRITEs to Byte “d” (DQd pins).

7. All inputs except OE# and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.

8. Wait states are inserted by setting CKE# HIGH.

9. This device contains circuitry that will ensure that the outputs will be in High-Z during power-up.

10. The device incorporates a 2-bit burst counter. Address wraps to the initial address every fourth burst cycle.

11. The address counter is incremented for all CONTINUE BURST cycles.

8Mb: 512K x 18, 256K x 32/36 Pipelined ZBT SRAM

MT55L512L18P_2.p65 – Rev. 6/01

MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.

18

8Mb: 512K x 18, 256K x 32/36

PIPELINED ZBT SRAM

*Stresses greater than those listed under “Absolute

Maximum Ratings” may cause permanent damage to

the device. This is a stress rating only, and functional

operation of the device at these or any other conditions

above those indicated in the operational sections of

this specification is not implied. Exposure to absolute

maximum rating conditions for extended periods may

affect reliability.

**Junction temperature depends upon package

type, cycle time, loading, ambient temperature, and

airfloꢁ. See Micron Technical Note TN-05-14 for more

information.

ABSOLUTEMAXIMUMRATINGS*

Voltage on VDD Supply

Relative to VSS ................................... -0.5V to +4.6V

Voltage on V^DDQ Supply

Relative to V^SS.......................................-0.5V to VDD

VIN -0.5V to VDDQ + 0.5V

Storage Temperature ꢂplastic) .......... -55°C to +150°C

Storage Temperature ꢂFBGA) .......... -55°C to +125°C

Junction Temperature** .................................. +150°C

Short Circuit Output Current ..........................100mA

3.3VI/ODCELECTRICALCHARACTERISTICSANDOPERATINGCONDITIONS

(0°C ≤ T_A≤ +70°C; VDD, VDDQ = +3.3V 0.165V unless otherwise noted)

DESCRIPTION

CONDITIONS

DQ pins

SYMBOL

VIH

MIN

2.0

MAX

VDD + 0.3

0.8

UNITS

V

NOTES

1, 2

3

Input High (Logic 1) Voltage

Input Low (Logic 0) Voltage

Input Leakage Current

Output Leakage Current

VIH

2.0

V

VIL

-0.3

-1.0

V

0V ≤ VIN ≤ VDD

Output(s) disabled,

ILI

1.0

µA

ILO

1.0

0V ≤ VIN ≤ VDD

Output High Voltage

Output Low Voltage

Supply Voltage

IOH = -4.0mA

VOH

VOL

2.4

–

V

1, 4

1

IOL = 8.0mA

0.4

VDD

3.135

3.465

VDD

Isolated Output Buffer Supply

VDDQ

1, 5

NOTE: 1. All voltages referenced to VSS (GND).

t

2. Overshoot:

VIH ≤ +4.6V for t ≤ KHKH/2 for I ≤ 20mA

t

Undershoot: V^IL≥ -0.7V for t ≤ KHKH/2 for I ≤ 20mA

Power-up: VIH ≤ +3.465V and VDD ≤ +3.135V for t ≤ 200ms

3. MODE pin has an internal pull-up, and input leakage = 10µA.

4. The load used for V^OH, VOL testing is shown in Figure 2. AC load current is higher than the shown DC values. AC I/O

curves are available upon request.

5. VDDQ should never exceed VDD. VDD and VDDQ can be externally wired together to the same power supply.

8Mb: 512K x 18, 256K x 32/36 Pipelined ZBT SRAM

MT55L512L18P_2.p65 – Rev. 6/01

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8Mb: 512K x 18, 256K x 32/36

PIPELINED ZBT SRAM

2.5VI/ODCELECTRICALCHARACTERISTICSANDOPERATINGCONDITIONS

(0°C ≤ T_A≤ +70°C; VDD = +3.3V 0.165V; VDDQ = +2.5V +0.4V/-0.125V unless otherwise noted)

DESCRIPTION

CONDITIONS

Data bus (DQx)

Inputs

SYMBOL MIN

MAX

VDDQ + 0.3

VDD + 0.3

0.7

UNITS

V

NOTES

1, 2

3

Input High (Logic 1) Voltage

VIHQ

VIH

VIL

1.7

V

Input Low (Logic 0) Voltage

Input Leakage Current

Output Leakage Current

-0.3

-1.0

V

0V ≤ VIN ≤ VDD

Output(s) disabled,

0V ≤ VIN ≤ VDDQ (DQx)

IOH = -2.0mA

ILI

1.0

µA

IL^O

1.0

Output High Voltage

Output Low Voltage

VOH

VOL

1.7

2.0

–

V

1

IOH = -1.0mA

IOL = 2.0mA

–

0.7

0.4

3.465

2.9

IOL = 1.0mA

VOL

–

Supply Voltage

VDD

VDDQ

3.135

2.375

Isolated Output Buffer Supply

TQFP CAPACITANCE

DESCRIPTION

CONDITIONS

T_A= +25°C; f = 1 MHz

VDD = +3.3V

SYMBOL

TYP

3

MAX

4

UNITS

pF

NOTES

Control Input Capacitance

Input/Output Capacitance (DQ)

Address Capacitance

Clock Capacitance

CI

CO

CA

CCK

4

5

pF

3

3.5

pF

3

pF

BGACAPACITANCE

DESCRIPTION

CONDITIONS

T_A= +25°C; f = 1 MHz

VDD = 3.3V

SYMBOL

TYP

4

MAX

7

UNITS

pF

NOTES

Address/Control Input Capacitance

Input/Output Capacitance (DQ)

Address Capacitance

CI

CO

CA

4

4.5

4

5.5

7

pF

Clock Capacitance

CCK

4.5

5.5

pF

FBGA CAPACITANCE

DESCRIPTION

CONDITIONS

SYMBOL TYP

MAX

3.5

5

UNITS NOTES

Address/Control Input Capacitance

Output Capacitance (Q)

Clock Capacitance

CI

CO

2.5

4

pF

4, 5

T_A= 25°C; f = 1 MHz

CCK

2.5

3.5

NOTE: 1. All voltages referenced to VSS (GND).

t

2. Overshoot:

VIH ≤ +4.6V for t ≤ KHKH/2 for I ≤ 20mA

t

Undershoot: VIL ≥ -0.7V for t ≤ KHKH/2 for I ≤ 20mA

Power-up: VIH ≤ +3.465V and VDD ≤ +3.135V for t ≤ 200ms

3. MODE pin has an internal pull-up, and input leakage = 10µA.

4. This parameter is sampled.

5. Preliminary package data.

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8Mb: 512K x 18, 256K x 32/36

PIPELINED ZBT SRAM

IDD OPERATINGCONDITIONSANDMAXIMUMLIMITS

(Note 1) (0°C ≤ T_A≤ +70°C; VDD = +3.3V 0.165V unless otherwise noted)

MAX

-7.5

DESCRIPTION

CONDITIONS

SYMBOL TYP

-6

-10

UNITS NOTES

Power Supply

Current: Operating or ≥ VIH; Cycle time ≥ KC (MIN);

Device selected; All inputs ≤ VIL

t

I

DD

200

10

500

400

25

300

mA

2, 3, 4

V

DD = MAX; Outputs open

Power Supply

Current: Idle

Device selected; V^DD= MAX;

CKE# ≥ V^IH

;

IDD

1

25

20

All inputs ≤ V^SS+ 0.2 or ≥ VDD - 0.2;

t

Cycle time ≥ KC (MIN)

CMOS Standby

TTL Standby

Device deselected; VDD = MAX;

All inputs ≤ V^SS+ 0.2 or ≥ VDD - 0.2;

All inputs static; CLK frequency = 0

I

SB

2

0.5

6

10

25

10

25

10

25

mA

3, 4

Device deselected; VDD = MAX;

All inputs ≤ V^ILor ≥ VIH

;

I

3

All inputs static; CLK frequency = 0

Clock Running

Snooze Mode

Device deselected; VDD = MAX;

ADV/LD# ≥ VIH; All inputs ≤ VSS + 0.2

I

4

45

120

10

75

10

60

10

mA

3, 4

4

t

or ≥ VDD - 0.2; Cycle time ≥ KC (MIN)

ZZ ≥ VIH

ISB

2

Z

0.5

TQFP THERMAL RESISTANCE

DESCRIPTION

CONDITIONS

SYMBOL

TYP

UNITS NOTES

Thermal Resistance

(Junction to Ambient)

Test conditions follow standard test methods

and procedures for measuring thermal

impedance, per EIA/JESD51.

θ

40

°C/W

5

JA

Thermal Resistance

(Junction to Top of Case)

θ

8

°C/W

5

JC

BGATHERMALRESISTANCE

DESCRIPTION

CONDITIONS

SYMBOL

TYP

UNITS NOTES

Junction to Ambient

(Airflow of 1m/s)

Test conditions follow standard test methods

and procedures for measuring thermal

impedance, per EIA/JESD51.

θ_JA

40

°C/W

5

Junction to Case (Top)

θ_JC

9

°C/W

5

NOTE: 1. VDDQ = +3.3V 0.165V for 3.3V I/O configuration; VDDQ = +2.5V +0.4V/-0.125V for 2.5V I/O

configuration.

2. IDD is specified with no output current and increases with faster cycle times. IDDQ increases with faster cycle times and

greater output loading.

3. “Device deselected” means device is in a deselected cycle as defined in the truth table. “Device selected” means device

is active (not in deselected mode).

4. Typical values are measured at +3.3V, +25°C and 10ns cycle time.

5. This parameter is sampled.

8Mb: 512K x 18, 256K x 32/36 Pipelined ZBT SRAM

MT55L512L18P_2.p65 – Rev. 6/01

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8Mb: 512K x 18, 256K x 32/36

PIPELINED ZBT SRAM

FBGA THERMAL RESISTANCE

DESCRIPTION

CONDITIONS

SYMBOL

TYP

UNITS NOTES

Junction to Ambient

(Airflow of 1m/s)

Test conditions follow standard test methods

and procedures for measuring thermal

impedance, per EIA/JESD51.

θ_JA

40

°C/W 1, 11

Junction to Case (Top)

θ_JC

θ_JB

9

°C/W 1, 11

Junction to Pins (Bottom)

17

ACELECTRICALCHARACTERISTICS

(Notes 2, 3, 4) (0°C ≤ T_A≤ +70°C; VDD = +3.3V 0.165V unless otherwise noted)

-6

-7.5

MAX

-10

DESCRIPTION

SYMBOL MIN

MAX

MIN

MAX UNITS NOTES

Clock

t

Clock cycle time

Clock frequency

Clock HIGH time

Clock LOW time

Output Times

Clock to output valid

Clock to output invalid

Clock to output in Low-Z

Clock to output in High-Z

OE# to output valid

OE# to output in Low-Z

OE# to output in High-Z

Setup Times

KHKH

6.0

7.5

10

ns

MHz

ns

f

KF

KHKL

KLKH

166

133

4.2

100

5.0

t

1.7

2.0

3.2

5

t

ns

t

KHQV

KHQX

KHQX1

3.5

ns

1.5

6

t

6, 7, 8, 9

2

6, 7, 8, 9

t

KHQZ

GLQV

GLQX

3.5

4.2

3.5

5.0

t

0

t

GHQZ

3.5

4.2

5.0

t

Address

AVKH

1.5

1.7

2.0

ns

10

t

Clock enable (CKE#)

Control signals

Data-in

EVKH

t

CVKH

t

DVKH

Hold Times

Address

Clock enable (CKE#)

Control signals

Data-in

t

KHAX

KHEX

KHCX

KHDX

0.5

ns

10

t

NOTE: 1. This parameter is sampled.

2. OE# can be considered a “Don’t Care” during WRITEs; however, controlling OE# can help fine-tune a system for

turnaround timing.

3. Test conditions as specified with output loading as shown in Figure 1 for 3.3V I/O (VDDQ = +3.3V 0.165V) and

Figure 3 for 2.5V I/O (VDDQ = +2.5V +0.4V/-0.125V).

4. A WRITE cycle is defined by R/W# LOW having been registered into the device at ADV/LD# LOW. A READ cycle is

defined by R/W# HIGH with ADV/LD# LOW. Both cases must meet setup and hold times.

5. Measured as HIGH above VIH and LOW below VIL.

6. Refer to Technical Note TN-55-01, “Designing with ZBT SRAMs,” for a more thorough discussion on these parameters.

7. This parameter is sampled.

8. This parameter is measured with output loading as shown in Figure 2 for 3.3V I/O and Figure 4 for 2.5V I/O.

9. Transition is measured 200mV from steady state voltage.

10. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK

when they are being registered into the device. All other synchronous inputs must meet the setup and hold times

with stable logic levels for all rising edges of clock (CLK) when the chip is enabled. Chip enable must be valid at each

rising edge of CLK when ADV/LD# is LOW to remain enabled.

11. Preliminary package data.

8Mb: 512K x 18, 256K x 32/36 Pipelined ZBT SRAM

MT55L512L18P_2.p65 – Rev. 6/01

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8Mb: 512K x 18, 256K x 32/36

PIPELINED ZBT SRAM

3.3V I/O AC TEST CONDITIONS

2.5V I/O AC TEST CONDITIONS

Input pulse levels ...................................VSS to 3.3V

Input rise and fall times..................................... 1ns

Input timing reference levels .......................... 1.5V

Output reference levels ................................... 1.5V

Output load ............................. See Figures 1 and 2

Input pulse levels ...................................VSS to 2.5V

Input rise and fall times..................................... 1ns

Input timing reference levels ........................ 1.25V

Output reference levels ................................. 1.25V

Output load ............................. See Figures 3 and 4

3.3V I/O Output Load Equivalents

2.5V I/O Output Load Equivalents

Q

Z_O= 50Ω

50Ω

Z_O= 50

50

V_T= 1.5V

V_T= 1.25V

Figure 1

Figure 3

+3.3V

317

+2.5V

225Ω

5pF

Q

5pF

225Ω

351

Figure 2

Figure 4

LOAD DERATING CURVES

The Micron 512K x 18, 256K x 32, and 256K x 36 ZBT

SRAM timing is dependent upon the capacitive loading

on the outputs.

Consult the factory for copies of I/O current versus

voltage curves.

8Mb: 512K x 18, 256K x 32/36 Pipelined ZBT SRAM

MT55L512L18P_2.p65 – Rev. 6/01

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8Mb: 512K x 18, 256K x 32/36

PIPELINED ZBT SRAM

SNOOZE MODE

SNOOZE MODE is a loꢁ-current, “poꢁer-doꢁn”

mode in ꢁhich the device is deselected and current is

reduced to I^SB2Z. The duration of SNOOZE MODE is

dictated by the length of time the ZZ pin is in a HIGH

state. After the device enters SNOOZE MODE, all inputs

except ZZ become disabled and all outputs go to

High-Z.

the ZZ pin becomes a logic HIGH, I^SB2Z is guaranteed

after the time ^tZZI is met. Any READ or WRITE opera-

tion pending ꢁhen the device enters SNOOZE MODE is

not guaranteed to complete successfully. Therefore,

SNOOZE MODE must not be initiated until valid pend-

ing operations are completed. Similarly, ꢁhen exiting

t

SNOOZE MODE during RZZ, only a DESELECT or

The ZZ pin is an asynchronous, active HIGH input

that causes the device to enter SNOOZE MODE. When

READ cycle should be given.

SNOOZEMODEELECTRICALCHARACTERISTICS

DESCRIPTION

CONDITIONS

SYMBOL MIN

MAX

UNITS NOTES

Current during SNOOZE MODE

ZZ active to input ignored

ZZ inactive to input sampled

ZZ active to snooze current

ZZ inactive to exit snooze current

ZZ ≥ VIH

I

t

SB2Z

10

mA

t

ZZ

0

2( KHKH)

ns

1

t

RZZ

2( KHKH)

t

ZZI

2( KHKH)

t

RZZI

0

NOTE: 1. This parameter is sampled.

SNOOZE MODE WAVEFORM

CLK

t

ZZ

t

RZZ

ZZ

t

ZZI

I

SUPPLY

I

ISB2Z

t

RZZI

ALL INPUTS

(except ZZ)

DESELECT or READ Only

Outputs (Q)

High-Z

DON’T CARE

8Mb: 512K x 18, 256K x 32/36 Pipelined ZBT SRAM

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8Mb: 512K x 18, 256K x 32/36

PIPELINED ZBT SRAM

READ/WRITE TIMING

1

2

3

4

5

6

7

8

9

10

t

KHKH

t

CLK

t

EVKH KHEX

KLKH

KHKL

CKE#

t

CVKH KHCX

CE#

ADV/LD#

R/W#

BWx#

A1

A2

A4

KHQV

A3

A5

A6

A7

ADDRESS

DQ

t

DVKH KHDX

t

KHQX

GLQV

KHQX1

KHQZ

t

AVKH KHAX

D(A1)

D(A2)

D(A2+1)

Q(A3)

Q(A4)

Q(A4+1)

D(A5)

Q(A6)

t

GHQZ

t

KHQX

t

GLQX

OE#

COMMAND

WRITE

D(A1)

WRITE

D(A2)

BURST

WRITE

READ

Q(A3)

READ

Q(A4)

BURST

READ

WRITE

D(A5)

READ

Q(A6)

WRITE

D(A7)

DESELECT

D(A2+1)

Q(A4+1)

DON’T CARE

UNDEFINED

READ/WRITE TIMING PARAMETERS

-6

-7.5

-10

-6

-7.5

-10

SYM

MIN

MAX

MIN

MAX

MIN

MAX

UNITS

SYM

MIN

MAX

3.5

MIN

MAX

MIN

MAX

UNITS

ns

t

KHKH

6.0

7.5

10

ns

MHz

ns

GHQZ

4.2

5.0

f

KF

166

133

100

AVKH

EVKH

CVKH

DVKH

KHAX

KHEX

KHCX

KHDX

1.5

0.5

1.7

0.5

2.0

0.5

ns

t

KHKL

1.7

2.0

3.2

ns

t

KLKH

ns

t

KHQV

3.5

4.2

5.0

ns

t

KHQX

1.5

ns

t

KHQX1

ns

t

KHQZ

3.5

4.2

3.5

5.0

ns

t

GLQV

ns

t

GLQX

0

ns

NOTE: 1. For this waveform, ZZ is tied LOW.

2. Burst sequence order is determined by MODE (0 = linear, 1 = interleaved). BURST operations are optional.

3. CE# represents three signals. When CE# = 0, it represents CE# = 0, CE2# = 0, CE2 = 1.

4. Data coherency is provided for all possible operations. If a READ is initiated, the most current data is used. The most

recent data may be from the input data register.

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8Mb: 512K x 18, 256K x 32/36

PIPELINED ZBT SRAM

NOP, STALL, AND DESELECT CYCLES

1

2

3

4

5

6

7

8

9

10

CLK

CKE#

CE#

ADV/LD#

R/W#

BWx#

A1

A2

A3

A4

A5

ADDRESS

t

KHQZ

D(A1)

Q(A2)

Q(A3)

D(A4)

Q(A5)

KHQX

DQ

t

COMMAND

WRITE

D(A1)

READ

Q(A2)

STALL

READ

Q(A3)

WRITE

D(A4)

STALL

NOP

READ

Q(A5)

DESELECT

CONTINUE

DESELECT

DON’T CARE

UNDEFINED

NOP, STALL, AND DESELECT TIMING PARAMETERS

-6

-7.5

-10

SYM

MIN

1.5

MAX

MIN

1.5

MAX

MIN

1.5

MAX

UNITS

ns

t

KHQX

t

KHQZ

1.5

3.5

1.5

3.5

1.5

3.5

ns

NOTE: 1. The IGNORE CLOCK EDGE or STALL cycle (clock 3) illustrates CKE# being used to create a “pause.” A WRITE is not

performed during this cycle.

2. For this waveform, ZZ and OE# are tied LOW.

3. CE# represents three signals. When CE# = 0, it represents CE# = 0, CE2# = 0, CE2 = 1.

4. Data coherency is provided for all possible operations. If a READ is initiated, the most current data is used. The most

recent data may be from the input data register.

8Mb: 512K x 18, 256K x 32/36 Pipelined ZBT SRAM

MT55L512L18P_2.p65 – Rev. 6/01

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8Mb: 512K x 18, 256K x 32/36

PIPELINED ZBT SRAM

100-PIN PLASTIC TQFP (JEDEC LQFP)

PIN #1 ID

+0.03

-0.02

0.15

0.32

+0.06

-0.10

+0.10

-0.15

0.65

22.10

20.10 0.10

DETAIL A

0.62

1.50 0.10

0.10

14.00 0.10

+0.20

16.00

+0.10

-0.05

0.25

-0.05

0.10

GAGE PLANE

1.00 (TYP)

1.40 0.05

0.60 0.15

DETAIL A

NOTE: 1. All dimensions in millimeters.

2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per

side.

8Mb: 512K x 18, 256K x 32/36 Pipelined ZBT SRAM

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8Mb: 512K x 18, 256K x 32/36

PIPELINED ZBT SRAM

165-PIN FBGA

0.85 0.075

0.12

C

SEATING PLANE

C

BALL A11

165X Ø 0.45

10.00

SOLDER BALL DIAMETER REFERS

TO POST REFLOW CONDITION. THE

PRE-REFLOW DIAMETER IS Ø 0.40

BALL A1

PIN A1 ID

1.20 MAX

1.00

TYP

PIN A1 ID

7.50 0.05

14.00

15.00 0.10

7.00 0.05

1.00

TYP

MOLD COMPOUND: EPOXY NOVOLAC

SUBSTRATE: PLASTIC LAMINATE

6.50 0.05

5.00 0.05

SOLDER BALL MATERIAL: EUTECTIC 63% Sn, 37% Pb

SOLDER BALL PAD: Ø .33mm

13.00 0.10

MAX

NOTE: 1. All dimensions in millimeters

or typical where noted.

MIN

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8Mb: 512K x 18, 256K x 32/36

PIPELINED ZBT SRAM

119-PINBGA

22.00 0.20

19.94 0.10

Substrate material:

BT resin laminate

0.60 0.10

0.90 0.10

14.00 0.10

0.15

11.94 0.10

2.40 MAX

SEATING PLANE

A1 CORNER

(dimension applies to a

noncollapsed solder ball)

0.75 0.15

Ø

1.27 (TYP)

7.62

1.27 (TYP)

20.32

MAX

NOTE: 1. All dimensions in millimeters

or typical where noted.

MIN

2. Solder ball land pad is 0.6mm.

8000 S. Federal Way, P.O. Box 6, Boise, ID 83707-0006, Tel: 208-368-3900

E-mail:prodmktg@micron.com,Internet:http://www.micronsemi.com,CustomerCommentLine:800-932-4992

Micron is a registered trademark of Micron Technology, Inc.

ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc.,

and the architecture is supported by Micron Technology, Inc., and Motorola Inc.

8Mb: 512K x 18, 256K x 32/36 Pipelined ZBT SRAM

MT55L512L18P_2.p65 – Rev. 6/01

MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.

29

8Mb: 512K x 18, 256K x 32/36

PIPELINED ZBT SRAM

REVISION HISTORY

Removed note "Not Recommended for Neꢁ Designs," Rev. 6/01 ................................................................ June 7/01

Added industrial temperature references and notes, Rev. 3/01................................................................ March 19/01

Changed 16Mb references to 18Mb

Changed NC/DQPx to NF/DQPx

Added 119-pin PBGA package, Rev. 1/01, FINAL ............................................................................................ 1/10/01

Removed FBGA Part Marking Guide, Rev. 8/00, FINAL .................................................................................... 8/1/00

Added FBGA Part Marking Guide, REV 7/00, FINAL ...................................................................................... 7/20/00

Added Revision History

Removed 119-Pin PBGA package and references

Added 165-pin FBGA Package........................................................................................................................... 6/13/00

Removed "Smart ZBT" references ....................................................................................................................... 6/13/00

8Mb: 512K x 18, 256K x 32/36 Pipelined ZBT SRAM

MT55L512L18P_2.p65 – Rev. 6/01

MicronTechnology,Inc.,reservestherighttochangeproductsorspecificationswithoutnotice.

30

型号	制造商	描述	价格	文档
MT55L512L18PF-10	CYPRESS	ZBT SRAM, 512KX18, 5ns, CMOS, PBGA165, 13 X 15 MM, FBGA-165	获取价格
MT55L512L18PF-10IT	CYPRESS	ZBT SRAM, 512KX18, 5ns, CMOS, PBGA165, 13 X 15 MM, FBGA-165	获取价格
MT55L512L18PF-6	CYPRESS	ZBT SRAM, 512KX18, 3.5ns, CMOS, PBGA165, 13 X 15 MM, FBGA-165	获取价格
MT55L512L18PF-6IT	CYPRESS	ZBT SRAM, 512KX18, 3.5ns, CMOS, PBGA165, 13 X 15 MM, FBGA-165	获取价格
MT55L512L18PF-7.5	CYPRESS	ZBT SRAM, 512KX18, 4.2ns, CMOS, PBGA165, 13 X 15 MM, FBGA-165	获取价格
MT55L512L18PT-10	CYPRESS	ZBT SRAM, 512KX18, 5ns, CMOS, PQFP100, PLASTIC, TQFP-100	获取价格
MT55L512L18PT-10IT	CYPRESS	ZBT SRAM, 512KX18, 5ns, CMOS, PQFP100, PLASTIC, MS-026BHA, TQFP-100	获取价格
MT55L512L18PT-10Z	CYPRESS	ZBT SRAM, 512KX18, 5.2ns, CMOS, PQFP100, PLASTIC, MS-026BHA, TQFP-100	获取价格
MT55L512L18PT-11	CYPRESS	ZBT SRAM, 512KX18, 8.5ns, CMOS, PQFP100, PLASTIC, MS-026BHA, TQFP-100	获取价格
MT55L512L18PT-12	CYPRESS	ZBT SRAM, 512KX18, 9ns, CMOS, PQFP100, PLASTIC, MS-026BHA, TQFP-100	获取价格

MT55L512L18PB-7.5IT

MT55L512L18PB-7.5IT 概述

MT55L512L18PB-7.5IT 数据手册

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