17531A
更新时间：2025-01-23 08:43:08
品牌：FREESCALE
描述：700 mA Dual H-Bridge Motor Driver with 3.0 V Compatible Logic I/O
概述
数据手册17531A 概述
700 mA Dual H-Bridge Motor Driver with 3.0 V Compatible Logic I/O 与3.0 V兼容逻辑700毫安双H桥电机驱动器的I / O
17531A 数据手册
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PDF下载Document Number: MPC17531A
Rev. 3.0, 2/2008
Freescale Semiconductor
Technical Data
700 mA Dual H-Bridge Motor
Driver with 3.0 V Compatible
Logic I/O
17531A
The 17531A is a monolithic dual H-Bridge power IC ideal for
portable electronic applications containing bipolar step motors and/or
brush DC-motors (e.g., cameras and disk drive head positioners).
DUAL H-BRIDGE
The 17531A operates from 2.0 V to 8.6 V using the internal charge
pump, with independent control of each H-Bridge via parallel MCU
interface. The device features built-in shoot-through current
protection and an undervoltage shutdown function.
The 17531A has four operating modes: Forward, Reverse, Brake,
and Tri-Stated (High Impedance). The 17531A has a low total
RDS(ON) of 1.2 Ω (max @ 25°C).
The 17531A efficiently drives many types of micromotors with low
power dissipation owing to its low output resistance and high output
slew rates. The H-Bridge outputs can be independently pulse width
modulated (PWM’ed) at up to 200 kHz for speed/torque and current
control.
VMFP SUFFIX
EV SUFFIX (PB-FREE)
98ASA10616D
QFN SUFFIX
EP SUFFIX (PB-FREE)
98ARL10577D
20-TERMINAL VMFP
24-TERMINAL QFN
Features
ORDERING INFORMATION
• Low Total RDS(ON) 0.8 W (Typ), 1.2 Ω (Max) @ 25°C
• Output Current 0.7 A (DC)
• Shoot-Through Current Protection Circuit
• PWM Control Input Frequency up to 200 kHz
• Built-In Charge Pump Circuit
Temperature
Device
Package
Range (T )
A
MPC17531AEV/EL
MPC17531AEP/R2
20 VMFP
24 QFN
-20°C to 65°C
• Low Power Consumption
• Undervoltage Detection and Shutdown Circuit
• Power Save Mode with Current Draw ≤ 2.0 µA
• Pb-Free Packaging Designated by Suffix Codes EV and EP
3.0 V
5.0 V
17531A
VDD
C1L
C1H
C2L
C2H
VM
OUT1A
CRES OUT1B
Bipolar
Step
Motor
IN1A OUT2A
N
IN1B
S
OUT2B
MCU
IN2A
IN2B
PSAVE
GND
Figure 1. 17531A Simplified Application Diagram
Freescale Semiconductor, Inc. reserves the right to change the detail specifications,
as may be required, to permit improvements in the design of its products.
© Freescale Semiconductor, Inc., 2005. All rights reserved.
INTERNAL BLOCK DIAGRAM
INTERNAL BLOCK DIAGRAM
CRES
C2H
C1H
C1L
Charge
Pump
C2L
Low-
Voltage
VDD
Shutdown
VM1
IN1A
IN1B
OUT1A
OUT1B
H-Bridge
VDD
PGND1
VM2
Level Shifter
Predriver
Control
Logic
PSAVE
IN2A
OUT2A
OUT2B
H-Bridge
IN2B
LGND
PGND2
Figure 2. 17531A Simplified Internal Block Diagram
17531A
Analog Integrated Circuit Device Data
Freescale Semiconductor
2
TERMINAL CONNECTIONS
TERMINAL CONNECTIONS
1
20
19
VDD
IN1A
LGND
IN2A
2
3
18
17
IN2B
IN1B
4
PSAVE
VM2
5
16
15
14
13
12
11
OUT2A
PGND1
OUT1A
VM1
OUT2B
PGND2
OUT1B
C2L
6
7
8
9
CRES
C2H
C1L
10
C1H
Figure 3. 17531A, 20-Terminal VMFP Connections
Table 1. 17531A, 20-Terminal VMFP Definitions
A functional description of each terminal can be found in the Functional Terminal Description section beginning on page 10.
Terminal
Number
Terminal
Name
Formal Name
Definition
Control circuit power supply terminal.
1
2
VDD
IN1A
Logic Supply
Logic Input Control 1A
Logic Input Control 1B
Power Save
Logic input control of OUT1A (refer to Table 6, Truth Table, page 9).
Logic input control of OUT1B (refer to Table 6, Truth Table, page 9).
Logic input controlling power save mode.
3
IN1B
4
PSAVE
OUT2A
PGND1
OUT1A
VM1
Output A of H-Bridge channel 2.
5
H-Bridge Output 2A
Power Ground 1
High-current power ground 1.
6
Output A of H-Bridge channel 1.
7
H-Bridge Output 1A
Motor Drive Power Supply 1
Predriver Power Supply
Charge Pump 2H
Positive power source connection for H-Bridge 1 (Motor Drive Power Supply).
Internal triple charge pump output as predriver power supply.
Charge pump bucket capacitor 2 (positive pole).
Charge pump bucket capacitor 1 (positive pole).
Charge pump bucket capacitor 1 (negative pole).
Charge pump bucket capacitor 2 (negative pole).
Output B of H-Bridge channel 1.
8
9
CRES
C2H
10
11
12
13
14
15
16
17
18
19
20
C1H
C1L
Charge Pump 1H
Charge Pump 1L
C2L
Charge Pump 2L
OUT1B
PGND2
OUT2B
VM2
H-Bridge Output 1B
Power Ground 2
High-current power ground 2.
Output B of H-Bridge channel 2.
H-Bridge Output 2B
Motor Drive Power Supply 2
Logic Input Control 2B
Logic Input Control 2A
Logic Ground
Positive power source connection for H-Bridge 2 (Motor Drive Power Supply).
Logic input control of OUT2B (refer to Table 6, Truth Table, page 9).
Logic input control of OUT2A (refer to Table 6, Truth Table, page 9).
Low-current logic signal ground.
IN2B
IN2A
LGND
17531A
Analog Integrated Circuit Device Data
Freescale Semiconductor
3
TERMINAL CONNECTIONS
Transparent Top View of Package
24
23
22
21
20
19
1
2
3
4
5
6
18
17
16
15
14
13
NC
VM2
PSAVE
OUT2A
PGND1
OUT1A
NC
NC
OUT2B
PGND2
OUT1B
C2L
7
8
9
10
11
12
Figure 4. 17531A, 24-Terminal QFN Connections
Table 2. 17531A, 24-Terminal QFN Definitions
A functional description of each terminal can be found in the Functional Terminal Description section beginning on page 10.
Terminal
Number
Terminal
Name
Formal Name
Definition
1, 6, 7, 17
NC
No Connect
This terminal is not used.
2
Logic input controlling power save mode.
Output A of H-Bridge channel 2.
High-current power ground 1.
PSAVE
OUT2A
PGND1
OUT1A
VM1
Power Save
3
H-Bridge Output 2A
Power Ground 1
H-Bridge Output 1A
4
5
Output A of H-Bridge channel 1.
8
Motor Drive Power Supply 1 Positive power source connection for H-Bridge 1 (Motor Drive Power Supply).
9
C
Predriver Power Supply
Charge Pump 2H
Charge Pump 1H
Charge Pump 1L
Charge Pump 2L
H-Bridge Output 1B
Power Ground 2
Internal triple charge pump output as pre-driver power supply.
Charge pump bucket capacitor 2 (positive pole).
Charge pump bucket capacitor 1 (positive pole).
Charge pump bucket capacitor 1 (negative pole).
Charge pump bucket capacitor 2 (negative pole).
Output B of H-Bridge channel 1.
RES
10
11
12
13
14
15
16
18
19
20
21
22
23
24
C2H
C1H
C1L
C2L
OUT1B
PGND2
OUT2B
VM2
High-current power ground 2.
H-Bridge Output 2B
Output B of H-Bridge channel 2.
Motor Drive Power Supply 2 Positive power source connection for H-Bridge 2 (Motor Drive Power Supply).
IN2B
Logic Input Control 2B
Logic Input Control 2A
Logic Ground
Logic input control of OUT2B (refer to Table 6, Truth Table, page 9).
Logic input control of OUT2A (refer to Table 6, Truth Table, page 9).
Low-current logic signal ground.
IN2A
LGND
V
Control circuit power supply terminal.
Logic Supply
DD
IN1A
IN1B
Logic Input Control 1A
Logic Input Control 1B
Logic input control of OUT1A (refer to Table 6, Truth Table, page 9).
Logic input control of OUT1B (refer to Table 6, Truth Table, page 9).
17531A
Analog Integrated Circuit Device Data
Freescale Semiconductor
4
MAXIMUM RATINGS
MAXIMUM RATINGS
Table 3. Maximum Ratings
All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or
permanent damage to the device.
Ratings
Symbol
Value
Unit
Motor Supply Voltage
Charge Pump Output Voltage
Logic Supply Voltage
Signal Input Voltage
V
-0.5 to 11.0
-0.5 to 14.0
-0.5 to 5.0
V
V
V
V
A
M
V
C
RES
DD
V
V
-0.5 to V +0.5
DD
IN
Driver Output Current
Continuous
I
O
0.7
1.4
I
Peak (1)
OPK
ESD Voltage
V
Human Body Model (2)
Machine Model (3)
VESD1
VESD2
±1200
±150
Operating Junction Temperature
T
-20 to 150
-20 to 65
-65 to 150
50
°C
°C
J
Operating Ambient Temperature
Storage Temperature Range
T
A
T
°C
STG
Thermal Resistance (4)
RθJA
°C/W
Power Dissipation (5)
P
D
W
1.0
2.5
WMFP
QFN
Terminal Soldering Temperature (6)
TSOLDER
260
°C
Notes
1.
T = 25°C. Pulse width = 10 ms at 200 ms intervals.
A
2. ESD1 testing is performed in accordance with the Human Body Model (CZAP = 100 pF, RZAP = 1500 Ω).
3. ESD2 testing is performed in accordance with the Machine Model (CZAP = 200 pF, RZAP = 0 Ω).
4. For QFN only, mounted on 37 x 50 Cu area (1.6 mm FR-4 PCB).
5.
T = 25°C.
A
6. Terminal soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits
may cause malfunction or permanent damage to the device.
17531A
Analog Integrated Circuit Device Data
Freescale Semiconductor
5
STATIC ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics
Characteristics noted under conditions TA = 25°C, VDD = 3.0 V, VM = 5.0 V, GND = 0 V unless otherwise noted. Typical values
noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER INPUT
Motor Supply Voltage (Using Internal Charge Pump) (7)
V
M-CP
V
2.0
–
5.0
–
8.6
10
V
V
V
Motor Supply Voltage (
Applied Externally) (8)
V
M-NCP
CRES
V
CRES-VM
5.0
2.7
6.0
3.0
–
V
Gate Drive Voltage - Motor Supply Voltage (
Logic Supply Voltage
Applied Externally) (9)
CRES
V
3.6
V
DD
Driver Quiescent Supply Current
No Signal Input
µA
I
QM
–
–
–
–
100
1.0
I
QM-PSAVE
Power Save Mode
mA
mA
Logic Quiescent Supply Current
No Signal Input (10)
I
QVDD
–
–
–
–
1.0
1.0
I
QVDD-
Power Save Mode
PSAVE
Operating Power Supply Current
Logic Supply Current (11)
I
VDD
–
–
–
–
3.0
0.7
I
CRES
Charge Pump Circuit Supply Current (12)
VDDDET
1.0
–
1.6
0.8
2.5
1.2
V
Low V
Detection Voltage (13)
DD
Driver Output ON Resistance (14)
DS(ON)
R
Ohms
GATE DRIVE
V
Gate Drive Voltage (12)
No Current Load
CRES
V
V
12
13
13.5
V
Gate Drive Ability (Internally Supplied)
I
CRESload
8.5
9.2
0.1
–
C
= -1.0 mA
RES
Recommended External Capacitance (C1L–C1H, C2L–C2H, C
–GND)
C
0.01
1.0
µF
RES
CP
Notes
7. Gate drive voltage
V
V
C
is applied from an external source. 2 x V
+ V must be <
C
max (13.5 V).
RES
RES
DD
M
V
8. No internal charge pump used.
V
C
is applied from an external source.
RES
V
9.
R
I
is not guaranteed if
C
- V < 5.0 V. Also, function is not guaranteed if
C
- V < 3.0 V.
DS(ON)
RES
M
RES M
10. QVDD includes the current to pre-driver circuit.
I
11.
V
includes the current to predriver circuit at fIN = 100 kHz.
DD
12. At fIN = 20 kHz.
V
13. Detection voltage is defined as when the output becomes high-impedance after V
V
drops below the detection threshold.
C
is
DD
RES
applied from an external source. 2 x V
14. IO = 0.7 A source + sink.
+ V must be <
C
max (13.5 V).
DD
M
RES
17531A
Analog Integrated Circuit Device Data
Freescale Semiconductor
6
STATIC ELECTRICAL CHARACTERISTICS
Table 4. Static Electrical Characteristics (continued)
Characteristics noted under conditions TA = 25°C, VDD = 3.0 V, VM = 5.0 V, GND = 0 V unless otherwise noted. Typical values
noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
CONTROL LOGIC
Logic Input Voltage
Logic Inputs (2.7 V < V
V
V
0
–
VDD
V
IN
IH
< 3.3 V)
DD
V
x0.7
–
–
–
x0.3
V
High-Level Input Voltage
Low-Level Input Voltage
High-Level Input Current
Low-Level Input Current
DD
V
–
–
V
V
IL
DD
I
–
1.0
–
µA
µA
µA
IH
I
-1.0
–
–
IL
I -PSAVE
50
100
PSAVE Terminal Input Current Low
IL
17531A
Analog Integrated Circuit Device Data
Freescale Semiconductor
7
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 5. Dynamic Electrical Characteristics
Characteristics noted under conditions TA = 25°C, VDD = 3.0 V, VM = 5.0 V, GND = 0 V unless otherwise noted. Typical values
noted reflect the approximate parameter means at TA = 25°C under nominal conditions unless otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
INPUT
Pulse Input Frequency
f
–
–
–
–
200
kHz
IN
Input Pulse Rise Time (15)
Input Pulse Fall Time (17)
OUTPUT
t
1.0
µs
R
(16)
t
–
–
1.0
µs
µs
F
(16)
Propagation Delay Time (18)
Turn-ON Time
tPLH
tPHL
–
–
0.1
0.1
0.5
0.5
Turn-OFF Time
Charge Pump Wake-Up Time (19)
Low-Voltage Detection Time
t
–
–
1.0
–
3.0
10
ms
ms
VGON
t
VDDDET
Notes
15. Time is defined between 10% and 90%.
16. That is, the input waveform slope must be steeper than this.
17. Time is defined between 90% and 10%.
18. Output load is 8.0 Ω DC.
19.
C
= 0.1 µF.
CP
17531A
Analog Integrated Circuit Device Data
Freescale Semiconductor
8
TIMING DIAGRAMS
TIMING DIAGRAMS
IN1,
IN2,
VDDDETon
VDDDEToff
2.5 V
50%
50%
PSAVE
VDD
0.8 V
tPLH
tPHL
t
t
VDDDET
VDDDET
90%
10%
90%
OUTA,
OUTB
0%
(<1.0 µA)
IM
Figure 5. tPLH, tPHL, and tPZH Timing
Figure 6. Low-Voltage Detection Timing
V
DD
t
VGON
V
C
RES
11 V
Figure 7. Charge Pump Timing
Table 6. Truth Table
INPUT
OUTPUT
Charge Pump and Low
Voltage Detector
PSAVE
IN1A
IN2A
IN1B
IN2B
OUT1A
OUT2A
OUT1B
OUT2B
L
L
L
L
H
L
H
L
L
L
L
H
L
L
L
RUN
RUN
RUN
RUN
STOP
H
H
X
H
Z
Z
H
X
Z
Z
H = High.
L = Low.
Z = High impedance.
X = Don’t care.
PSAVE terminal is pulled up to V
with internal resistance.
DD
17531A
Analog Integrated Circuit Device Data
Freescale Semiconductor
9
FUNCTIONAL DESCRIPTION
INTRODUCTION
FUNCTIONAL DESCRIPTION
INTRODUCTION
The 17531A is a monolithic dual H-Bridge ideal for
portable electronic applications to control bipolar step motors
and brush DC motors such as those found in camera len
assemblies, camera shutters, and optical disk drives. The
device features an on-board charge pump, as well as built-in
shoot-through current protection and undervoltage
shutdown.
The 17531A has four operating modes: Forward, Reverse,
Brake, and Tri-Stated (High Impedance). The MOSFETs
comprising the output bridge have a total source +sink
RDS(ON) ≤ 1.2 Ω.
The 17531A can simultaneously drive two brush DC
motors or one bipolar step motor. The drivers are designed to
be PWM’ed at frequencies up to 200 kHz.
FUNCTIONAL TERMINAL DESCRIPTION
LOGIC SUPPLY (VDD)
MOTOR DRIVE POWER SUPPLY (VM1 AND VM2)
The VDD terminal carries the logic supply voltage and
current into the logic sections of the IC. VDD has an
undervoltage threshold. If the supply voltage drops below the
undervoltage threshold, the output power stage switches to a
tri-state condition. When the supply voltage returns to a level
that is above the threshold, the power stage automatically
resumes normal operation according to the established
condition of the input terminals.
The VM terminals carry the main supply voltage and
current into the power sections of the IC. This supply then
becomes controlled and/or modulated by the IC as it delivers
the power to the loads attached between the OUTput
terminals. All VM terminals must be connected together on
the printed circuit board.
CHARGE PUMP (C1L AND C1H, C2L AND C2H)
These two pairs of terminals, the C1L and C1H and the
C2L and C2H, connect to the external bucket capacitors
required by the internal charge pump. The typical value for
the bucket capacitors is 0.1 µF.
LOGIC INPUT CONTROL (IN1A, IN1B, IN2A, AND
IN2B)
These logic input terminals control each H-Bridge output.
IN1A logic HIGH = OUT1A HIGH. However, if all inputs are
taken HIGH, the outputs bridges are both tri-stated (refer to
Table 6, Truth Table, page 9).
PREDRIVER POWER SUPPLY (CRES)
The CRES terminal is the output of the internal charge
pump. Its output voltage is approximately three times of VDD
voltage. The VCRES voltage is power supply for the internal
predriver circuit of H-Bridges.
POWER SAVE (PSAVE)
The PSAVE terminal is a HIGH = TRUE power save mode
input. When PSAVE = HIGH, all H-Bridge outputs (OUT1A,
OUT1B, OUT2A, and OUT2B) are tri-stated (High-Z),
regardless of logic inputs (IN1A, IN1B, IN2A, and IN2B)
states, and the internal charge pump and low voltage
detection current are shut off to save power.
POWER GROUND (PGND)
Power ground terminals. They must be tied together on the
PCB.
LOGIC GROUND (LGND)
H-BRIDGE OUTPUT (OUT1A, OUT1B, OUT2A, AND
OUT2B)
Logic ground terminal.
These terminals provide connection to the outputs of each
of the internal H-Bridges (see Figure 2, 17531A Simplified
Internal Block Diagram, page 2).
17531A
Analog Integrated Circuit Device Data
Freescale Semiconductor
10
TYPICAL APPLICATIONS
FUNCTIONAL TERMINAL DESCRIPTION
TYPICAL APPLICATIONS
Figure 8 shows a typical application for the 17531A. When
applying the gate voltage to the CRES terminal from an
The internal charge pump of this device is generated from
the VDD supply; therefore, care must be taken to provide
sufficient gate-source voltage for the high-side MOSFETs
when VM >> VDD (e.g., VM = 5.0 V, VDD = 3.3 V), in order to
ensure full enhancement of the high-side MOSFET channels.
external source, be sure to connect it via a resistor equal to,
V
or greater than, RG
=
C
/0.02 Ω.
RES
3.3 V 5.0 V
17531A
VDD
VM
C1L
C1H
NC C2L
NC C2H
NC
NC
V
CRES < 14 V
OUT1A
V
RG
> CRES/0.02 Ω
CRES
RG
0.01 µF
OUT1B
OUT2A
IN1A
IN1B
IN2A
MCU
IN2B
OUT2B
PSAVE
GND
NC = No Connect
Figure 8. 17531A Typical Application Diagram
PCB LAYOUT
CEMF SNUBBING TECHNIQUES
Care must be taken to protect the IC from potentially
damaging CEMF spikes induced when commutating currents
in inductive loads. Typical practice is to provide snubbing of
voltage transients via placing a capacitor or zener at the
supply terminal (VM) (see Figure 9).
When designing the printed circuit board (PCB), connect
sufficient capacitance between power supply and ground
terminals to ensure proper filtering from transients. For all
high-current paths, use wide copper traces and shortest
possible distances.
3.3 V
5.0 V
3.3 V
5.0 V
17531A
17531A
VM
VM
VDD
VDD
C1L
C1L
C1H
C2L
C1H
C2L
OUT
OUT
OUT
OUT
C2H
CRES
C2H
CRES
GND
GND
Figure 9. CEMF Snubbing Techniques
17531A
Analog Integrated Circuit Device Data
Freescale Semiconductor
11
PACKAGING
PACKAGE DIMENSIONS
PACKAGING
PACKAGE DIMENSIONS
For the most current package revision, visit www.freescale.com and perform a keyword search using the “98A” drawing number listed below.
EV (Pb-FREE) SUFFIX
20-LEAD VMFP
PLASTIC PACKAGE
98ASA10816D
ISSUE A
17531A
Analog Integrated Circuit Device Data
Freescale Semiconductor
12
PACKAGING
PACKAGE DIMENSIONS
EV (Pb-FREE) SUFFIX
20-LEAD VMFP
PLASTIC PACKAGE
98ASA10816D
ISSUE A
17531A
Analog Integrated Circuit Device Data
Freescale Semiconductor
13
PACKAGING
PACKAGE DIMENSIONS
EV (Pb-FREE) SUFFIX
20-LEAD VMFP
PLASTIC PACKAGE
98ASA10816D
ISSUE A
17531A
Analog Integrated Circuit Device Data
Freescale Semiconductor
14
PACKAGING
PACKAGE DIMENSIONS
17531A
Analog Integrated Circuit Device Data
Freescale Semiconductor
15
PACKAGING
PACKAGE DIMENSIONS
EP (Pb-FREE) SUFFIX
24-LEAD QFN
PLASTIC PACKAGE
98ARL10577D
ISSUE A
17531A
Analog Integrated Circuit Device Data
Freescale Semiconductor
16
PACKAGING
PACKAGE DIMENSIONS
EP (Pb-FREE) SUFFIX
24-LEAD QFN
PLASTIC PACKAGE
98ARL10577D
ISSUE A
17531A
Analog Integrated Circuit Device Data
Freescale Semiconductor
17
PACKAGING
PACKAGE DIMENSIONS
EP (Pb-FREE) SUFFIX
24-LEAD QFN
PLASTIC PACKAGE
CASE 1508-01
ISSUE A
17531A
Analog Integrated Circuit Device Data
Freescale Semiconductor
18
REVISION HISTORY
REVISION HISTORY
REVISION
DATE
DESCRIPTION OF CHANGES
•
•
Implemented Revision History page
Converted to Freescale format
9/2005
2.0
2/2008
•
Corrected Table 2, Pin Definitiuons on page 4.
3.0
17531A
Analog Integrated Circuit Device Data
Freescale Semiconductor
19
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MPC17531A
Rev. 3.0
2/2008
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