ICS601M-01

更新时间:2024-10-08 01:49:41
品牌:ICSI
描述:Low Phase Noise Clock Multiplier

ICS601M-01 概述

Low Phase Noise Clock Multiplier 低相位噪声时钟乘法器

ICS601M-01 数据手册

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ICS601-01  
Low Phase Noise Clock Multiplier  
Description  
Features  
The ICS601-01 is a low cost, low phase noise, high  
performance clock synthesizer for any applications  
that require low phase noise and low jitter. It is  
ICS’ lowest phase noise multiplier, and also the  
lowest CMOS part in the industry. Using ICS’  
patented analog and digital Phase Locked Loop  
(PLL) techniques, the chip accepts a 10-27 MHz  
crystal or clock input, and produces output clocks  
up to 156 MHz at 3.3 V.  
• Packaged in 16 pin SOIC or TSSOP  
• Uses fundamental 10 - 27 MHz crystal, or clock  
• Patented PLL with the lowest phase noise  
• Output clocks up to 156 MHz at 3.3 V  
• Low phase noise: -132 dBc/Hz at 10 kHz  
• Output Enable function tri states outputs  
• Low jitter - 18 ps one sigma  
• Full swing CMOS outputs with 25 mA drive  
capability at TTL levels  
• Advanced, low power, sub-micron CMOS process  
• Industrial temperature version available  
• 3.3 V or 5 V operation  
Block Diagram  
VDD  
Phase  
Comparator  
Charge  
Pump  
Loop  
Filter  
Output  
Buffer  
Reference  
Divide  
CLK  
VCO  
X1/ICLK  
X2  
VCO  
Divide  
Crystal  
Oscillator  
Output  
Buffer  
REFOUT  
ROM Based  
Multipliers  
GND  
S3 S2 S1 S0  
OE  
REFEN  
MDS 601-01 G  
1
Revision 090800  
Printed 11/14/00  
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126• (408) 295-9800tel • www.icst.com  
ICS601-01  
Low Phase Noise Clock Multiplier  
Multiplier Select Table  
Pin Assignment  
S3 S2 S1 S0 CLK (see note 2 on following page)  
CLK  
REFEN  
VDD  
VDD  
VDD  
X2  
GND  
1
16  
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
TEST  
TEST  
15 GND  
14 GND  
2
3
4
5
6
7
Input x1  
Input x3  
13  
12  
REFOUT  
OE  
Input x4  
Input x5  
Input x6  
11 S0  
10 S3  
Input x8  
S1  
TEST  
S2  
9
Crystal osc. pass through (no PLL)  
Input x2  
X1/ICLK  
8
ICS601-01  
TEST  
Input x8  
Input x10  
Input x12  
Input x16  
0=connect directly to ground  
1=connect directly to VDD  
Pin Descriptions  
Number  
Name  
CLK  
REFEN  
VDD  
VDD  
VDD  
X2  
Type Description  
1
2
O
I
Clock output from VCO. Output frequency equals the input frequency times multiplier.  
Reference clock enable. Turns off the buffered crystal oscillator clock (stops low) when low.  
Connect to +3.3V or +5V. Must match other VDDs.  
3
P
P
P
XO  
I
4
Connect to +3.3V or +5V. Must match other VDDs.  
5
Connect to +3.3V or +5V. Must match other VDDs.  
6
Crystal connection. Connect to a 10 - 27 MHz fundamental parallel mode crystal.  
Multiplier select pin 1. Determines CLK output per table above. Internal pull-up.  
Crystal connection. Connect to a 10-27 MHz fundamental parallel mode crystal, or clock  
Multiplier select pin 2. Determines CLK output per table above. Internal pull-up.  
Multiplier select pin 3. Determines CLK output per table above. Internal pull-up.  
Multiplier select pin 0. Determines CLK output per table above. Internal pull-up.  
Output Enable. Tri-states both output clocks when low. Internal pull-up.  
Buffered crystal oscillator clock output. Controlled by REFEN.  
Connect to ground.  
7
S1  
8
X1/ICLK  
S2  
XI  
I
9
10  
11  
12  
13  
14  
15  
16  
S3  
I
S0  
I
OE  
I
REFOUT  
GND  
GND  
GND  
O
P
P
P
Connect to ground.  
Connect to ground.  
Key: I = Input with internal pull-up resistor; O = output; P = power supply connection; XI, XO = crystal  
connections.  
MDS 601-01 G  
2
Revision 090800  
Printed 11/14/00  
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126• (408) 295-9800tel • www.icst.com  
ICS601-01  
Low Phase Noise Clock Multiplier  
Achieving Low Phase Noise  
Figure 1 shows a typical phase noise measurement in a 125 MHz system. There are a few simple steps that  
can be taken to achieve these levels of phase noise from the ICS601-01. Variations in VDD will increase the  
phase noise, so it is important to have a stable, low noise supply voltage at the device. Use decoupling  
capacitors of 0.1 µF in parallel with 0.01 µF. It is important to have these capacitors as close as possible to  
the ICS601-01 supply pins.  
Disabling the REFOUT clock is also important for achieving low phase noise; lab tests have shown that this  
can reduce the phase noise by as much as 10 dBc/Hz.  
0
-20  
-40  
-60  
-80  
-100  
-120  
-140  
10.0E+0  
100.0E+0  
1.0E+3  
10.0E+3  
100.0E+3  
1.0E+6  
10.0E+6  
Offset from Carrier (Hz)  
Figure 1. Phase Noise of ICS601-01 at 125 MHz out, 25 MHz crystal input.  
VDD = 3.3 V, REFOUT disabled.  
External Components/Crystal Selection  
The ICS601-01 requires a minimum number of external components for proper operation. Decoupling  
capacitors of 0.01 µF and 0.1 µF should be connected between VDD and GND, as close to the part as  
possible. A series termination resistor of 33 Wmay be used for each clock output. The crystal must be  
connected as close to the chip as possible. The crystal should be fundamental mode, parallel resonant. Do  
not use third overtone. For exact tuning when using a crystal, capacitors should be connected from pins X1  
to ground and X2 to ground. In general, the value of these capacitors is given by the following equation,  
where C is the crystal load capacitance: Crystal caps (pF) = (C -5) x 2. So for a crystal with 16 pF load  
L
L
capacitance, two 22 pF caps can be used. For any given board layout, ICS can measure the board  
capacitance and recommend the exact capacitance value to use.  
MDS 601-01 G  
3
Revision 090800  
Printed 11/14/00  
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126• (408) 295-9800tel • www.icst.com  
ICS601-01  
Low Phase Noise Clock Multiplier  
Electrical Specifications  
Parameter  
Conditions  
Minimum  
Typical  
Maximum  
Units  
ABSOLUTE MAXIMUM RATINGS (note 1)  
Supply voltage, VDD  
Referenced to GND  
7
VDD+0.5  
70  
V
V
Inputs and Clock Outputs  
Ambient Operating Temperature  
Ambient Operating Temperature, I version  
Soldering Temperature  
Referenced to GND  
-0.5  
0
°C  
°C  
°C  
°C  
Industrial temperature  
Max of 10 seconds  
-40  
85  
260  
Storage temperature  
-65  
150  
DC CHARACTERISTICS (VDD = 3.3 V unless noted)  
Operating Voltage, VDD  
3.0  
5.5  
(VDD/2)-1  
0.8  
V
V
Input High Voltage, VIH, X1/ICLK pin only  
Input Low Voltage, VIL, X1/ICLK pin only  
Input High Voltage, VIH  
Note 3  
Note 3  
(VDD/2)+1  
V
2
V
Input Low Voltage, VIL  
V
Output High Voltage, VOH, CMOS level  
Output High Voltage, VOH  
Output Low Voltage, VOL  
IOH=-4mA  
VDD-0.4  
2.4  
V
IOH=-12mA  
IOL=12mA  
V
0.4  
30  
V
Operating Supply Current, IDD  
Short Circuit Current  
No Load, 125 MHz  
Each output  
22  
±60  
5
mA  
mA  
pF  
±40  
10  
Input Capacitance  
AC CHARACTERISTICS (VDD = 3.3 V unless noted)  
Input Frequency  
OE, select pins  
27  
156  
1.5  
1.5  
55  
MH z  
MH z  
ns  
Output Frequency  
at 3.3V or 5V  
Output Clock Rise Time  
Output Clock Fall Time  
Output Clock Duty Cycle  
0.8 to 2.0V, no load  
0.8 to 2.0V, no load  
At VDD/2  
ns  
45  
50  
%
Maximum Absolute Jitter, short term, 125 MHz No load, REF off  
±50  
18  
±75  
25  
ps  
Maximum Jitter, one sigma, 125 MHz (x5)  
Phase Noise, relative to carrier, 125 MHz (x5)  
Phase Noise, relative to carrier, 125 MHz (x5)  
Phase Noise, relative to carrier, 125 MHz (x5)  
Phase Noise, relative to carrier, 125 MHz (x5)  
No load, REF off  
100 Hz offset  
1 kHz offset  
ps  
-105  
-120  
-128  
-121  
-108  
-123  
-132  
-125  
dBc/Hz  
dBc/Hz  
dBc/Hz  
dBc/Hz  
10 kHz offset  
100 kHz offset  
Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged  
exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability.  
2. The phase relationship between input and output can change at power up. For a fixed phase relationship, see the ICS570  
or ICS670.  
3. Switching occurs nominally at VDD/2.  
MDS 601-01 G  
4
Revision 090800  
Printed 11/14/00  
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126• (408) 295-9800tel • www.icst.com  
ICS601-01  
Low Phase Noise Clock Multiplier  
Package Outline and Package Dimensions  
(For current dimensional specifications, see JEDEC no. 95.)  
16 pin narrow SOIC, TSSOP (in mm)  
SOIC  
Symbol Min Max  
TSSOP  
Min  
Max  
1.20  
0.15  
0.30  
0.20  
5.10  
4.50  
A
A1  
B
C
D
E
1.35  
0.10  
0.33  
0.19  
9.80  
3.80  
5.80  
1.75  
0.25  
0.51  
0.25  
10.00  
4.00  
6.20  
-
0.05  
0.19  
0.09  
4.90  
E
H
4.30  
H
e
6.40 BSC  
0.65 BSC  
0.45  
1.27 BSC  
0.40 1.27  
L
0.75  
D
A
A1  
C
B
L
e
Ordering Information  
Part/Order Number  
ICS601M-01  
Marking  
Shipping packaging  
tubes  
Package  
Temperature  
ICS601M-01  
ICS601M-01  
ICS601M-01I  
ICS601M-01I  
ICS601G-01  
ICS601G-01  
16 pin narrow SOIC 0 to 70 °C  
16 pin narrow SOIC 0 to 70 °C  
16 pin narrow SOIC -40 to 85 °C  
16 pin narrow SOIC -40 to 85 °C  
ICS601M-01T  
ICS601M-01I  
ICS601M-01IT  
ICS601G-01  
tape and reel  
tubes  
tape and reel  
tubes  
tape and reel  
16 pin TSSOP  
16 pin TSSOP  
0 to 70 °C  
0 to 70 °C  
ICS601G-01T  
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its  
use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is  
intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary  
environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does  
not authorize or warrant any ICS product for use in life support devices or critical medical instruments.  
MDS 601-01 G  
5
Revision 090800  
Printed 11/14/00  
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126• (408) 295-9800tel • www.icst.com  

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