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841S012BKIT

更新时间：2025-07-05 19:06:14
品牌：IDT
描述：Clock Generator, 250MHz, 8 X 8 MM, 0.925 MM HEIGHT, MO-220, VFQFN-56

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免费 PCB/SMT

841S012BKIT 概述

Clock Generator, 250MHz, 8 X 8 MM, 0.925 MM HEIGHT, MO-220, VFQFN-56 时钟发生器

841S012BKIT 规格参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Active零件包装代码：QFN
包装说明：VQCCN,针数：56
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：5.52
JESD-30 代码：S-XQCC-N56JESD-609代码：e0
长度：8 mm端子数量：56
最高工作温度：85 °C最低工作温度：-40 °C
最大输出时钟频率：250 MHz封装主体材料：UNSPECIFIED
封装代码：VQCCN封装形状：SQUARE
封装形式：CHIP CARRIER, VERY THIN PROFILE峰值回流温度（摄氏度）：225
主时钟/晶体标称频率：25 MHz认证状态：Not Qualified
座面最大高度：1 mm最大供电电压：3.465 V
最小供电电压：3.135 V标称供电电压：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：TIN LEAD
端子形式：NO LEAD端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：30
宽度：8 mmuPs/uCs/外围集成电路类型：CLOCK GENERATOR, OTHER
Base Number Matches：1

841S012BKIT 数据手册

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PRELIMINARY  
CRYSTAL-TO-0.7V DIFFERENTIAL HCSL/  
LVCMOS FREQUENCY SYNTHESIZER  
ICS841S012I  
GENERAL DESCRIPTION  
FEATURES  
The ICS841S012I is an optimized PCIe, sRIO and  
• Tꢁo 0.7V differential HCSL outputs (Bank A), configurable for  
PCIe (100MHz or 250MHz) and sRIO (100MHz or 125MHz)  
clock signals  
ICS  
HiPerClockS™  
Gigabit Ethernet Frequency Synthesizer and a  
member of HiperClocks™family of high perfor-  
mance clock solutions from IDT. The ICS841S012I  
uses a 25MHz parallel resonant crystal to gener-  
Eight LVCMOS/LVTTL outputs (Banks B/C),  
15Ω typical output impedance  
ate 33.33MHz - 200MHz clock signals, replacing solutions  
requiring multiple oscillator and fanout buffer solution. The  
device supports 0.25ꢀ center-spread, and -0.5ꢀ doꢁn-  
spread clocking ꢁith tꢁo spread select pins (SSC[1:0]). The  
VCO operates at frequency of 2GHz. The device has three  
output banks: Bank A ꢁith tꢁo HCSL outputs, 100MHz –  
250MHz; Bank B ꢁith seven 33.33MHz – 200MHz LVCMOS/  
LVTTL outputs; and Bank C ꢁith one 33.33MHz – 200MHz  
LVCMOS/LVTTL output.  
Tꢁo REF_OUT LVCMOS/LVTTL clock outputs,  
20Ω typical output impedance  
• Selectable crystal oscillator interface, 25MHz, 18pF parallel  
resonant crystal or one LVCMOS/LVTTL single-ended  
reference clock input  
• Supports the folloꢁing output frequencies:  
HCSL Bank A: 100MHz, 125MHz, 200MHz and 250MHz  
LVCMOS/LVTTL Bank B/C: 33.33MHz, 50MHz, 66.67MHz,  
100MHz, 125MHz, 133.33MHz, 166.67MHz and 200MHz  
All Banks A, B and C have their oꢁn dedicated frequency  
select pins and can be independently set for the frequencies  
mentioned above. The loꢁ jitter characteristic of the  
ICS841S012I makes it an ideal clock source for PCIe, sRIO  
and Gigabit Ethernet applications. Designed for netꢁorking and  
industrial applications, the ICS841S012I can also drive the high-  
speed clock inputs of communication processors, DSPs,  
sꢁitches and bridges.  
• VCO: 2GHz  
• Spread spectrum clock: 0.25ꢀ center-spread and  
-0.5ꢀ doꢁn-spread  
• PLL bypass and output enable  
• RMS period jitter: 15ps (typical), QB outputs  
• Full 3.3V supply mode  
• -40°C to 85°C ambient operating temperature  
• Available in both standard (RoHS 5) and lead-free (RoHS 6)  
packages  
PIN ASSIGNMENT  
56 55 54 53 52 51 50 49 48 47 46 45 44 43  
42  
41  
VDD  
REF_OUT0  
REF_OUT1  
GND  
1
VDDOC  
QC  
2
GND  
QBC_OE  
VDDA  
VDDA  
GND  
GND  
IREF  
QA0  
3
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
4
5
ICS841S012I  
GND  
56-Lead VFQFN  
6
REF_IN  
VDD  
8mm x 8mm x 0.925mm  
package body  
7
REF_SEL  
XTAL_IN  
XTAL_OUT  
BYPASS  
8
9
K Package  
Top Vieꢁ  
10  
11  
12  
13  
14  
nQA0  
QA1  
nQA1  
REF_OE  
nMR  
VDD  
VDD  
15 16 17 18 19 20 21 22 23 24 25 26 27 28  
The Preliminary Information presented herein represents a product in pre-production.The noted characteristics are based on initial product characterization  
and/or qualification.Integrated DeviceTechnology, Incorporated (IDT) reserves the right to change any circuitry or specifications ꢁithout notice.  
IDT™ / ICS™ 0.7V HCSL/LVCMOS FREQUENCY SYNTHESIZER  
1
ICS841S012BKI REV. A MAY 1, 2008  
ICS841S012I  
CRYSTAL-TO-0.7V DIFFERENTIAL HCSL/LVCMOS FREQUENCY SYNTHESIZER  
PRELIMINARY  
BLOCK DIAGRAM  
Pullup  
QA_OE  
2
Pulldoꢁn  
Pulldoꢁn  
F_SELA[1:0]  
QA0  
nQA0  
QA1  
BYPASS  
XTAL_IN  
÷NA  
25MHz  
nQA1  
1
0
OSC  
0
1
XTAL_OUT  
PLL  
VCO  
2GHz  
QB0  
Pulldoꢁn  
REF_IN  
QB1  
QB2  
Pulldoꢁn  
REF_SEL  
M = ÷80  
QB3  
QB4  
÷NB  
3
Pulldoꢁn  
F_SELB[2:0]  
IREF  
QB5  
QB6  
QC  
÷NC  
3
2
Pulldoꢁn  
Pullup  
F_SELC[2:0]  
nMR  
Pullup  
Pullup  
QBC_OE  
SSC[1:0]  
Spread  
Spectrum  
REF_OUT0  
REF_OUT1  
Pulldoꢁn  
REF_OE  
IDT™ / ICS™ 0.7V HCSL/LVCMOS FREQUENCY SYNTHESIZER  
2
ICS841S012BKI REV. A MAY 1, 2008  
ICS841S012I  
CRYSTAL-TO-0.7V DIFFERENTIAL HCSL/LVCMOS FREQUENCY SYNTHESIZER  
PRELIMINARY  
TABLE 1. PIN DESCRIPTIONS  
Number  
Name  
Type  
Description  
1, 7, 14, 28,  
29  
VDD  
Poꢁer  
Output  
Core supply pins.  
2,  
3
REF_OUT0,  
REF_OUT1  
Single-ended LVCMOS/LVTTL reference clock outputs.  
20Ω typical output impedance.  
4, 5, 15, 27,  
35, 36, 40,  
46, 50, 54  
GND  
Poꢁer  
Poꢁer supply ground.  
6
REF_IN  
Input Pulldoꢁn Single-ended LVCMOS/LVTTL reference clock input.  
Reference select pin. When HIGH selects REF_IN. When LOW,  
selects crystal. LVCMOS/LVTTL interface levels. See Table 3E.  
Crystal oscillator interface. XTAL_OUT is the output.  
XTAL_IN is the input.  
8
REF_SEL  
Input Pulldoꢁn  
Input  
9,  
10  
XTAL_IN,  
XTAL_OUT  
When HIGH bypasses PLL. When LOW, selects N divider.  
LVCMOS/LVTTL interface levels.  
Active HIGH REF_OUT enables/disables pin.  
LVCMOS/LVTTL interface levels. See Table 3H.  
Active LOW Master Reset. When logic LOW, the internal dividers  
are reset and the outputs are in high impedance (HI-Z). When logic  
HIGH, the internal dividers and the outputs are enabled.  
LVCMOS/LVTTL interface levels.  
11  
12  
BYPASS  
REF_OE  
Input Pulldoꢁn  
Input Pulldoꢁn  
13  
nMR  
Input  
Input  
Pullup  
Pullup  
16,  
17  
SSC1,  
SSC0  
SSC control pin. LVCMOS/LVTTL interface levels. See Table 3D.  
18,  
19,  
20  
21,  
22,  
23  
F_SELB2,  
F_SELB1,  
F_SELB0  
F_SELC2,  
F_SELC1,  
F_SELC0  
F_SELA1,  
F_SELA0  
Frequency select pins for QBx outputs. See Table 3B.  
LVCMOS/LVTTL interface levels.  
Input Pulldoꢁn  
Frequency select pins for QC output. See Table 3C.  
LVCMOS/LVTTL interface levels.  
Input Pulldoꢁn  
Input Pulldoꢁn  
24,  
25  
Frequency select pins for QAx/nQAx outputs. See Table 3A.  
LVCMOS/LVTTL interface levels.  
Output enable pin for Bank A outputs.  
LVCMOS/LVTTL interface levels. See Table 3F.  
26  
QA_OE  
Input  
Pullup  
Pullup  
30, 31  
32, 33  
nQA1, QA1  
nQA0, QA  
Output  
Differential Bank A clock outputs. HCSL interface levels.  
External fixed precision resistor (475Ω) from this pin to ground  
provides a reference current used for differential current-mode  
QAx/nQAx clock outputs.  
34  
IREF  
Output  
37, 38  
39  
VDDA  
Poꢁer  
Input  
Analog supply pin.  
Output enable pin for Bank B and Bank C outputs.  
LVCMOS/LVTTL Interface levels. See Table 3G.  
Single-ended Bank C clock output. LVCMOS/LVTTL interface levels.  
15Ω typical output impedance.  
QBC_OE  
41  
QC  
Output  
42  
VDDOC  
VDDOB  
Poꢁer  
Poꢁer  
Output supply pin for QC LVCMOS output.  
43, 48, 52, 56  
Output supply pins for QBx LVCMOS outputs.  
44, 45,  
47, 49,  
51, 53, 55  
QB0, QB1,  
QB2, QB3,  
QB4, QB5, QB6  
Single-ended Bank B clock outputs. LVCMOS/LVTTL interface  
levels. 15Ω typical output impedance.  
Output  
NOTE: Pullup and Pulldoꢁn refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.  
IDT™ / ICS™ 0.7V HCSL/LVCMOS FREQUENCY SYNTHESIZER  
3
ICS841S012BKI REV. A MAY 1, 2008  
ICS841S012I  
CRYSTAL-TO-0.7V DIFFERENTIAL HCSL/LVCMOS FREQUENCY SYNTHESIZER  
PRELIMINARY  
TABLE 2. PIN CHARACTERISTICS  
Symbol Parameter  
Test Conditions  
Minimum Typical Maximum Units  
CIN  
Input Capacitance  
4
pF  
Poꢁer Dissipation  
Capacitance  
CPD  
QB[0:6], QC  
VDD, VDDOB, VDDOC = 3.465V  
9
pF  
RPULLUP  
Input Pullup Resistor  
51  
51  
15  
20  
kΩ  
kΩ  
Ω
RPULLDOWN Input Pulldoꢁn Resistor  
QB[0:6], QC  
ROUT  
Output Impedance  
REF_OUT[1:0]  
Ω
TABLE 3A. F_SELA FREQUENCY SELECT FUNCTION TABLE  
Inputs  
Output Frequency (25MHz Ref.)  
F_SELA1 F_SELA0  
M Divider Value  
NA Divider Value  
QA[0:1]/nQA[0:1] (MHz)  
L
L
L
H
L
80  
80  
80  
80  
20  
16  
10  
8
100  
125  
200  
250  
H
H
H
TABLE 3B. F_SELB FREQUENCY SELECT FUNCTION TABLE  
Inputs  
Output Frequency (25MHz Ref.)  
F_SELB2  
F_SELB1  
F_SELB0  
M Divider Value NB Divider Value  
QB[0:6] (MHz)  
33.33  
50  
L
L
L
L
L
H
L
80  
80  
80  
80  
80  
80  
80  
80  
60  
40  
30  
20  
16  
15  
12  
10  
L
H
H
L
66.67  
100  
L
H
L
H
H
H
H
125  
L
H
L
133.33  
166.67  
200  
H
H
H
TABLE 3C. F_SELC FREQUENCY SELECT FUNCTION TABLE  
Inputs  
Output Frequency (25MHz Ref.)  
F_SELC2  
F_SELC1  
F_SELC0  
M Divider Value NC Divider Value  
QC (MHz)  
33.33  
50  
L
L
L
L
L
H
L
80  
80  
80  
80  
80  
80  
80  
80  
60  
40  
30  
20  
16  
15  
12  
10  
L
H
H
L
66.67  
100  
L
H
L
H
H
H
H
125  
L
H
L
133.33  
166.67  
200  
H
H
H
IDT™ / ICS™ 0.7V HCSL/LVCMOS FREQUENCY SYNTHESIZER  
4
ICS841S012BKI REV. A MAY 1, 2008  
ICS841S012I  
CRYSTAL-TO-0.7V DIFFERENTIAL HCSL/LVCMOS FREQUENCY SYNTHESIZER  
PRELIMINARY  
TABLE 3D. SSC FUNCTION TABLE  
Input  
TABLE 3E. REF_SEL FUNCTION TABLE  
Input  
Input Reference  
SSC1  
SSC0  
Mode  
REF_SEL  
0
0
1
1
0
1
0
1
0 to -0.5ꢀ Doꢁn-spread  
0.25ꢀ Center-spread  
0.25ꢀ Center-spread  
SSC Off (default)  
0
1
XTAL  
REF_IN  
TABLE 3F. QA_OE FUNCTION TABLE  
Input  
TABLE 3G. QBC_OE FUNCTION TABLE  
Input  
Function  
Function  
QA_OE  
QBC_OE  
0
1
QA[0:1]/nQA[0:1] disabled (Hi-Z)  
QA[0:1]/nQA[0:1] enabled  
0
1
QB[0:6] and QC disabled (Hi-Z)  
QB[0:6] and QC enabled  
TABLE 3H. REF_OE FUNCTION TABLE  
Input  
TABLE 3I. nMR FUNCTION TABLE  
Input  
Function  
REF_OE  
Function  
nMR  
0
1
REF_OUT[0:1] disabled (Hi-Z)  
REF_OUT[0:1] enabled  
0
Device reset, output divider disabled (Hi-Z)  
Output enabled  
1
NOTE: This device requires a reset signal after poꢁer-up to  
function properly.  
IDT™ / ICS™ 0.7V HCSL/LVCMOS FREQUENCY SYNTHESIZER  
5
ICS841S012BKI REV. A MAY 1, 2008  
ICS841S012I  
CRYSTAL-TO-0.7V DIFFERENTIAL HCSL/LVCMOS FREQUENCY SYNTHESIZER  
PRELIMINARY  
ABSOLUTE MAXIMUM RATINGS  
Supply Voltage, V  
4.6V  
NOTE: Stresses beyond those listed under Absolute  
Maximum Ratings may cause permanent damage to the  
device.These ratings are stress specifications only. Functional op-  
eration of product at these conditions or any conditions beyond  
those listed in the DC Characteristics or AC Characteristics is not  
implied. Exposure to absolute maximum rating conditions for ex-  
tended periods may affect product reliability.  
DD  
Inputs, V  
-0.5V to VDD + 0.5 V  
-0.5V to VDDO + 0.5V  
I
Outputs, VO  
Package Thermal Impedance, θJA 31.4°C/W (0 mps)  
Storage Temperature, T -65°C to 150°C  
STG  
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDOB = VDDOC = 3.3V 5ꢀ, TA = -40°C TO 85°C  
Symbol  
VDD  
Parameter  
Test Conditions  
Minimum Typical Maximum Units  
Core Supply Voltage  
Analog Supply Voltage  
3.135  
VDD – 0.20  
3.135  
3.3  
3.3  
3.3  
3.465  
VDD  
V
V
V
VDDA  
VDDOB, VDDOC Output Supply Voltage  
3.465  
IDD  
Poꢁer Supply Current  
Analog Supply Current  
250  
20  
mA  
mA  
IDDA  
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDOB = VDDOC = 3.3V 5ꢀ, TA = -40°C TO 85°C  
Symbol Parameter Test Conditions Minimum Typical Maximum Units  
VIH  
VIL  
Input High Voltage  
Input Loꢁ Voltage  
QA_OE, QBC_OE,  
2
VDD + 0.3  
0.8  
V
V
-0.3  
V
DD = VIN = 3.465V  
5
µA  
nMR, SSC0, SSC1,  
F_SELA[0:1],  
F_SELB[0:2].  
F_SELC[0:2],  
Input  
High Current  
IIH  
VDD = VIN = 3.465V  
150  
µA  
REF_OE, BYPASS,  
REF_IN, REF_SEL  
QA_OE, QBC_OE,  
nMR, SSC0, SSC1,  
V
DD = 3.465V, VIN = 0V  
-150  
µA  
µA  
F_SELA[0:1],  
F_SELB[0:2].  
F_SELC[0:2],  
Input  
Loꢁ Current  
IIL  
VDD = 3.465V, VIN = 0V  
-5  
REF_OE, BYPASS,  
REF_IN, REF_SEL  
VOH  
VOL  
Output High Voltage; NOTE 1  
Output Loꢁ Voltage; NOTE 1  
VDDOB, VDDOC = 3.3V 5ꢀ  
VDDOB, VDDOC = 3.3V 5ꢀ  
2.6  
V
V
0.5  
NOTE 1: Outputs terminated ꢁith 50Ω to VDDOB, C/2. See Parameter Measurement Information,  
Output Load Test Circuit diagram.  
IDT™ / ICS™ 0.7V HCSL/LVCMOS FREQUENCY SYNTHESIZER  
6
ICS841S012BKI REV. A MAY 1, 2008  
ICS841S012I  
CRYSTAL-TO-0.7V DIFFERENTIAL HCSL/LVCMOS FREQUENCY SYNTHESIZER  
PRELIMINARY  
TABLE 5. CRYSTAL CHARACTERISTICS  
Parameter  
Test Conditions  
Minimum  
Fundamental  
25  
Typical Maximum Units  
Mode of Oscillation  
Frequency  
MHz  
Ω
Equivalent Series Resistance (ESR)  
Shunt Capacitance  
Drive Level  
50  
7
pF  
100  
µW  
NOTE: Characterized using an 18pF parallel resonant crystal.  
TABLE 6. AC CHARACTERISTICS, VDD = VDDOB = VDDOC = 3.3V 5ꢀ, TA = -40°C TO 85°C  
Symbol Parameter  
Test Conditions  
Minimum Typical Maximum Units  
QB[0:6]  
33.33  
100  
200  
250  
200  
MHz  
MHz  
MHz  
ps  
fOUT  
Output Frequency  
QA[0:1]/nQA[0:1]  
QC  
33.33  
QB[0:6]  
35  
10  
50  
45  
55  
50  
7
Output Skeꢁ;  
NOTE 1, 2  
tsk(o)  
tsk(b)  
QA[0:1]/nQA[0:1]  
ps  
Bank Skeꢁ; NOTE 2, 3  
across Banks B and C  
ps  
QA[0:1]/nQA[0:1]  
ps  
Cycle-to-Cycle  
Jitter; NOTE 2  
tjit(cc)  
QB[0:6]  
ps  
QC  
ps  
QA[0:1]/nQA[0:1]  
QB[0:6], QC  
ps  
tjit(per)  
FM  
RMS Period Jitter  
15  
ps  
SSC Modulation  
Frequency  
Banks A, B, C  
29  
33.33  
850  
kHz  
VHIGH  
VLOW  
Voltage High  
Voltage Loꢁ  
660  
-150  
250  
mV  
mV  
mV  
mV  
VCROSS  
Absolute Crossing Voltage  
550  
140  
ΔVCROSS Total Variation of VCROSS over all edges  
measured betꢁeen  
0.175V to 0.525V  
Bank A  
175  
45  
700  
ps  
Output  
Rise/Fall Time  
tR / tF  
Banks B, C  
Bank A  
20ꢀ - 80ꢀ  
350  
50  
ps  
ꢀ
ꢀ
55  
odc  
Output Duty Cycle  
Banks B, C  
NOTE 1: Defined as skeꢁ betꢁeen outputs at the same supply voltages and ꢁith equal load conditions.  
Measured at VDDOB, C/2.  
NOTE 2: This parameter is defined in accordance ꢁith JEDEC Standard 65.  
NOTE 3: Defined as skeꢁ ꢁithin a bank of outputs at the same supply voltage and ꢁith equal load conditions.  
IDT™ / ICS™ 0.7V HCSL/LVCMOS FREQUENCY SYNTHESIZER  
7
ICS841S012BKI REV. A MAY 1, 2008  
ICS841S012I  
CRYSTAL-TO-0.7V DIFFERENTIAL HCSL/LVCMOS FREQUENCY SYNTHESIZER  
PRELIMINARY  
PARAMETER MEASUREMENT INFORMATION  
3.3V 5ꢀ  
1.65V 5ꢀ  
3.3V 5ꢀ  
1.65V 5ꢀ  
Measurement  
Point  
VDD  
100Ω  
100Ω  
SCOPE  
33Ω  
VDD,  
VDDOB,  
VDDA  
VDDOC  
VDDA  
49.9Ω  
Qx  
2pF  
HCSL  
LVCMOS  
GND  
Measurement  
Point  
33Ω  
GND  
49.9Ω  
2pF  
475Ω  
IREF  
-1.65V 5ꢀ  
0V  
3.3V CORE/3.3V LVCMOS OUTPUT LOAD AC TEST CIRCUIT  
3.3V CORE/3.3V HCSL OUTPUT LOAD AC TEST CIRCUIT  
nQx  
Qx  
VDDOX  
Qx  
Qy  
2
nQy  
VDDOX  
2
Qy  
tsk(o)  
tsk(o)  
LVCMOS OUTPUT SKEW  
HCSL OUTPUT SKEW  
Rise Edge Rate  
Fall Edge Rate  
+150mV  
0.0V  
80ꢀ  
tF  
80ꢀ  
-150mV  
20ꢀ  
20ꢀ  
Q - nQ  
QC,  
QB0:QB6,  
tR  
REF_OUT0,  
REF_OUT1  
DIFFERENTIAL MEASUREMENT POINTS FOR RISE/FALL TIME  
8 ICS841S012BKI REV. A MAY 1, 2008  
LVCMOS OUTPUT RISE/FALL TIME  
IDT™ / ICS™ 0.7V HCSL/LVCMOS FREQUENCY SYNTHESIZER  
ICS841S012I  
CRYSTAL-TO-0.7V DIFFERENTIAL HCSL/LVCMOS FREQUENCY SYNTHESIZER  
PRELIMINARY  
PARAMETER MEASUREMENT INFORMATION, CONTINUED  
VOH  
VDDOX  
2
Qx:Qx  
VREF  
VOL  
VDDOX  
2
1σ contains 68.26ꢀ of all measurements  
2σ contains 95.4ꢀ of all measurements  
Qx:Qx  
3σ contains 99.73ꢀ of all measurements  
4σ contains 99.99366ꢀ of all measurements  
6σ contains (100-1.973x10-7)ꢀ of all measurements  
tsk(b)  
Histogram  
Reference Point  
(Trigger Edge)  
Mean Period  
(First edge after trigger)  
(where X = Bank A or Bank B)  
RMS PERIOD JITTER  
BANK SKEW  
nQA0, nQA1  
QA0, QA1  
VDDO  
2
VDDO  
2
VDDO  
2
QC,  
QB0:QB6,  
REF_OUT0,  
➤
➤
➤
➤
tcycle n  
tcycle n+1  
➤
➤
tcycle n  
tcycle n+1  
➤
➤
REF_OUT1  
tjit(cc) = tcycle n – tcycle n+1  
tjit(cc) = tcycle n – tcycle n+1  
1000 Cycles  
1000 Cycles  
LVCMOS CYCLE-TO-CYCLE JITTER  
DIFFERENTIAL CYCLE-TO-CYCLE JITTER  
Clock Period (Differential)  
Positive Duty  
Cycle (Differential)  
Negative Duty  
Cycle (Differential)  
VDDOX  
2
QC,  
0.0V  
QB0:QB6,  
REF_OUT0,  
REF_OUT1  
tPW  
tPERIOD  
Q - nQ  
tPW  
x 100ꢀ  
odc =  
tPERIOD  
LVCMOS OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD  
DIFFERENTIAL MEASUREMENT POINTS FOR DUTY CYCLE/PERIOD  
9 ICS841S012BKI REV. A MAY 1, 2008  
IDT™ / ICS™ 0.7V HCSL/LVCMOS FREQUENCY SYNTHESIZER  
ICS841S012I  
CRYSTAL-TO-0.7V DIFFERENTIAL HCSL/LVCMOS FREQUENCY SYNTHESIZER  
PRELIMINARY  
PARAMETER MEASUREMENT INFORMATION, CONTINUED  
nQ  
VCROSS_DELTA = 140mV  
Q
SE MEASUREMENT POINTS FOR DELTA CROSS POINT  
IDT™ / ICS™ 0.7V HCSL/LVCMOS FREQUENCY SYNTHESIZER  
10  
ICS841S012BKI REV. A MAY 1, 2008  
ICS841S012I  
CRYSTAL-TO-0.7V DIFFERENTIAL HCSL/LVCMOS FREQUENCY SYNTHESIZER  
PRELIMINARY  
APPLICATION INFORMATION  
POWER SUPPLY FILTERING TECHNIQUES  
As in any high speed analog circuitry, the poꢁer supply pins are  
vulnerable to random noise. To achieve optimum jitter perfor-  
mance, poꢁer supply isolation is required.The ICS841S012I pro-  
vides separate poꢁer supplies to isolate any high sꢁitching noise  
from the outputs to the internal PLL. VDD, VDDA, VDDOB, and VDDOC  
should be individually connected to the poꢁer supply  
plane through vias, and 0.01µF bypass capacitors should be used  
for each pin. Figure 1 illustrates this for a generic VDD pin and  
also shoꢁs that VDDA requires that an additional10Ω resistor  
along ꢁith a 10µF bypass capacitor be connected to the VDDA pin.  
3.3V  
VDD  
.01μF  
.01μF  
10Ω  
VDDA  
10μF  
FIGURE 1. POWER SUPPLY FILTERING  
The 10Ω resistor can also be replaced by a ferrite bead.  
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS  
INPUTS:  
OUTPUTS:  
LVCMOS OUTPUTS  
CRYSTAL INPUTS  
For applications not requiring the use of the crystal oscillator  
input, both XTAL_IN and XTAL_OUT can be left floating. Though  
not required, but for additional protection, a 1kΩ resistor can be  
tied from XTAL_IN to ground.  
All unused LVCMOS output can be left floating. We recommend  
that there is no trace attached.  
DIFFERENTIAL OUTPUT  
All unused differential outputs can be left floating.We recommend  
that there is no trace attached. Both sides of the differential output  
pair should either be left floating or terminated.  
REF_IN INPUT  
For applications not requiring the use of the reference clock,  
it can be left floating. Though not required, but for additional  
protection, a 1kΩ resistor can be tied from the REF_IN to ground.  
LVCMOS CONTROL PINS  
All control pins have internal pull-ups or pull-doꢁns; additional  
resistance is not required but can be added for additional  
protection. A 1kΩ resistor can be used.  
IDT™ / ICS™ 0.7V HCSL/LVCMOS FREQUENCY SYNTHESIZER  
11  
ICS841S012BKI REV. A MAY 1, 2008  
ICS841S012I  
CRYSTAL-TO-0.7V DIFFERENTIAL HCSL/LVCMOS FREQUENCY SYNTHESIZER  
PRELIMINARY  
CRYSTAL INPUT INTERFACE  
The ICS841S012I has been characterized ꢁith 18pF parallel  
resonant crystals. The capacitor values shoꢁn in Figure 2 beloꢁ  
ꢁere determined using a 25MHz, 18pF parallel resonant crystal  
and ꢁere chosen to minimize the ppm error.  
XTAL_IN  
C1  
X1  
Crystal  
XTAL_OUT  
C2  
FIGURE 2. CRYSTAL INPUt INTERFACE  
LVCMOS TO XTAL INTERFACE  
The XTAL_IN input can accept a single-ended LVCMOS signal  
through an AC coupling capacitor. A general interface diagram is  
shoꢁn in Figure 3. The XTAL_OUT pin can be left floating. The  
input edge rate can be as sloꢁ as 10ns. For LVCMOS inputs, it is  
recommended that the amplitude be reduced from full sꢁing to  
half sꢁing in order to prevent signal interference ꢁith the poꢁer  
rail and to reduce noise.This configuration requires that the output  
impedance of the driver (Ro) plus the series resistance (Rs) equals  
the transmission line impedance.In addition, matched termination  
at the crystal input ꢁill attenuate the signal in half. This can be  
done in one of tꢁo ꢁays. First, R1 and R2 in parallel should equal  
the transmission line impedance. For most 50Ω applications, R1  
and R2 can be 100Ω.This can also be accomplished by removing  
R1 and making R2 50Ω.  
VDD  
VDD  
R1  
.1uf  
Ro  
Rs  
Zo = 50  
XTAL_I N  
R2  
Zo = Ro + Rs  
XTAL_OUT  
FIGURE 3. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE  
IDT™ / ICS™ 0.7V HCSL/LVCMOS FREQUENCY SYNTHESIZER  
12  
ICS841S012BKI REV. A MAY 1, 2008  
ICS841S012I  
CRYSTAL-TO-0.7V DIFFERENTIAL HCSL/LVCMOS FREQUENCY SYNTHESIZER  
PRELIMINARY  
VFQFN EPADTHERMAL RELEASE PATH  
In order to maximize both the removal of heat from the package  
and the electrical performance, a land pattern must be  
incorporated on the Printed Circuit Board (PCB) ꢁithin the footprint  
of the package corresponding to the exposed metal pad or  
exposed heat slug on the package, as shoꢁn in Figure 4. The  
solderable area on the PCB, as defined by the solder mask, should  
be at least the same size/shape as the exposed pad/slug area on  
the package to maximize the thermal/electrical performance.  
Sufficient clearance should be designed on the PCB betꢁeen the  
outer edges of the land pattern and the inner edges of pad pattern  
for the leads to avoid any shorts.  
are application specific and dependent upon the package poꢁer  
dissipation as ꢁell as electrical conductivity requirements. Thus,  
thermal and electrical analysis and/or testing are recommended  
to determine the minimum number needed. Maximum thermal  
and electrical performance is achieved ꢁhen an array of vias is  
incorporated in the land pattern. It is recommended to use as  
many vias connected to ground as possible. It is also  
recommended that the via diameter should be 12 to 13mils (0.30  
to 0.33mm) ꢁith 1oz copper via barrel plating. This is desirable to  
avoid any solder ꢁicking inside the via during the soldering process  
ꢁhich may result in voids in solder betꢁeen the exposed pad/  
slug and the thermal land. Precautions should be taken to  
eliminate any solder voids betꢁeen the exposed heat slug and  
the land pattern. Note: These recommendations are to be used  
as a guideline only. For further information, refer to the Application  
Note on the Surface Mount Assembly of Amkor’s Thermally/  
Electrically Enhance Leadfame Base Package, Amkor Technology.  
While the land pattern on the PCB provides a means of heat  
transfer and electrical grounding from the package to the board  
through a solder joint, thermal vias are necessary to effectively  
conduct from the surface of the PCB to the ground plane(s). The  
land pattern must be connected to ground through these vias.  
The vias act as “heat pipes”. The number of vias (i.e.“heat pipes”)  
SOLDER  
SOLDER  
PIN  
PIN  
EXPOSED HEAT SLUG  
PIN PAD  
GROUND PLANE  
LAND PATTERN  
(GROUND PAD)  
PIN PAD  
THERMAL VIA  
FIGURE 4. P.C.ASSEMBLY FOR EXPOSED PAD THERMAL RELEASE PATH –SIDE VIEW (DRAWING NOT TO SCALE)  
IDT™ / ICS™ 0.7V HCSL/LVCMOS FREQUENCY SYNTHESIZER  
13  
ICS841S012BKI REV. A MAY 1, 2008  
ICS841S012I  
CRYSTAL-TO-0.7V DIFFERENTIAL HCSL/LVCMOS FREQUENCY SYNTHESIZER  
PRELIMINARY  
RECOMMENDEDT ERMINATION  
Figure 5A is the recommended termination for applications  
ꢁhich require the receiver and driver to be on a separate PCB.  
All traces should be 50Ù impedance.  
FIGURE 5A. RECOMMENDED TERMINATION  
Figure 5B is the recommended termination for applications  
ꢁhich require a point to point connection and contain the  
driver and receiver on the same PCB. All traces should all be  
50Ù impedance.  
FIGURE 5B. RECOMMENDED TERMINATION  
IDT™ / ICS™ 0.7V HCSL/LVCMOS FREQUENCY SYNTHESIZER  
14  
ICS841S012BKI REV. A MAY 1, 2008  
ICS841S012I  
CRYSTAL-TO-0.7V DIFFERENTIAL HCSL/LVCMOS FREQUENCY SYNTHESIZER  
PRELIMINARY  
POWER CONSIDERATIONS  
This section provides information on poꢁer dissipation and junction temperature for the ICS841S012I.  
Equations and example calculations are also provided.  
1. Poꢁer Dissipation.  
The total poꢁer dissipation for the ICS841S012I is the sum of the core poꢁer plus the poꢁer dissipated in the load(s).  
The folloꢁing is the poꢁer dissipation for VDD = 3.3V + 5ꢀ = 3.465V, ꢁhich gives ꢁorst case results.  
Core and HCSL Output Power Dissipation  
•
Poꢁer (core) = VDD_MAX * (IDD + IDDA ) = 3.465V * (250mA + 20mA) = 935.6mW  
Poꢁer (HCSL) = 44.5mW/Load Output Pair  
If all outputs are loaded, the total poꢁer is 2 * 44.5mW = 89mW  
LVCMOS Output Power Dissipation, ROUT = 15Ω  
•
•
•
•
Output Impedance ROUT Poꢁer Dissipation due to Loading 50Ω to VDDO/2  
Output Current IOUT = VDDO_MAX / [2 * (50Ω + ROUT)] = 3.465V / [2 * (50Ω + 15Ω)] = 26.7mA  
Poꢁer Dissipation on the ROUT per LVCMOS output  
2
Poꢁer (ROUT) = ROUT * (IOUT  
)
= 15Ω * (26.7mA)2 = 10.7mW per output  
Total Poꢁer Dissipation on the ROUT  
Total Power (ROUT = 15Ω) = 10.7mW * 7 = 74.9mW  
Dynamic Poꢁer Dissipation at 200MHz  
2
Poꢁer (200MHz) = CPD * Frequency * (VDDO  
)
= 9pF * 200MHz * (3.465V)2 = 21.6mW per output  
Total Power (200MHz) = 21.6mW * 7 = 151.2mW  
LVCMOS Output Power Dissipation, ROUT = 20Ω  
•
•
•
•
Output Impedance ROUT Poꢁer Dissipation due to Loading 50Ω to VDDO/2  
Output Current IOUT = VDDO_MAX / [2 * (50Ω + ROUT)] = 3.465V / [2 * (50Ω + 20Ω)] = 24.75mA  
Poꢁer Dissipation on the ROUT per LVCMOS output  
2
Poꢁer (ROUT) = ROUT * (IOUT  
)
= 20Ω * (24.75mA)2 = 12.3mW per output  
Total Poꢁer Dissipation on the ROUT  
Total Power (ROUT = 20Ω) = 12.3mW * 2 = 24.6mW  
Dynamic Poꢁer Dissipation at 25MHz  
2
Poꢁer (25MHz) = CPD * Frequency * (VDDO  
)
= 9pF * 25MHz * (3.465V)2 = 2.7mW per output  
Total Power (25MHz) = 2.7mW * 2 = 5.4mW  
Total Power Dissipation  
•
Total Power  
= Poꢁer (core) + Poꢁer (HCSL) + Total Poꢁer (ROUT= 15Ω) + Total Poꢁer (200MHz) + Total Poꢁer (ROUT= 20Ω) +  
Total Poꢁer (25MHz)  
= 935.6mW + 89mW + 74.9mW + 151.2mW + 24.6mW + 5.4mW  
= 1280.7mW  
IDT™ / ICS™ 0.7V HCSL/LVCMOS FREQUENCY SYNTHESIZER  
15  
ICS841S012BKI REV. A MAY 1, 2008  
ICS841S012I  
CRYSTAL-TO-0.7V DIFFERENTIAL HCSL/LVCMOS FREQUENCY SYNTHESIZER  
PRELIMINARY  
2. Junction Temperature.  
Junction temperature, Tj, is the temperature at the junction of the bond ꢁire and bond pad and directly affects the reliability  
of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.  
The equation for Tj is as folloꢁs: Tj = θJA * Pd_total + TA  
Tj = Junction Temperature  
θJA = Junction-to-Ambient Thermal Resistance  
Pd_total = Total Device Poꢁer Dissipation (example calculation is in section 1 above)  
TA = Ambient Temperature  
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used.  
Assuming 1 meter per second air floꢁ and a multi-layer board, the appropriate value is 27.5°C/W per Table 7.  
Therefore, Tj for an ambient temperature of 85°C ꢁith all outputs sꢁitching is:  
85°C + 1.281W * 27.5°C/W = 120.2°C. This is beloꢁ the limit of 125°C.  
This calculation is only an example. Tj ꢁill obviously vary depending on the number of loaded outputs, supply voltage, air  
floꢁ, and the type of board (single layer or multi-layer).  
TABLE 7. THERMAL RESISTANCE θJA FOR 56 LEAD VFQFN, FORCED CONVECTION  
θJA by Velocity (Meters per second)  
0
1
2.5  
Multi-Layer PCB, JEDEC Standard Test Boards  
31.4°C/W  
27.5°C/W  
24.6°C/W  
IDT™ / ICS™ 0.7V HCSL/LVCMOS FREQUENCY SYNTHESIZER  
16  
ICS841S012BKI REV. A MAY 1, 2008  
ICS841S012I  
CRYSTAL-TO-0.7V DIFFERENTIAL HCSL/LVCMOS FREQUENCY SYNTHESIZER  
PRELIMINARY  
3. Calculations and Equations.  
The purpose of this section is to calculate poꢁer dissipation on the IC per HCSL output pair.  
HCSL output driver circuit and termination are shoꢁn in Figure 6.  
V
DD  
IOUT = 17mA  
VOUT  
RREF  
=
475Ω  
1ꢀ  
RL  
50Ω  
IC  
FIGURE 6. HCSL DRIVER CIRCUIT AND TERMINATION  
HCSL is a current steering output ꢁhich sources a maximum of 17mA of current per output. To calculate ꢁorst case on-chip poꢁer  
dissipation, use the folloꢁing equations ꢁhich assume a 50Ω load to ground.  
The highest poꢁer dissipation occurs at maximum VDD  
Poꢁer = (VDD_MAX – VOUT ) * IOUT, since VOUT = IOUT * RL  
.
= (VDD_MAX – IOUT * RL) * IOUT  
= (3.465V – 17mA * 50Ω) * 17mA  
Total Poꢁer Dissipation per output pair = 44.5mW  
IDT™ / ICS™ 0.7V HCSL/LVCMOS FREQUENCY SYNTHESIZER  
17  
ICS841S012BKI REV. A MAY 1, 2008  
ICS841S012I  
CRYSTAL-TO-0.7V DIFFERENTIAL HCSL/LVCMOS FREQUENCY SYNTHESIZER  
PRELIMINARY  
RELIABILITY INFORMATION  
TABLE 8. θJAVS. AIR FLOW TABLE FOR 56 LEAD VFQFN  
θJA by Velocity (Meters per second)  
0
1
2.5  
Multi-Layer PCB, JEDEC Standard Test Boards  
31.4°C/W  
27.5°C/W  
24.6°C/W  
TRANSISTOR COUNT  
The transistor count for ICS841S012I is: 11,537  
IDT™ / ICS™ 0.7V HCSL/LVCMOS FREQUENCY SYNTHESIZER  
18  
ICS841S012BKI REV. A MAY 1, 2008  
ICS841S012I  
CRYSTAL-TO-0.7V DIFFERENTIAL HCSL/LVCMOS FREQUENCY SYNTHESIZER  
PRELIMINARY  
PACKAGE OUTLINE - K SUFFIX FOR 56 LEAD VFQFN  
(Ref.)  
N & N  
Seating Plane  
(N -1)x e  
(Ref.)  
Even  
A1  
IndexArea  
L
A3  
E2  
e
2
N
N
(Ty p.)  
If N & N  
are Even  
Anvil  
Singulation  
1
2
(N -1)x e  
(Ref.)  
OR  
E2  
2
TopView  
b
e
Thermal  
Base  
A
(Ref.)  
D2  
D
N & N  
Odd  
2
0. 08  
C
Chamfer 4x  
0.6 x 0.6 max  
OPTIONAL  
D2  
C
NOTE: The folloꢁing package mechanical draꢁing is a generic  
draꢁing that applies to any pin count VFQFN package.This draꢁ-  
ing is not intended to convey the actual pin count or pin layout of  
this device.The pin count and pinout are shoꢁn on the front page.  
The package dimensions are in Table 8 beloꢁ.  
TABLE 9. PACKAGE DIMENSIONS  
JEDEC VARIATION  
ALL DIMENSIONS IN MILLIMETERS  
SYMBOL  
MINIMUM  
MAXIMUM  
N
A
56  
0.80  
0
1.0  
A1  
A3  
b
0.05  
0.25 Reference  
0.18  
0.30  
e
0.50 BASIC  
ND  
NE  
D
14  
14  
8.0  
D2  
E
4.35  
4.65  
8.0  
E2  
L
5.05  
0.3  
5.35  
0.55  
Reference Document: JEDEC Publication 95, MO-220  
IDT™ / ICS™ 0.7V HCSL/LVCMOS FREQUENCY SYNTHESIZER  
19  
ICS841S012BKI REV. A MAY 1, 2008  
ICS841S012I  
CRYSTAL-TO-0.7V DIFFERENTIAL HCSL/LVCMOS FREQUENCY SYNTHESIZER  
PRELIMINARY  
TABLE 10. ORDERING INFORMATION  
Part/Order Number  
841S012BKI  
Marking  
TBD  
Package  
Shipping Packaging Temperature  
56 lead VFQFN  
tray  
-40°C to 85°C  
841S012BKIT  
TBD  
56 lead VFQFN  
1000 tape & reel  
tray  
-40°C to 85°C  
-40°C to 85°C  
-40°C to 85°C  
841S012BKILF  
841S012BKILFT  
ICS841S012BIL  
ICS841S012BIL  
56 lead "Lead-Free" VFQFN  
56 lead "Lead-Free" VFQFN  
1000 tape & reel  
NOTE: Parts that are ordered ꢁith an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.  
While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology, Incorporated (IDT) assumes no responsibility for either its use or for  
infringement of any patents or other rights of third parties, ꢁhich ꢁould result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and  
industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended ꢁithout additional processing by IDT. IDT  
reserves the right to change any circuitry or specifications ꢁithout notice. IDT does not authorize or ꢁarrant any IDT product for use in life support devices or critical medical instruments.  
IDT™ / ICS™ 0.7V HCSL/LVCMOS FREQUENCY SYNTHESIZER  
20  
ICS841S012BKI REV. A MAY 1, 2008  
ICS841S012I  
CRYSTAL-TO-0.7V DIFFERENTIAL HCSL/LVCMOS FREQUENCY SYNTHESIZER  
PRELIMINARY  
Innovate with IDT and accelerate your future networks. Contact:  
www.IDT.com  
For Sales  
For Tech Support  
netcom@idt.com  
Corporate Headquarters  
Integrated Device Technology, Inc.  
6024 Silver Creek Valley Road  
San Jose, CA 95138  
800-345-7015 (inside USA)  
+408-284-8200 (outside USA)  
Fax: 408-284-2775  
+480-763-2056  
ꢁꢁꢁ.IDT.com/go/contactIDT  
United States  
800-345-7015 (inside USA)  
+408-284-8200 (outside USA)  
© 2008 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change ꢁithout notice. IDT, the IDT logo, ICS and HiPerClockS are trademarks  
of Integrated Device Technology, Inc. Accelerated Thinking is a service mark of Integrated Device Technology, Inc. All other brands, product names and marks are or may be  
trademarks or registered trademarks used to identify products or services of their respective oꢁners.  
Printed in USA  

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