IDT70T15L25PFG中文资料_数据手册_规格书

PRELIMINARY

IDT70T16/5L

HIGH-SPEED 2.5V

16/8K X 9 DUAL-PORT

STATIC RAM

ꢀeatures

◆

True Dual-Ported memory cells which allow simultaneous

reads of the same memory location

High-speed access

M/S = VIH for BUSY output flag on Master

M/S = VIL for BUSY input on Slave

Busy and Interrupt Flag

On-chip port arbitration logic

◆

– Commercial:20/25ns(max.)

– Industrial:25ns (max.)

Full on-chip hardware support of semaphore signaling

between ports

Low-power operation

◆

– IDT70T16/5L

Fully asynchronous operation from either port

LVTTL-compatible, single 2.5V (±100mV) power supply

Available in an 80-pin TQFP and 100-pin fpBGA

Industrial temperature range (–40°C to +85°C) is available

for selected speeds

Active:200mW(typ.)

Standby:600µW(typ.)

IDT70T16/5 easily expands data bus width to 18 bits or

◆

more using the Master/Slave select when cascading more

than one device

ꢀunctionalBlockDiagram

OEL

OER

CER

CEL

R/

R

W

R/WL

I/O0L- I/O8L

I/O0R-I/O8R

I/O

Control

(2,3)

BUSYL

BUSYR

(1)

A13R

A13L

Address

Decoder

MEMORY

ARRAY

Address

Decoder

A0R

A0L

14

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

CEL

OEL

CER

OER

R/WR

R/

L

W

SEML

SEMR

INTR

M/S

(3)

INTL

5663 drw 01

NOTES:

1. A¹³is a NC for IDT70T15.

2. (MASTER): BUSY is output; (SLAVE): BUSY is input.

3. BUSY outputs and INT outputs are non-tri-stated push-pull drivers.

AUGUST 2002

1

DSC 5663/1

PRELIMINARY

IDT70T16/5L

High-Speed 2.5V 16/8K x 9 Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

Description

reads or writes to any location in memory. An automatic power down

featurecontrolledbyCEpermitstheon-chipcircuitryofeachporttoenter

a very low standby power mode.

FabricatedusingIDT’sCMOShigh-performancetechnology,these

devices typicallyoperate ononly200mWofpower.

The IDT70T16/5 is a high-speed 16/8K x 9 Dual-Port Static RAM.

TheIDT70T16/5isdesignedtobeusedasstand-aloneDual-PortRAMs

orasacombinationMASTER/SLAVEDual-PortRAMfor18-bit-or-more

wider systems. Using the IDT MASTER/SLAVE Dual-Port RAM ap-

proachin18-bitorwidermemorysystemapplicationsresultsinfull-speed,

error-freeoperationwithouttheneedforadditionaldiscretelogic.

This device provides two independent ports with separate control,

address,andI/Opinsthatpermitindependent,asynchronousaccessfor

TheIDT70T16/5ispackagedinan80-pinTQFP(ThinQuadFlatpack)

and a 100-pin fpBGA (fine pitch Ball Grid array) .

PinConfigurations^(1,2,3,4)

07/11/02

INDEX

60

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

43

42

41

NC

1

2

NC

A5L

2L

I/O

4L

3L

A

3

I/O3L

I/O4L

A

4

A2L

5

I/O

5L

SS

V

A1L

6

A0L

I/O

6L

7L

7

IDT70T16/5PF

INTL

BUSYL

V^SS

8

I/O

(5)

PN80-1

V^DD

NC

9

10

11

12

13

14

15

16

17

18

19

20

80-Pin TQFP

M/S

SS

V

(6)

Top View

BUSYR

I/O0R

INT

R

1R

I/O

A

0R

2R

A1R

A2R

A3R

A4R

NC

V^DD

I/O3R

I/O4R

5R

6R

I/O

NC

,

5663 drw 02

NOTES:

1. A¹³is a NC for IDT70T15.

2. All V^DDpins must be connected to power supply.

3. All V^SSpins must be connected to ground supply.

4. Package body is approximately 1.18 in x 1.18 in x 0.16 in.

5. This package code is used to reference the package diagram.

6. This text does not imply orientation of Part-marking.

2

6.42

PRELIMINARY

IDT70T16/5L

High-Speed 2.5V 16/8K x 9 Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

PinConfigurations(con't.)^(1,2,3,4)

IDT70T16/5BF

BF100⁽⁵⁾

100-PinfpBGA

TopView⁽⁶⁾

08/14/02

A1

A2

A3

A6

A7

A8

A9

A4

A5

A10

6R

9R

12R

SS

R

W

A

V

NC R/

NC

SS

7R

6R

NC

V

I/O

B1

B2

B3

B6

B7

13R

B9

B4

B5

B8

B10

(1)

8R

5R

2R

0R

A

8R

I/O

NC

A

10R

A

R

OE

NC

I/O

NC

C1

C5

C6

C2

C3

C4

D4

C7

C8

C9

C10

3R

A

NC

A

4R

A

7R

CER

NC

NC I/O3R

D1

D2

D6

D9

D3

D5

D7

D8

D10

1R

A

INTR

5R

I/O

11R

SEM

R

1R

I/O

A

NC

E5

E6

E7

E8

E9

E10

E1

E2

E3

E4

SS

V

SS

V

4R

I/O

2R

I/O

0R

I/O

DD

BUSY

R

L

1L

A

V

M/

S

A

F7

F5

F6

F9

F10

F1

F2

F3

F8

F4

V

DD

SS BUSY

0L

A

V

DD

V

SS

I/O6L I/O7L

V

5L

I/O

NC

G1

G5

G2

G4

G6

G8

G9

G3

G7

G10

L

INT

3L

A

NC

SEM

L

3L

I/O

SS

V

6L

A

4L

I/O

NC

,

H7

H8

H9

H10

H5

H6

H3

H4

H1

H2

8L

2L

I/O

NC

NC I/O

CE

L

10L

11L

12L

NC

A

NC

2L

5L

A

J1

J2

J3

J4

J5

J6

J7

J8

J9

J10

(1)

13L

A

4L

A

8L

A

NC

WL

SS

V

R/

NC

1L

I/O

K6

K8

K10

K5

K7

K9

K2

K4

K1

K3

DD

V

0L

I/O

NC

9L

A

DD

V

OEL

NC

7L

A

56 63 drw 0 3

NOTES:

1. A¹³is a NC for IDT70T15.

2. All VDD pins must be connected to power supply.

3. All V^SSpins must be connected to ground.

4. BF-100 package body is approximately 10mm x 10mm x 1.4mm with 0.8mm ball pitch.

5. This package code is used to reference the package diagram.

6. This text does not indicate orientation of the actual part marking.

6.432

PRELIMINARY

IDT70T16/5L

High-Speed 2.5V 16/8K x 9 Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

PinNames

Left Port

Right Port

Names

CE^L

CE^R

Chip Enable

W^L

W^R

R/

Read/Write Enable

Output Enable

Address

OE^L

0L

OE^R

(1)

13L

0R

13R

A

- A

A

- A

0L

8L

0R

8R

I/O - I/O

SEM^R

INT^R

Data Input/Output

Semaphore Enable

Interrupt Flag

SEM^L

INT^L

BUSY^L

BUSY^R

S

Busy Flag

M/

Master or Slave Select

Power (2.5V)

DD

V

SS

V

Ground (0V)

5663 tbl 01

NOTE:

1. A¹³is a NC for IDT70T15.

Truth Table I: Non-Contention Read/Write Control

Inputs⁽¹⁾

Outputs

R/W

I/O^0-8

Mode

CE

H

L

OE

X

L

SEM

H

X

L

High-Z

DATA^IN

DATA^OUT

High-Z

Deselcted: Power-Down

Write to Memory

Read Memory

H

L

H

X

H

X

H

X

Outputs Disabled

5663 tbl 02

NOTE:

1.

Condition: A0L — A13L ≠ A0R — A13R

Truth Table II: Semaphore Read/Write Control⁽¹⁾

Inputs

Outputs

R/W

H

I/O^0-8

Mode

Read Semaphore Flag Data Out (I/O⁰- I/O⁸)

CE

H

OE

L

SEM

L

DATA^OUT

IN

DATA

0

H

↑

X

L

Write I/O into Semaphore Flag

____

L

X

L

Not Allowed

5663 tbl 03

NOTE:

1. There are eight semaphore flags written to via I/O⁰and read from all I/Os (I/O0-I/O8). These eight semaphores are addressed by A0 - A2.

4

6.42

PRELIMINARY

IDT70T16/5L

High-Speed 2.5V 16/8K x 9 Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

AbsoluteMaximumRatings⁽¹⁾

MaximumOperating

TemperatureandSupplyVoltage⁽¹⁾

Symbol

Rating

Comm ercial

Unit

V

& Indus trial

Grade

Ambient

Temperature

GND

V^DD

(2 )

TERM

Te rminal Voltag e

with Re s p e ct to GND

-0.5 to +3.6

-55 to +125

V

Commercial

0^OC to +70^OC

0V

2.5V 100mV

+

Te mp e rature Und e r Bias

^oC

T

BIAS^{(3 )}

STG

JN

OUT

Industrial

-40^OC to +85^OC

2.5V 100mV

+

T

S torage Te mp e rature

J unctio n Te mp e rature

DC Outp ut Curre nt

-65 to +150

+150

^oC

5663 tbl 05

NOTES:

T

1. This is the parameter T^A. This is the "instant on" case temperature.

I

50

mA

5663 tbl 04

NOTES:

1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may

cause permanent damage to the device. This is a stress rating only and

functional operation of the device at these or any other conditions above

those indicated in the operational sections of this specification is not implied.

Exposure to absolute maximum rating conditions for extended periods may

affect reliability.

RecommendedDCOperating

Conditions

2. V^TERMmust not exceed VDD+ 0.3V.

3. Ambient Temperature Under Bias. No AC Conditions. Chip Deselected.

Symbol

Parameter

Sup ply Vo ltage

Ground

Min.

Typ.

Max.

Unit

V

DD

SS

2.4

2.5

2.6

V

0

V

^DD+0.3^{(2 )}

0.7

V

____

V

IH

Inp ut Hig h Vo ltag e

Input Low Voltage

1.7

V

-0.3^{(1 )}

V

____

V

IL

5663 tbl 06

NOTES:

1. V^IL> -1.5V for pulse width less than 10ns.

2. V^TERMmust not exceed VDD + 0.3V.

Capacitance⁽¹⁾(TA = +25°C, f = 1.0MHz)

Symbol

Parameter

Input Capacitance

Output Capacitance

Conditions^{(2 )}

Max. Unit

C

IN

V^IN= 3dV

9

pF

C

OUT

V^OUT= 3dV

10

pF

5663 tbl 07

NOTES:

1. This parameter is determined by device characteristics but is not production

tested.

2. 3dV references the interpolated capacitance when the input and output signals

switch from 0V to 3V or from 3V to 0V .

DC Electrical Characteristics Over the

Operating Temperature and Supply Voltage Range (VDD = 2.5V ± 100mV)

70T16/5L

Symbol

Parameter

Input Leakage Curre nt^{(1 )}

Output Leakage Curre nt

Output Low Voltage

Test Conditions

Min.

Max.

Unit

µA

V

___

|ILI

|ILO

OL

|

V

DD = 2.6V, VIN = 0V to VDD

5

___

|

CE = VIH , VOUT = 0V to VDD

OL = +2mA

OH = -2mA

V

I

0.4

___

V

OH

Output High Voltage

I

2.0

V

5663 tbl 08

NOTE:

1. At V^DD< 2.0V, Input leakages are undefined.

6.452

PRELIMINARY

IDT70T16/5L

High-Speed 2.5V 16/8K x 9 Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range(VDD = 2.5V ± 100mV)

70T16/5L20

Com'l Only

70T16/5L25

Com'l

& Ind

Symbol

Parameter

Test Condition

Version

COM'L

Typ.^{(2 )}

Max.

Typ.^{(2 )}

Max.

Unit

I_DD

Dynamic Ope rating

Current

(Both Ports Active )

mA

L

80

140

70

100

7

130

160

17

CE = VIL, Outputs Disable d

SEM = VIH

____

(3 )

IND

f = fMAX

I

S B1

Standby Current

(Both Ports - TTL

Le ve l Inputs)

mA

COM'L

IND

12

20

CE

R

and CE

L

= VIH

L

= VIH

SEM

R

=

SEM

____

(3 )

12

25

f = fMAX

(1 )

I

S B2

Standby Current

(One Port - TTL

Le ve l Inputs)

COM'L

CE^"A"= VIL and CE^"B"= VIH

L

55

90

40

55

80

Active Port Outputs Disabled,

(3 )

f=fMAX

____

IND

----

100

SEM

R

=

L

SEM = VIH

I

S B3

Full Standby Current

Both Ports CE

L

and

mA

COM'L

L

0.05

2.5

0.05

0.2

40

2.5

5.0

80

(Both Ports

-

CE > V^DD- 0.2V,

IN > V^DD- 0.2V or

IN < 0.2V, f = 0^{(4 )}

> V^DD-0.2V

R

CMOS Leve l Inputs)

V

SEM

____

IND

R

=

SEM

L

I

S B4

Full Standby Current

(One Port -

CMOS Leve l Inputs)

CE^"A"< 0.2V and

COM'L

(1 )

55

90

CE^"B"> V - 0.2V

SEM

R

=

S^DE^DM

L

> V^DD-0.2V

V

IN > V^DD- 0.2V or VIN < 0.2V

____

IND

55

100

Active Port Outputs Disabled,

f = fMAX

(3 )

5663 tbl 09

NOTES:

1. Port "A" may be either left or right port. Port "B" is the opposite from port "A".

2. DD = 2.5V, TA = +25°C, and are not production tested. IDD dc = 85mA (typ.)

V

3. At f = f^MAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/tRC, and using “AC Test Conditions” of input

levels of GND to 3V.

4. f = 0 means no address or control lines change.

OutputLoadsand

AC Test Conditions

Input Pulse Levels

GND to 2.5V

3ns Max.

1.25V

50Ω

,

Input Rise/Fall Times

Input Timing Reference Levels

Output Reference Levels

Output Load

DATAOUT

1.25V

BUSY

INT

10pF / 5pF*

(Tester)

1.25V

Figures 1

5663 drw 04

5663 tbl 10

Figure 1. AC Output Test Load

*(For t^LZ, tHZ, tWZ, tOW)

Timing of Power-Up / Power-Down

CE

tPU

PD

t

CC

I

50%

SB

I

,

5663 drw 06

6

6.42

PRELIMINARY

IDT70T16/5L

High-Speed 2.5V 16/8K x 9 Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

AC Electrical Characteristics Over the

OperatingTemperatureandSupplyVoltageRange

70T16/5L20

Com'l Only

70T16/5L25

Com'l

& Ind

Symbol

Parameter

Min.

Max.

Min.

Max.

Unit

READ CYCLE

____

t

RC

AA

ACE

ABE

AOE

OH

LZ

HZ

PU

PD

SOP

SAA

Read Cycle Time

20

25

ns

____

t

Address Access Time

20

25

____

Chip Enable Access Time^{(3 )}

Byte Enable Access Time^{(3 )}

t

ns

Output Enable Access Time^{(3 )}

Output Hold from Address Change

Output Low-Z Time^(1,2)

t

12

13

____

t

3

____

t

3

____

Output High-Z Time ^(1,2)

t

12

15

____

Chip Enable to Power Up Time ^(1,2)

Chip Disable to Power Down Time ^(1,2)

t

0

____

t

20

25

____

t

Semaphore Flag Update Pulse (OE or SEM

)

10

____

Semaphore Address Access ^{(3 )}

t

20

25

ns

5663 tbl 11

NOTES:

1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure1).

2. This parameter is guaranteed by device characterization, but is not production tested.

3. To access RAM, CE = V^ILand SEM = VIH. To access semaphore, CE = VIH and SEM = VIL.

Waveform of Read Cycles⁽⁵⁾

tRC

ADDR

(4)

tAA

(4)

tACE

CE

(4)

tAOE

OE

R/W

(1)

t_OH

tLZ

VALID DATA⁽⁴⁾

DATAOUT

(2)

tHZ

BUSYOUT

(3,4)

5663 drw 05

tBDD

NOTES:

1. Timing depends on which signal is asserted last, OE or CE.

2. Timing depends on which signal is de-asserted first, CE or OE.

3. t^BDDdelay is required only in cases where the opposite port is completing a write operation to the same address location. For simultaneous read operations BUSY

has no relation to valid output data.

4. Start of valid data depends on which timing becomes effective last: t^AOE, tACE, tAA or tBDD.

5. SEM = V^IH.

6.472

PRELIMINARY

IDT70T16/5L

High-Speed 2.5V 16/8K x 9 Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

AC Electrical Characteristics Over the

OperatingTemperatureandSupplyVoltage

70T16/5L20

Com'l Only

70T16/5L25

Com'l

& Ind

Symbol

Parameter

Min.

Max.

Min.

Max.

Unit

WRITE CYCLE

____

t

WC

EW

AW

AS

WP

WR

DW

HZ

DH

WZ

OW

SWRD

SPS

Write Cycle Time

20

15

0

25

20

0

ns

t

Chip Enable to End-of-Write⁽³⁾

Address Valid to End-of-Write

Addre ss Set-up Time ⁽³⁾

Write Pulse Width

t

15

0

20

0

t

Write Recovery Time

Data Valid to End-of-Write

Output High-Z Time^(1,2)

Data Hold Time⁽⁴⁾

t

15

____

t

12

15

____

t

0

Write Enable to Output in High-Z^(1,2)

Output Active from End-of-Write ^{(1, 2 ,4 )}

SEM Flag Write to Re ad Time

12

15

____

t

____

t

0

5

0

5

____

t

ns

SEM Flag Contention Window

5663 tbl 12

NOTES:

1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 1).

2. This parameter is guaranteed by device characterization, but is not production tested.

3. To access RAM, CE = V^ILand SEM = VIH. To access semaphore, CE = VIH and SEM = VIL. Either condition must be valid for the entire tEW time.

4. The specification for t^DHmust be met by the device supplying write data to the SRAM under all operating conditions. Although tDH and tOW values will vary over

voltage and temperature, the actual t^DHwill always be smaller than the actual tOW.

8

6.42

PRELIMINARY

IDT70T16/5L

High-Speed 2.5V 16/8K x 9 Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

Timing Waveform of Write Cycle No. 1, R/W Controlled Timing^(1,5,8)

tWC

ADDRESS

(7)

tHZ

OE

tAW

CE or SEM⁽⁹⁾

(3)

(2)

(6)

tWR

t_AS

t_WP

R/W

(7)

tLZ

tOW

tWZ

(4)

OUT

DATA

tDW

tDH

DATAIN

5663 drw 07

Timing Waveform of Write Cycle No. 2,CE Controlled Timing^(1,5)

t

WC

ADDRESS

AW

t

CE or SEM⁽⁹⁾

(6)

AS

t

EW⁽²⁾

t

WR⁽³⁾

t

R/W

t

DW

t

DH

DATAIN

5663 drw 08

NOTES:

1. R/W or CE must be HIGH during all address transitions.

2. A write occurs during the overlap (t^EWor tWP) of a LOW CE and a LOW R/W for memory array writing cycle.

3. t^WRis measured from the earlier of CE or R/W (or SEM or R/W) going HIGH to the end of write cycle.

4. During this period, the I/O pins are in the output state and input signals must not be applied.

5. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.

6. Timing depends on which enable signal is asserted last, CE or R/W.

7. This parameter is guaranteed by device characterization but is not production tested. Transition is measured 0mV from steady state with the Output Test Load

(Figure 1).

8. If OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of t^WPor (tWZ + tDW) to allow the I/O drivers to turn off and data to be

placed on the bus for the required t^DW. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as

the specified t^WP.

9. To access RAM, CE = V^ILand SEM = VIH. To access Semaphore, CE = VIH and SEM = VIL. tEW must be met for either condition.

6.492

PRELIMINARY

IDT70T16/5L

High-Speed 2.5V 16/8K x 9 Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

Timing Waveform of Semaphore Read after Write Timing, Either Side⁽¹⁾

t

SAA

VALID ADDRESS

t

A -A

0 2

t

WR

AW

t

ACE

t

EW

SEM

t

OH

t

DW

t

SOP

DATAIN

VALID

DATAOUT

I/O

VALID⁽²⁾

t

AS

t

WP

t

DH

W

R/

AOE

t

SWRD

t

OE

Read Cycle

Write Cycle

5663 drw 09

NOTES:

1. CE = VIH for the duration of the above timing (both write and read cycle).

2. “DATA^OUTVALID” represents all I/O's (I/O0-I/O8) equal to the semaphore value.

Timing Waveform of Semaphore Write Condition^(1,3,4)

A_0"A"-A_{2 "A"}

MATCH

SIDE⁽²⁾"A"

R/

W

"A"

SEM"A"

t_SPS

A

0"B"-A2 "B"

MATCH

SIDE⁽²⁾

"B"

R/

W"B"

SEM"B"

5663 drw 10

NOTES:

1. D^OR= DOL =VIH, CER = CEL =VIH.

2. All timing is the same for left and right ports. Port“A” may be either left or right port. “B” is the opposite port from “A”.

3. This parameter is measured from R/W^“A”or SEM“A” going HIGH to R/W“B” or SEM“B” going HIGH.

4. If t^SPSis not satisfied, there is no guarantee which side will obtain the semaphore flag.

10

6.42

PRELIMINARY

IDT70T16/5L

High-Speed 2.5V 16/8K x 9 Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

AC Electrical Characteristics Over the

OperatingTemperatureandSupplyVoltageRange

70T16/5L20

Com'l Only

70T16/5L25

Com'l

& Ind

Symbol

Parameter

Min.

Max.

Min.

Max.

Unit

BUSY TIMING (M/S = VIH)

____

t

BAA

BDA

BAC

BDC

APS

BDD

WH

20

ns

BUSY Access Time from Address Match

BUSY Disable Time from Address Not Matched

BUSY Access Time from Chip Enable LOW

BUSY Disable Time from Chip Enable HIGH

Arbitration Priority Set-up Time⁽²⁾

t

17

____

t

5

____

BUSY Disable to Valid Data⁽³⁾

t

30

(5)

____

t

Write Hold After BUSY

15

17

BUSY TIMING (M/S = VIL)

____

BUSY Input to Write⁽⁴⁾

t

WB

0

ns

(5)

t_WH

Write Hold After

15

17

BUSY

PORT-TO-PORT DELAY TIMING

____

t

WDD

Write Pulse to Data Delay⁽¹⁾

45

35

50

35

ns

t

DDD

Write Data Valid to Read Data Delay ⁽¹⁾

ns

5663 tbl 13

NOTES:

1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveformof Write with Port-to-Port Read and BUSY (M/S = V^IH)".

2. To ensure that the earlier of the two ports wins.

3. t^BDDis a calculated parameter and is the greater of 0, tWDD – tWP (actual) or tDDD – tDW (actual).

4. To ensure that the write cycle is inhibited on Port "B" during contention on Port "A".

5. To ensure that a write cycle is completed on Port "B" after contention on Port "A".

6. 'X' in part numbers indicates power rating (S or L).

Timing Waveform of Read with BUSY^(2,4,5)(M/S = VIH)

t

WC

MATCH

ADDR_"A"

t_WP

R/

W

"A"

t_DH

t_DW

VALID

DATA_{IN "A"}

(1)

t_APS

MATCH

ADDR"B"

t_BDD

t_BDA

BUSY"B"

t

WDD

DATA_{OUT "B"}

VALID

(3)

t_DDD

NOTES:

1. To ensure that the earlier of the two ports wins. t^APSis ignored for M/S=VIL.

2. CE^L= CER = VIL.

5663 drw 11

3. OE = V^ILfor the reading port.

4. If M/S=V^IL(SLAVE), BUSY is an input. Then for this example BUSY“A” = VIH and BUSY“B” input is shown above.

5. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from Port "A".

6.1412

PRELIMINARY

IDT70T16/5L

High-Speed 2.5V 16/8K x 9 Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

Timing Waveform of Write with BUSY⁽³⁾

tWP

R/ "A"

W

tWB

BUSY"B"

R/W"B"

(1)

tWH

(2)

5663 drw 12

NOTES:

1. t^WHmust be met for both BUSY input (SLAVE) and output (MASTER).

2. BUSY is asserted on port "B" blocking R/W^"B", until BUSY"B" goes HIGH.

3. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from Port "A".

Waveform of BUSY Arbitration Controlled by CE Timing⁽¹⁾(M/S = VIH)

ADDR

and

"A"

ADDRESSES MATCH

"B"

CE"A"

CE"B"

(2)

t

APS

t

BAC

t

BDC

BUSY"B"

5663 drw 13

Waveform of BUSY Arbitration Cycle Controlled by Address Match

Timing⁽¹⁾(M/S = VIH)

ADDR"A"

ADDR"B"

BUSY_"B"

ADDRESS "N"

(2)

t

APS

MATCHING ADDRESS "N"

BAA

t

BDA

t

5663 drw 14

NOTES:

1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.

2. If t^APSis not satisfied, the BUSY signal will be asserted on one side or another but there is no guarantee on which side BUSY will be asserted.

12

6.42

PRELIMINARY

IDT70T16/5L

High-Speed 2.5V 16/8K x 9 Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

AC Electrical Characteristics Over the

OperatingTemperatureandSupplyVoltageRange

70T16/5L25

Com'l

& Ind

70T16/5L20

Com'l Only

Symbol

Parameter

Min.

Max.

Min.

Max.

Unit

INTERRUPT TIMING

____

t

AS

Ad dre s s S e t-up Time

Write Re co ve ry Time

Inte rrup t S e t Tim e

0

ns

t_WR

0

____

t

IN S

20

____

t_{IN R}

Inte rrup t Re s e t Tim e

ns

5663 tbl 14

Waveform of Interrupt Timing⁽¹⁾

tWC

INTERRUPT SET ADDRESS ⁽²⁾

ADDR_"A"

(4)

(3)

tWR

t_AS

CE"A"

R/

W"A"

(3)

t_INS

INT"B"

5663 drw 15

t_RC

INTERRUPT CLEAR ADDRESS ⁽²⁾

ADDR_"B"

CE"B"

(3)

t_AS

OE"B"

(3)

t_INR

INT"B"

5663 drw 16

NOTES:

1. All timing is the same for left and right ports. Port “A” may be either the left or right port. Port “B” is the port opposite from “A”.

2. See Interrupt truth table.

3. Timing depends on which enable signal (CE or R/W) is asserted last.

4. Timing depends on which enable signal (CE or R/W) is de-asserted first.

6.1432

PRELIMINARY

IDT70T16/5L

High-Speed 2.5V 16/8K x 9 Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

Truth Table III Interrupt ꢀlag⁽¹⁾

Left Port

Right Port

R/W^L

L

A13L-A0L

3FFF⁽⁴⁾

X

R/W^R

X

A13R-A0R

X

Function

Set Right INT^RFlag

Reset Right INT^RFlag

Set Left INT^LFlag

CE^L

L

OE^L

X

INT^L

X

CE^R

X

OE^R

X

INT^R

(2)

L

(3)

X

L

3FFF⁽⁴⁾

3FFE⁽⁴⁾

X

H

(3)

X

L

X

(2)

X

L

3FFE⁽⁴⁾

H

X

Reset Left INT^LFlag

5663 tbl 15

NOTES:

1. Assumes BUSY^L= BUSYR = VIH.

2. If BUSY^L= VIL, then no change.

3. If BUSY^R= VIL, then no change.

4. A¹³is a NC for IDT70T15, therefore Interrupt Addresses are 1FFF and 1FFE.

Truth Table IV Address BUSY

Arbitration

Inputs

Outputs

(4 )

A^OL-A^13L

(1 )

A^OR-A^13R

NO MATCH

MATCH

Function

Normal

CE^L

CE^R

X

BUSY^L

BUSY^R

X

H

X

H

MATCH

H

(3)

L

MATCH

(2)

Write Inhibit

5663 tbl 16

NOTES:

1. Pins BUSYL and BUSYR are both outputs when the part is configured as a master. Both are inputs when configured as a slave. BUSYX outputs on the

IDT70T16/5 are push-pull, not open drain outputs. On slaves the BUSY^Xinput internally inhibits writes.

2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address

and enable inputs of this port. If t^APSis not met, either BUSYL or BUSYR = LOW will result. BUSYL and BUSYR outputs can not be LOW simultaneously.

3. Writes to the left port are internally ignored when BUSY^Loutputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored

when BUSY^Routputs are driving LOW regardless of actual logic level on the pin.

4. A¹³is a NC for IDT70T15. Address comparison will be for A0 - A12.

Truth Table V Example of Semaphore Procurement Sequence^(1,2,3)

Functions

D⁰- D⁸Left

D⁰- D⁸Right

Status

No Action

1

0

1

0

1

0

1

0

1

0

1

Semaphore free

Left Port Writes "0" to Semaphore

Right Port Writes "0" to Semaphore

Left Port Writes "1" to Semaphore

Left Port Writes "0" to Semaphore

Right Port Writes "1" to Semaphore

Left Port Writes "1" to Semaphore

Right Port Writes "0" to Semaphore

Right Port Writes "1" to Semaphore

Left Port Writes "0" to Semaphore

Left Port Writes "1" to Semaphore

NOTES:

Left port has semaphore token

No change. Right side has no write access to semaphore

Right port obtains semaphore token

No change. Left port has no write access to semaphore

Left port obtains semaphore token

Semaphore free

Right port has semaphore token

Semaphore free

Left port has semaphore token

Semaphore free

5663 tbl 17

1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70T16/5.

2. There are eight semaphore flags written to via I/O⁰and read from all I/Os (I/O0 - I/O8). These eight semaphores are addressed by A0 - A2.

e. CE = V^IH, SEM = VIL to access the semaphores. Refer to the semaphore Read/Write Truth Table.

14

6.42

PRELIMINARY

IDT70T16/5L

High-Speed 2.5V 16/8K x 9 Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

CE

MASTER

Dual Port

RAM

CE

SLAVE

Dual Port

RAM

BUSY

(R)

(L)

BUSY (L) BUSY

(R)

MASTER

Dual Port

RAM

CE

SLAVE

Dual Port

RAM

CE

BUSY (R)

BUSY (L)

BUSY (R)

BUSY (L)

5663 drw 17

Figure 3. Busy and chip enable routing for both width and depth expansion with IDT70T16/5 RAMs.

the BUSY pins HIGH. If desired, unintended write operations can be

ꢀunctionalDescription

prevented to a port by tying the BUSY pin for that port LOW.

The BUSY outputs on the IDT70T16/5 RAM in master mode, are

push-pulltypeoutputs anddonotrequirepullupresistors tooperate.If

theseRAMsarebeingexpandedindepth,thentheBUSYindicationfor

the resulting array requires the use of an external AND gate.

TheIDT70T16/5provides twoports withseparatecontrol, address

and I/O pins that permit independent access for reads or writes to any

location in memory. The IDT70T16/5 has an automatic power down

featurecontrolledbyCE.TheCEcontrolson-chippowerdowncircuitry

thatpermitstherespectiveporttogointoastandbymodewhennotselected

(CE HIGH).Whenaportis enabled,access totheentirememoryarray

ispermitted.

WidthExpansionBusyLogic

Master/SlaveArrays

When expanding an IDT70T16/5 RAM array in width while using

BUSYlogic, one masterpartis usedtodecide whichside ofthe RAM

arraywillreceiveaBUSYindication,andtooutputthatindication.Any

number of slaves to be addressed in the same address range as the

masteruse the BUSYsignalas awriteinhibitsignal.Thus onthe

IDT70T16/5 RAM the BUSY pin is an output if the part is used as a

master (M/S pin = H), and the BUSY pin is an input if the part used as

a slave (M/S pin = L) as shown in Figure 3.

Iftwoormoremasterpartswereusedwhenexpandinginwidth,asplit

decisioncouldresultwithonemasterindicatingBUSYononesideofthe

arrayandanothermasterindicatingBUSYononeothersideofthearray.

Thiswouldinhibitthewriteoperationsfromoneportforpartofawordand

inhibitthewriteoperationsfromtheotherportfortheotherpartoftheword.

TheBUSYarbitration,onamaster,isbasedonthechipenableand

address signals only. Itignores whetheranaccess is a readorwrite. In

a master/slave array, bothaddress andchipenable mustbe validlong

enoughforaBUSYflagtobeoutputfromthemasterbeforetheactualwrite

pulsecanbeinitiatedwiththeR/Wsignal.Failuretoobservethistimingcan

resultina glitchedinternalwrite inhibitsignalandcorrupteddata inthe

slave.

Interrupts

Iftheuserchoosestheinterruptfunction,amemorylocation(mail

box or message center) is assigned to each port. The left port

interruptflag(INT^L)is assertedwhentherightportwrites tomemory

location 3FFE where a write is defined as the CE = R/W = VIL per

TruthTable III. The leftportclears the interruptbyanaddress location

3FFE access when CE^R=OER =VIL, R/W is a "don't care". Likewise,

the rightportinterruptflag(INTR)is assertedwhenthe left portwrites

to memory location 3FFF(1FFE or 1FFF for IDT70T15) and to clear

theinterrupt flag(INTR),theright portmustaccessmemorylocation

3FFF. The message (9 bits) at 3FFE or 3FFF(1FFE or 1FFF for

IDT70T15) is user-defined since it is in an addressable SRAM

location.Iftheinterruptfunctionisnotused,addresslocations3FFE

and 3FFF (1FFE or 1FFF for IDT70T15) are not used as mail boxes

butare still partofthe randomaccess memory. RefertoTruthTable

IIIfortheinterruptoperation.

BusyLogic

BusyLogicprovidesahardwareindicationthatbothportsoftheRAM

haveaccessedthesamelocationatthesametime.Italsoallowsoneofthe

twoaccessestoproceedandsignalstheothersidethattheRAMis“busy”.

TheBUSYpincanthenbeusedtostalltheaccessuntiltheoperationon

theothersideiscompleted.Ifawriteoperationhasbeenattemptedfrom

thesidethatreceivesaBUSYindication,thewritesignalisgatedinternally

topreventthewritefromproceeding.

TheuseofBUSYlogicisnotrequiredordesirableforallapplications.

InsomecasesitmaybeusefultologicallyORtheBUSYoutputstogether

anduse anyBUSYindicationas aninterruptsource toflagthe eventof

anillegalorillogicaloperation.IfthewriteinhibitfunctionofBUSYlogicis

notdesirable,theBUSYlogiccanbedisabledbyplacingthepartinslave

modewiththeM/Spin.OnceinslavemodetheBUSYpinoperatessolely

asawriteinhibitinputpin.Normaloperationcanbeprogrammedbytying

Semaphores

The IDT70T16/5are extremelyfastDual-Port16/8Kx9StaticRAMs

withanadditional8addresslocationsdedicatedtobinarysemaphoreflags.

TheseflagsalloweitherprocessorontheleftorrightsideoftheDual-Port

RAMtoclaimaprivilegeovertheotherprocessorforfunctionsdefinedby

thesystemdesigner’ssoftware.Asanexample,thesemaphorecanbe

usedbyoneprocessortoinhibittheotherfromaccessingaportionofthe

Dual-Port RAM or any other shared resource.

The Dual-PortRAMfeatures a fastaccess time, andbothports are

completelyindependentofeachother.Thismeansthattheactivityonthe

leftportinnowayslows theaccess timeoftherightport.Bothports are

6.1452

PRELIMINARY

IDT70T16/5L

High-Speed 2.5V 16/8K x 9 Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

iswrittenintoanunusedsemaphorelocation,thatflagwillbesettoazero

on that side and a one on the other side (see Truth Table V). That

semaphorecannowonlybemodifiedbythesideshowingthezero.When

aoneiswrittenintothesamelocationfromthesameside,theflagwillbe

settoaoneforbothsides(unlessasemaphorerequestfromtheotherside

ispending)andthencanbewrittentobybothsides.Thefactthattheside

which is able to write a zero into a semaphore subsequently locks out

writes from the other side is what makes semaphore flags useful in

interprocessorcommunications.(Athoroughdiscussionontheuseofthis

featurefollowsshortly.)Azerowrittenintothesamelocationfromtheother

side willbe storedinthe semaphore requestlatchforthatside untilthe

semaphoreisfreedbythefirstside.

Whenasemaphoreflagisread,itsvalueisspreadintoalldatabitsso

thataflagthatisaonereadsasaoneinalldatabitsandaflagcontaining

azeroreadsasallzeros.Thereadvalueislatchedintooneside’soutput

registerwhenthatside'ssemaphoreselect(SEM)andoutputenable(OE)

signalsgoactive.Thisservestodisallowthesemaphorefromchanging

stateinthemiddleofareadcycleduetoawritecyclefromtheotherside.

Becauseofthislatch,arepeatedreadofasemaphoreinatestloopmust

cause either signal (SEM or OE) to go inactive or the output will never

change.

AsequenceWRITE/READmustbeusedbythesemaphoreinorder

to guarantee that no system level contention will occur. A processor

requestsaccesstosharedresourcesbyattemptingtowriteazerointoa

semaphorelocation.Ifthesemaphoreisalreadyinuse,thesemaphore

requestlatchwillcontainazero,yetthesemaphoreflagwillappearasone,

afactwhichtheprocessorwillverifybythesubsequentread(seeTruth

TableV).Asanexample,assumeaprocessorwritesazerototheleftport

atafreesemaphorelocation.Onasubsequentread,theprocessorwill

verifythatithaswrittensuccessfullytothatlocationandwillassumecontrol

overtheresourceinquestion.Meanwhile,ifaprocessorontherightside

attempts towriteazerotothesamesemaphoreflagitwillfail,as willbe

verifiedbythefactthataonewillbereadfromthatsemaphoreontheright

side during subsequent read. Had a sequence of READ/WRITE been

used instead,systemcontentionproblemscouldhaveoccurredduring

the gap between the read and write cycles.

Itisimportanttonotethatafailedsemaphorerequestmustbefollowed

byeitherrepeatedreadsorbywritingaoneintothesamelocation.The

reasonforthisiseasilyunderstoodbylookingatthesimplelogicdiagram

ofthesemaphoreflaginFigure4.Twosemaphorerequestlatchesfeed

into a semaphore flag. Whichever latch is first to present a zero to the

semaphoreflagwillforceitssideofthesemaphoreflagLOWandtheother

sideHIGH.Thisconditionwillcontinueuntilaoneiswrittentothesame

semaphorerequestlatch.Shouldtheotherside’ssemaphorerequestlatch

havebeenwrittentoazerointhemeantime,thesemaphoreflagwillflip

overtotheothersideassoonasaoneiswrittenintothefirstside’srequest

latch.Thesecondside’sflagwillnowstayLOWuntilitssemaphorerequest

latchiswrittentoaone.Fromthisitiseasytounderstandthat,ifasemaphore

is requestedandthe processorwhichrequesteditnolongerneeds the

resource, the entire system can hang up until a one is written into that

semaphorerequestlatch.

identicalinfunctiontostandardCMOSStaticRAMandcanbereadfrom,

orwrittento,atthesametimewiththeonlypossibleconflictarisingfromthe

simultaneous writing of, or a simultaneous READ/WRITE of, a non-

semaphorelocation.Semaphoresareprotectedagainstsuchambiguous

situationsandmaybeusedbythesystemprogramtoavoidanyconflicts

inthenon-semaphoreportionoftheDual-PortRAM.Thesedeviceshave

anautomaticpower-downfeaturecontrolledbyCE,theDual-PortRAM

enable,andSEM,thesemaphoreenable.TheCEandSEMpinscontrol

on-chippowerdowncircuitrythatpermits the respective porttogointo

standbymodewhennotselected. Thisistheconditionwhichisshownin

Truth Table I where CE and SEM are both HIGH.

SystemswhichcanbestusetheIDT70T16/5containmultipleproces-

sorsorcontrollersandaretypicallyveryhigh-speedsystemswhichare

softwarecontrolledorsoftwareintensive.Thesesystemscanbenefitfrom

a performance increase offered by the IDT70T16/5's hardware sema-

phores,whichprovidealockoutmechanismwithoutrequiringcomplex

programming.

Softwarehandshakingbetweenprocessors offers themaximumin

systemflexibilitybypermittingsharedresourcestobeallocatedinvarying

configurations. The IDT70T16/5 does not use its semaphore flags to

control any resources through hardware, thus allowing the system

designertotalflexibilityinsystemarchitecture.

An advantage of using semaphores rather than the more common

methodsofhardwarearbitrationisthatwaitstatesareneverincurredin

either processor. This can prove to be a major advantage in very high-

speedsystems.

How the Semaphore ꢀlags Work

Thesemaphorelogicisasetofeightlatcheswhichareindependent

oftheDual-PortRAM.Theselatchescanbeusedtopassaflag,ortoken,

fromoneporttotheothertoindicatethatasharedresourceisinuse.The

semaphores provide a hardware assist for a use assignment method

called“TokenPassingAllocation.”Inthismethod,thestateofasemaphore

latchisusedasatokenindicatingthatsharedresourceisinuse.Iftheleft

processorwantstousethisresource,itrequeststhetokenbysettingthe

latch.Thisprocessorthenverifiesitssuccessinsettingthelatchbyreading

it. If it was successful, it proceeds to assume control over the shared

resource.Ifitwasnotsuccessfulinsettingthelatch,itdeterminesthatthe

rightsideprocessorhassetthelatchfirst, hasthetokenandisusingthe

sharedresource.Theleftprocessorcantheneitherrepeatedlyrequest

that semaphore’s status or remove its request for that semaphore to

performanothertaskandoccasionallyattemptagaintogaincontrolofthe

tokenviathesetandtestsequence.Oncetherightsidehasrelinquished

thetoken,theleftsideshouldsucceedingainingcontrol.

ThesemaphoreflagsareactiveLOW.Atokenisrequestedbywriting

azerointoasemaphorelatchandisreleasedwhenthesamesidewrites

aonetothatlatch.

TheeightsemaphoreflagsresidewithintheIDT70T16/5inaseparate

memoryspacefromtheDual-PortRAM.This addressspaceisaccessed

byplacingaLOWinputontheSEMpin(whichactsasachipselectforthe

semaphore flags) and using the other control pins (Address, OE, and

R/W)as theywouldbe usedinaccessinga standardstaticRAM. Each

oftheflagshasauniqueaddresswhichcanbeaccessedbyeitherside

throughaddresspinsA0–A2.Whenaccessingthesemaphores,noneof

theotheraddresspinshasanyeffect.

The criticalcase ofsemaphore timingis whenbothsides requesta

single token by attempting to write a zero into it at the same time. The

semaphorelogicisspeciallydesignedtoresolvethisproblem.Ifsimulta-

neousrequestsaremade,thelogicguaranteesthatonlyonesidereceives

thetoken.Ifonesideisearlierthantheotherinmakingtherequest,thefirst

Whenwritingtoasemaphore,onlydatapinD0 isused.Ifalowlevel

16

6.42

PRELIMINARY

IDT70T16/5L

High-Speed 2.5V 16/8K x 9 Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

sidetomaketherequestwillreceivethetoken.Ifbothrequestsarriveat

Once the left side was finished with its task, it would write a one to

thesametime,theassignmentwillbearbitrarilymadetooneportorthe Semaphore 0 and may then try to gain access to Semaphore 1. If

other. Semaphore1wasstilloccupiedbytherightside,theleftsidecouldundo

One caution that should be noted when using semaphores is that itssemaphorerequestandperformothertasksuntilitwasabletowrite,then

semaphoresalonedonotguaranteethataccesstoaresourceissecure. readazerointoSemaphore1.Iftherightprocessorperformsasimilartask

Aswithanypowerfulprogrammingtechnique,ifsemaphoresaremisused withSemaphore0,thisprotocolwouldallowthetwoprocessorstoswap

ormisinterpreted, a software errorcaneasilyhappen.

8Kblocks ofDual-PortRAMwitheachother.

Initializationofthesemaphoresisnotautomaticandmustbehandled

The blocks do not have to be any particular size and can even be

viatheinitializationprogramatpower-up.Sinceanysemaphorerequest variable, depending upon the complexity of the software using the

flagwhichcontainsazeromustberesettoaone,allsemaphoresonboth semaphoreflags.AlleightsemaphorescouldbeusedtodividetheDual-

sidesshouldhaveaonewrittenintothematinitializationfrombothsides PortRAMorothersharedresources intoeightparts. Semaphores can

to assure that they will be free when needed.

evenbeassigneddifferentmeaningsondifferentsidesratherthanbeing

given a common meaning as was shown in the example above.

Semaphores are a useful form of arbitration in systems like disk

interfaceswheretheCPUmustbelockedoutofasectionofmemoryduring

atransferandtheI/Odevicecannottolerateanywaitstates.Withtheuse

ofsemaphores,oncethetwodeviceshasdeterminedwhichmemoryarea

was“off-limits”totheCPU,boththeCPUandtheI/Odevicescouldaccess

theirassignedportionsofmemorycontinuouslywithoutanywaitstates.

Semaphoresarealsousefulinapplicationswherenomemory“WAIT”

stateisavailableononeorbothsides.Onceasemaphorehandshakehas

been performed, both processors can access their assigned RAM

segmentsatfullspeed.

Anotherapplicationisintheareaofcomplexdatastructures.Inthis

case,blockarbitrationisveryimportant.Forthisapplicationoneprocessor

mayberesponsibleforbuildingandupdatingadatastructure.Theother

processorthenreadsandinterpretsthatdatastructure.Iftheinterpreting

processorreadsanincompletedatastructure,amajorerrorconditionmay

exist.Therefore,somesortofarbitrationmustbeusedbetweenthetwo

differentprocessors.Thebuildingprocessorarbitratesfortheblock,locks

itandthenisabletogoinandupdatethedatastructure.Whentheupdate

is completed, the data structure block is released. This allows the

interpretingprocessortocomebackandreadthecompletedatastructure,

therebyguaranteeingaconsistentdatastructure.

UsingSemaphoresSomeExamples

Perhapsthesimplestapplicationofsemaphoresistheirapplicationas

resource markers forthe IDT70T16/5’s Dual-PortRAM. Saythe 16Kx

9RAMwastobedividedintotwo8Kx9blockswhichweretobededicated

atanyonetimetoservicingeithertheleftorrightport.Semaphore0could

be used to indicate the side which would control the lower section of

memory,andSemaphore1couldbedefinedastheindicatorfortheupper

sectionofmemory.

Totakearesource,inthis examplethelower8KofDual-PortRAM,

the processor on the left port could write and then read a zero in to

Semaphore0.Ifthistaskweresuccessfullycompleted(azerowasread

backratherthana one), the leftprocessorwouldassume controlofthe

lower8K.Meanwhiletherightprocessorwasattemptingtogaincontrolof

theresourceaftertheleftprocessor,itwouldreadbackaoneinresponse

tothezeroithadattemptedtowriteintoSemaphore0.Atthis point,the

softwarecouldchoosetotryandgaincontrolofthesecond8Ksectionby

writing,thenreadingazerointoSemaphore1.Ifitsucceededingaining

control,itwouldlockouttheleftside.

L PORT

R PORT

SEMAPHORE

REQUEST FLIP FLOP

SEMAPHORE

REQUEST FLIP FLOP

D0

D

Q

WRITE

SEMAPHORE

READ

SEMAPHORE

READ

,

5663 drw 18

Figure 4. IDT70T16/5 Semaphore Logic

6.1472

PRELIMINARY

IDT70T16/5L

High-Speed 2.5V 16/8K x 9 Dual-Port Static RAM

Industrial and Commercial Temperature Ranges

OrderingInformation

IDT XXXXX

A

999

A

Device

Type

Power

Speed

Package

Process/

Temperature

Range

Blank

I

Commercial (0 C to +70 C)

°

(1)

Industrial (-40 C to +85 C)

°

PF

BF

80-pin TQFP (PN80-1)

100-pin BGA (BF100)

fp

Commercial Only

Commercial & Industrial

20

25

Speed in Nanoseconds

L

Low Power

70T16 144K (16K x 9) 2.5V Dual-Port RAM

70T15

72K (4K x 9) 2.5V Dual-Port RAM

5663 drw 19

NOTE:

1. Contact your local sales office for industrial temp range for other speeds, packages and powers.

PreliminaryDatasheet:Definition

"PRELIMINARY'datasheetscontaindescriptionsforproductsthatareinearlyrelease.

DatasheetDocumentHistory

08/15/02:

InitialPublicRelease

CORPORATE HEADQUARTERS

for SALES:

for Tech Support:

2975StenderWay

Santa Clara, CA 95054

800-345-7015 or 408-727-6116

fax: 408-492-8674

831-754-4613

DualPortHelp@idt.com

www.idt.com

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

18

6.42

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	QFP
包装说明：	1.18 X 1.18 INCH, 0.16 INCH HEIGHT, TQFP-80	针数：	80
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.32.00.41	风险等级：	5.84
Is Samacsys：	N	最长访问时间：	25 ns
JESD-30 代码：	S-PQFP-G80	JESD-609代码：	e3
长度：	14 mm	内存密度：	73728 bit
内存集成电路类型：	DUAL-PORT SRAM	内存宽度：	9
湿度敏感等级：	3	功能数量：	1
端子数量：	80	字数：	8192 words
字数代码：	8000	工作模式：	ASYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	8KX9	封装主体材料：	PLASTIC/EPOXY
封装代码：	LQFP	封装形状：	SQUARE
封装形式：	FLATPACK, LOW PROFILE	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	260	认证状态：	Not Qualified
座面最大高度：	1.6 mm	最大供电电压 (Vsup)：	2.6 V
最小供电电压 (Vsup)：	2.4 V	标称供电电压 (Vsup)：	2.5 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	MATTE TIN
端子形式：	GULL WING	端子节距：	0.65 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	30
宽度：	14 mm	Base Number Matches：	1

型号	制造商	描述	价格	文档
IDT70T15L25PFG8	IDT	Dual-Port SRAM, 8KX9, 25ns, CMOS, PQFP80, 1.18 X 1.18 INCH, 0.16 INCH HEIGHT, TQFP-80	获取价格
IDT70T15L25PFGI	IDT	Dual-Port SRAM, 8KX9, 25ns, CMOS, PQFP80, 1.18 X 1.18 INCH, 0.16 INCH HEIGHT, TQFP-80	获取价格
IDT70T15L25PFI	IDT	HIGH-SPEED 2.5V 16/8K X 9 DUAL-PORT STATIC RAM	获取价格
IDT70T15L25PFI8	IDT	Dual-Port SRAM, 8KX9, 25ns, CMOS, PQFP80, 1.18 X 1.18 INCH, 0.16 INCH HEIGHT, TQFP-80	获取价格
IDT70T15L999BF	IDT	HIGH-SPEED 2.5V 16/8K X 9 DUAL-PORT STATIC RAM	获取价格
IDT70T15L999BFI	IDT	HIGH-SPEED 2.5V 16/8K X 9 DUAL-PORT STATIC RAM	获取价格
IDT70T15L999PF	IDT	HIGH-SPEED 2.5V 16/8K X 9 DUAL-PORT STATIC RAM	获取价格
IDT70T15L999PFI	IDT	HIGH-SPEED 2.5V 16/8K X 9 DUAL-PORT STATIC RAM	获取价格
IDT70T16	IDT	HIGH-SPEED 2.5V 16/8K X 9 DUAL-PORT STATIC RAM	获取价格
IDT70T16/5L	IDT	HIGH-SPEED 2.5V 16/8K X 9 DUAL-PORT STATIC RAM	获取价格

IDT70T15L25PFG

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