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IDT8P34S1102I

更新时间：2025-06-11 22:16:23
品牌：IDT
描述：1:2 LVDS Output 1.8V Fanout Buffer

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IDT8P34S1102I 概述

1:2 LVDS Output 1.8V Fanout Buffer

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IDT8P34S1102I  
Datasheet  
1:2 LVDS Output 1.8V Fanout Buffer  
Features  
Description  
The IDT8P34S1102I is a high-performance differential LVDS fanout  
buffer. The device is designed for the fanout of high-frequency, very  
low additive phase-noise clock and data signals.  
• Two low skew, low additive jitter LVDS output pairs  
• One differential clock input pair  
• Differential CLK, nCLK pairs can accept the following differential  
The IDT8P34S1102I is characterized to operate from a 1.8V power  
supply. Guaranteed output-to-output and part-to-part skew  
characteristics make the IDT8P34S1102I ideal for those clock  
distribution applications demanding well-defined performance and  
repeatability. One differential input and two low skew outputs are  
available. The integrated bias voltage reference enables easy  
interfacing of single-ended signals to the differential device input. The  
device is optimized for low power consumption and low additive  
phase noise.  
input levels: LVDS, CML  
• Maximum input clock frequency: 1.2GHz  
• Output skew: 3ps (typical)  
• Propagation delay: 400ps (maximum)  
• Low additive phase jitter, RMS; fREF = 156.25MHz,  
12kHz- 20MHz: 42fs (typical)  
• Maximum device current consumption (IEE): 48mA  
• Full 1.8V supply voltage  
• Lead-free (RoHS 6), 16-Lead VFQFN packaging  
• -40°C to 85°C ambient operating temperature  
Block Diagram  
Pin Assignment  
V
DD  
12 11 10  
9
Q0  
CLK  
nQ0  
13  
8
V
nc  
REF  
nCLK  
Q1  
nQ1  
nc 14  
nc 15  
7 nCLK  
6 CLK  
16  
5
VDD  
GND  
1
2
3
4
VREF  
VREF  
IDT8P34S1102I  
16-lead VFQFN  
3mm x 3mm x 0.925mm package body  
1.7mm x 1.7mm ePad Size  
NL Package  
Top View  
©2017 Integrated Device Technology, Inc.  
1
September 20, 2017  
IDT8P34S1102I Datasheet  
Pin Description and Pin Characteristic Tables  
Note 1.  
Table 1. Pin Descriptions  
Number  
Name  
GND  
nc  
Type  
Description  
1, 16  
Power  
Unused  
Power  
Input  
Power supply ground.  
Do not connect.  
2, 3, 4, 13, 14, 15  
5
6
VDD  
CLK  
Power supply pins.  
Pulldown  
Non-inverting differential clock/data input.  
Pulldown/  
Pullup  
7
8
nCLK  
VREF  
Input  
Inverting differential clock input.  
Bias voltage reference. Provides an input bias voltage for the CLK, nCLK input  
pair in AC-coupled applications. Refer to Figures 2B and 2C for applicable  
AC-coupled input interfaces.  
Output  
9, 10  
Q0, nQ0  
Q1, nQ1  
Output  
Output  
Differential output pair 0. LVDS interface levels.  
Differential output pair 1. LVDS interface levels.  
11, 12  
1.  
Pulldown and Pullup refers to an internal input resistors. See Table 2, Pin Characteristics, for typical values.  
Table 2. Pin Characteristics  
Symbol  
Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
CIN  
Input Capacitance  
2
pF  
RPULLDOWN  
RPULLUP  
Input Pulldown Resistor  
Input Pullup Resistor  
51  
51  
k  
k  
Absolute Maximum Ratings  
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress  
specifications only. Functional operation of the product at these conditions or any conditions beyond those listed in the DC Characteristics or  
AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.  
Item  
Rating  
Supply Voltage, VDD  
Inputs, VI  
4.6V  
-0.5V to VDD + 0.5V  
Outputs, IO  
Continuous Current  
Surge Current  
10mA  
15mA  
Input Sink/Source, IREF  
±2mA  
Maximum Junction Temperature, TJ,MAX  
Storage Temperature, TSTG  
125°C  
-65°C to 150°C  
2000V  
ESD - Human Body ModelNote 1.  
ESD - Charged Device ModelNote 1.  
1500V  
1.  
According to JEDEC JS-001-2012/JESD22-C101E.  
©2017 Integrated Device Technology, Inc.  
2
September 20, 2017  
IDT8P34S1102I Datasheet  
DC Electrical Characteristics  
Table 3A. Power Supply DC Characteristics, V = 1.8V ± 5%, T = -40°C to 85°C  
DD  
A
Symbol Parameter  
VDD Power Supply Voltage  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
1.71  
1.8  
1.89  
V
IDD  
Power Supply Current  
Q0 to Q1 terminated 100between nQx, Qx  
40  
48  
mA  
Table 3B. Differential Input Characteristics, V = 1.8V ± 5%, T = -40°C to 85°C  
DD  
A
Symbol Parameter  
IIH Input High Current  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
CLK, nCLK  
CLK  
VIN = VDD = 1.89V  
IN = 0V, VDD = 1.89V  
IN = 0V, VDD = 1.89V  
150  
µA  
V
V
-10  
µA  
µA  
IIL  
Input Low Current  
nCLK  
-150  
Reference Voltage for Input  
BiasNote 1.  
VREF  
VPP  
IREF = +100µA, VDD = 1.8V  
VDD = 1.89V  
0.9  
0.2  
0.9  
1.30  
1.0  
V
V
V
Peak-to-Peak VoltageNote3.  
Common Mode Input VoltageNote 2.  
VCMR  
VDD – (VPP/2)  
Note 3.  
1.  
2.  
3.  
VREF specification is applicable to the AC-coupled input interfaces shown in Figures 2B and 2C.  
Common mode input voltage is defined as crosspoint voltage.  
VIL should not be less than -0.3V and VIH should not be higher than VDD  
.
Note 1.  
Table 3C. LVDS DC Characteristics, V = 1.8V ± 5%, T = -40°C to 85°C  
DD  
A
Symbol Parameter  
Test Conditions  
Minimum  
Typical  
Maximum  
Units  
VOD  
VOD  
VOS  
Differential Output Voltage  
outputs loaded with 100   
247  
454  
mV  
VOD Magnitude Change  
Offset Voltage  
50  
1.40  
50  
mV  
V
1.0  
VOS  
VOS Magnitude Change  
mV  
1.  
Output drive current must be sufficient to drive up to 30cm of PCB trace (assume nominal 50impedance)  
©2017 Integrated Device Technology, Inc.  
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September 20, 2017  
IDT8P34S1102I Datasheet  
AC Electrical Characteristics  
Note 1.  
Table 4. AC Electrical Characteristics, V = 1.8V ± 5%, T = -40°C to 85°  
DD  
A
Symbol Parameter  
Test Conditions  
Minimum  
Typical  
Maximum Units  
fREF  
Input Frequency CLK, nCLK  
1.2  
GHz  
V/ns  
ps  
V/t  
tPD  
Input Edge Rate CLK, nCLK  
Propagation DelayNote 2. Note 3.  
Output SkewNote 4. Note 5.  
Pulse Skew  
1.5  
CLK, nCLK to any Qx, nQx  
150  
400  
15  
tsk(o)  
tsk(p)  
3
ps  
fREF = 100MHz  
20  
ps  
tsk(pp) Part-to-Part SkewNote 6.  
250  
ps  
fREF = 122.88MHz Square Wave, VPP = 1V,  
Integration Range: 1kHz – 40MHz  
61  
50  
85  
62  
fs  
fs  
fs  
fs  
fs  
fs  
fs  
fs  
fs  
ps  
ps  
fREF = 122.88MHz Square Wave, VPP = 1V,  
Integration Range: 10kHz – 20MHz  
fREF = 122.88MHz Square Wave, VPP = 1V,  
50  
62  
Integration Range: 12kHz – 20MHz  
fREF = 156.25MHz Square Wave, VPP = 1V,  
Integration Range: 1kHz – 40MHz  
63  
85  
Buffer Additive Phase Jitter,  
fREF = 156.25MHz Square Wave, VPP = 1V,  
Integration Range: 10kHz – 20MHz  
tJIT  
RMS; refer to Additive Phase  
Jitter Section  
42  
61  
fREF = 156.25MHz Square Wave, VPP = 1V,  
42  
61  
Integration Range: 12kHz – 20MHz  
fREF = 156.25MHz Square Wave, VPP = 0.5V,  
Integration Range: 1kHz – 40MHz  
76  
100  
74  
fREF = 156.25MHz Square Wave, VPP = 0.5V,  
Integration Range: 10kHz – 20MHz  
55  
f
REF = 156.25MHz Square Wave, VPP = 0.5V,  
Integration Range: 12kHz – 20MHz  
55  
74  
10% to 90%,  
outputs loaded with 100  
200  
115  
400  
260  
tR / tF  
Output Rise/ Fall Time  
20% to 80%,  
outputs loaded with 100  
1.  
Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is  
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equi-  
librium has been reached under these conditions.  
2.  
3.  
4.  
5.  
6.  
Measured from the differential input crossing point to the differential output crossing point.  
Input VPP is 0.4V.  
Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross points.  
This parameter is defined in accordance with JEDEC Standard 65.  
Defined as skew between outputs on different devices operating at the same supply voltage, same frequency, same temperature and  
with equal load conditions. Using the same type of input on each device, the outputs are measured at the differential cross points.  
©2017 Integrated Device Technology, Inc.  
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September 20, 2017  
IDT8P34S1102I Datasheet  
Additive Phase Jitter  
The spectral purity in a band at a specific offset from the fundamental  
compared to the power of the fundamental is called the dBc Phase  
Noise. This value is normally expressed using a Phase noise plot  
and is most often the specified plot in many applications. Phase noise  
is defined as the ratio of the noise power present in a 1Hz band at a  
specified offset from the fundamental frequency to the power value of  
the fundamental. This ratio is expressed in decibels (dBm) or a ratio  
of the power in the 1Hz band to the power in the fundamental. When  
the required offset is specified, the phase noise is called a dBc value,  
which simply means dBm at a specified offset from the fundamental.  
By investigating jitter in the frequency domain, we get a better  
understanding of its effects on the desired application over the entire  
time record of the signal. It is mathematically possible to calculate an  
expected bit error rate given a phase noise plot.  
Additive Phase Jitter @ 50fs (typical)  
Offset from Carrier Frequency (Hz)  
As with most timing specifications, phase noise measurements have  
issues relating to the limitations of the measurement equipment. The  
noise floor of the equipment can be higher or lower than the noise  
floor of the device. Additive phase noise is dependent on both the  
noise floor of the input source and measurement equipment.  
Measured using a Wenzel Oscillator as the input source.  
©2017 Integrated Device Technology, Inc.  
5
September 20, 2017  
IDT8P34S1102I Datasheet  
Additive Phase Jitter  
The spectral purity in a band at a specific offset from the fundamental  
compared to the power of the fundamental is called the dBc Phase  
Noise. This value is normally expressed using a Phase noise plot  
and is most often the specified plot in many applications. Phase noise  
is defined as the ratio of the noise power present in a 1Hz band at a  
specified offset from the fundamental frequency to the power value of  
the fundamental. This ratio is expressed in decibels (dBm) or a ratio  
of the power in the 1Hz band to the power in the fundamental. When  
the required offset is specified, the phase noise is called a dBc value,  
which simply means dBm at a specified offset from the fundamental.  
By investigating jitter in the frequency domain, we get a better  
understanding of its effects on the desired application over the entire  
time record of the signal. It is mathematically possible to calculate an  
expected bit error rate given a phase noise plot.  
Additive Phase Jitter @ 42fs (typical)  
Offset from Carrier Frequency (Hz)  
Measured using a Wenzel Oscillator as the input source.  
As with most timing specifications, phase noise measurements have  
issues relating to the limitations of the measurement equipment. The  
noise floor of the equipment can be higher or lower than the noise  
floor of the device. Additive phase noise is dependent on both the  
noise floor of the input source and measurement equipment.  
©2017 Integrated Device Technology, Inc.  
6
September 20, 2017  
IDT8P34S1102I Datasheet  
Parameter Measurement Information  
V
DD  
V
nCLK  
CLK  
DD  
GND  
1.8V LVDS Output Load Test Circuit  
Differential Input Level  
nCLK  
CLK  
nQx  
Qx  
nQy  
Qy  
nQy  
Qy  
tPLH  
tPHL  
tsk(p)= |tPHL - tPLH  
|
Pulse Skew  
Output Skew  
Part 1  
nQx  
nCLK  
CLK  
Qx  
Part 2  
nQy  
nQ[0:1]  
Q[0:1]  
Qy  
tPD  
tsk(pp)  
Part-to-Part Skew  
Propagation Delay  
©2017 Integrated Device Technology, Inc.  
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September 20, 2017  
IDT8P34S1102I Datasheet  
Parameter Measurement Information, continued  
nQ[0:1]  
Q[0:1]  
nQ[0:1]  
Q[0:1]  
80%  
80%  
tR  
90%  
90%  
tR  
VOD  
20%  
VOD  
10%  
20%  
10%  
tF  
tF  
Output Rise/Fall Time, 20% – 80%  
Output Rise/Fall Time, 10% – 90%  
Differential Output Voltage Setup  
Offset Voltage Setup  
©2017 Integrated Device Technology, Inc.  
8
September 20, 2017  
IDT8P34S1102I Datasheet  
Applications Information  
Wiring the Differential Input to Accept Single-Ended Levels  
Figure 1 shows how a differential input can be wired to accept single  
ended levels. The reference voltage V1= VDD/2 is generated by the  
bias resistors R1 and R2. The bypass capacitor (C1) is used to help  
filter noise on the DC bias. This bias circuit should be located as  
close to the input pin as possible. The ratio of R1 and R2 might need  
to be adjusted to position the V1in the center of the input voltage  
swing. For example, if the input clock swing is 1.8V and VDD = 1.8V,  
R1 and R2 value should be adjusted to set V1 at 0.9V. The values  
below are for when both the single ended swing and VDD are at the  
same voltage. This configuration requires that the sum of the output  
impedance of the driver (Ro) and the series resistance (Rs) equals  
the transmission line impedance. In addition, matched termination at  
the input will attenuate the signal in half. This can be done in one of  
two ways. First, R3 and R4 in parallel should equal the transmission  
line impedance. For most 50applications, R3 and R4 can be 100.  
The values of the resistors can be increased to reduce the loading for  
slower and weaker LVCMOS driver. When using single-ended  
signaling, the noise rejection benefits of differential signaling are  
reduced. Even though the differential input can handle full rail  
LVCMOS signaling, it is recommended that the amplitude be  
reduced. The datasheet specifies a lower differential amplitude,  
however this only applies to differential signals. For single-ended  
applications, the swing can be larger, however VIL cannot be less  
than -0.3V and VIH cannot be more than VDD + 0.3V. Though some  
of the recommended components might not be used, the pads should  
be placed in the layout. They can be utilized for debugging purposes.  
The datasheet specifications are characterized and guaranteed by  
using a differential signal.  
Recommended Schematic for Wiring a Differential Input to Accept Single-ended Levels  
©2017 Integrated Device Technology, Inc.  
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September 20, 2017  
IDT8P34S1102I Datasheet  
1.8V Differential Clock Input Interface  
The CLK /nCLK accepts LVDS and other differential signals. The  
differential input signal must meet both the VPP and VCMR input  
requirements. Figures 2A to 2D show interface examples for the CLK  
/nCLK input driven by the most common driver types. The input  
interfaces suggested here are examples only. If the driver is from  
another vendor, use their termination recommendation. Please  
consult with the vendor of the driver component to confirm the driver  
termination requirements.  
Figure 2A. Differential Input Driven by an  
LVDS Driver - DC Coupling  
Figure 2B. Differential Input Driven by an  
LVPECL Driver - AC Coupling  
Figure 2C. Differential Input Driven by an  
LVDS Driver - AC Coupling  
Figure 2D. Differential Input Driven by a CML Driver  
©2017 Integrated Device Technology, Inc.  
10  
September 20, 2017  
IDT8P34S1102I Datasheet  
Recommendations for Unused Output Pins  
Outputs:  
LVDS Outputs  
Unused LVDS outputs must either have a 100differential  
termination or have a 100pull-up resistor to VDD in order to ensure  
proper device operation.  
LVDS Driver Termination  
For a general LVDS interface, the recommended value for the  
termination impedance (ZT) is between 90and 132. The actual  
value should be selected to match the differential impedance (Z0) of  
your transmission line. A typical point-to-point LVDS design uses a  
100parallel resistor at the receiver and a 100differential  
transmission-line environment. In order to avoid any  
transmission-line reflection issues, the components should be  
surface mounted and must be placed as close to the receiver as  
possible. IDT offers a full line of LVDS compliant devices with two  
types of output structures: current source and voltage source. The  
standard termination schematic as shown in the first figure can be  
used with either type of output structure. The second figure, which  
can also be used with both output types, is an optional termination  
with center tap capacitance to help filter common mode noise. The  
capacitor value should be approximately 50pF. If using a  
non-standard termination, it is recommended to contact IDT and  
confirm if the output structure is current source or voltage source  
type. In addition, since these outputs are LVDS compatible, the input  
receiver’s amplitude and common-mode input range should be  
verified for compatibility with the output.  
Standard LVDS Termination  
Optional LVDS Termination  
©2017 Integrated Device Technology, Inc.  
11  
September 20, 2017  
IDT8P34S1102I Datasheet  
VFQFN EPAD Thermal Release Path  
In order to maximize both the removal of heat from the package and  
the electrical performance, a land pattern must be incorporated on  
the Printed Circuit Board (PCB) within the footprint of the package  
corresponding to the exposed metal pad or exposed heat slug on the  
package, as shown in Figure 4. The solderable area on the PCB, as  
defined by the solder mask, should be at least the same size/shape  
as the exposed pad/slug area on the package to maximize the  
thermal/electrical performance. Sufficient clearance should be  
designed on the PCB between the outer edges of the land pattern  
and the inner edges of pad pattern for the leads to avoid any shorts.  
and dependent upon the package power dissipation as well as  
electrical conductivity requirements. Thus, thermal and electrical  
analysis and/or testing are recommended to determine the minimum  
number needed. Maximum thermal and electrical performance is  
achieved when an array of vias is incorporated in the land pattern. It  
is recommended to use as many vias connected to ground as  
possible. It is also recommended that the via diameter should be 12  
to 13mils (0.30 to 0.33mm) with 1oz copper via barrel plating. This is  
desirable to avoid any solder wicking inside the via during the  
soldering process which may result in voids in solder between the  
exposed pad/slug and the thermal land. Precautions should be taken  
to eliminate any solder voids between the exposed heat slug and the  
land pattern. Note: These recommendations are to be used as a  
guideline only. For further information, please refer to the Application  
Note on the Surface Mount Assembly of Amkor’s Thermally/  
Electrically Enhance Leadframe Base Package, Amkor Technology.  
While the land pattern on the PCB provides a means of heat transfer  
and electrical grounding from the package to the board through a  
solder joint, thermal vias are necessary to effectively conduct from  
the surface of the PCB to the ground plane(s). The land pattern must  
be connected to ground through these vias. The vias act as “heat  
pipes”. The number of vias (i.e. “heat pipes”) are application specific  
SOLDER  
PIN  
SOLDER  
EXPOSED HEAT SLUG  
PIN  
PIN PAD  
GROUND PLANE  
LAND PATTERN  
(GROUND PAD)  
PIN PAD  
THERMAL VIA  
P.C. Assembly for Exposed Pad Thermal Release Path – Side View (drawing not to scale)  
©2017 Integrated Device Technology, Inc.  
12  
September 20, 2017  
IDT8P34S1102I Datasheet  
Power Considerations  
This section provides information on power dissipation and junction temperature for the IDT8P34S1102I. Equations and example calculations  
are also provided.  
1. Power Dissipation.  
The total power dissipation for the IDT8P34S1102I is the sum of the core power plus the output power dissipation due to the load. The following  
is the power dissipation for VDD = 1.8V + 5% = 1.89V, which gives worst case results.  
The maximum current at 85°C is as follows:  
IDD_MAX = 48mA  
Power (core)MAX = VDD_MAX * IDD_MAX = 1.89V * 48mA = 90.72mW  
Total Power_MAX = 90.72mW  
2. Junction Temperature.  
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad directly affects the reliability of the device. The  
maximum recommended junction temperature is 125°C. Limiting the internal transistor junction temperature, Tj, to 125°C ensures that the bond  
wire and bond pad temperature remains below 125°C.  
The equation for Tj is as follows: Tj = JA * Pd_total + TA  
Tj = Junction Temperature  
JA = Junction-to-Ambient Thermal Resistance  
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)  
TA = Ambient Temperature  
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance JA must be used. Assuming no air flow and  
a multi-layer board, the appropriate value is 74.7°C/W per Table 5 below.  
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:  
85°C + 0.091W * 74.7°C/W = 91.8°C. This is below the limit of 125°C.  
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow and the type of  
board (multi-layer).  
Table 5. Thermal Resistance for 16-lead VFQFN  
JA  
JA vs. Air Flow (m/s)  
Meters per Second  
0
1
2.5  
Multi-Layer PCB, JEDEC Standard Test Boards  
74.7°C/W  
65.3°C/W  
58.5°C/W  
©2017 Integrated Device Technology, Inc.  
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September 20, 2017  
IDT8P34S1102I Datasheet  
Reliability Information  
Table 6. vs. Air Flow Table for a 16-lead VFQFN  
JA  
JA vs. Air Flow (m/s)  
Meters per Second  
0
1
2.5  
Multi-Layer PCB, JEDEC Standard Test Boards  
74.7°C/W  
65.3°C/W  
58.5°C/W  
Transistor Count  
The transistor count for the IDT8P34S1102I is: 935  
Package Outline Drawings  
The package outline drawings are located in the last section of this document. The package information is the most current data available and  
is subject to change without notice or revision of this document.  
Ordering Information  
Table 7. Ordering Information  
Part/Order Number  
Marking  
Package  
Shipping Packaging  
Temperature  
8P34S1102NLGI  
S102I  
“Lead-Free” 16-lead VFQFN  
Tube  
-40C to 85C  
8P34S1102NLGI8  
S102I  
“Lead-Free” 16-lead VFQFN  
Tape & Reel  
-40C to 85C  
Revision History  
Revision Date  
Description of Change  
Updated the package outline drawings; however, no mechanical changes  
Completed other minor improvements  
September 20, 2017  
February 26, 2014  
Ordering Info: Changed Tray to Tube.  
Corporate Headquarters  
6024 Silver Creek Valley Road  
San Jose, CA 95138 USA  
www.IDT.com  
Sales  
Tech Support  
www.IDT.com/go/support  
1-800-345-7015 or 408-284-8200  
Fax: 408-284-2775  
www.IDT.com/go/sales  
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notice, at IDT’s sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guaranteed to perform the same way when installed  
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14  
September 20, 2017  

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