2ED1324S12P中文资料_数据手册_规格书

2ED2181 (4) S06F

2ED1324S12P/2ED1323S12P

1200 V half-bridge gate driver with Active Miller Clamp and Short Circuit Clamp

Features

Product summary



Unique Infineon Thin-Film-Silicon On Insulator (SOI)-technology

V_{S_OFFSET}= 1200 V (maximum)

I_o+/ I_o-= 2.3 A / 2.3 A (peak)

V_CC= 13 V to 20 V (typical)

Propagation delay = 500 ns typ.

Dead-time = 380 ns typ.

Floating channel designed for bootstrap operation

Maximum bootstrap voltage (VB node) of + 1225 V

Operating voltages (VS node) upto + 1200 V

Negative VS transient voltage immunity of 100 V

With repetitive 700 ns pulses



2.3 A / 2.3 A peak output source / sink current capability

Integrated ultra-fast over-current protection (OCP)

± 5% high accuracy reference threshold

Less than 1 us over-current sense to output shutdown

Integrated Active Miller Clamp (AMC) with 2 A sink current capability

Integrated Short Circuit Clamp (SCC) function

Integrated ultra-fast, low resistance bootstrap diode

Integrated dead-time and shoot-through prevention logic (2ED1324S12P)

Enable, Fault, and programmable Fault clear RFE input

Logic operational up to –8 V on VS Pin

Independent per channel undervoltage lockout (UVLO)

25 V VCC supply voltage (maximum)

Separate Logic (VSS) and output ground (COM)

Greater than 5 mm clearance / creepage



Package

2 kV HBM ESD capability

PG-DSO-20-U03

(20 fine-pitch leads)

Typical applications



Industrial Drives

Embedded inverters for Motor Control in Pumps, Fans

Commercial and Lite Commercial Air Conditioning

Product validation

Qualified for industrial applications according to the relevant tests of JEDEC78/20/22

Ordering information

Standard pack

Sales Product Name Package type

Orderable part number

Form

Tape and Reel

Quantity

1,000

2ED1324S12P

2ED1323S12P

PG-DSO-20-U03

2ED1324S12PXUMA1

2ED1323S12PXUMA1

1,000

Datasheet

www.infineon.com/soi

Please read the Important Notice and Warnings at the end of this document

Page 1 of 34

V1.1

2023-03-16

2ED1324S12P/2ED1323S12P

1200 V half-bridge gate driver with Active Miller Clamp and Short Circuit Clamp

Description

The 2ED132x family contains devices, which control IGBT or SiC MOSFET power devices with a maximum blocking

voltage of +1200 V in half bridge configurations. Based on the used SOI-technology there is an excellent

ruggedness on transient voltages. No parasitic thyristor structures are present in the device. Hence, the design

is very robust against parasitic latch up across the operating temperature and voltage range.

The two independent driver outputs are controlled at the low-side using two different CMOS resp. LSTTL

compatible signals, down up to 3.3V logic. The device includes an under-voltage detection unit with hysteresis

characteristic.

The 2ED132x has symmetric undervoltage lockout levels, which support strongly the integrated ultrafast

bootstrap diode. Additionally, the offline gate clamping function provides an inherent protection of the

transistors for parasitic turn-on by floating gate conditions, when the IC is not supplied via VCC.

VCC

VBUS

VCC

VB

HO

HC

Refer to lead assignments for

correct pin configuration. This

diagram shows electrical

connections only. Please refer to

our application notes and design

tips for proper circuit board

layout.

HIN

LIN

VS

To Load

RFE

2ED1324

2ED1323

VCC

ITRIP

LO

LC

VSS

COM

*Bootstrap diode is monolithically integrated

Figure 1

Typical application block diagram

Summary of feature comparison of the 2ED132x family:

Table 1

Source /

sink drive

(peak - A)

Integrated

Cross

conduction

prevention

Sales Product

Name

Key

Features

t_ON/ t_OFF

(typ)

Package Type

Bootstrap

Deadtime

Diode

OCP, AMC,

SCC, RFE

+ 2.3 / - 2.3

2ED1324S12P PG-DSO-20-U03

2ED1323S12P PG-DSO-20-U03

Yes

No

380 ns

None

Yes

500 ns

350 ns

OCP, AMC,

SCC, RFE

PG-DSO-16-U02 + 2.3 / - 4.6

2ED1322S12M

OCP, RFE

Yes

No

380 ns

None

Yes

500 ns

350 ns

+ 2.3 / - 4.6

2ED1321S12M PG-DSO-16-U02

Datasheet

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2 of 34

V 1.1

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2ED1324S12P/2ED1323S12P

1200 V half-bridge gate driver with Active Miller Clamp and Short Circuit Clamp

1

Table of contents

Features

Product summary ........................................................................................................................1

Typical applications.....................................................................................................................................................1

Product validation .......................................................................................................................................................1

Ordering information...................................................................................................................................................1

Description

2

1

2

Table of contents ................................................................................................................... 3

Block diagram........................................................................................................................ 4

3

3.1

3.2

Pin configuration and functionality.......................................................................................... 5

Pin configuration.....................................................................................................................................5

Pin functionality ......................................................................................................................................6

4

Electrical parameters ............................................................................................................. 7

Absolute maximum ratings.....................................................................................................................7

Recommended operating conditions.....................................................................................................8

Static electrical characteristics...............................................................................................................9

Dynamic electrical characteristics........................................................................................................11

4.1

4.2

4.3

4.4

5

5.1

5.2

5.3

5.4

5.5

5.6

5.7

Application information and additional details.........................................................................12

Gate drive...............................................................................................................................................12

Switching relationships.........................................................................................................................12

Timing diagram .....................................................................................................................................13

Deadtime ...............................................................................................................................................14

Matched propagation delays ................................................................................................................14

Input logic compatibility.......................................................................................................................15

Undervoltage lockout ...........................................................................................................................15

Shoot-through protection.....................................................................................................................16

Enable, Fault reporting and programmable fault clear timer .............................................................16

Over-current protection........................................................................................................................17

Truth table: Undervoltage lockout, OCP and Enable...........................................................................18

Daisy Chain Multiple Devices ................................................................................................................18

Bootstrap diode.....................................................................................................................................19

Calculating the bootstrap capacitance C_BS..........................................................................................20

Tolerant to negative transients on input pins......................................................................................22

Negative voltage transient tolerance of VS pin....................................................................................22

NTSOA – Negative Transient Safe Operating Area ...............................................................................23

Active Miller Clamp................................................................................................................................24

Short Circuit Clamp...............................................................................................................................26

PCB layout tips ......................................................................................................................................26

5.8

5.9

5.10

5.11

5.12

5.13

5.14

5.15

5.16

5.17

5.18

5.19

5.20

6

7

8

9

Qualification information.......................................................................................................28

Related products...................................................................................................................29

Package details.....................................................................................................................30

Part marking information ......................................................................................................31

10

Additional documentation and resources.................................................................................32

10.1

Infineon online forum resources ..........................................................................................................32

11

Revision history ....................................................................................................................33

Datasheet

www.infineon.com/soi

3 of 34

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2ED1324S12P/2ED1323S12P

1200 V half-bridge gate driver with Active Miller Clamp and Short Circuit Clamp

2

Block diagram

VB

S

Input

Noise

filter

Latch

&

UV Detect

HV Level

Shifter

HIN

HO

Driver

Deadtime & Shoot-

Through Prevention

R

Input

Noise

filter

VS

HC

LIN

Logic

VSS

VS

UV

Detect

VCC

LO

ITRIP

RFE

ITRIP

Noise

filter

VSS/COM

Level

Shifter

Driver

Delay

COM

LC

Noise

filter

Logic

com

Figure 2

Block diagram of 2ED1324S12P

Datasheet

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4 of 34

V 1.1

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2ED1324S12P/2ED1323S12P

1200 V half-bridge gate driver with Active Miller Clamp and Short Circuit Clamp

3

Pin configuration and functionality

3.1

Pin configuration

1

2

NC

NC 20

NC 19

3

4

5

6

7

8

9

NC

HIN

LIN

RFE

VSS

ITRIP

COM

NC

VS

HC

HO

VB

18

17

16

15

10 LC

11 LO

12 VCC

13 NC

14

20-Lead PG-DSO-20-U03 (300 mil)

2ED1324S12P/2ED1323S12P

Figure 3

Pin assignment (top view)

Datasheet

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5 of 34

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2ED1324S12P/2ED1323S12P

1200 V half-bridge gate driver with Active Miller Clamp and Short Circuit Clamp

3.2

Pin functionality

Table 2

Symbol

Description

HIN

LIN

Logic input for high side gate driver output (HO), in phase with HO

Logic input for low side gate driver output (LO), in phase with LO

Integrated fault reporting function like over-current protection (OCP), or low-side

undervoltage lockout and the fault clear timer. This pin has negative logic and an

open-drain output. The use of over-current protection requires the use of

external components

RFE

VSS

Logic ground

Analog input for over-current shutdown. When active, OCP shuts down outputs

and activates RFE low. When OCP becomes inactive, RFE stays active low for an

externally set time t_FLTCLR, then automatically becomes inactive (open-drain high

impedance)

ITRIP

COM

LC

Low-side gate drive return

Low-side Active Miller Clamp & Short Circuit Clamp

Low-side driver output

LO

VCC

VS

Low-side and logic supply voltage

High voltage floating supply return

High-side Active Miller Clamp & Short Circuit Clamp

High-side driver output

HC

HO

VB

High-side gate drive floating supply

Datasheet

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2ED1324S12P/2ED1323S12P

1200 V half-bridge gate driver with Active Miller Clamp and Short Circuit Clamp

4

Electrical parameters

4.1

Absolute maximum ratings

Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage

parameters are absolute voltages referenced to COM unless otherwise stated in the table. The thermal resistance

and power dissipation ratings are measured under board mounted and still air conditions. (Ta = 25^oC).

Table 3

Absolute maximum ratings

Symbol

Definition

High-side floating well supply voltage ^{Note 1}

High-side floating well supply return voltage ^{Note 1}

High-side floating supply voltage (V_Bvs. V_S)

(internally clamped)

Floating gate drive output voltage

Low side supply voltage (V_CCvs. V_SS) (internally

clamped)

Min.

-0.5

V_B– 25

Max.

1225

V_B+ 0.5

Units

V_B

V_S

V_BS

-1

V_S- 0.5

-1

25

V_B+ 0.5

25

V_HO/HC

V_CCGND

V

Low side supply voltage (V_CCvs. V_COM) (internally

clamped)

V_CC

-1

25

V_LO/LC

V_IN

Low-side output voltage

–0.5

V_SS- 5

V_CC+ 0.5

Logic input voltage (HIN, LIN, RFE, ITRIP)

Maximum short circuit clamping time

(I_CLAMP/OUT= 500 mA)

t_CLP

—

10

µs

dV_S/dt Allowable V_Soffset supply transient relative to COM

—

50

1.5

81

V/ns

W

Note 2

P_D

Rth_JA

Package power dissipation @ T_A+25ºC

Thermal resistance, junction to ambient ^{Note 3}

Characterization parameter junction to package

top^{Note 3}

ºC/W

ºC

Ψ_Jtop

5

T_J

T_S

T_L

Junction temperature

Storage temperature

Lead temperature (soldering, 10 seconds)

-40

-55

—

150

300

Note 1: In case VCC > VB there is an additional power dissipation in the internal bootstrap diode between pins VCC and VB in case of

activated bootstrap diode

Note 2: Consistent power dissipation of all outputs. All parameters inside operating range

Note 3: Obtained in a simulation on a JEDEC-standard and Ta = 50 °C, PD= 1W, PCB: JEDEC 2s2p (JESD 51-5)

Datasheet

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7 of 34

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2ED1324S12P/2ED1323S12P

1200 V half-bridge gate driver with Active Miller Clamp and Short Circuit Clamp

4.2

Recommended operating conditions

For proper operation, the device should be used within the recommended conditions. All voltage parameters

are absolute voltages referenced to COM unless otherwise stated in the table. The offset rating is tested with

supplies of (V_CC– COM) = (V_B– V_S) = 15 V. (Ta = 25^oC).

Table 4

Recommended operating conditions

Symbol

Definition

Bootstrap voltage

High-side floating well supply voltage

Min

V_S+ 13

13

Max

V_S+ 20

20

Units

V_B

V_BS

V_S

High-side floating well supply offset voltage ^{Note 1}

Transient High-side floating well supply offer

-8

1200

V_St

-100

1200

Note 2

voltage (<700ns)

V

V_HO/HC

V_CC

V_LO/LC

V_IN

Floating gate drive output voltage

Low-side supply voltage

Low-side output voltage

Logic input voltage (HIN, LIN, RFE, ITRIP)

Logic ground

V_S

13

0

V_SS

-5

V_B

20

V_CC

5

V_SS

0.3

-40

t_IN

T_A

Minimal pulse width for ON or OFF

Ambient temperature

—

125

µs

ºC

Note 1: Logic operational for V_Sof -8 V to +1200 V

Note 2: In case V_CC> V_Bthere is an additional power dissipation in the internal bootstrap diode between pins V_CCand V_B. Insensitivity of

bridge output to negative transient voltage up to –100 V is not subject to production test – verified by design / characterization

Datasheet

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2ED1324S12P/2ED1323S12P

1200 V half-bridge gate driver with Active Miller Clamp and Short Circuit Clamp

4.3

Static electrical characteristics

(V_CC– COM) = (V_B– V_S) = 15 V, V_SS= COM and T_A= 25 °C unless otherwise specified. The V_IL,V_IHand I_INparameters are

referenced to COM and are applicable to the respective input leads: HIN and LIN. The V_Oand I_Oparameters are

referenced to V_S/ COM and are applicable to the respective output leads HO or LO. The V_CCUVparameters are

referenced to COM. The V_BSUVparameters are referenced to V_S.

Table 5

Symbol

Static electrical characteristics

Definition

V_BSsupply undervoltage positive going

threshold

Min.

Typ.

Max.

Units

Test Conditions

V_BSUV

11.5

12.2

12.9

+

V_BSsupply undervoltage negative going

threshold

V_BSsupply undervoltage hysteresis

V_CCsupply undervoltage positive going

threshold

V_BSUV

10.6

0.5

11.3

0.9

12

—

-

V

V_BSUVHY

V_CCUV

11.5

12.2

12.9

+

V_CCsupply undervoltage negative going

threshold

V_CCsupply undervoltage hysteresis

V_CCUV

10.6

0.5

—

11.3

0.9

12

—

-

V_CCUVHY

V_B= 1215V

V_S= 1200 V

I_LK

I_QBS

I_QCC

High-side floating well offset supply leakage

0.5

20

uA

V

Quiescent V_BSsupply current

Quiescent V_CCsupply current

V_OHHigh level output voltage drop, V_cc- V_{LO ,}V_B- V_HO

V_OLLow level output voltage drop, V_O

—

1.4

180

600

0.32

0.18

2.0

350

1000

0.7

0.4

—

V_IN= 0V or 3.3V

I_O= 100 mA

I_o+meanMean output current from 4.5 V to 7.5 V

C_L= 56 nF

R_L= 0 Ω

PW ≤ 10 µs

C_L= 56 nF

R_L= 0 Ω

1

I_o+

Peak output current turn-on

—

1.4

—

2.3

2.0

2.3

—

A

V

I_o-meanMean output current from 7.5 V to 4.5 V

1

I_o-

Peak output current turn-off

PW ≤ 10 µs

V_IH

V_IL

Logic “1” input voltage (HIN, LIN, EN)

Logic “0” input voltage (HIN, LIN, EN)

1.7

0.7

15

—

2.0

0.9

35

0

2.3

1.1

60

—

1

—

1

I_IN+Input bias current (Output = High)

I_IN-Input bias current (Output = Low)

I_RFE+Logic “1” Input bias current (RFE)

I_RFE-Logic “0” Input bias current (RFE)

I_ITRIP+Logic “1” Input bias current (ITRIP)

I_ITRIP-Logic “0” Input bias current (ITRIP)

V_IN= 3.3 V

V_IN= 0 V

V_RFE= 3.3 V

µA

= 0 V

V_RFE

—

0

V_IN= 1 V

V_IN= 0 V

—

Bootstrap diode forward voltage between Vcc

and VB

Bootstrap diode forward current between Vcc

and VB

V_FBSD

—

40

18

—

1

1.2

100

42

V

I_F= 0.3 mA

V_CC-V_B= 4 V

I_FBSD

70

30

35

2.1

mA

V_F1= 4 V,

V_F2= 5 V

R_BSDBootstrap diode resistance

Ω

RFE low on resistance of the pull-down

transistor

R_on,FLT

70

V_RFE= 0.5 V

I_OUT-= 200 mA

V_CC/V_BSopen

V_ACTSDActive shut-down voltage

—

2.4

V

Datasheet

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2ED1324S12P/2ED1323S12P

1200 V half-bridge gate driver with Active Miller Clamp and Short Circuit Clamp

I_OUTL= 20 mA

into clamping PIN

HC/LC

I_OUTL= 100 mA

I_OUTL= 1 A

V_CLAMP1

—

0.03

0.08

Low level clamp voltage of Active Miller Clamp

V_CLAMP2

—

0.18

1.9

0.4

3.4

1

V_CLAMP3

Mean low level clamp current of Active Miller

Clamp

Clamp threshold voltage of Active Miller

Clamp

1

I_CLAMPL

1.4

1.6

2.0

—

A

V

V_CLAMP

2.5

IN = High,

OUT = High

I_OUT= 500 mA

pulse test,

Clamping voltage (CLAMP) (V_CLAMP- V_B, V_CLAMP

V_CC) of Short Circuit Clamping

-

1

V_CLPclamp

—

1.5

—

t_CLPmax= 10 μs)

V_th,OCPOCP comparator threshold

V_th,OCPHOCP comparator hysteresis

0.416

0.04

0.44

0.05

0.464

—

¹Not subjected to production test, verified by design/characterization

Datasheet

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2ED1324S12P/2ED1323S12P

1200 V half-bridge gate driver with Active Miller Clamp and Short Circuit Clamp

4.4

Dynamic electrical characteristics

V_CC= V_BS= 15 V, T_A= 25 ^oC and C_L= 1000 pF unless otherwise specified.

Table 6 Dynamic electrical characteristics

Symbol Definition

Min.

400

250

400

250

—

Typ.

500

350

500

350

48

Max.

700

500

700

500

80

Units

Test Conditions

2ED1324

2ED1323

2ED1324

2ED1323

t_ON

Turn-on propagation delay

V_IN= 0 V or 3.3 V

V_S= 0 V or 1200 V

t_OFFTurn-off propagation delay

t_R

t_F

Turn-on rise time

Turn-off fall time

V_IN= 0 or 3.3 V

C_L= 4.9 nF

V_RFE= 0.5 V,

—

48

80

ns

T_ENRFE Enable propagation delay

400

100

500

150

700

V_LO/V_HO= 20%

Input filter time at LIN/HIN for

t_FILINturn-on and -off

2ED1324

2ED1323

—

V_IN= 0 & 3.3 V

25

35

—

t_FILENRFE Input filter time

t_FLTCLRRFE Fault-clear time

t_OCPfilITRIP Filter time

100

150

220

V_ITRIP= 0.1 V,

V_RFE= 2.1 V

V_ITRIP= 1 V

V_ITRIP= 1V

V_OUT= 3V

120

0.3

0.4

160

0.5

—

0.7

0.9

t_OCPOUT,LSOCP Sense to Low-side OUT LOW delay

t_OCPOUT,HSOCP Sense to High-side OUT LOW delay

0.65

s

µ

V_ITRIP= 1V

V_OUT= 3V

0.6

0.85

1.1

V_ITRIP= 1V

V_RFE= 10%

t_OCPFLTOCP Sense to RFE LOW delay

t_UVLOFILUVLO Noise filter

0.4

1.0

—

0.65

1.5

10

0.9

—

Delay matching time (HS & LS turn-

external dead time >

500 ns

MT

60

on/off)

V_IN= 0 & 3.3 V

external dead time 0ns

PW_IN> 1 µs

DT Dead time (2ED1324 only)

MDT Matching Dead time (2ED1324 only)

PM Output pulse width matching

260

—

380

10

20

540

80

ns

Datasheet

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2ED1324S12P/2ED1323S12P

1200 V half-bridge gate driver with Active Miller Clamp and Short Circuit Clamp

5

Application information and additional details

5.1

Gate drive

The 2ED132xS12 HVIC is designed to drive IGBTs or SiC MOSFETs. Figure 4 and Figure 5 illustrate several

parameters associated with the gate drive functionality of the HVIC. The output current of the HVIC, used to drive

the gate of the power switch, is defined as I_O. The voltage that drives the gate of the external power switch is

defined as V_HOfor the high-side power switch and V_LOfor the low-side power switch; this parameter is sometimes

generically called V_OUTand in this case does not differentiate between the high-side or low-side output voltage.

V_B

(or V_CC

)

(or V_CC)

I_O+

HO

(or LO)

+

I_O-

V_HO(or V_LO)

-

V_S

(or COM)

Figure 4

HVIC Sourcing current

Figure 5

HVIC Sinking current

5.2

Switching relationships

The relationships between the input and output signals of the 2ED132xS12 are illustrated below in Figure 6 and

Figure 7. From these figures, we can see the definitions of several timing parameters (i.e. t_ON, t_OFF, t_R, and t_F)

associated with this device, and the input filter function that is used to reject noise.

t_FILIN

t_IN

HIN/LIN

50%

t_IN< t_FILIN

HIN

LIN

HO/LO

HIN/LIN

HO/LO

t_F

t_ONt_R

t_OFF

low

90%

t_IN

HO

LO

t_IN> t_FILIN

10%

Figure 6

Switching timing diagram

Figure 7

Input filter

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2ED1324S12P/2ED1323S12P

1200 V half-bridge gate driver with Active Miller Clamp and Short Circuit Clamp

5.3

Timing diagram

Here below Figure 8 and Figure 9 illustrate the timing relationships of some of the functionality of the

2ED1324S12P as an example; this functionality is described in further detail later in this document. During

interval A of Figure 8, the HVIC has received the command to turn-on both the high- and low-side switches at the

same time; as a result, the shoot-through protection of the HVIC has prevented this condition. HVIC is keeping on

output channel that is already on ignoring the 2^ndinput signal.

Interval B of Figure 8 and Figure 9 shows that the signal on the ITRIP input pin has gone from a low to a high state;

as a result, all of the gate drive outputs have been disabled (i.e., see that HO has returned to the low state; LO is

also held low), and a fault condition is reported on the RFE pin, which goes 0V. Once the ITRIP input has returned

to the low state, the output will remain disabled and the fault condition reported until the voltage on the RFE pin

charges up to VRFE+ threshold; the charging characteristics are dictated by the RC network attached to the RFE

pin. After fault clear time HVIC is waiting for a new input signal on LIN/HIN before activate the output stage

(LO/HO).

During interval C of Figure 8 and Figure 10, we can see that the RFE pin has been pulled low (as is the case when

the driver IC has received a command from the control IC to shutdown); these results in the outputs (HO and LO)

being held in the low state until the RFE pin is pulled high. After an enable event HVIC will wait for a new input

signal on LIN/HIN before activate the output stage (LO/HO).

Figure 8

ITRIP

Input/ put timing diagram

0.5V

EN

t_EN

RFE

0.1V

FAULT

2.1V

0.5V

t_OCPFLT

t_FLTCLR

Any

output

HO1,2,3

LO1,2,3

3V

t_OCPOUT

Figure 9

OCP timing (low-side)

Figure 10 Enable delay time

definition

Datasheet

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2ED1324S12P/2ED1323S12P

1200 V half-bridge gate driver with Active Miller Clamp and Short Circuit Clamp

5.4

Deadtime

This 2ED1324S12P features integrated deadtime protection circuitry. The deadtime feature inserts a time period

(a minimum deadtime) in which both the high- and low-side power switches are held off; this is done to ensure

that the power switch being turned off has fully turned off before the second power switch is turned on. This

minimum deadtime is automatically inserted whenever the external deadtime is shorter than interal deadtime;

external deadtimes larger than internal deadtime are not modified by the gate driver. Figure 11 illustrates the

deadtime period and the relationship between the output gate signals.

The deadtime circuitry of 2ED1324S12P is matched with respect to the high- and low-side outputs. Figure 11

defines the two deadtime parameters (i.e., DT_LO-HOand DT_HO-LO); the deadtime matching parameter (MDT)

associated with the 2ED1324S12P specifies the maximum difference between DT_LO-HOand DT_HO-LO

.

HIN

50%

LIN

LO

90%

10%

DT_HO-LO

90%

DT_LO-HO

HO

10%

MDT = I DT_LO-HO– DT_HO-LO

I

Figure 11 Deadtime matching waveform definition

5.5

Matched propagation delays

The 2ED132xS12 is designed with propagation delay matching circuitry. With this feature, the IC’s response at

the output to a signal at the input requires approximately the same time duration (i.e., tON, tOFF) for both the low-

side channels and the high-side channels; the maximum difference is specified by the delay matching parameter

(MT). The propagation turn-on delay (t_ON) of the 2ED132xS12 is matched to the propagation turn-on delay (t_OFF).

50%

HIN

LIN

LO

HO

10%

MT

HO

MT

90%

LO

Figure 12 Delay matching waveform definition

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1200 V half-bridge gate driver with Active Miller Clamp and Short Circuit Clamp

5.6

Input logic compatibility

The input pins are based on a TTL and CMOS compatible input-threshold logic that is independent of the Vcc

supply voltage. With typical high threshold (V_IH) of 2.0 V and typical low threshold (V_IL) of 0.9 V, along with very

little temperature variation as summarized in Figure 13, the input pins are conveniently driven with logic level

PWM control signals derived from 3.3 V and 5 V digital power-controller devices. Wider hysteresis (typically 1.1 V)

offers enhanced noise immunity compared to traditional TTL logic implementations, where the hysteresis is

typically less than 0.5 V. 2ED132xS12 also features tight control of the input pin threshold voltage levels which

eases system design considerations and ensures stable operation across temperature. The 2ED132xS12 features

floating input protection wherein if any of the input pin is left floating, the output of the corresponding stage is

held in the low state. This is achieved using pull-down resistors on all the input pins (HIN, LIN) as shown in the

block diagram. The 2ED132xS12 has input pins that are capable of sustaining voltages higher than the bias

voltage applied on the Vcc pin of the device.

V_IH

V_IL

High

Low

Figure 13 HIN & LIN input thresholds

5.7

Undervoltage lockout

This IC provides undervoltage lockout protection on both the V_CC(logic and low-side circuitry) power supply and

the V_BS(high-side circuitry) power supply. Figure 14 is used to illustrate this concept; V_CC(or V_BS) is plotted over

time and as the waveform crosses the UVLO threshold (V_CCUV+/-or V_BSUV+/-)the undervoltage protection is enabled

or disabled.

Upon power-up, should the V_CCvoltage fail to reach the V_CCUV+threshold, the IC won’t turn-on. Additionally, if the

V_CCvoltage decreases below the V_CCUV-threshold during operation, the undervoltage lockout circuitry will

recognize a fault condition and shutdown the high and low-side gate drive outputs.

Upon power-up, should the V_BSvoltage fail to reach the V_BSUV+threshold, the IC won’t turn-on. Additionally, if the

V_BSvoltage decreases below the V_BSUV-threshold during operation, the undervoltage lockout circuitry will

recognize a fault condition, and shutdown the high-side gate drive outputs of the IC.

The UVLO protection ensures that the IC drives the external power devices only when the gate supply voltage is

sufficient to fully enhance the power devices. Without this feature, the gates of the external power switch could

be driven with a low voltage, resulting in the power switch conducting current while the channel impedance is

high; this could result in very high conduction losses within the power device and could lead to power device

failure.

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1200 V half-bridge gate driver with Active Miller Clamp and Short Circuit Clamp

V_CC

(or V_BS

)

V_CCUV+

(or V_BSUV+

)

V_CCUV-

(or V_BSUV-

)

Time

UVLO Protection

(Gate Drive Outputs Disabled)

Normal

Operation

Figure 14 UVLO protection

5.8

Shoot-through protection

The 2ED1324S12P is equipped with shoot-through protection circuitry (also known as cross-conduction

prevention circuitry). Figure 15 shows how this protection circuitry prevents both the high- and low-side switches

from conducting at the same time.

Note: 2ED1323S12P no shoot-through protection because it is a high-side and low-side gate driver, HO and LO

can turn on at the same time.

Figure 15 Illustration of shoot-through protection circuitry

5.9

Enable, Fault reporting and programmable fault clear timer

The 2ED132xS12 provides an enable functionality that allows it to shutdown or enable the HVIC and also provides

an integrated fault reporting output along with an adjustable fault clear timer. There are two situations that

would cause the IC to report a fault via the RFE pin. The first is an undervoltage condition of VCC and the second

is if the over-current feature has recognized a fault. Once the fault condition occurs, the RFE pin is internally

pulled to VSS and the fault clear timer is activated. The RFE output stays in the low state until the fault condition

has been removed and the fault clear timer expires; once the fault clear timer expires, the voltage on the RFE pin

will return to its external pull-up voltage.

The length of the fault clear time period (t_FLTCLR) is determined by exponential charging characteristics of the

capacitor where the time constant is set by R_RFEand C_RFE. Figure 16 shows that R_RFEis connected between the

external supply (V_DD) ¹⁾and the RFE pin, while C_RFEis placed between the RFE and VSS pins.

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2ED1324S12P/2ED1323S12P

1200 V half-bridge gate driver with Active Miller Clamp and Short Circuit Clamp

V_CC

HIN U

LIN U

HIN V

LIN V

HIN W

LIN W

V_DD

HIN

LIN

uC

HO

V_S

GK

R_RFE

RFE

LO

C_RFE

VSS

ITRIP

R

DC - BUS

Figure 16 Programming the fault clear timer

The design guidelines for this network are shown in Table 7

Table 7

Design guidelines

≤ 1 nF

C_RFE

Ceramic capacitor

0.5 MΩ to 2 MΩ

>> R_ON,RCIN

R_RFE

The length of the fault clear time period can be determined by using the formula below.

v_C(t) = V_f*(1-e^-t/RC

)

t_FLTCLR= - (R_RFE*C_RFE) *ln (1-V_RF+/V_DD) + 160us

The voltage on the RFE pin should not exceed the VDD of the uC power supply.

¹⁾In case VDD is higher than 5V, the R_RFEresistor needs to be at least 200 kΩ in order to limit the IC power

dissipation.

5.10

Over-current protection

The 2ED132xS12 is equipped with an over-current feature (ITIRP input pin). This functionality can sense over-

current events in the DC- bus or low side power switch. Once the HVIC detects an over-current event, the outputs

are shutdown, and RFE is pulled to VSS.

The level of current at which the over-current protection is initiated is determined by the resistor network (i.e.,

R0, R₁, and R2) connected to ITRIP as shown in Figure 17, and the ITRIP threshold (V_th,OCP). The circuit designer will

need to determine the maximum allowable level of current in the DC- bus and select R0, R₁, and R2 such that the

voltage at node VX reaches the over-current threshold (V_th,OCP) at that current level.

Vth,OCP = R0*IDC-*(R1/ (R1+R2))

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2ED1324S12P/2ED1323S12P

1200 V half-bridge gate driver with Active Miller Clamp and Short Circuit Clamp

DC BUS +

VCC

VB

HIN

LIN

RFE

HO

ITRIP

VS

To load

LO

VSS

COM

R2

R1

Vx

R0

DC BUS -

IDC-

Figure 17 Programming the over-current protection

For example, a typical value for resistor R0 could be 50 mΩ. The voltage of the ITRIP pin should not be allowed to

exceed 5 V; if necessary, an external voltage clamp may be used.

5.11

Truth table: Undervoltage lockout, OCP and Enable

Table 8 provides the truth table for the 2ED132xS12. The first line shows that the UVLO for VCC has been tripped;

the RFE output has gone low and the gate drive outputs have been disabled. VCCUV is not latched in this case

and when VCC is greater than VCCUV, the FAULT output returns the driver is functional.

The second case shows that the UVLO for VBS has been tripped and that the high-side gate drive outputs have

been disabled. After VBS exceeds the VBSUV threshold, HO will stay low until the HVIC input receives a new rising

transition of HIN. The third case shows the normal operation of the HVIC. The fourth case illustrates that the OCP

trip threshold has been reached and that the gate drive outputs have been disabled. This condition is stored in

the external RC network waiting for fault clear time. The last case shows when the HVIC has received an external

disable command through the RFE input to shutdown; as a result, the gate drive outputs have been disabled.

Table 8

2ED132xS12 UVLO, OCP, FLT/EN/RCIN

VCC

<

VBS

—

ITRIP

—

RFE

0

LO

0

HO

0

UVLO V_CC

UVLO V_BS

V_CCUV

<

15 V

15V

0 V

HIGH

LIN

0

V_BSUV

Normal

operation

15 V

15V

0 V

HIGH

LIN

0

HIN

0

OCP fault

>V_th,OCP

0 V

0

Disable

command

0

5.12

Daisy Chain Multiple Devices

The 2ED132xS12 can be daisy chained together for applications which require more than one device, such as in

the three phase circuit shown below. In Figure 18, the three 2ED132xS12 RFE pins are connected together. The

ITRIP sensing is only used on the first HVIC; the other two ITRIP pins are disabled by tying them to VSS. The

programmable fault clear timing components, R_RFEand C_RFE, are populated only once for the RFE pin. When a fault

occurs, either from ITRIP or UVLO, or an external command, all three HVICs are disabled via the daisy chained RFE

pin being pulled low to VSS.

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2ED1324S12P/2ED1323S12P

1200 V half-bridge gate driver with Active Miller Clamp and Short Circuit Clamp

DC + BUS

V_CC

HIN U

LIN U

HIN V

LIN V

HIN W

LIN W

V_DD

HIN

LIN

HIN

LIN

uC

HIN

LIN

HO

V_S

HO

V_S

HO

V_S

V

W

To

GK

R_RFE

Load

U

RFE

LO

C_RFE

VSS

ITRIP

R_SH

DC - BUS

Figure 18 Figure 13: Daisy Chain Circuit with Single Shunt

In Figure 19, three of the individual leg currents of the three phases can be measured. The RFE pins are connected

together with the components for the pin only populated for the first HVIC. Three of the ITRIP pins are used to

monitor the three of the individual leg current. A fault can occur by the ITRIP sensing network for either of the

three legs, shutting down all three 2ED132xS12 HVICs, which means all the three phases have over current

protection individually.

DC + BUS

V_CC

HIN U

LIN U

HIN V

LIN V

HIN W

LIN W

V_DD

HIN

LIN

HIN

LIN

uC

HIN

LIN

HO

V_S

HO

V_S

HO

V_S

V

W

To

GK

R_RFE

Load

U

RFE

LO

C_RFE

VSS

ITRIP

R_SH

DC - BUS

Figure 19 Daisy Chain circuit with Leg Shunt

5.13

Bootstrap diode

An ultra-fast bootstrap diode is monolithically integrated for establishing the high side supply. The dynamic

resistor of the diode helps to avoid extremely high inrush currents when initially charging the bootstrap

capacitor. The integrated diode with its resistrance helps save cost and improve reliability by reducing external

components as shown below Figure 20.

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2ED1324S12P/2ED1323S12P

1200 V half-bridge gate driver with Active Miller Clamp and Short Circuit Clamp

Figure 20 2ED132xS12 with integrated components

The low ohmic current limiting resistor provides essential advantages over other competitor devices with high

ohmic bootstrap structures. A low ohmic resistor such as in the 2ED132xS12 allows faster recharging of the

bootstrap capacitor during periods of small duty cycles on the low side transistor. The bootstrap diode is usable

for all kind power electronic converters. The bootstrap diode is a real pn-diode and is temperature robust. It can

be used at high temperatures with a low duty cycle of the low side transistor.

The bootstrap diode of the 2ED132xS12 works with all control algorithms of modern power electronics, such as

trapezoidal or sinusoidal motor drives control.

5.14

Calculating the bootstrap capacitance C_BS

Bootstrapping is a common method of pumping charges from a low potential to a higher one. With this technique

a supply voltage for the floating high side sections of the gate drive can be easily established according to Figure

21. This method has the advantage of being simple and low cost but may force some limitations on duty-cycle

and on-time since they are limited by the requirement to refresh the charge in the bootstrap capacitor. Proper

capacitor choice can reduce drastically these limitations.

I_BS

V_Bus

R_BSD_BS

VB

VCC

C_BS

T1

HO

VS

Gate

Drive

IC

D1

C_VCC

T2

LO

D2

GND

Figure 21 Half bridge bootstrap circuit in 2ED132xS12

When the low side power device turns on, it will force the potential of pin V_Sto GND. The existing difference

between the voltage of the bootstrap capacitor V_CBSand V_CCresults in a charging current I_BSinto the capacitor C_BS.

The current I_BSis a pulse current and therefore the ESR of the capacitor C_BSmust be very small in order to avoid

losses in the capacitor that result in lower lifetime of the capacitor. This pin is on high potential again after low

side is turned off and high side is conducting current. But now the bootstrap diode D_BSblocks a reverse current,

so that the charges on the capacitor cannot flow back to the capacitor C_VCC. The bootstrap diode D_BSalso takes

over the blocking voltage between pin V_Band V_CC. The voltage of the bootstrap capacitor can now supply the high

side gate drive sections. It is a general design rule for the location of bootstrap capacitors C_BS, that they must be

placed as close as possible to the IC. Otherwise, parasitic resistors and inductances may lead to voltage spikes,

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2ED1324S12P/2ED1323S12P

1200 V half-bridge gate driver with Active Miller Clamp and Short Circuit Clamp

which may trigger the undervoltage lockout threshold of the individual high side driver section. However, all

parts of the 2ED132xS12, which have the UVLO also contain a filter at each supply section in order to actively

avoid such undesired UVLO triggers.

The current limiting resistor R_BSaccording to Figure 21 reduces the peak of the pulse current during the low side

power device turn-on. The pulse current will occur at each turn-on of the low side power device, so that with

increasing switching frequency the capacitor C_BSis charged more frequently. Therefore a smaller capacitor is

suitable at higher switching frequencies. The bootstrap capacitor is mainly discharged by two effects: The high

side quiescent current and the gate charge of the high side MOSFET to be turned on.

The minimum size of the bootstrap capacitor is given by

푄_퐺푇푂푇

퐶_퐵푆

=

∆푉_퐵푆

V_BSis the maximum allowable voltage drop at the bootstrap capacitor within a switching period, typically 1 V.

It is recommended to keep the voltage drop below the undervoltage lockout (UVLO) of the high side and limit

V_BS≤ (V_CC– V_F– V_GSmin– V_DSon

)

V_GSmin> V_BSUV-, V_GSminis the minimum gate source voltage we want to maintain and V_BSUV-is the high-side supply

undervoltage negative threshold.

V_CCis the IC voltage supply, V_Fis bootstrapdiode forward voltage and V_DSonis drain-source voltage of low side

power device.

Please note, that the value Q_GTOTmay vary to a maximum value based on different factors as explained below and

the capacitor shows voltage dependent derating behavior of its capacitance.

The influencing factors contributing V_BSto decrease are:

- Power device turn on required Gate charge (Q_G)

- Power device gate-source leakage current (I_{LK_GS}

)

- Floating section quiescent current (I_QBS

- Floating section leakage current (I_LK)

- Bootstrap diode leakage current (I_{LK_DIODE}

- Charge required by the internal level shifters (푄_퐿푆): typical 1nC

- Bootstrap capacitor leakage current (I_{LK_CAP}

)

- High side on time (T_HON

)

Considering the above,

푄_퐺푇푂푇= 푄_퐺+ 푄_퐿푆+ (퐼_ꢀ퐵푆+ 퐼_퐿퐾+ 퐼_퐿퐾+ 퐼_퐿퐾

+ 퐼_퐿퐾) ∗ ꢆ_퐻푂푁

ꢅ퐴푃

ꢁꢂ

퐷ꢃꢄ퐷퐸

I_{LK_CAP}is only relevant when using an electrolytic capacitor and can be ignored if other types of capacitors are

used. It is strongly recommend using at least one low ESR ceramic capacitor (paralleling electrolytic capacitor

and low ESR ceramic capacitor may result in an efficient solution).

The above C_BSequation is valid for pulse by pulse considerations. It is easy to see, that higher capacitance values

are needed, when operating continuously at small duty cycles of low side. The recommended bootstrap

capacitance is therefore in the range up to 4.7 μF for most switching frequencies.

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2ED1324S12P/2ED1323S12P

1200 V half-bridge gate driver with Active Miller Clamp and Short Circuit Clamp

5.15

Tolerant to negative transients on input pins

Typically the driver's ground pin is connected close to the source pin of the power device. The microcontroller

which sends the HIN and LIN PWM signals refers to the same ground and in most cases there will be an offset

voltage between the microcontroller ground pin and driver ground because of ground bounce. The 2ED132xS12

can handle negative voltage spikes up to 5 V. Standard half bridge or high-side/low-side drivers only allow

negative voltage levels down to -0.3 V. The 2ED132xS12 has much better noise immunity capability on the input

pins.

Figure 22 Negative voltage tolerance on inputs of upto –5 V

5.16

Negative voltage transient tolerance of VS pin

A common problem in today’s high-power switching converters is the transient response of the switch node’s

voltage as the power switches transition on and off quickly while carrying a large current. A typical 3-phase

inverter circuit is shown in Figure 23, here we define the power switches and diodes of the inverter.

If the high-side switch (e.g., the IGBT Q1 in Figure 24) switches from on to off, while the U phase current is flowing

to an inductive load, a current commutation occurs from high-side switch (Q1) to the diode (D2) in parallel with

the low-side switch of the same inverter leg. At the same instance, the voltage node V_S1, swings from the positive

DC bus voltage to the negative DC bus voltage.

DC+ BUS

D3

D1

D5

Q1

Q3

Q5

W

V_S3

V

To

Input

Voltage

V_S2

U

Load

V_S1

D4

D2

D6

Q4

Q2

Q6

DC- BUS

Figure 23 Three phase inverter

Also when the V phase current flows from the inductive load back to the inverter (see Figure 24 C) and D)), and

Q4 IGBT switches on, the current commutation occurs from D3 to Q4. At the same instance, the voltage node, V_S2,

swings from the positive DC bus voltage to the negative DC bus voltage.

However, in a real inverter circuit, the VS voltage swing does not stop at the level of the negative DC bus, rather

it swings below the level of the negative DC bus. This undershoot voltage is called “negative V_Stransient”

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2ED1324S12P/2ED1323S12P

1200 V half-bridge gate driver with Active Miller Clamp and Short Circuit Clamp

DC+ BUS

D3

D1

D2

D3

D4

Q1

ON

Q3

OFF

Q1

OFF

Q3

OFF

I_U

I_V

V_S1

V_S2

V_S1

V_S2

I_V

I_U

D2

Q2

OFF

Q4

ON

Q2

OFF

Q4

OFF

DC- BUS

A)

D)

B)

C)

Figure 24 A) Q1 conducting B) D2 conducting

C) D3 conducting

D) Q4 conducting

The circuit shown in Figure 25-A depicts one leg of the three phase inverter; Figure 25-B and Figure 25-C show a

simplified illustration of the commutation of the current between Q1 and D2. The parasitic inductances in the

power circuit from the die bonding to the PCB tracks are lumped together in L_Cand L_Efor each IGBT. When the

high-side switch is on, V_S1is below the DC+ voltage by the voltage drops associated with the power switch and

the parasitic elements of the circuit. When the high-side power switch turns off, the load current momentarily

flows in the low-side freewheeling diode due to the inductive load connected to V_S1(the load is not shown in

these figures). This current flows from the DC- bus (which is connected to the COM pin of the HVIC) to the load

and a negative voltage between V_S1and the DC- Bus is induced (i.e., the COM pin of the HVIC is at a higher potential

than the V_Spin).

DC+ BUS

L_C1

DC+ BUS

+

V_LC1

-

D1

Q1

Q2

Q1

OFF

Q1

ON

+

L_E1

L_C2

I_U

V_LE1

-

V_S1

-

I_U

V_LC2

+

D2

-

Q2

OFF

Q2

OFF

V_D2

+

-

L_E2

DC- BUS

V_LE2

+

DC- BUS

A

DC- BUS

C

B

Figure 25 Figure A shows the Parasitic Elements. Figure B shows the generation of V_Spositive.

Figure C shows the generation of V_Snegative

5.17

NTSOA – Negative Transient Safe Operating Area

In a typical motor drive system, dV/dt is typically designed to be in the range of 3 – 5 V / ns. The negative VS

transient voltage can exceed this range during some events such as short circuit and over-current shutdown,

when di/dt is greater than in normal operation.

Infineon’s HVICs have been designed for the robustness required in many of today’s demanding applications. An

indication of the 2ED132xS12’s robustness can be seen in Figure 26, where the 2ED132xS12’s Safe Operating Area

is shown at V_BS=15 V based on repetitive negative VS spikes. A negative VS transient voltage falling in the grey

area (outside SOA) may lead to IC permanent damage; viceversa unwanted functional anomalies or permanent

damage to the IC do not appear if negative Vs transients fall inside the SOA.

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2ED1324S12P/2ED1323S12P

1200 V half-bridge gate driver with Active Miller Clamp and Short Circuit Clamp

Figure 26 Negative VS transient SOA for 2ED132xS12

Even though the 2ED132xS12 has been shown able to handle these large negative VS transient conditions, it is

highly recommended that the circuit designer always limit the negative VS transients as much as possible by

careful PCB layout and component use.

5.18

Active Miller Clamp

One of the common problems faced when switching an IGBT or SiC MOSFET is parasitic turn-on due to Miller

capacitor. This effect is noticeable in single supply gate drivers (0 to +15 V or 18 V). Due to this gate-collector

coupling, a high dVS/dt transient created during IGBT turn-off can induce parasitic turn-on (Gate voltage, VGE),

which is potentially dangerous (Figure 27).

VBUS

VB

RgH

2ED1324/3S12P

Q1

Q2

HO

HC

VS

dVS/dt

VCC

LO

CGC

Rgext

VGE

Rgint

LC

Low impedance

2 V

COM

Figure 27 Low side IGBT Parasitic Turn-On due to Miller capacitor

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2ED1324S12P/2ED1323S12P

1200 V half-bridge gate driver with Active Miller Clamp and Short Circuit Clamp

When turning on the high side IGBT (Q1) in a half-bridge, a voltage change dVS/dt occurs across the low side IGBT

(Q2). A current flows through the parasitic Miller capacitor CGC of Q2, the gate resistor (Rgext) and internal driver

gate resistor (Rgint). Figure 27 shows the current flow through the capacitor. This current value can be

approximated by the following formula:

dVS

ICGC = C^GCx

dt

This current creates a voltage drop across the gate resistors. If this voltage exceeds the IGBT gate threshold

voltage, a parasitic turn-on occurs. Designers should be aware that rising IGBT chip temperature leads to a slight

reduction of gate threshold voltage, usually in the range of mV/°C. It is even worse for SiC MOSFET because of its

lower VGS threshold .This parasitic turn-on can also be seen on Q1 when Q2 is turned on.

Figure 28 shows an example, the Q2 gate voltage comparison with or without miller clamp. The peak gate voltage

of Q2 is up to 2.7 V without miller clamp during the dVS/dt (4 V/ns) transition. Actually the minimum threshold of

gate voltage is 3.5 V for the SiC MOSFET IMW65R027M1H at T_J= 25 ℃. It is quite marginal to turn on Q2. While if

the gate drive has the miller clamp function, the VGS peak voltage is clamped to less than 0.5 V and far below the

threshold. No parasitic turn-on.

Note:



Blue channel: VS; Yellow channel: VGE of Q2 without miller clamp; White channel: VGE of Q2 with miller clamp

Q1/Q2: CoolSiCTM MOSFET IMW65R027M1H

Tested at room temperature.

Figure 28 VGS with or without Miller clamp

A Miller clamp allows sinking the Miller current across a low impedance path in this high dVS/dt situation.

Therefore in many applications, the use of a negative supply voltage can be avoided.

During turn-off, the gate voltage is monitored and the clamp output is activated when the gate voltage goes

below typical VCLAMP = 2.0 V. The clamp is designed for a Miller current up to ICLAMPL = 2.0 A.

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1200 V half-bridge gate driver with Active Miller Clamp and Short Circuit Clamp

5.19

Short Circuit Clamp

Figure 29 shows 2ED1324/3S12P integrated short circuit clamping diode, which limits the IGBT gate over voltage

during a short circuit (Low side IGBT Q2 is on, then high side IGBT Q1 unintentionally turns on, vice versa). The

over voltage is typically triggered by the capacitive feedback of the Miller capacitor by dVS/dt. The internal

clamping diode connected to LC/HC limits this voltage to a value slightly higher than the supply voltage. These

diode paths are rated for a maximum current of 0.5 A and the duration of 10 µs. Add an external Schottky diode

if higher currents are expected or a tighter clamping is desired.

VBUS

VB

RgH

2ED1324/3S12P

Q1

Q2

HO

HC

VS

dVS/dt

VCC

LO

on

Rg

LC

^{2 V}off

COM

Figure 29 Short circuit clamping circuitry

5.20

PCB layout tips

Distance between high and low voltage components: It’s strongly recommended to place the components tied

to the floating voltage pins (V_Band V_S) near the respective high voltage portions of the device. Please see the

Case Outline information in this datasheet for the details.

Ground Plane: In order to minimize noise coupling, the ground plane should not be placed under or near the high

voltage floating side.

Gate Drive Loops: Current loops behave like antennas and are able to receive and transmit EM noise (see Figure

30). In order to reduce the EM coupling and improve the power switch turn on/off performance, the gate drive

loops must be reduced as much as possible. Moreover, current can be injected inside the gate drive loop via the

IGBT collector-to-gate parasitic capacitance. The parasitic auto-inductance of the gate loop contributes to

developing a voltage across the gate-emitter, thus increasing the possibility of a self turn-on effect.

Datasheet

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2ED1324S12P/2ED1323S12P

1200 V half-bridge gate driver with Active Miller Clamp and Short Circuit Clamp

Figure 30 Avoid antenna loops

Supply Capacitor: It is recommended to place a bypass capacitor (C_IN) between the V_CCand COM pins. A ceramic

1μF ceramic capacitor is suitable for most applications. This component should be placed as close as possible

to the pins in order to reduce parasitic elements.

Routing and Placement: Power stage PCB parasitic elements can contribute to large negative voltage transients

at the switch node; it is recommended to limit the phase voltage negative transients. In order to avoid such

conditions, it is recommended to 1) minimize the high-side emitter to low-side collector distance, and 2)

minimize the low-side emitter to negative bus rail stray inductance. However, where negative VS spikes remain

excessive, further steps may be taken to reduce the spike. This includes placing a resistor (5 Ω or less) between

the VS pin and the switch node (see Figure 31 - A), and in some cases using a clamping diode between COM and

V_S(see Figure 31 - B). See DT04-4 at www.infineon.com for more detailed explanations.

Figure 31 Resistor between the VS pin and the switch node and clamping diode between

COM and V_S

Datasheet

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2ED1324S12P/2ED1323S12P

1200 V half-bridge gate driver with Active Miller Clamp and Short Circuit Clamp

6

Qualification information¹

Table 9

Qualification information

Industrial²

Note: This family of ICs has passed JEDEC’s Industrial

qualification. Consumer qualification level is granted by

extension of the higher Industrial level.

Qualification level

MSL2a³, 260°C

Moisture sensitivity level

ESD

PG-DSO-20-U03

(per IPC/JEDEC J-STD-020)

Class C3 (1.0 kV)

(per JESD22-C101)

Class 2 (2 kV)

Charged device model

Human body model

(per JEDEC standard JESD22-A115)

Class II Level A

(per JESD85)

Yes

IC latch-up test

RoHS compliant

¹Qualification standards can be found at Infineon’s web site www.infineon.com

²Higher qualification ratings may be available should the user have such requirements. Please contact your Infineon sales

representative for further information.

³Higher MSL ratings may be available for the specific package types listed here. Please contact your Infineon sales representative for

further information.

Datasheet

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1200 V half-bridge gate driver with Active Miller Clamp and Short Circuit Clamp

7

型号	制造商	描述	价格	文档
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