M5LV-320/120-12VC中文资料_数据手册_规格书

MACH 5 CPLD Family

Fifth Generation MACH Architecture

FEATURES

High logic densities and I/Os for increased logic integration

— 128 to 512 macrocell densities

— 68 to 256 I/Os

Wide selection of density and I/O combinations to support most application needs

— 6 macrocell density options

— 7 I/O options

— Up to 4 I/O options per macrocell density

— Up to 5 density & I/O options for each package

Performance features to ﬁt system needs

— 5.5 ns t Commercial, 7.5 ns t Industrial

PD

— 182 MHz f

CNT

— Four programmable power/speed settings per block

Flexible architecture facilitates logic design

— Multiple levels of switch matrices allow for performance-based routing

— 100% routability and pin-out retention

— Synchronous and asynchronous clocking, including dual-edge clocking

— Asynchronous product- or sum-term set or reset

— 16 to 64 output enables

— Functions of up to 32 product terms

Advanced capabilities for easy system integration

— 3.3-V & 5-V JEDEC-compliant operations

— IEEE 1149.1 compliant for boundary scan testing

— 3.3-V & 5-V in-system programmable via IEEE 1149.1 Boundary Scan Test Access Port

— PCI compliant (-5/-6/-7/-10/-12 speed grades)

— Safe for mixed supply voltage system design

— Bus-Friendly™ Inputs & I/Os

— Individual output slew rate control

— Hot socketing

— Programmable security bit

2

Advanced E CMOS process provides high performance, cost effective solutions

Supported by ispDesignEXPERT™ softw are for rapid logic development

— Supports HDL design methodologies with results optimized for MACH 5 devices

— Flexibility to adapt to user requirements

— Software partnerships that ensure customer success

Lattice and Third-party hardw are programming support

— LatticePRO™ software for in-system programmability support on PCs and Automated Test

Equipment

— Programming support on all major programmers including Data I/O, BP Microsystems, Advin,

and System General

Publication# 20446

Amendment/0

Rev: I

Issue Date: September 2000

1

Table 1 . MACH 5 Device Features

M5-128/1

M5LV-128

M5-192/1

M5-256/1

M5LV-256

M5-320

M5LV-320

M5-384

M5LV-384

M5-512

M5LV-512

Feature

Supply Voltage (V)

5

3.3

5

3.3

5

3.3

5

3.3

5

3.3

Macrocells

128

120

5.5

3.0

4.5

182

35

128

120

5.5

3.0

4.5

182

35

192

120

5.5

3.0

4.5

182

45

256

160

5.5

3.0

4.5

182

55

256

160

5.5

3.0

4.5

182

55

320

192

320

192

384

160

384

192

512

256

512

256

Maximum User I/O Pins

2

t

(ns)

6.5

PD

2

t (ns)

3.0

SS

2

t

(ns)

5.0

COS

2

f

(MHz)

167

70

167

70

167

75

167

75

167

100

Yes

167

100

Yes

CNT

Typical Static Power (mA)

IEEE 1149.1 Boundary Scan Compliant

PCI-Compliant

Yes

Note:

1. “M5-xxx” is for 5-V devices. “M5LV-xxx” is for 3.3-V devices.

2. Preliminary speciﬁcations for new 6.5ns (Tpd) speed grade. 7.5ns speed grade in production now.

GENERAL DESCRIPTION

®

The MACH 5 family consists of a broad range of high-density and high-I/O Complex

Programmable Logic Devices (CPLDs). The ﬁfth-generation MACH architecture yields fast speeds

at high CPLD densities, low power, and supports additional features such as in-system

programmability, Boundary Scan testability, and advanced clocking options (Table 1). The MACH

5 family offers 5-V (M5-xxx) and 3.3-V (M5LV-xxx) operation.

2

Manufactured in state-of-the-art ISO 9000 qualiﬁed fabrication facilities on E CMOS process

technologies, MACH 5 devices are available with pin-to-pin delays as fast as 5.5 ns (Table 2). The

5.5, 6.5, 7.5, 10, and 12-ns devices are compliant with the PCI Local Bus Speciﬁcation.

2

MACH 5 Family

Table 2. MACH 5 Speed Grades

1

Speed Grade

-10

Device

-5

-6

-7

C

-12

C, I

-15

C, I

I

-20

2

M5-128

C, I

I

M5-128/1

M5LV-128

M5-192/1

C

C, I

C,I

C, I

C

C, I

I

2

M5-256

C, I

M5-256/1

M5LV-256

M5-320

C

C, I

C

C, I

I

M5LV-320

M5-384

C, I

3

C

C, I

3

M5LV-384

M5-512

C

C, I

3

C

C, I

3

M5LV-512

C

C, I

Note:

1. C = Commercial grade, I = Industrial grade

2. /1 version recommended for new designs

3. Preliminary speciﬁcatons

With Lattice’s unique hierarchical architecture, the MACH 5 family provides densities up to 512

macrocells to support full system logic integration. Extensive routing resources ensure pinout

®

retention as well as high utilization. It is ideal for PAL block device integration and a wide range

of other applications including high-speed computing, low-power applications, communications,

and embedded control. At each macrocell density point, Lattice offers several I/O and package

options to meet a wide range of design needs (Table 3).

1

Table 3. MACH 5 Package and I/O Options

M5-128/1

M5LV-128

M5-256/1

M5LV-256

M5-320

M5LV-320

M5-384

M5LV-384

M5-512

M5LV-512

M5-192/1

Supply Voltage

100-pin TQFP

100-pin PQFP

144-pin TQFP

144-pin PQFP

160-pin PQFP

208-pin PQFP

240-pin PQFP

256-ball BGA

352-ball BGA

5

3.3

68, 74

68*

5

3.3

68*, 74

68

5

3.3

5

3.3

5

3.3

68

68*

104

120

104*

120

104*

120

104*

120

104*

120

120*

160

120

160

120*

160

120

160

120*

160

120

160

184*

192

184*

192*

184*

192*

184*

192*

184*

192*

256

184*

192*

256

Note:

1. The I/O options indicated with a “*” are obsolete, please contact factory for more information.

MACH 5 Family

3

Advanced power management options allow designers to incrementally reduce power while

maintaining the level of performance needed for today’s complex designs. I/O safety features

allow for mixed-voltage design, and both the 3.3-V and the 5-V device versions are in-system

programmable through an IEEE 1149.1 Test Access Port (TAP) interface.

FUNCTIONAL DESCRIPTION

The MACH 5 architecture consists of PAL blocks connected by two levels of interconnect. The block

interconnect provides routing among 4 PAL blocks. This grouping of PAL blocks joined by the

block interconnect is called a segment. The second level of interconnect, the segment

interconnect, ties all of the segments together. The only logic difference between any two MACH

5 devices is the number of segments. Therefore, once a designer is familiar with one device,

consistent performance can be expected across the entire family. All devices have four clock pins

available which can also be used as logic inputs.

CLK

Block:

16 MCs

4

Segment:

4 Blocks

Segment Interconnect

20446G-001

Figure 1. MACH 5 Block Diagram

The MACH 5 PAL blocks consist of the elements listed below (Figure 2). While each PAL block

resembles an independent PAL device, it has superior control and logic generation capabilities.

I/O cells

Product-term array and Logic Allocator

Macrocells

Register control generator

Output enable generator

I/O Cells

The I/Os associated with each PAL block have a path directly back to that PAL block called local

feedback. If the I/O is used in another PAL block, the interconnect feeder assigns a block interconnect

line to that signal. The interconnect feeder acts as an input switch matrix. The block and segment

interconnects provide connections between any two signals in a device. The block feeder assigns

block interconnect lines and local feedback lines to the PAL block inputs.

4

MACH 5 Family

2

OE Generator

Control Generator

32

Block

Feeder

16

Product-term

Array

Input Register

Path

2

32

Interconnect Feeder

20446G-002

Figure 2. PAL Block Structure

Product-Term Array and Logic Allocator

The product-term array uses the same sum-of-products architecture as PAL devices and consists of

32 inputs (plus their complements) and 64 product terms arranged in 16 clusters. A cluster is a sum-

of-products function with either 3 of 4 product terms.

Logic allocators assign the clusters to macrocells. Each macrocell can accept up to eight clusters of

three or four product terms, but a given cluster can only be steered to one macrocell (Table 4). If

only three product terms in a cluster are steered, the fourth can be used as an input to an XOR

gate for separate logic generation and/or polarity control.

The wide logic allocator is comprised of all 16 of the individual logic allocators and acts as an output

switch matrix by reassigning logic to macrocells to retain pinout as designs change. The logic

allocation scheme in the MACH 5 device allows for the implementation of large equations (up to

32 product terms) with only one pass through the logic array.

Table 4. Product Term Steering Options for PT Clusters and Macrocells

Macrocell

Available Clusters

C , C , C , C , C

Macrocell

Available Clusters

C , C , C , C , C , C , C , C

10 11 12

M

8

0

1

2

3

4

5

6

7

8

9

M

C , C , C , C , C , C

M

C , C , C , C , C , C , C , C

6 7 8 9 10 11 12 13

1

0

1

2

3

4

5

9

M

C , C , C , C , C , C , C

M

C , C , C , C , C , C , C , C

7 8 9 10 11 12 13 14

2

0

1

2

3

4

5

6

10

M

C , C , C , C , C , C , C , C

M

C , C , C , C , C , C , C , C

8 9 10 11 12 13 14 15

3

0

1

2

3

4

5

6

7

11

M

C , C , C , C , C , C , C , C

M

C , C , C , C , C , C , C , C

8 9 10 11 12 13 14 15

4

0

1

2

3

4

5

6

7

12

M

C , C , C , C , C , C , C , C

M

C , C , C , C , C , C , C

9 10 11 12 13 14 15

5

1

2

3

4

5

6

7

8

13

M

C , C , C , C , C , C , C , C

M

C , C , C , C , C , C

10 11 12 13 14 15

6

2

3

4

5

6

7

8

9

14

M

C , C , C , C , C , C , C , C

M

C , C , C , C , C

11 12 13 14 15

7

3

4

5

6

7

8

9

10

15

MACH 5 Family

5

Macrocells

The macrocells for MACH 5 devices consist of a storage element which can be conﬁgured for

combinatorial, registered or latched operation (Figure 3). The D-type ﬂip-ﬂops can be conﬁgured

as T-type, J-K, or S-R operation through the use of the XOR gate associated with each macrocell.

Each PAL block has the capability to provide two input registers by using macrocells 0 and 15. In

order to use this option, these macrocells must be accessed via the I/O pins associated with

macrocells 3 and 12, respectively. Once the macrocell is used as an input register, it cannot be used

for logic, so its clusters can be re-directed through the logic allocator to another macrocell. The

I/O pins associated with macrocells 0 and 15 can still be used as input pins. Although the I/O pins

for macrocells 3 and 12 are used to connect to the input registers, these macrocells can still be

used as “buried” macrocells to drive device logic via the matrix.

Macrocell

Logic

Allocator

5-8

Clusters/

MC

Q

D

Prog. Polarity

Mode

Selection

20446G-003

Figure 3. Macrocell Diagram

Control Generator

The control generator provides four conﬁgurable clock lines and three conﬁgurable set/reset lines to

each macrocell in a PAL block. Any of the four clock lines and any of the three set/reset lines can

be independently selected by any ﬂip-ﬂop within a block. The clock lines can be conﬁgured to

provide synchronous global (pin) clocks and asynchronous product term clocks, sum term clocks,

and latch enables (Figure 4). Three of the four global clocks, as well as two product-term clocks

and one sum-term clock, are available per PAL block. Positive or negative edge clocking is

available as well as advanced clocking features such as complementary and biphase clocking.

Complementary clocking provides two clock lines exactly 180 degrees out of phase, and is useful

in applications such as fast data paths. A biphase clock line clocks ﬂip-ﬂops on both the positive

and negative edges of the clock. The conﬁguration options for the four clock lines per PAL block

are as follows:

Clock Line 0 Options

Global clock (0, 1, 2, or 3) with positive or negative edge clock enable

Product-term clock (A*B*C)

Sum-term clock (A+B+C)

6

MACH 5 Family

Clock Line 1 Options

Global clock (0, 1, 2, or 3) with positive edge clock enable

Global clock (0, 1, 2, or 3) with negative edge clock enable

Global clock (0, 1, 2, or 3) with positive and negative edge clock enable (biphase)

Clock Line 2 Options

Global clock (0, 1, 2, or 3) with clock enable

Clock Line 3 Options

Complement of clock line 2 (same clock enable)

Product-term clock (if clock line 2 does not use clock enable

PT (0:3)

PINCLK (0:3)

MUX 4TO1

0

1

2

3

IN (0)

IN (1)

IN (2)

IN (3)

U1

MUX 2TO1

/CLK

CLKIN

Clock Enable

N (0)

OUT

CLK0

PT0

N (1)

F0

F1

PT (0:2)

SET0/RST0

SET1/RST1

PT0

PT1

MUX 4TO1

0

1

2

3

/CLK

CLK

IN (0)

IN (1)

IN (2)

MUX 2TO1

CLK1

OUT

PT1

OUT

IN (3)

U2

PT1

PT2

CLKEN1

BIPHASE

CLKEN2

/PT1(ST)

F0

F1

F0

MUX 2TO1

PT2

MUX 4TO1

PT2

SET2/RST2/LE

0

1

2

3

OUT

IN (0)

IN (1)

IN (2)

CLK2

/PT2

OUT

CLKIN

Clock Enable

F0

IN (3)

U3

Block

Sets/Reset

0–2, LE

F0

F1

MUX

2TO1

PT3

MUX 2TO1

/CLK2

CLK3

PTCLK

F0

Block

Clocks

0–3

20446G-004

20446G-005

Figure 4. Clock Generator

Figure 5. Set/Reset Generator

The set/reset generation portion of the control generator (Figure 5) creates three set/reset lines for

the PAL block. Each macrocell can choose one of these three lines or choose no set/reset at all.

All three lines can be conﬁgured for product term set/reset and two of the three lines can be

conﬁgured as sum term set/reset and one of the lines can be conﬁgured as product-term or sum-

term latch enable. While the set/reset signals are generated in the control generator, whether that

signal sets or resets a ﬂip-ﬂop is determined within the individual macrocell. The same signal can

set one ﬂip-ﬂop and reset another. PT2 or /PT2 can also be used as a latch enable for macrocells

conﬁgured as latches.

MACH 5 Family

7

OE Generator

There is one output enable (OE) generator per PAL block that generates two product-term driven

output enables. Each I/O cell is simply an output buffer. Each I/O cell within the PAL block can

choose to be permanently enabled, permanently disabled, or choose one of the two product term

output enables per PAL block (Figure 6).

Output Enable

Generator

V_CC

Internal Feedback

External Feedback

20446G-006

Figure 6. Output Enable Generator and I/O Cell

8

MACH 5 Family

MACH 5 TIMING MODEL

The primary focus of the MACH 5 timing model is to accurately represent the timing in a MACH 5

device, and at the same time, be easy to understand. This model accurately describes all

combinatorial and registered paths through the device, making a distinction between internal

feedback and external feedback. A signal uses internal feedback when it is fed back into the switch

matrix or block without having to go through the output buffer. The input register speciﬁcations

are also reported as internal feedback. When a signal is fed back into the switch matrix after having

gone through the output buffer, it is using external feedback.

The parameter, t , is deﬁned as the time it takes to go through the output buffer to the I/O pad.

BUF

If a signal goes to the internal feedback rather than to the I/O pad, the parameter designator is

followed by an “i”. By adding t

to this internal parameter, the external parameter is derived.

BUF

For example, t = t

+ t . A diagram representing the modularized MACH 5 timing model is

PD

PDi

BUF

shown in Figure 7. Refer to the Technical Note entitled MACH 5 Timing and High Speed Design

for a more detailed discussion about the timing parameters.

(External Feedback)

(Internal Feedback)

COMB/DFF/

LATCH

t_SLW

IN

OUT

t_{S (S/A)}

t_{H (S/A)}

t_SAL

t_HAL

t_SRR

t_PDi

t_{CO (S/A) i}

t_PDLi

t_GOAi

t_SRi

t_BUF

Q

t_PL1

t_PL2

t_PL3

INPUT REG/

INPUT LATCH

t_BLK

t_SEG

t_CES

t_CEH

t_PT

t_{SIR (S/A)}

t_{HIR (S/A)}

t_SIL

t_{CO (S/A) i}

Q

t_EA

t_ER

t_PDILi

t_GOAi

t_SRi

CE

SR

t_HIL

t_SRR

t_CES

t_CEH

CE

SR

PIN CLK

20446G-014

Figure 7. MACH 5 Timing Model

MACH 5 Family

9

MULTIPLE I/O AND DENSITY OPTIONS

The MACH 5 family offers six macrocell densities in a number of I/O options. This allows designers

to choose a device close to their logic density and I/O requirements, thus minimizing costs. For

the same package type, every density has the same pin-out. With proper design considerations, a

design can be moved to a higher or lower density part as required.

IEEE 1149.1 - COMPLIANT BOUNDARY SCAN TESTABILITY

Most MACH 5 devices have boundary scan registers and are compliant to the IEEE 1149.1 standard.

This allows functional testing of the circuit board on which the device is mounted through a serial

scan path that can access all critical logic nodes. Internal registers are linked internally, allowing

test data to be shifted in and loaded directly onto test nodes, or test node data to be captured and

shifted out for veriﬁcation. In addition, these devices can be linked into a board-level serial scan

path for more complete board-level testing.

IEEE 1149.1 - COMPLIANT IN-SYSTEM PROGRAMMING

Programming devices in-system provides a number of signiﬁcant beneﬁts including: rapid

prototyping, lower inventory levels, higher quality, and the ability to make in-ﬁeld modiﬁcations.

All MACH 5 devices provide in-system programming (ISP) capability through their IEEE 1149.1-

compliant Boundary Scan Test Access Port. By using the IEEE 1149.1-compliant Boundary Scan

Test Access Port as the communication interface through which ISP is achieved, customers get the

beneﬁt of a standard, well-deﬁned interface.

MACH 5 devices can be programmed across the commercial temperature and voltage range. The

PC-based LatticePRO software facilitates in-system programming of MACH 5 devices. LatticePRO

software takes the JEDEC ﬁle output produced by design implementation software, along with

information about the Boundary Scan chain, and creates a set of vectors that are used to drive the

Boundary Scan chain. LatticePRO software can use these vectors to drive a Boundary Scan chain

via the parallel port of a PC. Alternatively, LatticePRO software can output ﬁles in formats

understood by common automated test equipment. This equipment can then be used to program

MACH 5 devices during the testing of a circuit board.

PCI COMPLIANT

MACH 5 devices in the -5/-6/-7/-10/-12 speed grades are compliant with the PCI Local Bus

Speciﬁcation version 2.1, published by the PCI Special Interest Group (SIG). The 5-V devices are

fully PCI-compliant. The 3.3-V devices are mostly compliant but do not meet the PCI condition to

clamp the inputs as they rise above V because of their 5-V input tolerant feature. MACH 5

CC

devices provide the speed, drive, density, output enables and I/Os for the most complex PCI

designs.

10

MACH 5 Family

SAFE FOR MIXED SUPPLY VOLTAGE SYSTEM DESIGNS ¹

Both the 3.3-V and 5-V V MACH 5 devices are safe for mixed supply voltage system designs.

CC

The 5-V devices will not overdrive 3.3-V devices above the output voltage of 3.3 V, while they

accept inputs from other 3.3-V devices. The 3.3-V devices will accept inputs up to 5.5 V. Both the

3.3-V and 5-V versions have the same high-speed performance and provide easy-to-use mixed-

voltage design capability.

Note:

1. Excludes original M5-128, M5-192, and M5-256 while M5-128/1, M3-192/1 and M5-256/1 are supported. Please refer to

Application Note titled “Hot Socketing and Mixed Supply Design with MACH 4 and MACH 5 Devices”.

BUS-FRIENDLY INPUTS AND I/OS

All MACH 5 devices have inputs and I/Os which feature the Bus-Friendly circuitry incorporating

two inverters in series which loop back to the input. This double inversion weakly holds the input

at its last driven logic state. While it is a good design practice to tie unused pins to a known state,

the Bus-Friendly input structure pulls pins away from the input threshold voltage where noise can

cause high-frequency switching. At power-up, the Bus-Friendly latches are reset to a logic level

“1.” For the circuit diagram, please refer to the document entitled MACH Endurance

Characteristics on the Lattice Data Book CD-ROM or Lattice web site.

POWER MANAGEMENT

There are 4 power/speed options in each MACH 5 PAL block (Table 5). The speed and power

tradeoff can be tailored for each design. The signal speed paths in the lower-power PAL blocks

will be slower than those in the higher-power PAL blocks. This feature allows speed critical paths

to run at maximum frequency while the rest of the signal paths operate in a lower-power mode.

In large designs, there may be several different speed requirements for different portions of the

design.

Table 5. Power Levels

High Speed/High Power

100% Power

67% Power

40% Power

20% Power

Medium High Speed/Medium High Power

Medium Low Speed/Medium Low Power

Low Speed/Low Power

PROGRAMMABLE SLEW RATE

Each MACH 5 device I/O has an individually programmable output slew rate control bit. Each

output can be individually conﬁgured for the higher speed transition (3 V/ns) or for the lower

noise transition (1 V/ns). For high-speed designs with long, unterminated traces, the slow-slew rate

will introduce fewer reﬂections, less noise, and keep ground bounce to a minimum. For designs

with short traces or well terminated lines, the fast slew rate can be used to achieve the highest

speed. The slew rate is adjusted independent of power.

POWER-UP RESET/SET

All ﬂip-ﬂops power up to a known state for predictable system initialization. If a macrocell is

conﬁgured to SET on a signal from the control generator, then that macrocell will be SET during

device power-up. If a macrocell is conﬁgured to RESET on a signal from the control generator or

is not conﬁgured for set/reset, then that macrocell will RESET on power-up. To guarantee

MACH 5 Family

11

initialization values, the V rise must be monotonic and the clock must be inactive until the reset

CC

delay time has elapsed.

SECURITY BIT

A programmable security bit is provided on the MACH 5 devices as a deterrent to unauthorized

copying of the array conﬁguration patterns. Once programmed, this bit defeats readback of the

programmed pattern by a device programmer, securing proprietary designs from competitors.

Programming and veriﬁcation are also defeated by the security bit. The bit can only be reset by

erasing the entire device.

12

MACH 5 Family

MACH 5 PAL BLOCK

0

4

8

12 16 20 24

28 32 36 40 44 48

52 56 60 63

Output Enable

Macro

cell

I/O

Cell

I/O

M₀

Macro

cell

I/O

M₁

M₂

Cell

Macro

cell

I/O

Cell

Macro

cell

I/O

Cell

M₃

M₄

0

C₀

C₁

C₂

C₃

C₄

C₅

C₆

C₇

C₈

Macro

cell

I/O

Cell

Macro

cell

I/O

M₅

M₆

M₇

M₈

M₉

Cell

Macro

cell

I/O

Cell

Switch

Matrix

Macro

cell

I/O

Cell

I/O

Macro

cell

I/O

Cell

C₉

C₁₀

C₁₁

C₁₂

C₁₃

C₁₄

C₁₅

Macro

cell

I/O

Cell

I/O

Macro

cell

I/O

Cell

I/O

M₁₀

M₁₁

M₁₂

Macro

cell

I/O

Cell

63

Macro

cell

I/O

Cell

Macro

cell

I/O

M₁₃

M₁₄

M₁₅

Cell

Macro

cell

I/O

Cell

Macro

cell

I/O

Cell

16

7

Control

Generator

0

4

8

12 16 20 24

28 32 36 40 44 48

52 56 60 63

4

32

20446G-015

CLK

MACH 5 Family

13

BLOCK DIAGRAM — M5(LV)-128/XXX

SEGMENT 0

Block A/Macrocells 0-15

Block D/Macrocells 0-15

16

I/O Cells

2 PT OE

Control

2 PT OE

Control

2

16

Generator

Macrocells

7

32

64 PT

7 PT

64 PT

7 PT

64 x 73

AND Logic Array

and Logic Allocator

32

I

0, 1

Block Interconnect

2

64 x 73

AND Logic Array

and Logic Allocator

AND Logic Array

and Logic Allocator

7 PT

64 PT

7 PT

64 PT

32

16

32

Macrocells

Control

Generator

Macrocells

Control

Generator

7

2

16

2

16

2 PT OE

I/O Cells

16

I/O Cells

16

Block C/Macrocells 0-15

Block B/Macrocells 0-15

CLK0

CLK1

CLK2

CLK3

S E G M E N T I N T E R C O N N E C T

4

Block A/Macrocells 0-15

Block D/Macrocells 0-15

16

I/O Cells

2 PT OE

Control

2 PT OE

Control

2

16

Generator

Macrocells

7

32

64 PT

7 PT

64 PT

7 PT

64 x 73

AND Logic Array

64 x 73

AND Logic Array

and Logic Allocator

32

I

2, 3

Block Interconnect

2

64 x 73

AND Logic Array

and Logic Allocator

AND Logic Array

and Logic Allocator

7 PT

64 PT

7 PT

64 PT

32

16

32

Macrocells

Control

Generator

Macrocells

Control

Generator

7

2

16

2

16

2 PT OE

I/O Cells

16

I/O Cells

16

Block B/Macrocells 0-15

Block C/Macrocells 0-15

SEGMENT 1

20446G-007

14

MACH 5 Family

BLOCK DIAGRAM — M5-192/XXX

20446G-008

MACH 5 Family

15

BLOCK DIAGRAM — M5(LV)-256/XXX

20446G-009

16

MACH 5 Family

BLOCK DIAGRAM — M5(LV)-320/XXX

20446G-010

MACH 5 Family

17

BLOCK DIAGRAM — M5(LV)-384/XXX

20446G-011

18

MACH 5 Family

BLOCK DIAGRAM — M5(LV)-512/XXX

Continued

20446G-012

MACH 5 Family

19

BLOCK DIAGRAM — M5(LV)-512/XXX

Continued

20446G-013

20

MACH 5 Family

ABSOLUTE MAXIMUM RATINGS

OPERATING RANGES

M5

Commercial (C) Devices

Storage Temperature . . . . . . . . . . . . . .-65°C to +150°C

Ambient Temperature (T )

A

Operating in Free Air . . . . . . . . . . . . . . . 0°C to +70°C

Device Junction

Temperature (Note 1) . . . . . . . . . . . +130°C or +150°C

Supply Voltage

Supply Voltage (V )

with Respect to Ground . . . . . . . . . +4.75 V to +5.25 V

CC

with Respect to Ground . . . . . . . . . . . -0.5 V to +7.0 V

Industrial (I) Devices

DC Input Voltage . . . . . . . . . . . . . . . . . -0.5 V to 5.5 V

Static Discharge Voltage . . . . . . . . . . . . . . . . . 2000 V

Latchup Current (-40°C to +85°C) . . . . . . . . . . 200 mA

Ambient Temperature (T )

A

Operating in Free Air . . . . . . . . . . . . . . -40°C to +85°C

Supply Voltage (V )

CC

with Respect to Ground . . . . . . . . . . . +4.5 V to +5.5 V

Str esses a bove those listed u n der Absolu te Ma ximu m

Ratings may cause permanent device failure. Functionality at

or a bove these limits is not implied. Exposure to Absolute

Ma ximum Ra tings for extended periods ma y a ffect device

reliability.

Operating ranges deﬁne those limits between which the

functionality of the device is guaranteed.

5-V DC CHARACTERISITICS OVER OPERATING RANGES

Parameter

Symbol

Parameter Description

Output HIGH Voltage

Test Description

= -3.2 mA, V = Min, V = V or V

IL

Min Typ Max

Unit

I

2.4

V

OH

CC

IN

IH

(For M5-128/1, M5-192/1, M5-256/1, M5-320,

M5-384, M5-512 Devices)

I

= 0 mA, V = Max, V = V or V

IL

3.3

V

OH

CC

IN

IH

V

OH

I

= -3.2 mA, V = Min, V = V or V

IL

2.4

3.6

0.5

V

Output HIGH Voltage

OH

CC

IN

IH

(For M5-128, M5-192, M5-256 Devices)

I

= -2.5 mA, V = 5.25 V, V = V or V

CC IN IH IL

OH

V

Output LOW Voltage (Note 2)

Input HIGH Voltage

I = +16 mA, V = Min, V = V or V

OL CC IN IH IL

OL

Guaranteed Input Logical HIGH Voltage for all Inputs

(Note 3)

V

2.0

V

IH

Guaranteed Input Logical LOW Voltage for all Inputs

(Note 3)

V

Input LOW Voltage

0.8

IL

I

Input HIGH Leakage Current

V = 5.25, V = Max (Note 4)

10

-10

10

µA

mA

IH

IN

CC

I

Input LOW Leakage Current

V = 0, V = Max (Note 4)

IN CC

IL

I

Off-State Output Leakage Current HIGH

Off-State Output Leakage Current LOW

Output Short-Circuit Current

V

= 5.25, V = Max, V = V or V (Note 4)

OZH

OUT CC IN IH IL

I

V

= 0, V = Max, V = V or V (Note 4)

-10

OZL

OUT

CC

IN

IH

IL

I

V

= 0.5 V = Max, V = V or V (Note 5)

-30

-180

SC

OUT

CC

IN

IH

IL

Note:

1. 150° for M5-128, M5-192 and M5-256 devices. 130° for M5-128/1, M5-192/1, M5-256/1, M5-320, M5-384 and M5-512 devices.

2. Total I between ground pins should not exceed 64 mA.

OL

3. These are absolute values with respect to device ground, and all overshoots due to system and/or tester noise are included.

4. I/O pin leakage is the worst case of I and I

or I and I

.

IL

OZL

IH

OZH

5. Not more than one output should be shorted at a time. Duration of the short-circuit should not exceed one second.

MACH 5 Family

21

ABSOLUTE MAXIMUM RATINGS

OPERATING RANGES

M5LV

Commercial (C) Devices

Storage Temperature . . . . . . . . . . . . . .-65°C to +150°C

Device Junction Temperature . . . . . . . . . . . . . +130°C

Ambient Temperature (T )

Operating in Free Air . . . . . . . . . . . . . . . 0°C to +70°C

A

Supply Voltage (V )

with Respect to Ground . . . . . . . . . . . +3.0 V to +3.6 V

CC

Supply Voltage

with Respect to Ground . . . . . . . . . . . -0.5 V to +4.5 V

Industrial (I) Devices

DC Input Voltage . . . . . . . . . . . . . . . . . -0.5 V to 5.5 V

Static Discharge Voltage . . . . . . . . . . . . . . . . . 2000 V

Latchup Current (-40°C to +85°C) . . . . . . . . . . 200 mA

Ambient Temperature (T )

A

Operating in Free Air . . . . . . . . . . . . . . -40°C to +85°C

Supply Voltage (V )

with Respect to Ground . . . . . . . . . . . +3.0 V to +3.6 V

CC

Str esses a bove those listed u n der Absolu te Ma ximu m

Ratings may cause permanent device failure. Functionality at

or a bove these limits is not implied. Exposure to Absolute

Ma ximum Ra tings for extended periods ma y a ffect device

reliability.

Operating ranges deﬁne those limits between which the

functionality of the device is guaranteed.

3.3-V DC CHARACTERISITICS OVER OPERATING RANGES

Parameter

Symbol

Parameter Description

Output HIGH Voltage

Test Description

Min

Max

Unit

V

V = Min

I

= -100 µA

I = 3.2 mA

OH

V -0.2

CC

OH

CC

V

OH

V = V

V

2.4

V

IN

IH or IL

I

= 100 µA

0.2

0.5

5.5

0.8

10

V

V = Min

OL

CC

V

Output LOW Voltage

OL

V = V

V

I

= 16 mA (Note 1)

V

IN

IH or IL

OL

V

Input HIGH Voltage

V

≥ V Min or V ≤ V Max (Note 2)

2.0

V

IH

OUT

OH

OUT

OL

V

Input LOW Voltage

V

≥ V Min or V ≤ V Max (Note 2)

-0.3

V

IL

OUT

OH

OUT

OL

I

Input HIGH Leakage Current

Input LOW Leakage Current

Off-State Output Leakage Current HIGH

Off-State Output Leakage Current LOW

Output Short-Circuit Current

V = 3.6, V = Max (Note 3)

µA

mA

IH

IN

CC

I

V = 0, V = Max (Note 3)

-10

10

IL

IN

CC

I

V

= 3.6, V = Max, V = V or V (Note 3)

OZH

OUT CC IN IH IL

I

V

= 0, V = Max, V = V or V (Note 3)

-10

-160

OZL

OUT

CC

IN

IH

IL

I

V

= 0.5 V = Max, V = V or V (Note 4)

-15

SC

OUT

CC

IN

IH

IL

Notes:

1. Total I between ground pins should not exceed 64 mA.

OL

2. These are absolute values with respect to device ground, and all overshoots due to system and/or tester noise are included.

3. I/O pin leakage is the worst case of I and I or I and I

.

OZH

IL

OZL

IH

4. Not more than one output should be shorted at one time. Duration of the short-circuit should not exceed one second.

22

MACH 5 Family

M5(LV) TIMING PARAMETERS OVER OPERATING RANGES¹

-5

-6

-7

-10

-12

-15

-20

Min Max Min Max Min Max Min Max Min Max Min Max Min Max Unit

Combinatorial Delay:

Internal combinatorial propagation

t

3.5

5.5

4.5

6.5

5.5

7.5

8.0

10.0

12.0

13.0

15.0

18.0 ns

20.0 ns

PDi

delay

t

Combinatorial propagation delay

10.0

PD

Registered Delays:

t

Synchronous clock setup time

Asynchronous clock setup time

Synchronous clock hold time

Asynchronous clock hold time

Synchronous clock to internal output

Synchronous clock to output

3.0

0.0

3.0

0.0

3.0

4.0

0.0

4.0

5.0

0.0

5.0

6.0

0.0

6.0

8.0

7.0

0.0

7.0

10.0

8.0

0.0

8.0

ns

SS

t

SA

t

ns

HS

t

ns

HA

t

2.5

4.5

6.0

8.0

3.0

5.0

6.0

8.0

4.0

6.0

5.0

7.0

6.0

8.0

10.0 ns

12.0 ns

18.0 ns

20.0 ns

COSi

t

10.0

15.0

17.0

COS

t

Asynchronous clock to internal output

Asynchronous clock to output

8.0

10.0

12.0

13.0

15.0

COAi

t

10.0

COA

Latched Delays:

t

Latch setup time

3.0

4.0

3.0

4.0

5.0

6.0

7.0

8.0

ns

SAL

t

Latch hold time

HAL

t

Transparent latch internal

6.0

8.0

7.0

9.0

7.0

9.0

8.0

9.0

10.0

12.0

10.0 ns

PDLi

Propagation delay through transparent

latch

t

10.0

11.0

12.0 ns

PDL

t

Gate to internal output

Gate to output

7.0

9.0

8.0

9.0

10.0

12.0

11.0

13.0

12.0 ns

14.0 ns

GOAi

t

10.0

11.0

GOA

Input Register Delays:

Input register setup time using a

t

2.0

0.0

3.0

6.0

2.0

0.0

3.0

6.0

2.0

0.0

3.0

6.0

3.0

0.0

4.0

7.0

3.0

0.0

4.0

7.0

3.0

0.0

4.0

7.0

3.0

0.0

4.0

7.0

ns

SIRS

synchronous clock

Input register setup time using an

asynchronous clock

t

SIRA

Input register hold time using a

synchronous clock

t

HIRS

Input register hold time using an

asynchronous clock

t

HIRA

Input Latch Delays:

t

Input latch setup time

Input latch hold time

Transparent input latch

2.0

6.0

2.0

6.0

2.0

6.0

3.0

7.0

3.0

7.0

3.0

7.0

3.0

7.0

ns

SIL

t

HIL

t

5.0

5.5

6.0

ns

PDILi

Output Delays:

t

Output buffer delay

Slow slew rate delay

Output enable time

Output disable time

2.0

2.5

7.5

2.0

2.5

7.5

2.0

2.5

9.5

2.0

2.5

2.0

2.5

2.0

2.5

2.0

2.5

ns

BUF

t

SLW

t

10.0

12.0

15.0

20.0 ns

EA

t

ER

MACH 5 Family

23

M5(LV) TIMING PARAMETERS OVER OPERATING RANGES¹(CONTINUED)

-5

-6

-7

-10

-12

-15

-20

Min Max Min Max Min Max Min Max Min Max Min Max Min Max Unit

Power Delays:

4.0

(5.0)

4.0

(5.0)

4.0

(5.0)

4.0

(5.0)

4.0

(5.0)

4.0

(5.0)

t

Power level 1 delay (Note 2)

Power level 2 delay (Note 2)

Power level 3 delay (Note 2)

4.0

6.0

9.0

ns

PL1

6.0

(9.0)

6.0

(9.0)

6.0

(9.0)

6.0

(9.0)

6.0

(9.0)

6.0

(9.0)

t

PL2

9.0

(17.5)

9.0

(17.5)

9.0

(17.5)

9.0

(17.5)

9.0

(17.5)

9.0

(17.5)

t

PL3

Additional Cluster Delay:

Product term cluster delay

Interconnect Delays:

t

0.3

ns

PT

t

Block interconnect delay

1.5

4.5

1.5

4.5

1.5

5.0

2.0

6.0

2.0

6.0

2.0

6.0

2.0

6.0

ns

BLK

t

Segment interconnect delay

SEG

Reset and Preset Delays:

Asynchronous reset or preset to internal

t

6.0

8.0

10.0

12.0

14.0

16.0

16.0 ns

18.0 ns

SRi

register output

Asynchronous reset or preset to register

output

t

10.0

SR

t

Reset and set register recovery time

Asynchronous reset or preset width

5.5

3.0

7.5

4.0

7.5

4.0

8.0

5.0

9.0

6.0

10.0

7.0

11.0

8.0

ns

SRR

t

SRW

Clock Enable Delays:

t

Clock enable setup time

Clock enable hold time

4.0

3.0

5.0

4.0

5.0

4.0

6.0

5.0

7.0

6.0

7.0

6.0

8.0

7.0

ns

CES

t

CEH

Width:

t

Global clock width low (Note 3)

Global clock width high (Note 3)

Product term clock width low

Product term clock width high

2.5

3.0

4.0

3.0

4.0

5.0

6.0

7.0

6.0

8.0

ns

WLS

t

WHS

t

WLA

t

WHA

Gate width low (for low transparent) or

high (for high transparent)

t

3.0

4.0

5.0

6.0

7.0

8.0

ns

GWA

t

Input register clock width low or high

WIR

24

MACH 5 Family

M5(LV) TIMING PARAMETERS OVER OPERATING RANGES¹(CONTINUED)

-5

-6

-7

-10

-12

-15

-20

Min Max Min Max Min Max Min Max Min Max Min Max Min Max Unit

Frequency:

External feedback, PAL block level. Min

of 1/(t + t ) or 1/(t + t

133

182

200

91

125

167

91

100

125

167

71.4

83.3

125

83.3

100

125

58.8

66.7

100

71.4

83.3

100

55.6

62.5

83.3

41.7

45.5

71.4

45.5

50.0

83.3

35.7

38.5

62.5

MHz

)

SS COS

WLS WHS

Internal feedback, PAL block level. Min

of 1/(t + t ) or 1/(t +t

f

MAX

)

SS COSi

WLS WHS

No feedback PAL block level. Min of

1/(t + t ) or 1/(t + t )

WLS WHS

SS HS

External feedback, PAL block level. Min

of 1/(t + t ) or 1/(t + t

47.6

52.6

83.3

)

SA COA

WLA WHA

Internal feedback, PAL block level. Min

of 1/(t + t ) or 1/(t +t

f

111

167

111

125

MAXA

)

SA COAi

WLA WHA

No feedback, PAL block level. Min of

1/(t + t ) or 1/(t + t )

WLA WHA

SA HA

Maximum input register frequency

1/(t +t ) or 1/(2 x t

f

MAXI

)

WICW

SIRS HIRS

Notes:

1. See “MACH Switching Test Circuits” documentation on the Lattice Data Book CD-ROM or Lattice web site.

2. Numbers in parentheses are for M5-128, M5-192, M5-256.

3. If a signal is used as both a clock and a logic array input, then the maximum input frequency applies (f

/2).

MAX

MACH 5 Family

25

CAPACITANCE¹

Parameter

Parameter Symbol

Description

Test conditions

Typ

12

Unit

pF

C

I/CLK pin

I/O pin

V =2.0 V

3.3 V or 5 V, 25º C, 1 MHz

IN

C

V

=2.0 V

10

pF

I/O

OUT

1. These parameters are not 100% tested, but are calculated at initial characterization and at any time the design is modiﬁed where

these parameters may be affected.

I_CCvs. FREQUENCY

These curves represent the typical power consumption for a particular device at system frequency.

The selected “typical” pattern is a 16-bit up-down counter. This pattern ﬁlls the device and

exercises every macrocell. Maximum frequency shown uses internal feedback and a D-type

register. Power/Speed are optimized to obtain the highest counter frequency and the lowest

power. The highest frequency (LSBs) is placed in common PAL blocks, which are set to high

power. The lowest frequency signals (MSBs) are placed in a common PAL block and set to

lowest power. For a more detailed discussion about MACH 5 power consumption, refer to the

application note entitled MACH 5 Power in the Application Notes section on the Lattice Data Book

CD-ROM or Lattice web site.

I_CCCURVES AT HIGH /LOW POWER MODES

V

= 5 V or 3.3 V, T = 25º C

A

CC

700

600

500

400

300

200

M5(LV)-512 high power

M5(LV)-384 high power

M5(LV)-320 high power

M5-256/1 and

M5LV-25 high power

M5-192/1 high power

M5-128/1 and M5LV-128 high power

M5(LV)-512 low power

M5(LV)-384 low power

M5(LV)-320 low power

M5-256/1 and M5LV-256 low power

100

0

M5-192/1 low power

M5-128/1 and M5LV-128 low power

20446G-048

Frequency (MHz)

Figure 8. I Curves at High/Low Pow er Modes

CC

26

MACH 5 Family

V

= 5 V, T = 25º C

A

CC

700

600

500

400

300

200

M5-256 high power

M5-192 high power

M5-128 high power

M5-256 low power

M5-192 low power

M5-128 low power

100

0

Frequency (MHz)

20446G-049

Figure 9. I Curves at High/Low Pow er Modes

CC

MACH 5 Family

27

100-PIN PQFP CONNECTION DIAGRAM

Top View

100-Pin PQFP (68 I/O)

M5-128

M5LV-128*

M5-128

M5LV-128*

M5-192*

M5-256*

M5LV-256

M5-256*

M5LV-256

GND

TDI

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

1

2

3

4

5

6

7

8

80

79

78

77

76

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

GND

TDO

0A14 0A12 0A12

0B13 0B13 0B13

0B12 0B12 0B12

0B11 0B11 0B11

I/O51

I/O50

I/O49

I/O48

I/O47

I/O46

I/O45

I/O44

I/O43

I3/CLK3

GND

V_CC

3A12 2A12 0D14

3B13 2B13 0C13

3B12 2B12 0C12

3B11 2B11 0C11

0B8

0B7

0B4

0B3

0B2

0B8

0B7

0B4

0B3

0B2

0B8

0B7

0B4

0B3

0B2

3B8

3B7

3B4

3B3

3B2

2B8

2B7

2B4

2B3

2B2

0C8

0C7

0C4

0C3

0C2

9

I/O6

I/O7

I/O8

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

I0/CLK0

V_CC

GND

I1/CLK1

I/O9

I/O10

I/O11

I/O12

I/O13

I/O14

I/O15

I/O16

I/O17

TCK

V_CC

I2/CLK2

I/O42

I/O41

I/O40

I/O39

I/O38

I/O37

I/O36

I/O35

I/O34

TMS

1B2

1B3

1B4

1B7

1B8

1B2

1B3

1B4

1B7

1B8

1B2

1B3

1B4

1B7

1B8

2B2

2B3

2B4

2B7

2B8

2C2

2C3

2C4

2C7

2C8

1C2

1C3

1C4

1C7

1C8

1B11 1B11 1B11

1B12 1B12 1B12

1B13 1B13 1B13

1A14 1A12 1A12

2B11 2C11 1C11

2B12 2C12 1C12

2B13 2C13 1C13

2A12 2D12 1D14

GND

M5-256*

M5LV-256

M5-256*

M5LV-256

M5-192*

M5-128

M5LV-128*

M5-128

M5LV-128*

*Package obsolete, contact factory.

20446G-016

Pin Designations

CLK = Clock

V

= Supply Voltage

3

D

15

CC

GND = Ground

TDI = Test Data In

TCK = Test Clock

Macrocell (0-15)

PAL Block (A-D)

Segment (0-3)

I

= Input

I/O

NC

= Input/Output

= No Connect

TMS = Test Mode Select

TDO = Test Data Out

28

MACH 5 Family

100-PIN TQFP CONNECTION DIAGRAM – 68 I/O

Top View

100-Pin TQFP (68 I/O)

M5-128

M5LV-128

M5-192

M5-256

M5LV-256*

TDI

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

1

2

3

4

5

6

7

8

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

GND

TDO

0A14 0A12

0B13 0B13

0B12 0B12

0B11 0B11

0A12

0B13

0B12

0B11

0B8

0B7

0B4

0B3

0B2

I/O51

I/O50

I/O49

I/O48

I/O47

I/O46

I/O45

I/O44

I/O43

I3/CLK3

GND

3A12 2A12 0D14

3B13 2B13 0C13

3B12 2B12 0C12

3B11 2B11 0C11

0B8

0B7

0B4

0B3

0B2

0B8

0B7

0B4

0B3

0B2

3B8

3B7

3B4

3B3

3B2

2B8

2B7

2B4

2B3

2B2

0C8

0C7

0C4

0C3

0C2

9

I/O8

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

I0/CLK0

V_CC

GND

I1/CLK1

I/O9

I/O10

I/O11

I/O12

I/O13

I/O14

I/O15

I/O16

I/O17

TCK

V_CC

I2/CLK2

I/O42

I/O41

I/O40

I/O39

I/O38

I/O37

I/O36

I/O35

I/O34

TMS

1B2

1B3

1B4

1B7

1B8

1B2

1B3

1B4

1B7

1B8

1B2

1B3

1B4

1B7

1B8

1B11

1B12

1B13

1A12

2B2

2B3

2B4

2B7

2B8

2C2

2C3

2C4

2C7

2C8

1C2

1C3

1C4

1C7

1C8

1B11 1B11

1B12 1B12

1B13 1B13

1A14 1A12

2B11 2C11 1C11

2B12 2C12 1C12

2B13 2C13 1C13

2A12 2D12 1D14

M5-256

M5LV-256*

M5-256

M5LV-256*

M5-192

M5-128

M5LV-128

*Package obsolete, contact factory.

20446G-017

Pin Designations

CLK = Clock

V

= Supply Voltage

3

D

15

CC

GND = Ground

TDI = Test Data In

TCK = Test Clock

Macrocell (0-15)

PAL Block (A-D)

Segment (0-3)

I

= Input

I/O

NC

= Input/Output

= No Connect

TMS = Test Mode Select

TDO = Test Data Out

MACH 5 Family

29

100-PIN TQFP CONNECTION DIAGRAM – 74 I/O

Top View

100-Pin TQFP (74 I/O)

M5LV-128

M5LV-256

M5LV-128

M5LV-256

TDI

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

1

2

3

4

5

6

7

8

75

74

73

72

71

70

69

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

51

GND

TDO

0A14

0B13

0B12

0B11

0B8

0B7

0B4

0B3

0B2

0A12

0B13

0B12

0B11

0B8

0B7

0B4

0B3

0B2

I/O54

I/O53

I/O52

I/O51

I/O50

I/O49

I/O48

I/O47

I/O46

I3/CLK3

GND

3A12

3B13

3B12

3B11

3B8

0D14

0C13

0C12

0C11

0C8

3B7

0C7

9

3B4

0C4

I/O8

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

3B3

0C3

I0/CLK0

V_CC

GND

I1/CLK1

I/O9

I/O10

I/O11

I/O12

I/O13

I/O14

I/O15

I/O16

I/O17

TCK

3B2

0C2

V_CC

I2/CLK2

I/O45

I/O44

I/O43

I/O42

I/O41

I/O40

I/O39

I/O38

I/O37

TMS

1B2

1B3

1B4

1B7

1B8

1B11

1B12

1B13

1A14

1B2

1B3

1B4

1B7

1B8

1B11

1B12

1B13

1A12

2B2

1C2

2B3

1C3

2B4

1C4

2B7

1C7

2B8

1C8

2B11

2B12

2B13

2A12

1C11

1C12

1C13

1D14

M5LV-256

M5LV-128

20446G-018

Pin Designations

CLK = Clock

V

= Supply Voltage

3

D

15

CC

GND = Ground

TDI = Test Data In

TCK = Test Clock

Macrocell (0-15)

I

= Input

I/O

NC

= Input/Output

= No Connect

TMS = Test Mode Select

TDO = Test Data Out

PAL Block (A-D)

Segment (0-3)

30

MACH 5 Family

144-PIN PQFP CONNECTION DIAGRAM

Top View

144-Pin PQFP

M5-128

M5LV-128*

M5-192*

M5-256*

M5LV-256*

M5-256*

M5LV-256*

TDI

I/O0

I/O1

I/O2

I/O3

I/O4

GND

I/O5

I/O6

I/O7

1

2

3

4

5

6

7

8

108

107

106

105

104

103

102

101

100

99

98

97

96

95

94

93

92

91

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

75

TDO

0A14 0A12

0B13 0A13

0B12 0A14 0A10

0B11 0B13 0A11

0B10 0B12 0A12

0A8

0A9

I/O77

I/O76

I/O75

I/O74

I/O73

GND

I/O72

I/O71

I/O70

I/O69

GND

I/O68

I/O67

I/O66

I/O65

I3/CLK3

GND

3A8

3A9

2A12 0D14

2A13 0C13

3A10 2A14 0C12

3A11 2B13 0C11

3A12 2B12 0C10

0B8 0B11 0B13

3B13 2B11 0C8

3B12 2B8

3B11 2B5

0B7

0B6

0B5

0B8 0B12

0B5 0B11

0B4

9

0C7

0C6

0C5

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

0B8

I/O8

GND

I/O9

I/O10

I/O11

I/O12

I0/CLK0

V_CC

GND

I1/CLK1

I/O13

I/O14

I/O15

I/O16

GND

I/O17

I/O18

I/O19

I/O20

GND

I/O21

I/O22

I/O23

I/O24

I/O25

TCK

3B8

2B4

0B4

0B3

0B2

0B1

0B3

0B2

0B1

0B0

0B5

0B4

0B3

0B2

3B5

3B4

3B3

3B2

2B3

2B2

2B1

2B0

0C4

0C3

0C2

0C1

V_CC

I2/CLK2

I/O64

I/O63

I/O62

I/O61

GND

I/O60

I/O59

I/O58

I/O57

GND

I/O56

I/O55

I/O54

I/O53

I/O52

TMS

1B1

1B2

1B3

1B4

1B0

1B1

1B2

1B3

1B2

1B3

1B4

1B5

2B2

2B3

2B4

2B5

2C0

2C1

2C2

2C3

1C1

1C2

1C3

1C4

1B5

1B6

1B7

1B4

1B5 1B11

1B8 1B12

1B8

2B8

2B11 2C5

2B12 2C8

2C4

1C5

1C6

1C7

1B8 1B11 1B13

2B13 2C11 1C8

1B10 1B12 1A12

1B11 1B13 1A11

1B12 1A14 1A10

1B13 1A13

1A14 1A12

2A12 2C12 1C10

2A11 2C13 1C11

2A10 2D14 1C12

2A9

2A8

1A9

1A8

2D13 1C13

2D12 1D14

74

73

M5-256*

M5LV-256*

M5-192*

M5-128

M5LV-128*

*Package obsolete, contact factory.

20446G-019

Pin Designations

CLK = Clock

V

= Supply Voltage

3

D

15

CC

GND = Ground

TDI = Test Data In

TCK = Test Clock

Macrocell (0-15)

PAL Block (A-D)

Segment (0-3)

I

= Input

I/O

NC

= Input/Output

= No Connect

TMS = Test Mode Select

TDO = Test Data Out

MACH 5 Family

31

144-PIN TQFP CONNECTION DIAGRAM

Top View

144-Pin TQFP

M5LV-128

M5LV-256

TDI

I/O0

I/O1

I/O2

I/O3

I/O4

GND

I/O5

I/O6

I/O7

1

2

3

4

5

6

7

8

108

107

106

105

104

103

102

101

100

99

98

97

96

95

94

93

92

91

90

89

88

87

86

85

84

83

82

81

80

79

78

77

76

75

TDO

0A14

0B13

0B12 0A10

0B11 0A11

0B10 0A12

0A8

0A9

I/O77

I/O76

I/O75

I/O74

I/O73

GND

I/O72

I/O71

I/O70

I/O69

GND

I/O68

I/O67

I/O66

I/O65

I3/CLK3

GND

V_CC

I2/CLK2

I/O64

I/O63

I/O62

I/O61

GND

I/O60

I/O59

I/O58

I/O57

GND

I/O56

I/O55

I/O54

I/O53

I/O52

TMS

3A8

3A9

3A10 0C12

3A11 0C11

3A12 0C10

0D14

0C13

0B8 0B13

0B7 0B12

0B6 0B11

3B13 0C8

3B12 0C7

3B11 0C6

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

0B5

0B8

I/O8

GND

I/O9

I/O10

I/O11

I/O12

I0/CLK0

V_CC

GND

I1/CLK1

I/O13

I/O14

I/O15

I/O16

GND

I/O17

I/O18

I/O19

I/O20

GND

I/O21

I/O22

I/O23

I/O24

I/O25

TCK

3B8

0C5

0B4

0B3

0B2

0B1

0B5

0B4

0B3

0B2

3B5

3B4

3B3

3B2

0C4

0C3

0C2

0C1

1B1

1B2

1B3

1B4

1B2

1B3

1B4

1B5

2B2

2B3

2B4

2B5

1C1

1C2

1C3

1C4

1B5

1B8

2B8

1C5

1B6 1B11

1B7 1B12

1B8 1B13

2B11 1C6

2B12 1C7

2B13 1C8

1B10 1A12

1B11 1A11

1B12 1A10

1B13

1A14

2A12 1C10

2A11 1C11

2A10 1C12

2A9

2A8

1A9

1A8

1C13

1D14

74

73

M5LV-256

M5LV-128

20446G-020

Pin Designations

CLK = Clock

V

= Supply Voltage

3

D

15

CC

GND = Ground

TDI = Test Data In

TCK = Test Clock

Macrocell (0-15)

I

= Input

I/O

NC

= Input/Output

= No Connect

TMS = Test Mode Select

TDO = Test Data Out

PAL Block (A-D)

Segment (0-3)

32

MACH 5 Family

160-PIN PQFP CONNECTION DIAGRAM

Top View

160-Pin PQFP (128, 192, 256 Macrocells)

M5-128

M5LV-128

M5-192

M5-256

M5LV-256

TDI

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

GND

I/O8

I/O9

I/O10

I/O11

I/O12

I/O13

I/O14

I/O15

1

2

3

4

5

6

7

8

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

102

101

100

99

98

97

96

95

94

93

92

91

90

89

88

87

86

85

84

83

TDO

0A14

0A15

0B14

0B13

0B12

0B11

0B10

0B9

0A12

0A13

0A14

0A15

0B15

0B14

0B13

0B12

0A8

0A9

I/O91

I/O90

I/O89

I/O88

I/O87

I/O86

I/O85

I/O84

GND

I/O83

I/O82

I/O81

I/O80

I/O79

I/O78

I/O77

I/O76

I3/CLK3

GND

3A8

3A9

2A12

2A13

0D14

0D15

0C14

0C13

0C12

0C11

0C10

0C9

0A10

0A11

0A12

0A13

0A14

0A15

3A10 2A14

3A11 2A15

3A12 2B15

3A13 2B14

3A14 2B13

3A15 2B12

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

0B8

0B7

0B6

0B5

0B4

0B3

0B2

0B1

0B11

0B8

0B5

0B4

0B3

0B2

0B1

0B0

0B13

0B12

0B11

0B8

0B5

0B4

3B13 2B11

3B12 2B8

3B11 2B5

3B8

3B5

3B4

3B3

3B2

0C8

0C7

0C6

0C5

0C4

0C3

0C2

0C1

2B4

2B3

2B2

2B1

2B0

0B3

0B2

I0/CLK0

V

CC

GND

I1/CLK1

I/O16

I/O17

I/O18

I/O19

I/O20

I/O21

I/O22

I/O23

GND

I/O24

I/O25

I/O26

I/O27

I/O28

I/O29

I/O30

I/O31

TCK

V

CC

I2/CLK2

I/O75

I/O74

I/O73

I/O72

I/O71

I/O70

I/O69

I/O68

GND

I/O67

I/O66

I/O65

I/O64

I/O63

I/O62

I/O61

I/O60

TMS

1B1

1B2

1B3

1B4

1B5

1B6

1B7

1B8

1B0

1B1

1B2

1B3

1B4

1B5

1B8

1B11

1B2

1B3

1B4

1B5

1B8

1B11

1B12

1B13

2B2

2B3

2B4

2B5

2B8

2B11 2C5

2B12 2C8

2B13 2C11

2C0

2C1

2C2

2C3

2C4

1C1

1C2

1C3

1C4

1C5

1C6

1C7

1C8

1B9

1B10

1B11

1B12

1B13

1B14

1A15

1A14

1B12

1B13

1B14

1B15

1A15

1A14

1A13

1A12

1A15

1A14

1A13

1A12

1A11

1A10

1A9

2A15 2C12

2A14 2C13

2A13 2C14

2A12 2C15

2A11 2D15

2A10 2D14

1C9

1C10

1C11

1C12

1C13

1C14

1D15

1D14

2A9

2A8

2D13

2D12

1A8

82

81

M5-256

M5LV-256

M5-192

M5-128

M5LV-128

20446G-021

Pin Designations

CLK = Clock

V

= Supply Voltage

3

D

15

CC

GND = Ground

TDI = Test Data In

TCK = Test Clock

Macrocell (0-15)

PAL Block (A-D)

Segment (0-3)

I

= Input

I/O

NC

= Input/Output

= No Connect

TMS = Test Mode Select

TDO = Test Data Out

MACH 5 Family

33

160-PIN PQFP (WITH INTERNAL HEAT SPREADER) CONNECTION DIAGRAM

Top View

160-Pin PQFP (320, 384, 512 Macrocells)

M5-320*

M5LV-320

M5-320*

M5LV-320

M5-384*

M5LV-384

M5-384*

M5LV-384

M5-512*

M5LV-512

M5-512*

M5LV-512

TDI

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

GND

I/O8

I/O9

I/O10

I/O11

I/O12

I/O13

I/O14

I/O15

I0/CLK0

1

2

3

4

5

6

7

8

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

104

103

102

101

100

99

98

97

96

95

94

93

92

91

90

89

88

87

86

85

84

83

TDO

0A2

0A3

0A4

0A7

0A8

0A11

0A12

0A13

0A2

0A3

0A4

0A7

0A8

0A11

0A12

0A13

0A2

0A3

0A4

0A7

0A8

0A11

0A12

0A13

I/O91

I/O90

I/O89

I/O88

I/O87

I/O86

I/O85

I/O84

GND

I/O83

I/O82

I/O81

I/O80

I/O79

I/O78

I/O77

I/O76

I3/CLK3

GND

5A2

5A3

5A4

5A7

5A8

5A11 4A11

5A12 4A12

5A13 4A13

4A2

4A3

4A4

4A7

4A8

3A2

3A3

3A4

3A7

3A8

3A11

3A12

3A13

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

0D13 0D13 0D13

0D12 0D12 0D12

0D11 0D11 0D11

0D8

0D7

0D4

0D3

0D2

5D13 4D13

5D12 4D12

5D11 4D11

5D8

5D7

5D4

5D3

5D2

3D13

3D12

3D11

3D8

3D7

3D4

0D8

0D7

0D4

0D3

0D2

0D8

0D7

0D4

0D3

0D2

4D8

4D7

4D4

4D3

4D2

3D3

3D2

V

CC

GND

I1/CLK1

I/O16

I/O17

I/O18

I/O19

I/O20

I/O21

I/O22

I/O23

GND

I/O24

I/O25

I/O26

I/O27

I/O28

I/O29

I/O30

I/O31

TCK

V

CC

I2/CLK2

I/O75

I/O74

I/O73

I/O72

I/O71

I/O70

I/O69

I/O68

GND

I/O67

I/O66

I/O65

I/O64

I/O63

I/O62

I/O61

I/O60

TMS

1D2

1D3

1D4

1D7

1D8

1D2

1D3

1D4

1D7

1D8

1D2

1D3

1D4

1D7

1D8

4D2

4D3

4D4

4D7

4D8

4D11 3D11

4D12 3D12

4D13 3D13

3D2

3D3

3D4

3D7

3D8

2D2

2D3

2D4

2D7

2D8

1D11 1D11 1D11

1D12 1D12 1D12

1D13 1D13 1D13

2D11

2D12

2D13

1A15

1A14

1A13

1A12

1A11

1A10

1A9

1A13

1A12

1A11

1A8

1A7

1A4

1A13

1A12

1A11

1A8

1A7

1A4

4A13 3A13

4A12 3A12

4A11 3A11

4A8

4A7

4A4

4A3

4A2

2A15

2A14

2A13

2A12

2A11

2A10

2A9

3A8

3A7

3A4

3A3

3A2

1A3

1A2

1A3

1A2

1A8

82

81

2A8

M5-512*

M5LV-512

M5-384*

M5LV-384

M5-320*

M5LV-320

*Package obsolete, contact factory.

20446G-022

Pin Designations

CLK = Clock

V

= Supply Voltage

7

D

15

CC

GND = Ground

TDI = Test Data In

TCK = Test Clock

Macrocell (0-15)

I

= Input

I/O

NC

= Input/Output

= No Connect

TMS = Test Mode Select

TDO = Test Data Out

PAL Block (A-D)

Segment (0-7)

34

MACH 5 Family

208-PIN PQFP CONNECTION DIAGRAM

Top View

208-Pin PQFP (192, 256 Macrocells)

M5-256

M5LV-256

TDI

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

1

2

3

4

5

6

7

8

156

155

154

153

152

151

150

149

148

147

146

145

144

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

TDO

0A8

0A9

I/O119

I/O118

I/O117

I/O116

I/O115

I/O114

I/O113

I/O112

3A8

3A9

0A10

0A11

0A12

0A13

0A14

0A15

3A10

3A11

2A12

3A13

3A14

3A15

9

V

CC

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

V

CC

GND

I/O8

I/O9

0B13

0B12

0B11

0B10

0B9

0B8

0B7

0B6

I/O111

I/O110

I/O109

I/O108

I/O107

I/O106

I/O105

I/O104

GND

I/O103

I/O102

I/O101

I/O100

3B13

3B12

3B11

3B10

3B9

3B8

3B7

3B6

I/O10

I/O11

I/O12

I/O13

I/O14

I/O15

GND

I/O16

I/O17

I/O18

I/O19

0B5

0B4

0B3

0B2

3B5

3B4

3B3

3B2

I0/CLK0

I3/CLK3

GND

V

CC

V

CC

GND

I1/CLK1

I/O20

I/O21

I/O22

I/O23

GND

I/O24

I/O25

I/O26

I/O27

I/O28

I/O29

I/O30

I/O31

GND

I2/CLK2

I/O99

I/O98

I/O97

I/O96

GND

I/O95

I/O94

I/O93

I/O92

I/O91

I/O90

I/O89

I/O88

GND

1B2

1B3

1B4

1B5

2B2

2B3

2B4

2B5

1B6

1B7

1B8

2B6

2B7

2B8

2B9

2B10

2B11

2B12

2B13

1B9

1B10

1B11

1B12

1B13

V

CC

V

CC

1A15

1A14

1A13

1A12

1A11

1A10

1A9

I/O32

I/O33

I/O34

I/O35

I/O36

I/O37

I/O38

I/O39

TCK

I/O87

I/O86

I/O85

I/O84

I/O83

I/O82

I/O81

I/O80

TMS

2A15

2A14

2A13

2A12

2A11

2A10

2A9

1A8

2A8

M5-256

M5LV-256

20446G-023

Pin Designations

CLK = Clock

V

= Supply Voltage

3

D

15

CC

GND = Ground

TDI = Test Data In

TCK = Test Clock

Macrocell (0-15)

PAL Block (A-D)

Segment (0-3)

I

= Input

I/O

NC

= Input/Output

= No Connect

TMS = Test Mode Select

TDO = Test Data Out

MACH 5 Family

35

208-PIN PQFP (WITH INTERNAL HEAT SPREADER) CONNECTION DIAGRAM

Top View

208-Pin PQFP (320, 384, 512 Macrocells)

M5-320

M5LV-320

M5-320

M5LV-320

M5-384

M5LV-384

M5-384

M5LV-384

M5-512

M5LV-512

TDI

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

1

2

3

4

5

6

7

8

156

155

154

153

152

151

150

149

148

147

146

145

144

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

128

127

126

125

124

123

122

121

120

119

118

117

116

115

114

113

112

111

110

109

108

107

106

105

TDO

0A2

0A3

0A4

0A7

0A8

0A11 0A11

0A12 0A12

0A13 0A13

0A2

0A3

0A4

0A7

0A8

0A2

0A3

0A4

0A7

0A8

0A11

0A12

0A13

I/O119

I/O118

I/O117

I/O116

I/O115

I/O114

I/O113

I/O112

5A2

5A3

5A4

5A7

4A2

4A3

4A4

4A7

4A8

4A11 3A11

4A12 3A12

4A13 3A13

3A2

3A3

3A4

3A7

3A8

5A8

5A11

5A12

5A13

9

V

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

V

CC

GND

CC

GND

I/O8

I/O9

0D15 0D15 0D15

0D14 0D14 0D14

0D13 0D13 0D13

0D12 0D12 0D12

0D11 0D11 0D11

0D10 0D10 0D10

I/O111

I/O110

I/O109

I/O108

I/O107

I/O106

I/O105

I/O104

GND

I/O103

I/O102

I/O101

I/O100

I3/CLK3

GND

5D15 4D15 3D15

5D14 4D14 3D14

5D13 4D13 3D13

5D12 4D12 3D12

5D11 4D11 3D11

5D10 4D10 3D10

I/O10

I/O11

I/O12

I/O13

I/O14

I/O15

GND

I/O16

I/O17

I/O18

I/O19

I0/CLK0

0D9

0D8

0D9

0D8

0D9

0D8

5D9

5D8

4D9

4D8

3D9

3D8

0D7

0D4

0D3

0D2

0D7

0D4

0D3

0D2

0D7

0D4

0D3

0D2

5D7

5D4

5D3

5D2

4D7

4D4

4D3

4D2

3D7

3D4

3D3

3D2

V

CC

GND

I1/CLK1

I/O20

I/O21

I/O22

I/O23

GND

I/O24

I/O25

I/O26

I/O27

I/O28

I/O29

I/O30

I/O31

GND

V

CC

I2/CLK2

I/O99

I/O98

I/O97

I/O96

GND

I/O95

I/O94

I/O93

I/O92

I/O91

I/O90

I/O89

I/O88

GND

1D2

1D3

1D4

1D7

1D2

1D3

1D4

1D7

1D2

1D3

1D4

1D7

4D2

4D3

4D4

4D7

3D2

3D3

3D4

3D7

2D2

2D3

2D4

2D7

1D8

1D9

1D8

1D9

1D8

1D9

4D8

4D9

3D8

3D9

2D8

2D9

1D10 1D10 1D10

1D11 1D11 1D11

1D12 1D12 1D12

1D13 1D13 1D13

1D14 1D14 1D14

1D15 1D15 1D15

4D10 3D10 2D10

4D11 3D11 2D11

4D12 3D12 2D12

4D13 3D13 2D13

4D14 3D14 2D14

4D15 3D15 2D15

V

CC

1A15 1A13

1A14 1A12

1A13 1A11

1A12

1A11

1A10

1A9

1A13

1A12

1A11

1A8

1A7

1A4

I/O32

I/O33

I/O34

I/O35

I/O36

I/O37

I/O38

I/O39

TCK

I/O87

I/O86

I/O85

I/O84

I/O83

I/O82

I/O81

I/O80

TMS

4A13

4A12

4A11

4A8

4A7

4A4

3A13 2A15

3A12 2A14

3A11 2A13

3A8

3A7

3A4

3A3

3A2

1A8

1A7

1A4

1A3

1A2

2A12

2A11

2A10

2A9

1A3

1A2

4A3

4A2

1A8

2A8

M5-512

M5LV-512

M5-384

M5LV-384

M5-320

M5LV-320

20446G-024

Pin Designations

CLK = Clock

V

= Supply Voltage

7

D

15

CC

GND = Ground

TDI = Test Data In

TCK = Test Clock

Macrocell (0-15)

PAL Block (A-D)

Segment (0-7)

I

= Input

I/O

NC

= Input/Output

= No Connect

TMS = Test Mode Select

TDO = Test Data Out

36

MACH 5 Family

240-PIN PQFP CONNECTION DIAGRAM

Top View

240-Pin PQFP

M5-320*

M5LV-320*

M5-384*

M5LV-384*

M5-384*

M5LV-384*

M5-512*

M5LV-512*

M5-512*

M5LV-512*

TDI

I/O0

I/O1

I/O2

I/O3

I/O4

I/O5

I/O6

I/O7

1

2

3

4

5

6

7

8

180

179

178

177

176

175

174

173

172

171

170

169

168

167

166

165

164

163

162

161

160

159

158

157

156

155

154

153

152

151

150

149

148

147

146

145

144

143

142

141

140

139

138

137

136

135

134

133

132

131

130

129

128

127

126

125

124

123

122

121

TDO

0A2

0A3

0A4

0A7

0A8

0A11

0A12

0A13

0A2

0A3

0A4

0A7

0A8

0A11

0A12

0A13

0A2

0A3

0A4

0A7

0A8

0A11

0A12

0A13

I/O139

I/O138

I/O137

I/O136

I/O135

I/O134

I/O133

I/O132

5A2

5A3

5A4

5A7

4A2

4A3

4A4

4A7

3A2

3A3

3A4

3A7

5A8

4A8

3A8

5A11

5A12

5A13

4A11

4A12

4A13

3A11

3A12

3A13

9

V

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

49

50

51

52

53

54

55

56

57

58

59

60

V

CC

GND

I/O8

I/O9

GND

0D15 0D15

0D14 0D14

0D13 0D13

0D12 0D12

0D11 0D11

0D10 0D10

0D15

0D14

0D13

0D12

0D11

0D10

0D9

I/O131

I/O130

I/O129

I/O128

I/O127

I/O126

I/O125

I/O124

GND

I/O123

I/O122

I/O121

I/O120

I/O119

I/O118

I/O117

I/O116

I3/CLK3

GND

5D15

5D14

5D13

5D12

5D11

5D10

5D9

4D15 3D15

4D14 3D14

4D13 3D13

4D12 3D12

4D11 3D11

4D10 3D10

I/O10

I/O11

I/O12

I/O13

I/O14

I/O15

GND

I/O16

I/O17

I/O18

I/O19

I/O20

I/O21

I/O22

I/O23

0D9

0D8

0D9

0D8

4D9

4D8

3D9

3D8

0D8

5D8

0D7

0D6

0D5

0D4

0D3

0D2

0D1

0D0

0D7

0D6

0D5

0D4

0D3

0D2

0D1

0D0

0D7

0D6

0D5

0D4

0D3

0D2

0D1

0D0

5D7

5D6

5D5

5D4

5D3

5D2

5D1

5D0

4D7

4D6

4D5

4D4

4D3

4D2

4D1

4D0

3D7

3D6

3D5

3D4

3D3

3D2

3D1

3D0

I0/CLK0

V

CC

GND

I1/CLK1

I/O24

I/O25

I/O26

I/O27

I/O28

I/O29

I/O30

I/O31

GND

I/O32

I/O33

I/O34

I/O35

I/O36

I/O37

I/O38

I/O39

GND

V

CC

I2/CLK2

I/O115

I/O114

I/O113

I/O112

I/O111

I/O110

I/O109

I/O108

GND

I/O107

I/O106

I/O105

I/O104

I/O103

I/O102

I/O101

I/O100

GND

1D0

1D1

1D2

1D3

1D4

1D5

1D6

1D7

1D0

1D1

1D2

1D3

1D4

1D5

1D6

1D7

1D0

1D1

1D2

1D3

1D4

1D5

1D6

1D7

4D0

4D1

4D2

4D3

4D4

4D5

4D6

4D7

3D0

3D1

3D2

3D3

3D4

3D5

3D6

3D7

2D0

2D1

2D2

2D3

2D4

2D5

2D6

2D7

1D8

1D9

1D8

1D9

1D8

1D9

4D8

4D9

3D8

3D9

2D8

2D9

1D10 1D10

1D11 1D11

1D12 1D12

1D13 1D13

1D14 1D14

1D15 1D15

1D10

1D11

1D12

1D13

1D14

1D15

4D10

4D11

4D12

4D13

4D14

4D15

3D10 2D10

3D11 2D11

3D12 2D12

3D13 2D13

3D14 2D14

3D15 2D15

V

CC

1A15

1A14

1A13

1A12

1A11

1A10

1A9

1A13

1A12

1A11

1A8

1A7

1A4

1A13

1A12

1A11

1A8

1A7

1A4

I/O40

I/O41

I/O42

I/O43

I/O44

I/O45

I/O46

I/O47

TCK

I/O99

I/O98

I/O97

I/O96

I/O95

I/O94

I/O93

I/O92

TMS

4A13

4A12

4A11

4A8

4A7

4A4

3A13

3A12

3A11

3A8

3A7

3A4

2A15

2A14

2A13

2A12

2A11

2A10

2A9

1A3

1A2

1A3

1A2

4A3

4A2

3A3

3A2

1A8

2A8

M5-512*

M5LV-512*

M5-512*

M5LV-512*

M5-384*

M5LV-384*

M5-384*

M5LV-384*

M5-320*

M5LV-320*

M5-320*

M5LV-320*

*Package obsolete, contact factory.

20446G-025

Pin Designations

CLK = Clock

V

= Supply Voltage

7

D

15

CC

GND = Ground

TDI = Test Data In

TCK = Test Clock

Macrocell (0-15)

PAL Block (A-D)

Segment (0-7)

I

= Input

I/O

NC

= Input/Output

= No Connect

TMS = Test Mode Select

TDO = Test Data Out

MACH 5 Family

37

256-BALL BGA CONNECTION DIAGRAM —

M5-320, M5LV-320*, M5-384*, M5LV-384*, M5-512*, M5LV-512*

Bottom View (I/O Pin-outs)

256-Ball BGA

Pin Designations

CLK = Clock

GND = Ground

I

= Input

I/O

NC

= Input/Output

= No Connect

= Supply Voltage

V

CC

TDI = Test Data In

TCK = Test Clock

TMS = Test Mode Select

TDO = Test Data Out

20446G-026

*Package obsolete, contact factory.

38

MACH 5 Family

256-BALL BGA CONNECTION DIAGRAM — M5-320, M5LV-320*

Bottom View (Macrocell Association)

256-Ball BGA

Pin Designations

CLK = Clock

GND = Ground

I

= Input

I/O

NC

= Input/Output

= No Connect

= Supply Voltage

V

CC

TDI = Test Data In

TCK = Test Clock

TMS = Test Mode Select

TDO = Test Data Out

4

D

15

Macrocell (0-15)

PAL Block (A-D)

Segment (0-4)

*Package obsolete, contact factory.

20446G-029

MACH 5 Family

39

256-BALL BGA CONNECTION DIAGRAM — M5-384*, M5LV-384*

Bottom View (Macrocell Association)

256-Ball BGA

Pin Designations

CLK = Clock

GND = Ground

I

= Input

I/O

NC

= Input/Output

= No Connect

= Supply Voltage

V

CC

TDI = Test Data In

TCK = Test Clock

TMS = Test Mode Select

TDO = Test Data Out

5

D

15

Macrocell (0-15)

PAL Block (A-D)

Segment (0-5)

*Package obsolete, contact factory.

20446G-028

40

MACH 5 Family

256-BALL BGA CONNECTION DIAGRAM — M5-512*, M5LV-512*

Bottom View (Macrocell Association)

256-Ball BGA

Pin Designations

CLK = Clock

GND = Ground

I

= Input

I/O

NC

= Input/Output

= No Connect

= Supply Voltage

V

CC

TDI = Test Data In

TCK = Test Clock

TMS = Test Mode Select

TDO = Test Data Out

5

D

15

Macrocell (0-15)

PAL Block (A-D)

Segment (0-5)

20446G-027

*Package obsolete, contact factory.

MACH 5 Family

41

352-BALL BGA CONNECTION DIAGRAM — M5-512, M5LV-512

Bottom View (I/O Pin-outs)

352-Ball BGA

Pin Designations

CLK = Clock

GND = Ground

I

= Input

I/O

NC

= Input/Output

= No Connect

= Supply Voltage

V

CC

TDI = Test Data In

TCK = Test Clock

TMS = Test Mode Select

TDO = Test Data Out

20446G-030

42

MACH 5 Family

352-BALL BGA CONNECTION DIAGRAM — M5-512, M5LV-512

Bottom View (I/O Pin-outs)

352-Ball BGA

Pin Designations

CLK = Clock

GND = Ground

I

= Input

I/O

NC

= Input/Output

= No Connect

= Supply Voltage

V

CC

TDI = Test Data In

TCK = Test Clock

TMS = Test Mode Select

TDO = Test Data Out

7

D

15

Macrocell (0-15)

PAL Block (A-D)

Segment (0-7)

20446G-031

MACH 5 Family

43

5V M5 ORDERING INFORMATION^1,2

Lattice standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed

by a combination of the elements below.

.

M5-

512 /256 -7

A

C

PROGRAMMING DESIGNATOR

Blank = Initial Algorithm

FAMILY TYPE

M5-

= MACH 5 (5-V V )

CC

/1

= First Revision

OPERATING CONDITIONS

MACROCELL DENSITY

C

I

= Commercial (0°C to +70°C)

= Industrial (-40°C to +85°C)

128

192

256

320

384

512

= 128 Macrocells

= 192 Macrocells

= 256 Macrocells

= 320 Macrocells

= 384 Macrocells

= 512 Macrocells

PACKAGE TYPE

Y

V

A

H

= Plastic Quad Flat Pack (PQFP)

= Thin Quad Flat Pack (TQFP)

= Ball Grid Array (BGA)

= Plastic Quad Flat Pack (PQFP)

with exposed heat sink

I/Os

/68 = 68 I/Os in 100-pin PQFP or TQFP

/74 = 74 I/Os in 100-pin TQFP

SPEED

/104 = 104 I/Os in 144-pin PQFP or TQFP

/120 = 120 I/Os in 160-pin PQFP

/160 = 160 I/Os in 208-pin PQFP

/192 = 192 I/Os in 256-ball BGA

/256 = 256 I/Os in 352-ball BGA

-5 = 5.5 ns t

-6 = 6.5 ns t

-7 = 7.5 ns t

PD

-10 = 10 ns t

-12 = 12 ns t

-15 = 15 ns t

-20 = 20 ns t

PD

Note:

1. See below for valid device/package combinations.

2. M5-128/1, M5-192/1 and M5-256/1 recommended for new designs.

.

Valid Combinations

M5-128/68

M5-128/104

M5-128/120

M5-192/68

M5-192/104

M5-192/120

M5-256/68

M5-256/104

M5-256/120

M5-256/160

YC, VC, YI, VI

YC, YI

M5-320/120

M5-320/160

M5-320/184

M5-320/192

M5-384/120

M5-384/160

M5-384/184

M5-384/192

M5-512/120

M5-512/160

M5-512/184

M5-512/192

M5-512/256

HC*, HI*

HC, YC**, HI, YI**

HC*, HI*

YC, YI

Commercial:

-5, -7, -10, -12, -15

Industrial:

YC*, VC, YI*, VI

YC*, YI*

AC, AI

Commercial:

HC*, HI*

YC, YI

-6, -7, -10, -12, -15 HC, YC**, HI, YI**

HC*, HI*

-7, -10, -12, -15, -20 YC*, VC, YI*, VI

YC*, YI*

YC, YI

Industrial:

AC*, AI*

HC*, HI*

-7, -10, -12, -15, -20

HC, YC**, HI, YI**

HC*, HI*

*Package obsolete, contact factory.

** Contact Factory for availability.

AC*, AI*

AC, AI

Device Marking

Actual device marking differs from the ordering part number

(OPN). All MACH devices are dual-marked with both

Commercial and Industrial grades. The Industrial grade is

slower, i.e., M5-512/256-7AC-10AI.

Valid Combinations

Valid Combinations list conﬁgurations p lanned to be

supported in volume for this device. Consult the local Lattice

sales o fﬁce to co n ﬁrm availab ility o f sp eciﬁc valid

combinations and to check on newly released combinations.

44

MACH 5 Family

3.3V M5LV ORDERING INFORMATION¹

Lattice standard products are available in several packages and operating ranges. The order number (Valid Combination) is formed

by a combination of the elements below.

M5LV-

512 /256 -7

A

C

FAMILY TYPE

OPERATING CONDITIONS

M5LV- = MACH 5 Low Voltage (3.3-V V

)

C

I

= Commercial (0°C to +70°C)

= Industrial (-40°C to +85°C)

CC

PACKAGE TYPE

MACROCELL DENSITY

128 = 128 Macrocells

256 = 256 Macrocells

320 = 320 Macrocells

384 = 384 Macrocells

512 = 512 Macrocells

Y

V

A

H

= Plastic Quad Flat Pack (PQFP)

= Thin Quad Flat Pack (TQFP)

= Ball Grid Array (BGA)

= Plastic Quad Flat Pack (PQFP)

with exposed heat sink

I/Os

SPEED

/68 = 68 I/Os in 100-pin PQFP or TQFP

/74 = 74 I/Os in 100-pin TQFP

-5 = 5.5 ns t

-6 = 6.5 ns t

-7 = 7.5 ns t

-10 = 10 ns t

-12 = 12 ns t

-15 = 15 ns t

-20 = 20 ns t

PD

/104 = 104 I/Os in 144-pin PQFP or TQFP

/120 = 120 I/Os in 160-pin PQFP

/160 = 160 I/Os in 208-pin PQFP

/192 = 192 I/Os in 256-ball BGA

/256 = 256 I/Os in 352-ball BGA

PD

Note:

1. See below for valid device/package combinations.

Valid Combinations

M5LV-128/68

M5LV-128/74

M5LV-128/104

M5LV-128/120

M5LV-256/68

M5LV-256/74

M5LV-256/104

M5LV-256/120

M5LV-256/160

YC*, VC, YI*, VI

M5LV-320/120

M5LV-320/160

M5LV-320/184

M5LV-320/192

M5LV-384/120

M5LV-384/160

M5LV-384/184

M5LV-384/192

M5LV-512/120

M5LV-512/160

M5LV-512/184

M5LV-512/192

M5LV-512/256

HC, YC**, HI, YI**

HC*, HI*

VC, VI

YC*, VC, YI*, VI

YC, YI

Commercial:

AC*, AI*

-5, -7, -10, -12

Commercial:

YC, VC*, YI, VI*

VC, VI

HC, YC**, HI, YI**

HC*, HI*

-6, -7, -10, -12, -15

Industrial:

-7, -10, -12, -15

YC*, VC, YI*, VI

YC, YI

Industrial:

AC*, AI*

-10, -12, -15, -20

YC, YI

HC, YC**, HI, YI**

HC*, HI*

*Package obsolete, contact factory.

** Contact Factory for availability.

AC*, AI*

Device Marking

AC, AI

Actual device marking differs from the ordering part number

(OPN). All MACH devices are dual-marked with both

Commercial and Industrial grades. The Industrial grade is

slower, i.e., M5LV-512/256-7AC-10AI.

Valid Combinations

Valid Combinations list conﬁgurations p lanned to be

supported in volume for this device. Consult the local Lattice

sales o fﬁce to co n ﬁrm availab ility o f sp eciﬁc valid

combinations and to check on newly released combinations.

MACH 5 Family

45

46

MACH 5 Family, 3.3-V Ind

47

型号	制造商	描述	价格	文档
M5LV-320/120-12VI	LATTICE	Fifth Generation MACH Architecture	获取价格
M5LV-320/120-12YC	LATTICE	Fifth Generation MACH Architecture	获取价格
M5LV-320/120-12YI	LATTICE	Fifth Generation MACH Architecture	获取价格
M5LV-320/120-15AC	LATTICE	Fifth Generation MACH Architecture	获取价格
M5LV-320/120-15AI	LATTICE	Fifth Generation MACH Architecture	获取价格
M5LV-320/120-15HC	LATTICE	Fifth Generation MACH Architecture	获取价格
M5LV-320/120-15HI	LATTICE	Fifth Generation MACH Architecture	获取价格
M5LV-320/120-15VC	LATTICE	Fifth Generation MACH Architecture	获取价格
M5LV-320/120-15VI	LATTICE	Fifth Generation MACH Architecture	获取价格
M5LV-320/120-15YC	LATTICE	Fifth Generation MACH Architecture	获取价格

M5LV-320/120-12VC

M5LV-320/120-12VC 概述

M5LV-320/120-12VC 数据手册

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