MAS9138

更新时间:2025-06-11 06:27:47
品牌:MAS
描述:ASYNCHRONOUS TO SYNCHRONOUS CONVERTER

MAS9138 概述

ASYNCHRONOUS TO SYNCHRONOUS CONVERTER 异步同步转换器

MAS9138 数据手册

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DA9138.005  
12 April, 2006  
MAS9138  
ASYNCHRONOUS TO SYNCHRONOUS CONVERTER  
Pin compatible with MAS7838  
Interfaces a duplex asynchronous to synchronous channel  
Modem speeds of 600, 1.2k, 2.4k, 4.8k, 7.2k, 9.6k, 12k,  
14.4k, 19.2k and 38.4k bps with a single 4.9152 MHz crystal  
DESCRIPTION  
MAS9138 is a single chip duplex asynchronous to  
synchronous converter. It converts asynchronous start  
stop characters to synchronous format, with stop bit  
deletion when required as defined in the CCITT  
recommendation V.14. On the receiver channel  
MAS9138 converts the incoming synchronous data to  
asynchronous start stop character format with stop bit  
insertion when required as defined in the CCITT  
recommendation V.14. MAS9138 implements the data  
modes for the synchronous interface as specified in the  
V.14. MAS9138 can be configured to operate at any  
frequency up to 38.4 kbits/s within these modes. The  
device contains a bit generator and frequency selection  
logic to allow easy operation at other data rates. With  
just one crystal the device can adapt to ten (10)  
different bit rates so it is ideally suited to be used with  
the most common modem systems ranging from V.22  
to V.34.  
FEATURES  
APPLICATION  
Implements CCITT recommendation V.14  
Bypass operation  
Character length from 8 to 11 bits including start  
stop and parity bits  
Data communication systems  
Adapts asynchronous terminals to synchronous  
modems  
Full or half card PC modems using UART as a data  
source  
Simplifying data multiplexing systems  
CMOS and LS-TTL compatible interface  
Low power consumption (typically 10 mW)  
No additional circuitry needed to perform conversion  
Single +3.3...+5V supply  
Operating temperature -40oC to 85oC  
16-pin PDIP and SO package  
BLOCK DIAGRAM  
CL1  
CL2  
VDD  
CONTROL  
XESR  
TMG  
OSC  
TSL  
O
S
C
ASYNC  
TO  
SYNC  
TXC  
TDO  
RXC  
RDI  
TDI  
SYNC  
TO  
ASYNC  
RDO  
XASY  
_>  
1
XHST  
VSS  
MAS9138  
1 (10)  
DA9138.005  
12 April, 2006  
PIN CONFIGURATION  
PDIP 16  
SO16  
MAS9138N  
1
16 VDD  
TSL  
MAS9138SB/SD  
RXC  
15  
TMG  
2
16 VDD  
15 RXC  
14 RDI  
RDO  
13  
12 XHST  
TSL 1  
TMG  
OSC  
TXC*  
2
3
4
RDI  
14  
13  
OSC 3  
4
5
6
RDO  
TXC*  
CL1  
12 XHST  
11 XASY  
10 TDO  
CL1 5  
CL2  
6
11  
10  
9
XASY  
TDO  
CL2  
XESR 7  
XESR 7  
VSS  
TDI  
VSS 8  
8
TDI  
9
Top marking: YYWW = Year Week, XXXXX.X = Lot Number, =ESD Indicator  
PIN DESCRIPTION  
Pin name  
Pin no.  
I/O  
Function  
PDIP  
SO  
TSL  
1
1
I
I
Timing select. 0 selects external sampling timing 16 x TXC from pin 2,  
TMG. 1 selects internal sampling timing.  
TMG  
2
2
Timing. Square wave timing signal 16 x TXC (TSL = 0) or 128 x  
TXCmax (TSL = 1).  
Max f = 10 Mhz when VDD = 5v and 5MHz when VDD = 3.3v.  
OSC  
TXC  
3
4
3
4
O
I
Oscillator. Output for crystal. If used, the crystal is connected between  
pins 2 and 3.  
Transmitter timing (MAS9138 only).  
Synchronous square wave timing for transmitter. The transmitted data  
output, TDO is synchronized to the rising edge of TXC. The duty cycle  
of TXC has to be 50% +/- 5%.  
CL1  
5
5
I
Character length. The total character length including one start bit, one  
stop bit and possible parity bit is selected with the CL1 and CL2  
signals.  
CL2  
6
7
6
7
I
I
XESR  
Extended signalling rate. The tolerance of the synchronous bit rate can  
be:  
XESR = 1 (basic signalling rate) TXC -2.5%...+1.0%  
XESR = 0 (extended signalling rate) TXC -2.5%...2.3%  
VSS  
8
8
G
Ground  
2 (10)  
DA9138.005  
12 April, 2006  
PIN DESCRIPTION  
Pin name  
Pin no.  
I/O  
Function  
PDIP  
SO  
TDI  
TDO  
XASY  
9
9
I
O
I
Transmitter data input. 1 = mark or stop bit. 0 = space, start or break  
signal.  
10  
11  
10  
11  
Transmitter data output. Output data is synchronized to the  
synchronous timing signal TXC (pin 4). 1 = mark. 0 = space.  
Asynchronous mode. XASY = 0 Asynchronous transmission, XASY = 1  
Synchronous transmission. In synchronous transmission the converter  
is totally bypassed in both directions: TDI = TDO, RDI = RDO  
XHST  
12  
12  
I
Higher speed signalling timing. XHST = 1 normal synchronous to  
asynchronous conversion (CCITT V.14). XHST = 0 asynchronous to  
synchronous conversion with higher speed synchronous timing (TXC,  
RXC). TXC and RXC timing must be 1-2% higher than the normal bit  
rate in order to allow some overspeed in the asynchronous data.  
On the receiver side the RX buffer is deleted and the synchronous  
data RDI is directly connected to the asynchronous output RDO.  
RDO  
RDI  
13  
14  
15  
16  
13  
14  
15  
16  
O
I
Receiver data output. RDO is the received data converted back to  
asynchrnous mode.  
1 = mark or stop bit, 0 = space, start or break signal  
Receiver data input. 1 = mark, 0 = space. The received data must be  
synchronized to the receiver timing RXC from the synchronous  
channel (pin 15).  
RXC  
VDD  
I
Receiver timing (MAS9138 only). Receiver square wave timing from  
the synchronous channel. The received data RDI must be  
synchronized to the rising edge of RXC.  
P
Power supply  
ABSOLUTE MAXIMUM RATINGS  
(GND = 0V)  
Parameter  
Symbol  
Conditions  
Min  
-0.5  
-55  
Max  
5.5  
Unit  
V
oC  
Supply Voltage  
Storage Temperature  
VDD  
Ts  
+150  
RECOMMEDED OPERATION CONDITIONS  
Parameter  
Symbol  
Conditions  
Min  
Typ  
Max  
Unit  
Supply Voltage  
VDD  
3
3.3 to  
5.0  
5.25  
V
Supply current  
IDD  
Ta  
VDD = 5V  
2
5
mA  
oC  
Operating Temperature  
-40  
+85  
3 (10)  
DA9138.005  
12 April, 2006  
ELECTRICAL CHARACTERISTICS  
©Inputs  
(test conditions: -40oC to 85oC)  
Parameter  
Symbol  
Conditions  
VDD=5V, VSS=0V  
Min  
Typ  
Max  
0.8  
Unit  
V
Input low voltage  
VIL  
VDD=3.3V, VSS=0V  
VDD=5V, VSS=0V  
0.4  
V
Input high voltage  
VIH  
IIL  
2
V
VDD=3.3V, VSS=0V  
VDD=5V, VSS=0V  
1.4  
V
Input leakage current  
-100  
-100  
1
µA  
µA  
pF  
pF  
kΩ  
VDD=3.3V, VSS=0V  
VDD=5V, VSS=0V  
Input capacitance load  
CI  
VDD=3.3V, VSS=0V  
VDD=5V, VSS=0V, VIN=0.4V  
1
Internal pull-up resistor for  
digital inputs  
Rpull-up  
150  
VDD=5V, VSS=0V, VIN=2.5V  
300  
275  
kΩ  
kΩ  
VDD=3.3V, VSS=0V,  
VIN=0.4V  
200  
600  
350  
VDD=3.3V, VSS=0V,  
VIN=1.5V  
1000  
1500  
kΩ  
©
Outputs (TDO, RDO)  
(test conditions: -40oC to 85oC)  
Parameter  
Symbol  
Conditions  
Min  
Typ  
Max  
0.4  
Unit  
V
Output low voltage  
VOL  
VDD=5V, VSS=0V, IOL=+1.8mA  
VDD=3.3V, VSS=0V,  
IOL=+0.6mA  
0.2  
V
Output high voltage  
VOH  
VDD=5V, VSS=0V, IOL=-4.3mA  
3.0  
1.8  
V
V
VDD=3.3V, VSS=0V, IOL=-  
2.1mA  
©
Outputs (OSC)  
(test conditions: -40oC to 85oC)  
Parameter  
Symbol  
Conditions  
Min  
Typ  
Max  
0.4  
Unit  
V
Output low voltage  
VOL  
VDD=5V, VSS=0V, IOL=+0.5mA  
VDD=3.3V, VSS=0V,  
IOL=+0.19mA  
0.2  
V
Output high voltage  
VOH  
VDD=5V, VSS=0V, IOL=-1.4mA  
3.0  
1.8  
V
VDD=3.3V, VSS=0V, IOL=-  
0.7mA  
4 (10)  
DA9138.005  
12 April, 2006  
©
Data timing  
(test conditions:VDD=3.3V - 5V, VSS=0V, -40oC to 85oC)  
Parameter  
Symbol  
Conditions  
Min  
Typ  
Max  
Unit  
Low to high logic transition  
time  
tR  
CL = 10pF  
20  
ns  
High to low logic transition  
time  
tR  
CL = 10 pF  
20  
ns  
(test conditions:VDD=3.3V - 5V, VSS=0V, -40oC to 85oC, TSL = 1)  
Parameter  
Symbol  
Conditions  
Min  
Typ  
Max  
Unit  
TDO delay time after TXC  
T1  
50  
TTXC/16  
+ 350  
ns  
RDI setup time before RXC  
RDI hold time after RXC  
T2  
T3  
1/4  
TRXC  
ns  
ns  
1/4  
TRXC  
(test conditions:VDD=3.3V - 5V, VSS=0V, -40oC to 85oC, TSL = 0, TMG = 16xTXC)  
Parameter  
Symbol  
Conditions  
Min  
Typ  
Max  
Unit  
TDO delay time after TXC  
T1  
50  
1/TMG  
+ 350  
ns  
RDI setup time before RXC  
RDI hold time after RXC  
T2  
T3  
1/4  
TRXC  
ns  
ns  
1/4  
TRXC  
TIMING DIAGRAMS  
The MAS9138 shifts the data out with rising edge of TXC. The data from RDI is read in with falling edge of RXC.  
TTXC  
TXC  
TDO  
delay  
T1  
TRXC  
RXC  
T3  
T2  
RDI  
5 (10)  
DA9138.005  
12 April, 2006  
FUNCTIONS  
©Asynchronous to synchronous converter  
The  
synchronous  
start-stop  
character,  
TDI  
every 8th character at maximum in the synchronous  
output data TDO. When extended signal rate (XESR =  
0) is used 4th stop bit may be deleted. When the  
transmitter detects a break signal( at least M bits of  
start polarity, where M is length of character), it sends  
2M + 3 bits of start - polarity to TDO. If the break is  
longer than 2M + 3 bits, then all bits are transferred to  
TDO. After a break signal, at least 2M bits of stop  
polarity must be transmitted before sending further  
data.  
(transmitter data input), is read into the Tx buffer.  
When the character is available the data bits are  
transferred as TDO (transmitter data output) with the  
synchronous timing signal TXC (transmitter clock).  
The bit rate of TDI must be the same as the TDO rate  
within -2.5%...+1% or -2.5%...+2.3% tolerance  
depending on XESR (extended signalling rate) signal.  
The transmitter adds extra stop bits to the  
synchronous data stream, if TDI is slower than TDO.  
The over speed is handled by deleting one stop bit in  
©Synchronous to asynchronous converter  
The synchronous RDI (receiver data input) is buffered  
to recognize the stop and start bits. If a missing stop  
bit is detected, it is added to the RDO (receiver data  
output). In this case the stop bits are shortened 12.5%  
©Converting with higher speed timing  
(25% if XESR = 0) during each character. When the  
receiver gets at least 2M + 3 bits of start polarity, it  
does not add stop bits to RDO. This enables the break  
signal to go through the buffer.  
An alternative method to handle the over speed in  
asynchronous data is to boost synchronous timing  
TXC and RXC by 1-2%. In this mode XHST (higher  
speed timing) = 0. In this case there is no need to  
©Timing selection  
The MAS9138 requires clock signals in order to  
function properly. The synchronous data transfer  
always requires the TXC clock. The clock is used  
internally for:  
-shifting data out from the TX buffer (to pin TDO)  
-detection of the bit rate in order to adjust the internal  
baud rate generator (only if TSL = 1)  
The asynchronous data transfer (pins TDI, TDO) is  
accomplished by generating an internal timing signal  
for the asychronous circuits. This internal timing signal  
(16T) is 16 times the TXC bit rate in order to sample  
the asynchronous data stream (TDI) at the proper  
delete any stop bits in the transmitter buffer. The  
break signal goes through unchanged. On the receiver  
side the synchronous data, RDI, is transferred directly  
to the asynchronous output RDO with RXC.  
speed. The internal clock 16T is either generated from  
a crystal frequency by dividing it by 8, 16, 21 1/3, 25  
3/5, 32, 42 2/3,64,128,256 or 512. Or it can also be  
generated externally and fed to pin TMG (TSL = 0).  
This is especially useful if the system already  
generates a clock which is 16 times the bit clock TXC  
as shown or if the bit rate is higher than 38.4 kHz. The  
divider is automatically selected by internal logic by  
measuring the TXC clock speed (TSL = 1). A crystal  
oscillator or a resonator can also be connected  
between pins 2 and 3. The crystal frequency should  
be 128 x TXCmax.  
Timing Circuits  
MAS 9138  
16 x TXC  
TXC  
EXTERNALLY GENERATED 16T CLOCK  
©Character Length CL1,CL2  
CL1  
CL2  
Conditions  
8 bits  
1
0
1
0
0
0
1
1
9 bits  
10 bits  
11 bits  
6 (10)  
DA9138.005  
12 April, 2006  
APPLICATION INFORMATION  
©Synchronous modem with asynchronous interface  
The MAS9138 is intended for applications where an asynchronous and synchronous data source must be linked  
together. A typical case appears in a data modem where the terminal interface of the modem has been specified to  
be asynchronous but the modem data pump operates in a synchronous fashion.  
RS232C  
MODEM CIRCUITS  
MAS9138  
INTERFACE  
TDO  
TXD  
RXD  
TDI  
TXC  
RDI  
RDO  
RXC  
PHONE LINE  
©Synchronous serial interface with uP interface  
Another application is a synchronous serial interface for uP which uses UART as a data source. The concept is  
illustrated below.  
RS-232-C  
V.24  
MAS9138  
TTL/V.28  
UART  
TxD  
RxD  
RDI  
uP-INTERFACE  
TDO  
RxC  
TxC  
7 (10)  
DA9138.005  
12 April, 2006  
APPLICATION INFORMATION  
©Data multiplexer  
A third application is a data multiplexing/demultiplexing system. The system accepts data from several sources.  
These data lines are sampled and the samples are sent through a multiplexer to a demultiplexer. To accomplish this,  
either a very high sample rate is needed or first convert the data to synchronous mode, where synchronous  
multiplexing can be used and only one sample per data bit is needed.  
MAS9138  
MAS9138  
RDI  
TDO  
TDI  
TDO  
RDO  
TDI  
RDI  
1
CH 1  
RDO  
1
MAS9138  
2
MAS9138  
2
FORWARD  
MUX/  
DEMUX  
MUX/  
DEMUX  
CH 2  
BACKWARD  
TIMING  
CH N  
N
N
©Synchronous modem with asynchronous interface  
The following application shows how to add an asynchronous interface to a synchronous modem with MAS9138. TSL  
and XHST inputs (pins 1 and 12) are connected to VDD. If the crystal is removed and the external 16 x TXC clock  
signal is used (dotted line) then tie the TSL input to ground. CL1, Cl2, XASY and XHST are user adjustable with  
jumpers or dip switches.  
+5v  
Synchronous  
Modem  
RS232C  
TDO TTL-Level  
16  
10  
TTL/V28  
78189A  
TDI  
TXD  
RXD  
9
TXC  
TXC TTL-Level  
RDI TTL-Level  
RXC TTL-Level  
4
470pF  
470pF  
14  
15  
RXC  
TTL/V28  
75189A  
RDO  
+5v  
13  
*)  
16 x TXC  
2
MAS9138  
TSL  
22pF  
1
-12v  
+12v  
XHST  
12  
CR 1  
9.8304MHz  
Ext. Signal Rate  
Char. Length  
Char. Length  
7
5
6
3
Modem  
Timing  
Circuit  
ASY/SYN Select  
11  
22pF  
8
mode  
selection  
jumpers  
*) Optional timing from the  
synchronous modem.  
In this case CR 1 can be  
eliminated.  
MAS9138 simplified application:  
V.28 interface for synchronous modem  
8 (10)  
DA9138.005  
12 April, 2006  
PACKAGE OUTLINES  
16LEADPDIPOUTLINE(300MILBODY)  
6.10  
7.11  
18.93  
21.33  
SEATING  
PLANE  
5-7°  
4
5
2
0.36  
0.56  
1.15  
1.77  
2.54  
BSC  
.
7.62  
BSC  
0
0.63TYPICAL  
1PIN  
ALLMEASUREMENTSINmm  
All dimensions are in accordance with JEDEC standard MS-001.  
16 LEAD SO OUTLINE (300 MIL BODY)  
1.27  
TYP.  
0-0.13  
RAD.  
0.36  
0.48  
5° TYP.  
5°TYP  
0.33 x 45°  
5° TYP.  
0.25 RAD.  
MIN.  
SEATING  
PLANE  
5° TYP.  
5° TYP.  
.
P
Y
T
6
8
.
0
10.10  
10.50  
PIN 1  
ALL MEASUREMENTS IN mm  
All dimensions in accordance with JEDEC standard MS-013.  
9 (10)  
DA9138.005  
12 April, 2006  
ORDERING INFORMATION  
Product Code  
MAS9138N  
Product  
Package  
PDIP16  
SO16  
Comments  
25 pcs/tube  
47 pcs/tube  
MAS9138ASB1  
MSB0091A Bake  
recommendation for surface  
mounted devices  
MAS9138A1SD06  
SO16 RoHS compliant Tape&Reel in MBB, 1000 pcs  
LOCAL DISTRIBUTOR  
MICRO ANALOG SYSTEMS CONTACTS  
Micro Analog Systems Oy  
Kamreerintie 2, P.O. Box 51  
FIN-02771 Espoo, FINLAND  
Tel. +358 9 80 521  
Fax +358 9 805 3213  
http://www.mas-oy.com  
NOTICE  
Micro Analog Systems Oy reserves the right to make changes to the products contained in this data sheet in order to improve the design or  
performance and to supply the best possible products. Micro Analog Systems Oy assumes no responsibility for the use of any circuits shown in this  
data sheet, conveys no license under any patent or other rights unless otherwise specified in this data sheet, and makes no claim that circuits are  
free from patent infringement. Applications for any devices shown in this data sheet are for illustration only and Micro Analog Systems Oy makes  
no claim or warranty that such applications will be suitable for the use specified without further testing or modification.  
10 (10)  

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