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DSC400-3333Q0094KI1T

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描述：Crystal-lessâ¢ Configurable Clock Generator

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DSC400-3333Q0094KI1T 概述

Crystal-lessâ¢ Configurable Clock Generator

DSC400-3333Q0094KI1T 数据手册

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DSC400-3333Q0094

Crystal-less™ Configurable Clock Generator

General Description

Features

The DSC400-3333Q0094 is

four output

• Frequencies and output formats:

- 125MHz LVDS x 1

- 100MHz LVDS x 2

crystal-less™ clock generator. It utilizes Microchip's

proven PureSilicon™ MEMS technology to provide

excellent jitter and stability while incorporating

additional device functionality.

- 50MHz LVDS x 1

• Low RMS phase jitter: <1ps (typ)

• High stability: ±50ppm, ±25ppm

• Wide temperature range

- Industrial: -40°C to +85°C

- Ext. commercial: -20°C to +70°C

The frequencies of the outputs can be identical or

independently derived from two shared PLLs. Each

output may be configured independently to support

LVCMOS, LVPECL, LVDS, or HCSL output

standards.

The DSC400-3333Q0094 provides two independent

select lines for choosing between two sets of pre-

configured frequencies per bank. It also has two OE

pins to allow for enabling and disabling outputs.

• High supply noise rejection: -50dBc

• Available pin-selectable frequency table

- 1 pin per bank for 2 frequency sets

• Excellent shock & vibration immunity

- Qualified to MIL-STD-883

Applications

• High reliability

• Communications and Networks

• Ethernet

- 1G, 10GBASE-T/KR/LR/SR, and FCoE

- 20x better MTF than quartz based devices

• Supply range of 2.25V to 3.6V

• AEC-Q100 automotive qualified

• 20-pin 5mm x 3.2mm QFN package

• Storage Area Networks

- SATA, SAS, Fibre Channel

• Passive Optical Networks

- EPON, 10G-EPON, GPON, 10G-GPON

• HD/SD/SDI Video & Surveillance

• Automotive

• Media and Video

• Embedded and Industrial

VDD1/VDD2

Block Diagram

Control Circuitry

CLK1+

125MHz LVDS

CLK1-

CLK4+

50MHz LVDS

CLK4-

Output

Control

And

MEMS

PLL

Dividers

OE1

FSB1

Control Circuitry

CLK3+

100MHz LVDS

CLK3-

CLK2+

100MHz LVDS

CLK2-

Output

Control

And

MEMS

PLL

Dividers

OE2

FSB2

ClockWorks is a registered trademark of Microchip Technology Inc.

VSS

Microchip Technology Inc.

http://www.microchip.com

January 23, 2017

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DSC400-3333Q0094

Ordering Information

Ordering Part Number

DSC400-3333Q0094KI1

DSC400-3333Q0094KI1T

DSC400-3333Q0094KI2

DSC400-3333Q0094KI2T

DSC400-3333Q0094KE1

DSC400-3333Q0094KE1T

DSC400-3333Q0094KE2

DSC400-3333Q0094KE2T

Temperature Range

-40°C to +85°C

-20°C to +70°C

High Stability

±50ppm

±25ppm

±50ppm

±25ppm

Shipping

Tube

Package

20-pin 5mm x 3.2mm QFN

Tape and Reel

Tube

Tape and Reel

Tube

Tape and Reel

Tube

Tape and Reel

Devices are Green and RoHS compliant. Sample material may have only a partial top mark.

Pin Configuration

OE1

VSS

OE2

20-pin 5mm x 3.2mm QFN

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Pin Description

Pin Number

Pin Name

OE1

Pin Type

Pin Function

Output enable for Bank 1 (CLK1 and CLK4); active high - see Table 1

Leave unconnected or connect to ground

Ground

VSS

PWR

VSS

Ground

CLK1-

CLK1+

CLK2-

CLK2+

VDD2

Complement output of differential pair 1

True output of differential pair 1

Complement output of differential pair 2

True output of differential pair 2

PWR

Power supply for Bank 2 (CLK3 and CLK2)

Input for selecting pre-configured frequencies on Bank 2 (CLK3 and CLK2)

No connect if the function is not used.

FSB2

OE2

Output enable for Bank 2 (CLK3 and CLK2); active high - see Table 1

Leave unconnected or connect to ground

Ground

VSS

PWR

VSS

Ground

CLK3-

CLK3+

CLK4-

CLK4+

VDD1

Complement output of differential pair 3

True output of differential pair 3

Complement output of differential pair 4

True output of differential pair 4

Power supply for Bank 1 (CLK1 and CLK4)

PWR

Input for selecting pre-configured frequencies on Bank 1 (CLK1 and CLK4)

No connect if the function is not used.

FSB1

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DSC400-3333Q0094

Operational Description

The DSC400-3333Q0094 is a crystal-less™ clock generator. Unlike older clock generators in the industry, it does not require an

external crystal to operate; it relies on integrated MEMS resonators that interface with internal PLLs. This technology enhances

performance and reliability by allowing tighter frequency stability over a far wider temperature range. In addition, the higher

resistance to shock and vibration decreases the aging rate, greatly improving product life in the system.

Inputs

There are 4 input signals in the device. Each has an internal (40kOhms) pull up, which defaults the selection to a high (1). Inputs

can be controlled through hardware strapping method with a resistor to ground to assert the input low (0). Inputs may also be

controlled by other components' GPIOs. In case more than one frequency set is desired, FSB1 and FSB2 are used for independent-

ly selecting one of two sets frequency per bank. FSB1 selects the pre-configured frequency set on Bank 1 (CLK1 and CLK4) and

FSB2 selects the pre-configured frequency set on Bank 2 (CLK3 and CLK2). If there is a requirement to disable outputs, the

inputs OE1 and OE2 are used to disable the banks of outputs. Outputs are disabled in tristate (Hi-Z) mode, see Table 1 below.

OE1

OE2

Bank 1 (CLK1 and CLK4)

Bank 2 (CLK3 and CLK2)

Hi-Z

Running

Hi-Z

Running

Table 1. Output Enable (OE) Selection Table

Outputs

The four outputs are grouped into two banks. Each bank is supplied by an independent VDD to allow for optimized noise

isolation between the two banks. Each bank provides two synchronous outputs generated by a common PLL:

• Bank 1 is composed of outputs CLK1 and CLK4

• Bank 2 is composed of outputs CLK3 and CLK2

Each output maybe pre-configured independently to be one of the following formats: LVCMOS, LVDS, LVPECL or HCSL.

In case the output is configured to be single ended (LVCMOS only), the frequency is generated on the true output (CLKx+) and

the complement output (CLKx-) is shut off in a low state. Frequencies can be chosen from 2.3MHz to 460MHz for differential

outputs and from 2.3MHz to 170MHz on LVCMOS outputs.

Output Clock Frequencies

Output

CLK1

CLK2

CLK3

CLK4

Frequency (MHz)

125

100

Power

VDD1 and VDD2 supply the power to banks 1 and 2 respectively. Each VDD may have different supply voltage from the other

as long as it is within the 2.25V to 3.6V range. Each VDD pin should have a 0.1µF capacitor to filter high frequency noise.

VSS is common to the entire device. The exposed die paddle should be connected to VSS.

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DSC400-3333Q0094

Absolute Maximum Ratings

Item

Min.

-0.3

Max.

+4.0

Units

Condition

Supply Voltage

Input Voltage

Junction Temp

Storage Temp

Soldering Temp

VDD + 0.3

+150

°C

-55

+150

+260

40sec max.

ESD

HBM

4000

400

CDM

1500

1000+ years of data retension on internal memory

Specifications (Unless specified otherwise: Ta = 25°C, VDD = 3.3V)

Parameter

Symbol

Condition

Min.

Typ.

Max.

Unit

Supply Voltage¹

VDD

2.25

3.6

OE (1:2) = 0

All outputs are disabled

Supply Current - Core²

Frequency Stability

IDDcore

±50

±25

All temp and VDD ranges

ppm

Aging - first year

Aging - after first year

Startup Time³

Fy1

Fy2⁺

tSU

1 year @ 25°C

±5

< ±1/yr

ppm

Year 2 and beyond @ 25°C

T = 25°C

Input Logic Levels

Input Logic High

Input Logic Low

VIH

VIL

0.75 x VDD

0.25 x VDD

Output Disable Time

tDA

tEN

Rpu

OE(1:2) transition from 1 to 0

OE(1:2) transition from 0 to 1

All input pins have an internal pull-up

Output Enable Time

Pull-Up Resistor

kOhms

Notes:

1. VDD pins should be filtered with 0.1µF capacitor connected between VDD and VSS.

2. The addition of IDDcore and IDDio provides total current consumption of the device.

3. tSU is time to 100ppm stable output frequency after VDD is applied and outputs are enabled.

4. Output Waveform figures below the parameters. See Output Waveform section.

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LVDS Outputs

RL = 100Ohms Differential

Output Offset Voltage

Delta Offset Voltage

Pk to Pk Output Swing

VOS

VPP

1.125

1.4

Single-Ended

350

200

Output Transition Time³

Rise Time

20% to 80%

RL = 50Ohms, CL = 2pF

Fall Time

CLK1

CLK2

CLK3

CLK4

125

100

Frequency

MHz

Output Duty Cycle

Supply Current - IO²

Period Jitter

SYM

Differential

IDDio Per output at 125MHz

JPER

2.5

psRMS

200kHz to 20MHz @ 156.25MHz

100kHz to 20MHz @ 156.25MHz

12kHz to 20MHz @ 156.25MHz

0.28

0.4

1.7

Integrated Phase Noise

JPH

psRMS

LVDS Typical Termination Scheme

If the 100Ohms clamping resistor does not exist inside the receiving device, it should be added externally on the PCB and

placed as close as possible to the receiver.

LVDS Output Waveform

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Connection Diagram

The connection Diagram below includes recommended capacitors to be placed on each VDD for noise filtering.

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Solder Reflow Profile

MSL 1 @ 260°C refer to JSTD-020C

Ramp-Up Rate (200°C to Peak Temp)

Preheat Time 150°C to 200°C

Time maintained above 217°C

Peak Temperature

3°C/sec Max.

60 - 180 sec

60 - 150 sec

255 - 260°C

20 - 40 sec

Time within 5°C of actual Peak

Ramp-Down Rate

6°C/sec Max.

8 min Max.

Time 25°C to Peak Temperature

January 23, 2017

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DSC400-3333Q0094

Package Information

20 QFN, 5.0mm x 3.2mm Package

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Recommended Solder Pad layout

Connect the center pad to ground plane for best thermal performance.

units: mm[inches]

Microchip makes no representations or warranties with respect to the accuracy or completeness of the information furnished in this data

sheet. This information is not intended as a warranty and Microchip does not assume responsibility for its use. Microchip reserves the right

to change circuitry, specifications and descriptions at any time without notice. No license, whether express, implied, arising by

estoppel or otherwise, to any intellectual property rights is granted by this document. Except as provided in Microchip's terms and

conditions of sale for such products, Microchip assumes no liability whatsoever, and Microchip disclaims any express or implied warranty

relating to the sale and/or use of Microchip products including liability or warranties relating to fitness for a particular purpose,

merchantability, or infringement of any patent, copyright or other intellectual property right.

Microchip products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction

of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a)

are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected

to result in a significant injury to the user. A Purchaser's use or sale of Microchip Products for use in life support appliances, devices

or systems is a Purchaser's own risk and Purchaser agrees to fully indemnify Microchip for any damages resulting from such use or sale.

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