29F400C-90中文资料_数据手册_规格书

MX29F400C T/B

4M-BIT [512Kx8/256Kx16] CMOS SINGLE VOLTAGE

5V ONLY BOOT SECTOR FLASH MEMORY

FEATURES

• 524,288 x 8/262,144 x 16 switchable

• Singlepowersupplyoperation

• Ready/Busy pin (RY/BY#)

-Providesahardwaremethodofdetectingprogramor

- 5.0V only operation for read, erase and program

operation

• Fast access time: 55/70/90ns

erase cycle completion

• Sector protect/chip unprotect for 5V only system

• Sectorprotection

• CompatiblewithMX29F400T/Bdevice

• Lowpowerconsumption

- Hardware method to disable any combination of

sectors from program or erase operations

-Temporarysectorunprotectallowscodechangesin

previously locked sectors

- 40mA maximum active current(5MHz)

- 1uA typical standby current

• Commandregisterarchitecture

• 100,000minimumerase/programcycles

• Latch-up protected to 100mA from -1V to VCC+1V

• Boot Code Sector Architecture

- T = Top Boot Sector

- B = Bottom Boot Sector

• Low VCC write inhibit is equal to or less than 3.2V

• Package type:

- Byte/word Programming (9us/11us typical)

- Sector Erase (Sector structure 16K-Bytex1, 8K-

Bytex2, 32K-Bytex1, and 64K-Byte x7)

• Auto Erase (chip & sector) and Auto Program

-Automaticallyeraseanycombinationofsectorswith

Erase Suspend capability.

- Automatically program and verify data at specified

address

- 44-pin SOP

- 48-pin TSOP

• Erasesuspend/EraseResume

- All Pb-free devices are RoHS Compliant

• Compatibility with JEDEC standard

- Pinout and software compatible with single-power

supply Flash

- Suspends an erase operation to read data from, or

program data to, another sector that is not being

erased, then resumes the erase

• Status Reply

• 20 years data retention

- Data# Polling & Toggle bit for detection of program

and erase cycle completion

GENERAL DESCRIPTION

The MX29F400C T/B is a 4-mega bit Flash memory or-

ganized as 512K bytes of 8 bits or 256K words of 16 bits.

MXIC's Flash memories offer the most cost-effective and

reliable read/write non-volatile random access memory.

The MX29F400CT/B is packaged in 44-pin SOP, 48-pin

TSOP. It is designed to be reprogrammed and erased in

system or in standard EPROM programmers.

during erase and programming, while maintaining maxi-

mum EPROM compatibility.

MXIC Flash technology reliably stores memory contents

even after 100,000 erase and program cycles. The MXIC

cell is designed to optimize the erase and programming

mechanisms. In addition, the combination of advanced

tunnel oxide processing and low internal electric fields

for erase and program operations produces reliable cy-

cling. The MX29F400CT/B uses a 5.0V±10%VCC sup-

ply to perform the High Reliability Erase and auto Pro-

gram/Erase algorithms.

The standard MX29F400C T/B offers access time as

fast as 55ns, allowing operation of high-speed micropro-

cessors without wait states. To eliminate bus conten-

tion, the MX29F400CT/B has separate chip enable (CE#)

and output enable (OE#) controls.

The highest degree of latch-up protection is achieved

with MXIC's proprietary non-epi process. Latch-up pro-

tection is proved for stresses up to 100 milliamps on

address and data pin from -1V to VCC + 1V.

MXIC's Flash memories augment EPROM functionality

with in-circuit electrical erasure and programming. The

MX29F400C T/B uses a command register to manage

this functionality. The command register allows for 100%

TTL level control inputs and fixed power supply levels

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MX29F400C T/B

PIN CONFIGURATIONS

44 SOP(500 mil)

PIN DESCRIPTION

SYMBOL PIN NAME

A0~A17

Address Input

Q0~Q14 Data Input/Output

RESET#

WE#

A8

A9

A10

A11

A12

A13

A14

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

24

23

NC

RY/BY#

A17

A7

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

Q15/A-1

CE#

Q15(Word mode)/LSB addr(Byte mode)

Chip Enable Input

A6

A5

A4

A3

A2

A1

A0

CE#

GND

OE#

Q0

Q8

Q1

Q9

Q2

Q10

Q3

Q11

WE#

Write Enable Input

BYTE#

Word/Byte Selection input

A15

A16

RESET# Hardware Reset Pin/Sector Protect

Unlock

BYTE#

GND

Q15/A-1

Q7

Q14

Q6

Q13

Q5

Q12

Q4

OE#

Output Enable Input

Ready/Busy Output

Power Supply Pin (+5V)

Ground Pin

RY/BY#

VCC

GND

VCC

48 TSOP (Standard Type) (12mm x 20mm)

1

2

3

4

5

6

7

8

A15

A14

A13

A12

A11

A10

A9

A8

NC

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

32

31

30

29

28

27

26

25

A16

BYTE#

GND

Q15/A-1

Q7

Q14

Q6

Q13

Q5

Q12

Q4

VCC

Q11

Q3

Q10

Q2

Q9

Q1

Q8

Q0

OE#

GND

CE#

A0

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

WE#

RESET#

NC

RY/BY#

NC

MX29F400CT/CB

A17

A7

A6

A5

A4

A3

A2

A1

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MX29F400C T/B

SECTOR STRUCTURE

MX29F400CT TOP BOOT SECTOR ADDRESS TABLE

Sector Size Address Range (in hexadecimal)

(Kbytes/

(x8)

(x16)

Sector A17 A16 A15 A14 A13 A12 Kwords)

AddressRange

SA0

SA1

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

SA10

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

0

X

0

X

0

64/32

32/16

8/4

00000h-0FFFFh

10000h-1FFFFh

20000h-2FFFFh

30000h-3FFFFh

40000h-4FFFFh

50000h-5FFFFh

60000h-6FFFFh

70000h-77FFFh

78000h-79FFFh

7A000h-7BFFFh

7C000h-7FFFFh

00000h-07FFFh

08000h-0FFFFh

10000h-17FFFh

18000h-1FFFFh

20000h-27FFFh

28000h-2FFFFh

30000h-37FFFh

38000h-3BFFFh

3C000h-3CFFFh

3D000h-3DFFFh

3E000h-3FFFFh

1

0

1

X

8/4

16/8

MX29F400CB BOTTOM BOOT SECTOR ADDRESS TABLE

Sector Size Address Range (in hexadecimal)

(Kbytes/

(x8)

(x16)

Sector A17 A16 A15 A14 A13 A12 Kwords)

AddressRange

SA0

SA1

SA2

SA3

SA4

SA5

SA6

SA7

SA8

SA9

SA10

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

X

0

1

X

0

1

16/8

8/4

00000h-03FFFh

04000h-05FFFh

06000h-07FFFh

08000h-0FFFFh

10000h-1FFFFh

20000h-2FFFFh

30000h-3FFFFh

40000h-4FFFFh

50000h-5FFFFh

60000h-6FFFFh

70000h-7FFFFh

00000h-01FFFh

02000h-02FFFh

03000h-03FFFh

04000h-07FFFh

08000h-0FFFFh

10000h-17FFFh

18000h-1FFFFh

20000h-27FFFh

28000h-2FFFFh

30000h-37FFFh

38000h-3FFFFh

X

32/16

64/32

Note: Address range is A17~A-1 in byte mode and A17~A0 in word mode.

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MX29F400C T/B

BLOCK DIAGRAM

WRITE

CONTROL

INPUT

PROGRAM/ERASE

CE#

OE#

WE#

STATE

MACHINE

(WSM)

HIGH VOLTAGE

LOGIC

STATE

REGISTER

ADDRESS

LATCH

FLASH

ARRAY

A0-A17

SOURCE

HV

AND

COMMAND

DATA

BUFFER

Y-PASS GATE

DECODER

PGM

DATA

HV

SENSE

AMPLIFIER

COMMAND

DATA LATCH

PROGRAM

DATA LATCH

I/O BUFFER

Q0-Q15/A-1

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MX29F400C T/B

dard microprocessor write timings. The device will auto-

matically pre-program and verify the entire array. Then

the device automatically times the erase pulse width,

provides the erase verification, and counts the number

of sequences. A status bit toggling between consecu-

tive read cycles provides feedback to the user as to the

status of the programming operation.

AUTOMATIC PROGRAMMING

The MX29F400C T/B is byte programmable using the

Automatic Programming algorithm. The Automatic Pro-

gramming algorithm makes the external system do not

need to have time out sequence nor to verify the data

programmed. The typical chip programming time at room

temperature of the MX29F400CT/B is less than 4.5 sec-

onds.

Register contents serve as inputs to an internal state-

machine which controls the erase and programming cir-

cuitry. During write cycles, the command register inter-

nally latches address and data needed for the program-

ming and erase operations. During a system write cycle,

addresses are latched on the falling edge, and data are

latched on the rising edge of WE# or CE#, whichever

happens first .

AUTOMATIC CHIP ERASE

The entire chip is bulk erased using 10 ms erase pulses

according to MXIC's Automatic Chip Erase algorithm.

Typical erasure at room temperature is accomplished in

less than 4 second. The Automatic Erase algorithm au-

tomatically programs the entire array prior to electrical

erase. The timing and verification of electrical erase are

controlled internally within the device.

MXIC's Flash technology combines years of EPROM

experience to produce the highest levels of quality, reli-

ability, and cost effectiveness.The MX29F400CT/B elec-

trically erases all bits simultaneously using Fowler-

Nordheim tunneling. The bytes are programmed by us-

ing the EPROM programming mechanism of hot electron

injection.

AUTOMATIC SECTOR ERASE

The MX29F400CT/B is sector(s) erasable using MXIC's

Auto Sector Erase algorithm. Sector erase modes allow

sectors of the array to be erased in one erase cycle. The

Automatic Sector Erase algorithm automatically programs

the specified sector(s) prior to electrical erase. The tim-

ing and verification of electrical erase are controlled in-

ternally within the device.

During a program cycle, the state-machine will control

the program sequences and command register will not

respond to any command set. During a Sector Erase

cycle, the command register will only respond to Erase

Suspend command.After Erase Suspend is completed,

the device stays in read mode. After the state machine

has completed its task, it will allow the command regis-

ter to respond to its full command set.

AUTOMATIC PROGRAMMING ALGORITHM

MXIC's Automatic Programming algorithm requires the

user to only write program set-up commands (including 2

unlock write cycle and A0H) and a program command

(program data and address). The device automatically

times the programming pulse width, provides the pro-

gram verification, and counts the number of sequences.

A status bit similar to Data# Polling and a status bit tog-

gling between consecutive read cycles, provide feedback

to the user as to the status of the programming opera-

tion.

AUTOMATIC ERASE ALGORITHM

MXIC's Automatic Erase algorithm requires the user to

write commands to the command register using stan-

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5

MX29F400C T/B

TABLE 1. SOFTWARE COMMAND DEFINITIONS

First Bus

Bus Cycle

Second Bus Third Bus

Cycle Cycle

Fourth Bus

Cycle

Fifth Bus

Cycle

Sixth Bus

Cycle

Command

Cycle Addr Data Addr Data Addr Data Addr Data

XXXH F0H

RA RD

Addr

Data Addr Data

Reset

1

Read

1

Read Silicon

ID

Word

Byte

4

555H AAH 2AAH 55H 555H 90H

AAAH AAH 555H 55H AAAH 90H

555H AAH 2AAH 55H 555H 90H

ADI DDI

Sector Protect Word

(SA) XX00H

x02H XX01H

(SA) 00H

x04H 01H

Verify

Byte

4

AAAH AAH 555H 55H AAAH 90H

Program

Word

Byte

Word

Byte

Word

Byte

4

6

1

6

555H AAH 2AAH 55H 555H A0H PA

AAAH AAH 555H 55H AAAH A0H PA

PD

Chip Erase

Sector Erase

555H AAH 2AAH 55H 555H 80H

AAAH AAH 555H 55H AAAH 80H

555H AAH 2AAH 55H 555H 80H

AAAH AAH 555H 55H AAAH 80H

XXXH B0H

555H AAH

AAAH AAH

555H AAH

AAAH AAH

2AAH 55H

555H 55H

2AAH 55H

555H 55H

555H 10H

AAAH 10H

SA

30H

Sector Erase Suspend

Sector Erase Resume

Unlock for sector

XXXH 30H

555H AAH 2AAH 55H 555H 80H

555H AAH

2AAH 55H

555H 20H

protect/unprotect

Note:

1. ADI = Address of Device identifier; A1=0, A0 = 0 for manufacture code,A1=0, A0 = 1 for device code, A2~A17=do not care.

(Refer to table 3)

DDI = Data of Device identifier : C2H for manufacture code, 23H/ABH (x8) and 2223H/22ABH (x16) for device code.

X = X can be VIL or VIH

RA=Address of memory location to be read.

RD=Data to be read at location RA.

2. PA = Address of memory location to be programmed.

PD = Data to be programmed at location PA.

SA = Address to the sector to be erased.

3. The system should generate the following address patterns: 555H or 2AAH to Address A10~A0 in word mode/AAAH or

555H to Address A10~A-1 in byte mode.

Address bit A11~A17=X=Don't care for all address commands except for Program Address (PA) and Sector

Address (SA). Write Sequence may be initiated with A11~A17 in either state.

4. For Sector Protect Verify operation:If read out data is 01H, it means the sector has been protected. If read out data is 00H, it

means the sector is still not being protected.

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6

MX29F400C T/B

COMMAND DEFINITIONS

Note that the Erase Suspend (B0H) and Erase Resume

(30H) commands are valid only while the Sector Erase

operation is in progress. Either of the two reset com-

mand sequences will reset the device(when applicable).

Device operations are selected by writing specific address

and data sequences into the command register. Writing

incorrect address and data values or writing them in the

improper sequence will reset the device to the read mode.

Table 1 defines the valid register command sequences.

TABLE 2. MX29F400C T/B BUS OPERATION

Pins

CE#

OE# WE# A0

A1

L

A6

X

A9

Q0 ~ Q15

Mode

Read Silicon ID

L

H

L

V_ID(2) C2H (Byte mode)

00C2H (Word mode)

Manufacture Code(1)

Read Silicon ID

Device Code(1)

Read

L

H

L

X

V_ID(2) 23H/ABH (Byte mode)

2223H/22ABH (Word mode)

L

H

L

H

X

H

L

A0

X

A1

X

A6

X

A9

X

D_OUT

Standby

X

H

HIGH Z

D_IN(3)

X

Output Disable

Write

X

A0

X

A1

X

A6

L

A9

H

Sector Protect without 12V

system (6)

L

Chip Unprotect without 12V

system (6)

L

H

L

X

H

X

H

X

H

X

Verify Sector Protect/Unprotect L

without 12V system (7)

H

X

Code(5)

HIGH Z

Reset

X

NOTES:

1. Manufacturer and device codes may also be accessed via a command register write sequence. Refer toTable 1.

2. VID is the Silicon-ID-Read high voltage, 11.5V to 12.5V.

3. Refer toTable 1 for valid Data-In during a write operation.

4. X can be VIL or VIH.

5. Code=00H/XX00H means unprotected.

Code=01H/XX01H means protected.

A17~A12=Sector address for sector protect.

6. Refer to sector protect/unprotect algorithm and waveform.

Must issue "unlock for sector protect/unprotect" command before "sector protect/unprotect without 12V system"

command.

7. The "verify sector protect/unprotect without 12V system" is only following "Sector protect/unprotect without 12V

system" command.

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MX29F400C T/B

SET-UP AUTOMATIC CHIP/SECTOR ERASE

COMMANDS

READ/RESET COMMAND

The read or reset operation is initiated by writing the

read/reset command sequence into the command reg-

ister. Microprocessor read cycles retrieve array data.

The device remains enabled for reads until the command

register contents are altered.

Chip erase is a six-bus cycle operation. There are two

"unlock" write cycles. These are followed by writing the

"set-up" command 80H. Two more "unlock" write cy-

cles are then followed by the chip erase command 10H.

If program-fail or erase-fail happen, the write of F0H will

reset the device to abort the operation. A valid com-

mand must then be written to place the device in the

desired state.

The Automatic Chip Erase does not require the device

to be entirely pre-programmed prior to executing the Au-

tomatic Chip Erase. Upon executing the Automatic Chip

Erase, the device will automatically program and verify

the entire memory for an all-zero data pattern. When the

device is automatically verified to contain an all-zero

pattern, a self-timed chip erase and verify begin. The

erase and verify operations are completed when the data

on Q7 is "1" at which time the device returns to the

Read mode. The system is not required to provide any

control or timing during these operations.

SILICON-ID-READ COMMAND

Flash memories are intended for use in applications where

the local CPU alters memory contents. As such, manu-

facturer and device codes must be accessible while the

device resides in the target system. PROM program-

mers typically access signature codes by raising A9 to

a high voltage. However, multiplexing high voltage onto

address lines is not generally desired system design

practice.

When using the Automatic Chip Erase algorithm, note

that the erase automatically terminates when adequate

erase margin has been achieved for the memory array(no

erase verification command is required).

The MX29F400CT/B contains a Silicon-ID-Read opera-

tion to supplement traditional PROM programming meth-

odology. The operation is initiated by writing the read

silicon ID command sequence into the command regis-

ter. Following the command write, a read cycle with

A1=VIL,A0=VIL retrieves the manufacturer code of C2H/

00C2H. A read cycle with A1=VIL, A0=VIH returns the

device code of 23H/2223H for MX29F400CT, ABH/22ABH

for MX29F400CB.

If the Erase operation was unsuccessful, the data on

Q5 is "1"(see Table 4), indicating the erase operation

exceed internal timing limit.

The automatic erase begins on the rising edge of the

lastWE# or CE#, whichever happens later, pulse in the

command sequence and terminates when the data on

Q7 is "1" and the data on Q6 stops toggling for two con-

secutive read cycles, at which time the device returns

to the Read mode.

TABLE 3. EXPANDED SILICON ID CODE

Pins

A0

A1

Q15~Q8 Q7 Q6 Q5

Q4 Q3 Q2 Q1 Q0 Code(Hex)

Manufacture code Word VIL

Byte VIL

VIL 00H

1

0

1

0

1

0

1

0

1

0

1

0

1

0

00C2H

VIL

X

C2H

Device code

Word VIH VIL 22H

Byte VIH VIL

Word VIH VIL 22H

2223H

for MX29F400CT

Device code

X

23H

22ABH

for MX29F400CB

Sector Protection

Verification

Byte VIH VIL

X

ABH

X

VIH

01H (Protected)

00H (Unprotected)

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MX29F400C T/B

SECTOR ERASE COMMANDS

The Automatic Sector Erase does not require the de-

vice to be entirely pre-programmed prior to executing

the Automatic Set-up Sector Erase command and Auto-

matic Sector Erase command. Upon executing the Au-

tomatic Sector Erase command, the device will auto-

matically program and verify the sector(s) memory for

an all-zero data pattern. The system is not required to

provide any control or timing during these operations.

erase margin has been achieved for the memory array

(no erase verification command is required). Sector

erase is a six-bus cycle operation. There are two "un-

lock" write cycles. These are followed by writing the set-

up command 80H. Two more "unlock" write cycles are

then followed by the sector erase command 30H. The

sector address is latched on the falling edge of WE# or

CE#, whichever happens later, while the command(data)

is latched on the rising edge of WE# or CE#, whichever

happens first. Sector addresses selected are loaded

into internal register on the sixth falling edge of WE# or

CE#, whichever happens later. Each successive sector

load cycle started by the falling edge of WE# or CE#,

whichever happens later, must begin within 30us from

the rising edge of the precedingWE# or CE#, whichever

happens First, otherwise, the loading period ends and

internal auto sector erase cycle starts. (Monitor Q3 to

determine if the sector erase timer window is still open,

see section Q3, Sector EraseTimer.) Any command other

than Sector Erase(30H) or Erase Suspend(B0H) during

the time-out period resets the device to read mode.

When the sector(s) is automatically verified to contain

an all-zero pattern, a self-timed sector erase and verify

begin. The erase and verify operations are complete

when the data on Q7 is "1" and the data on Q6 stops

toggling for two consecutive read cycles, at which time

the device returns to the Read mode. The system is not

required to provide any control or timing during these

operations.

When using the Automatic Sector Erase algorithm, note

that the erase automatically terminates when adequate

Table 4. Write Operation Status

Status

Q7

Q6

Q5

Q3

Q2 RY/BY#

Note1

Note2

Byte Program in Auto Program Algorithm

Auto Erase Algorithm

Q7# Toggle

0

N/A

1

No

0

Toggle

0

1

Toggle

0

Toggle

0

1

Erase Suspend Read

(Erase Suspended Sector)

No

Toggle

N/A Toggle

In Progress

Erase Suspended Mode

Erase Suspend Read

Data

Data Data Data Data

1

0

(Non-Erase Suspended Sector)

Erase Suspend Program

Q7# Toggle

0

1

N/A N/A

Byte Program in Auto Program Algorithm

N/A

1

No

Toggle

Exceeded

Time Limits Auto Erase Algorithm

0

Toggle

1

Toggle

0

Erase Suspend Program

Q7# Toggle

N/A N/A

Note:

1. Q7 and Q2 require a valid address when reading status information. Refer to the appropriate subsection for further details.

2. Q5 switches to '1' when an Auto Program or Auto Erase operation has exceeded the maximum timing limits.

See "Q5:Exceeded Timing Limits " for more information.

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9

MX29F400C T/B

nextWE# or CE#, pulse causes a transition to an active

programming operation. Addresses are latched on the

falling edge, and data are internally latched on the

rising edge of theWE# or CE#, whichever happens first,

pulse. The rising edge of WE# or CE#, whichever hap-

pens first, also begins the programming operation. The

system is not required to provide further controls or tim-

ings. The device will automatically provide an adequate

internally generated program pulse and verify margin.

ERASE SUSPEND

This command only has meaning while the state ma-

chine is executing Automatic Sector Erase operation, and

therefore will only be responded during Automatic Sector

Erase operation. When the Erase Suspend command is

written during a sector erase operation, the device re-

quires a maximum of 20us to suspend the erase opera-

tions. However, When the Erase Suspend command is

written during the sector erase time-out, the device im-

mediately terminates the time-out period and suspends

the erase operation. After this command has been ex-

ecuted, the command register will initiate erase suspend

mode. The state machine will return to read mode auto-

matically after suspend is ready. At this time, state ma-

chine only allows the command register to respond to

the Read Memory Array, Erase Resume and program

commands.

If the program operation was unsuccessful, the data on

Q5 is "1"(seeTable 4), indicating the program operation

exceed internal timing limit.The automatic programming

operation is completed when the data read on Q6 stops

toggling for two consecutive read cycles and the data

on Q7 and Q6 are equivalent to data written to these two

bits, at which time the device returns to the Read mode(no

program verify command is required).

The system can determine the status of the program

operation using the Q7 or Q6 status bits, just as in the

standard program operation.After an erase-suspend pro-

gram operation is complete, the system can once again

read array data within non-suspended sectors.

DATA# POLLING-Q7

The MX29F400C T/B also features Data# Polling as a

method to indicate to the host system that the Auto-

matic Program or Erase algorithms are either in progress

or completed.

ERASE RESUME

While the Automatic Programming algorithm is in opera-

tion, an attempt to read the device will produce the

complement data of the data last written to Q7. Upon

completion of the Automatic Program Algorithm an at-

tempt to read the device will produce the true data last

written to Q7. The Data# Polling feature is valid after the

rising edge of the fourth WE# or CE#, whichever hap-

pens first, pulse of the four write pulse sequences for

automatic program.

This command will cause the command register to clear

the suspend state and return back to Sector Erase mode

but only if an Erase Suspend command was previously

issued. Erase Resume will not have any effect in all

other conditions.Another Erase Suspend command can

be written after the chip has resumed erasing.However,

a 400us time delay must be required after the erase re-

sume command, if the system implements an endless

erase suspend/resume loop, or the number of erase sus-

pend/resume is exceeded 1024 times.The erase times

will be expended if the erase behavior always be sus-

pended.

While the Automatic Erase algorithm is in operation, Q7

will read "0" until the erase operation is competed. Upon

completion of the erase operation, the data on Q7 will

read "1". The Data# Polling feature is valid after the

rising edge of the sixthWE# or CE#, whichever happens

first pulse of six write pulse sequences for automatic

chip/sector erase.

SET-UP AUTOMATIC PROGRAM COMMANDS

To initiate Automatic Program mode, A three-cycle com-

mand sequence is required. There are two "unlock" write

cycles. These are followed by writing the Automatic Pro-

gram command A0H.

The Data# Polling feature is active during Automatic Pro-

gram/Erase algorithm or sector erase time-out. (see sec-

tion Q3 Sector EraseTimer)

Once the Automatic Program command is initiated, the

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10

MX29F400C T/B

pended. Alternatively, the system can use Q7.

RY/BY#:Ready/Busy#

If a program address falls within a protected sector, Q6

toggles for approximately 2 us after the program com-

mand sequence is written, then returns to reading array

data.

The RY/BY# is a dedicated, open-drain output pin that

indicates whether an Automatic Erase/Program algorithm

is in progress or complete. The RY/BY# status is valid

after the rising edge of the final WE# or CE#, whichever

happens first, pulse in the command sequence. Since

RY/BY# is an open-drain output, several RY/BY# pins

can be tied together in parallel with a pull-up resistor to

Vcc.

Q6 also toggles during the erase-suspend-program mode,

and stops toggling once the Automatic Program algorithm

is complete.

Table 4 shows the outputs for Toggle Bit I on Q6.

If the output is low (Busy), the device is actively erasing

or programming.(This includes programming in the Erase

Suspend mode.) If the output is high (Ready), the device

is ready to read array data (including during the Erase

Suspend mode), or is in the standby mode.

Q2:Toggle Bit II

The "Toggle Bit II" on Q2, when used with Q6, indicates

whether a particular sector is actively erasing (that is,

the Automatic Erase algorithm is in process), or whether

that sector is erase-suspended. Toggle Bit I is valid after

the rising edge of the final WE# or CE#, whichever hap-

pens first, pulse in the command sequence.

Table 4 shows the outputs for RY/BY#.

Q6:Toggle BIT I

Toggle Bit I on Q6 indicates whether an Automatic Pro-

gram or Erase algorithm is in progress or complete, or

whether the device has entered the Erase Suspend mode.

Toggle Bit I may be read at any address, and is valid

after the rising edge of the final WE# or CE#, whichever

happens first, pulse in the command sequence (prior to

the program or erase operation), and during the sector

time-out.

Q2 toggles when the system reads at addresses within

those sectors that have been selected for erasure. (The

system may use either OE# or CE# to control the read

cycles.) But Q2 cannot distinguish whether the sector

is actively erasing or is erase-suspended. Q6, by com-

parison, indicates whether the device is actively eras-

ing, or is in Erase Suspend, but cannot distinguish which

sectors are selected for erasure. Thus, both status bits

are required for sectors and mode information. Refer to

Table 4 to compare outputs for Q2 and Q6.

During an Automatic Program or Erase algorithm opera-

tion, successive read cycles to any address cause Q6

to toggle. The system may use either OE# or CE# to

control the read cycles.When the operation is complete,

Q6 stops toggling.

Reading Toggle Bits Q6/ Q2

After an erase command sequence is written, if all sec-

tors selected for erasing are protected, Q6 toggles and

returns to reading array data. If not all selected sectors

are protected, the Automatic Erase algorithm erases the

unprotected sectors, and ignores the selected sectors

that are protected.

Whenever the system initially begins reading toggle bit

status, it must read Q7-Q0 at least twice in a row to

determine whether a toggle bit is toggling. Typically, the

system would note and store the value of the toggle bit

after the first read. After the second read, the system

would compare the new value of the toggle bit with the

first. If the toggle bit is not toggling, the device has com-

pleted the program or erase operation. The system can

read array data on Q7-Q0 on the following read cycle.

The system can use Q6 and Q2 together to determine

whether a sector is actively erasing or is erase sus-

pended.When the device is actively erasing (that is, the

Automatic Erase algorithm is in progress), Q6 toggling.

When the device enters the Erase Suspend mode, Q6

stops toggling. However, the system must also use Q2

to determine which sectors are erasing or erase-sus-

However, if after the initial two read cycles, the system

determines that the toggle bit is still toggling, the sys-

tem also should note whether the value of Q5 is high

(see the section on Q5). If it is, the system should then

P/N:PM1200

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11

MX29F400C T/B

determine again whether the toggle bit is toggling, since

the toggle bit may have stopped toggling just as Q5 went

high. If the toggle bit is no longer toggling, the device

has successfully completed the program or erase opera-

tion. If it is still toggling, the device did not complete the

operation successfully, and the system must write the

reset command to return to reading array data.

program a non blank location without erasing. In this

case the device locks out and never completes the Au-

tomatic Algorithm operation. Hence, the system never

reads a valid data on Q7 bit and Q6 never stops toggling.

Once the Device has exceeded timing limits, the Q5 bit

will indicate a "1". Please note that this is not a device

failure condition since the device was incorrectly used.

The remaining scenario is that system initially determines

that the toggle bit is toggling and Q5 has not gone high.

The system may continue to monitor the toggle bit and

Q5 through successive read cycles, determining the sta-

tus as described in the previous paragraph. Alternatively,

it may choose to perform other system tasks. In this

case, the system must start at the beginning of the al-

gorithm when it returns to determine the status of the

operation.

DATA PROTECTION

The MX29F400C T/B is designed to offer protection

against accidental erasure or programming caused by

spurious system level signals that may exist during power

transition. During power up the device automatically re-

sets the state machine in the Read mode. In addition,

with its control register architecture, alteration of the

memory contents only occurs after successful comple-

tion of specific command sequences. The device also

incorporates several features to prevent inadvertent write

cycles resulting fromVCC power-up and power-down tran-

sition or system noise.

Q5

ExceededTiming Limits

Q5 will indicate if the program or erase time has exceeded

the specified limits (internal pulse count). Under these

conditions Q5 will produce a "1". This time-out condition

indicates that the program or erase cycle was not suc-

cessfully completed. Data# Polling and Toggle Bit are

the only operating functions of the device under this con-

dition.

TEMPORARY SECTOR UNPROTECT

This feature allows temporary unprotection of previously

protected sector to change data in-system.TheTempo-

rary Sector Unprotect mode is activated by setting the

RESET# pin toVID(11.5V-12.5V). During this mode, for-

merly protected sectors can be programmed or erased

as un-protected sector. Once VID is remove from the

RESET# pin, all the previously protected sectors are pro-

tected again.

If this time-out condition occurs during sector erase op-

eration, it specifies that a particular sector is bad and it

may not be reused. However, other sectors are still func-

tional and may be used for the program or erase opera-

tion. The device must be reset to use other sectors.

Write the Reset command sequence to the device, and

then execute program or erase command sequence. This

allows the system to continue to use the other active

sectors in the device.

Q3

Sector Erase Timer

After the completion of the initial sector erase command

sequence, the sector erase time-out will begin. Q3 will

remain low until the time-out is complete. Data# Polling

andToggle Bit are valid after the initial sector erase com-

mand sequence.

If this time-out condition occurs during the chip erase

operation, it specifies that the entire chip is bad or com-

bination of sectors are bad.

If this time-out condition occurs during the byte program-

ming operation, it specifies that the entire sector con-

taining that byte is bad and this sector may not be re-

used, (other sectors are still functional and can be re-

used).

If Data# Polling or theToggle Bit indicates the device has

been written with a valid erase command, Q3 may be

used to determine if the sector erase timer window is

still open. If Q3 is high ("1") the internally controlled

erase cycle has begun; attempts to write subsequent

commands to the device will be ignored until the erase

The time-out condition may also appear if a user tries to

P/N:PM1200

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12

MX29F400C T/B

operation is completed as indicated by Data# Polling or

Toggle Bit. If Q3 is low ("0"), the device will accept addi-

tional sector erase commands. To insure the command

has been accepted, the system software should check

the status of Q3 prior to and following each subsequent

sector erase command. If Q3 were high on the second

status check, the command may not have been accepted.

WRITE PULSE "GLITCH" PROTECTION

Noise pulses of less than 5ns(typical) on CE# or WE#

will not initiate a write cycle.

LOGICAL INHIBIT

Writing is inhibited by holding any one of OE# = VIL,

CE# = VIH or WE# = VIH. To initiate a write cycle CE#

and WE# must be a logical zero while OE# is a logical

one.

POWER SUPPLY DECOUPLING

In order to reduce power switching effect, each device

should have a 0.1uF ceramic capacitor connected be-

tween itsVCC and GND.

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13

MX29F400C T/B

TEMPORARY SECTOR UNPROTECT OPERATION

Start

RESET# = VID (Note 1)

Perform Erase or Program Operation

Operation Completed

RESET# = VIH

Temporary Sector Unprotect Completed(Note 2)

Notes :

1. All protected sectors are temporary unprotected.

VID=11.5V~12.5V

2. All previously protected sectors are protected again.

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14

MX29F400C T/B

TEMPORARY SECTOR UNPROTECT

Parameter Std. Description

Test Setup All Speed Options Unit

tVIDR

tRSP

VID Rise and Fall Time (See Note)

RESET# SetupTime forTemporary Sector Unprotect

Min

500

4

ns

us

Note:

Not 100% tested

TEMPORARY SECTOR UNPROTECT TIMING DIAGRAM

12V

RESET#

0 or 5V

Program or Erase Command Sequence

tVIDR

CE#

WE#

tRSP

RY/BY#

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15

MX29F400C T/B

AC CHARACTERISTICS

Parameter Std Description

Test Setup All Speed Options Unit

tREADY1

RESET# PIN Low (During Automatic Algorithms)

MAX

MIN

20

us

to Read or Write (See Note)

tREADY2

RESET# PIN Low (NOT During Automatic

Algorithms) to Read or Write (See Note)

RESET# Pulse Width (During Automatic Algorithms)

500

ns

tRP1

tRP2

tRH

10

500

0

us

ns

RESET# Pulse Width (NOT During Automatic Algorithms) MIN

RESET# HighTime Before Read(See Note)

RY/BY# Recovery Time(to CE#, OE# go low)

RY/BY# RecoveryTime(to WE# go low)

MIN

tRB1

tRB2

0

50

Note:Not 100% tested

RESET# TIMING WAVEFORM

RY/BY#

tRH

CE#, OE#

RESET#

tRP2

tReady2

Reset Timing NOT during Automatic Algorithms

tReady1

RY/BY#

CE#, OE#

WE#

tRB1

tRB2

RESET#

tRP1

Reset Timing during Automatic Algorithms

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16

MX29F400C T/B

POWER-UP SEQUENCE

ABSOLUTE MAXIMUM RATINGS

The MX29F400CT/B powers up in the Read only mode.

In addition, the memory contents may only be altered

after successful completion of the predefined command

sequences.

RATING

VALUE

-40^oC to 85^oC (*)

Ambient OperatingTemperature

AmbientTemperature with Power -55^oC to 125^oC

Applied

StorageTemperature

Applied InputVoltage

Applied OutputVoltage

VCC to Ground Potential

A9

-65^oC to 125^oC

-0.5V to 7.0V

-0.5V to 13.5V

SECTOR PROTECTION WITHOUT 12V SYS-

TEM

The MX29F400C T/B also feature a hardware sector

protectionmethodinasystemwithout12Vpowersupply.

The programming equipment do not need to supply 12

volts to protect sectors. The details are shown in sector

protectalgorithmandwaveform.

NOTICE:

Stresses greater than those listed under ABSOLUTE MAXI-

MUM RATINGS may cause permanent damage to the de-

vice. This is a stress rating only and functional operational

sections of this specification is not implied. Exposure to ab-

solute maximum rating conditions for extended period may

affect reliability.

CHIP UNPROTECT WITHOUT 12V SYSTEM

The MX29F400C T/B also feature a hardware chip

unprotection method in a system without 12V power

supply. The programming equipment do not need to

supply 12 volts to unprotect all sectors. The details are

shown in chip unprotect algorithm and waveform.

NOTICE:

Specifications contained within the following tables are sub-

ject to change.

* The automotive grade is under development.

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17

MX29F400C T/B

CAPACITANCE TA = 25^oC, f = 1.0 MHz

SYMBOL

CIN1

PARAMETER

MIN.

TYP

MAX.

8

UNIT

pF

CONDITIONS

VIN = 0V

Input Capacitance

Control Pin Capacitance

Output Capacitance

CIN2

12

pF

VIN = 0V

COUT

12

pF

VOUT = 0V

READ OPERATION

DC CHARACTERISTICS TA = -40^oC to 85^oC, VCC = 5V ±10%

SYMBOL PARAMETER

MIN.

TYP

MAX.

UNIT

CONDITIONS

ILI

Input Leakage Current

1

uA

mA

uA

mA

V

VIN = GND to VCC

VOUT = GND to VCC

CE# = VIH

ILO

Output Leakage Current

Standby VCC current

10

1

ISB1

ISB2

ICC1

ICC2

VIL

1(Note3) 5(Note3)

CE# = VCC ± 0.3V

IOUT = 0mA, f=5MHz

IOUT= 0mA, f=10MHz

Operating VCC current

Input Low Voltage

40

50

-0.3(NOTE 1)

0.8

VIH

Input High Voltage(NOTE 2) 0.7xVCC

Output Low Voltage

VCC + 0.3

0.45

V

VOL

VOH1

VOH2

V

IOL = 2.1mA, VCC= VCC MIN

IOH = -2mA, VCC= VCC MIN

IOH = -100uA,VCC=VCC MIN

Output High Voltage(TTL)

2.4

V

Output High Voltage(CMOS) VCC-0.4

V

NOTES:

1. VIL min. = -1.0V for pulse width is equal to or less than 50 ns.

VIL min. = -2.0V for pulse width is equal to or less than 20 ns.

2. VIH max. = VCC + 1.5V for pulse width is equal to or less than 20 ns

If VIH is over the specified maximum value, read operation cannot be guaranteed.

3. ISB2 20uA max. for Automotive grade. Which is under development.

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18

MX29F400C T/B

AC CHARACTERISTICS TA = -40^oC to 85^oC, VCC = 5V ± 10%

29F400C-55 29F400C-70

29F400C-90

SYMBOL PARAMETER

MIN. MAX. MIN. MAX. MIN. MAX. UNIT Conditions

tACC

tCE

Address to Output Delay

55

30

20

70

30

20

90

35

20

ns

CE#=OE#=VIL

OE#=VIL

CE# to Output Delay

OE# to Output Delay

OE# High to Output Float

(Note 1)

tOE

tDF

CE#=VIL

0

CE#=VIL

tOH

Address to Output hold

ns

CE#=OE#=VIL

TEST CONDITIONS:

Notes:

• Input pulse levels: 0.45V/0.7xVCC for 70ns & 90ns,

0V/0.7xVCC for 55ns

• Input rise and fall times: is equal to or less than 10ns

for 70ns & 90ns, 5ns for 55ns

1. tDF is defined as the time at which the output achieves

the open circuit condition and data is no longer driven.

2. Automotive grade is under development.

• Output load:1TTL gate + 100pF (Including scope and

jig) for 70ns & 90ns, 1TTLgate+30pF for 55ns max.

• Reference levels for measuring timing: 0.8V, 2.0V for

70ns & 90ns,1.5V for 55ns

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MX29F400C T/B

READ TIMING WAVEFORMS

VIH

ADD Valid

Addresses

VIL

tCE

VIH

CE#

VIL

VIH

WE#

tDF

VIL

tOE

VIH

OE#

tACC

VIL

tOH

HIGH Z

VOH

VOL

Outputs

DATA Valid

COMMAND PROGRAMMING/DATA PROGRAMMING/ERASE OPERATION

DC CHARACTERISTICS TA = -40^oC to 85^oC, VCC = 5V ± 10%

SYMBOL

ICC1 (Read)

ICC2

PARAMETER

MIN. TYP

MAX. UNIT CONDITIONS

OperatingVCC Current

40

50

mA

IOUT=0mA, f=5MHz

IOUT=0mA, f=10MHz

In Programming

ICC3 (Program)

ICC4 (Erase)

ICCES

In Erase

VCC Erase Suspend Current

2

CE#=VIH, Erase Suspended

Notes:

1. VIL min. = -0.6V for pulse width is equal to or less than 20ns.

2. If VIH is over the specified maximum value, programming operation cannot be guaranteed.

3. ICCES is specified with the device de-selected. If the device is read during erase suspend mode, current draw is

the sum of ICCES and ICC1 or ICC2.

4. All current are in RMS unless otherwise noted.

5. The Automotive grade is under development.

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MX29F400C T/B

AC CHARACTERISTICS TA = -40^oC to 85^oC, VCC = 5V ± 10%

Speed Option

SYMBOL PARAMETER

55(Note 2)

70

0

90

0

UNIT

ns

s

tOES

tCWC

tCEP

tCEPH

tAS

OE# setup time

MIN.

MAX.

TYP.

MAX.

TYP.

MAX.

TYP.

MAX.

MIN.

0

55

35

20

0

Commandprogrammingcycle

WE#programmingpulsewidth

WE#programmingpulsewidthHigh

Address setup time

70

35

20

0

90

45

20

0

tAH

Address hold time

45

30

0

45

30

0

45

0

tDS

Data setup time

tDH

Data hold time

tCESC

tDF

CE# setup time before command write

Output disable time (Note 1)

Erase time in auto chip erase

0

20

4

20

4

20

4

tAETC

32

0.7

15

9/11

300/360

50

0

32

0.7

15

9/11

300/360

50

0

32

0.7

15

9/11

300/360

50

0

s

tAETB

tAVT

Erase time in auto sector erase

s

Programming time in auto verify

(byte/wordprogramtime)

Sector address load time

CE# Hold Time

us

ns

tBAL

tCH

tCS

CE# setup to WE# going low

0

Notes:

1. tDF defined as the time at which the output achieves the open circuit condition and data is no longer driven.

2.Under condition ofVCC=5V±10%,CL=30pF,VIH/VIL=0.7xVCC/0V,VOH/VOL=1.5V/1.5V,IOL=2mA,IOH=2mA.

P/N:PM1200

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MX29F400C T/B

SWITCHING TEST CIRCUITS

DEVICE UNDER

TEST

2.7K ohm

+5V

CL

6.2K ohm

DIODES=IN3064

OR EQUIVALENT

CL=100pF Including jig capacitance for 70ns and 90ns

CL=30pF Including jig capacitance for 55ns

SWITCHING TEST WAVEFORMS for 29F400C T/B-70 and 29F400C T/B-90

0.7xVCC

2.0V

0.8V

2.0V

0.8V

TEST POINTS

0.45V

INPUT

OUTPUT

AC TESTING: Inputs are driven at 0.7xVCC for a logic "1" and 0.45V for a logic "0".

Input pulse rise and fall times are < 10ns.

SWITCHING TEST WAVEFORMS for 29F400C T/B-55

0.7xVCC

1.5V

TEST POINTS

0V

INPUT

OUTPUT

AC TESTING: Inputs are driven at 0.7xVCC for a logic "1" and 0V for a logic "0".

Input pulse rise and fall times are < 5ns.

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MX29F400C T/B

COMMAND WRITE TIMING WAVEFORM

VCC

5V

VIH

Addresses

ADD Valid

VIL

tAH

tAS

VIH

VIL

WE#

CE#

tOES

tCEPH1

tCEP

tCWC

VIH

VIL

tCS

tCH

tDH

VIH

VIL

OE#

Data

tDS

VIH

VIL

DIN

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MX29F400C T/B

AUTOMATIC PROGRAMMING TIMING WAVEFORM

ing after automatic verification starts. Device outputs

DATA# during programming and DATA# after programming

on Q7.(Q6 is for toggle bit; see toggle bit, Data# Polling,

timing waveform)

One byte data is programmed. Verify in fast algorithm

and additional programming by external control are not

required because these operations are executed auto-

matically by internal control circuit. Programming comple-

tion can be verified by Data# Polling and toggle bit check-

AUTOMATIC PROGRAMMING TIMING WAVEFORM (WORD MODE)

Vcc 5V

A11~A17

ADD Valid

2AAH

555H

A0~A10

WE#

555H

tAS

tCWC

tCEPH

tAH

tCESC

tAVT

CE#

OE#

tCEP

tDS tDH

tDF

Q0,Q1,Q2

Q4(Note 1)

DATA

Command In

Data In

Data# Polling

DATA#

Command In

Q7

Command #A0H

Command #55H

Command #AAH

(Q0~Q7)

tOE

Note :

(1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit

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MX29F400C T/B

AUTOMATIC PROGRAMMING ALGORITHM FLOWCHART (WORD MODE)

START

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data A0H Address 555H

Write Program Data/Address

NO

Toggle Bit Checking

Q6 not Toggled

YES

NO

Invalid

Verify Word Ok

Command

YES

NO

.

Q5 = 1

Reset

Auto Program Completed

YES

Auto Program Exceed

Timing Limit

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MX29F400C T/B

AUTOMATIC CHIP ERASE TIMING WAVEFORM

All data in chip are erased. External erase verification is

not required because data is erased automatically by

internal control circuit. Erasure completion can be veri-

fied by Data# Polling and toggle bit checking after auto-

matic erase starts. Device outputs 0 during erasure

and 1 after erasure on Q7.(Q6 is for toggle bit; see toggle

bit, Data# Polling, timing waveform)

AUTOMATIC CHIP ERASE TIMING WAVEFORM (WORD MODE)

Vcc 5V

A11~A17

2AAH

555H

2AAH

A0~A10

WE#

555H

tAS

tCWC

tAH

tCEPH

tAETC

CE#

OE#

tCEP

tDS tDH

Q0,Q1,

Command In

Q4(Note 1)

Data# Polling

Command In

Q7

Command #80H

Command #AAH

Command #55H

Command #10H

Command #AAH

Command #55H

(Q0~Q7)

Notes:

(1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit, Q2: Toggle bit

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MX29F400C T/B

AUTOMATIC CHIP ERASE ALGORITHM FLOWCHART (WORD MODE)

START

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data 80H Address 555H

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data 10H Address 555H

NO

Toggle Bit Checking

Q6 not Toggled

YES

NO

Invalid

DATA# Polling

Command

Q7 = 1

YES

NO

Q5 = 1

Reset

Auto Chip Erase Completed

YES

Auto Chip Erase Exceed

Timing Limit

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MX29F400C T/B

AUTOMATIC SECTOR ERASE TIMING WAVEFORM

Sector data indicated by A12 to A17 are erased. Exter-

nal erase verify is not required because data are erased

automatically by internal control circuit. Erasure comple-

tion can be verified by Data# Polling and toggle bit check-

ing after automatic erase starts. Device outputs 0 dur-

ing erasure and 1 after erasure on Q7.(Q6 is for toggle

bit; see toggle bit, Data# Polling, timing waveform)

AUTOMATIC SECTOR ERASE TIMING WAVEFORM (WORD MODE)

VCC 5V

Sector

Addressn

Sector

Address0

Sector

Address1

A12~A17

A0~A10

555H

tAS

2AAH

tCWC

tAH

WE#

CE#

tCEPH

tBAL

tAETB

tCEP

tDS

OE#

tDH

Command

In

Command

In

Q0,Q1,

Command

In

Command

In

Command

In

Command

In

Command

In

Command

In

Q4(Note 1)

Data# Polling

Command

In

Command

In

Command

In

Command

In

Command

In

Command

In

Command

In

Command

In

Q7

Command #AAH Command #55H Command #80H Command #AAH Command #55H Command #30H

(Q0~Q7)

Command #30H

Note:

(1). Q6:Toggle bit, Q5:Timing-limit bit, Q3: Time-out bit, Q2: Toggle bit

P/N:PM1200

REV. 1.0, DEC. 20, 2005

28

MX29F400C T/B

AUTOMATIC SECTOR ERASE ALGORITHM FLOWCHART (WORD MODE)

START

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data 80H Address 555H

Write Data AAH Address 555H

Write Data 55H Address 2AAH

Write Data 30H Sector Address

NO

Toggle Bit Checking

Q6 Toggled ?

Invalid Command

YES

Load Other Sector Addrss If Necessary

(Load Other Sector Address)

NO

Last Block

to Erase

YES

NO

Time-out Bit

Checking Q3=1 ?

YES

Toggle Bit Checking

Q6 not Toggled

YES

NO

Q5 = 1

Reset

Data# Polling

Q7 = 1

YES

Auto Block Erase Completed

Auto Block Erase Exceed

Timing Limit

P/N:PM1200

REV. 1.0, DEC. 20, 2005

29

MX29F400C T/B

ERASE SUSPEND/ERASE RESUME FLOWCHART

START

Write Data B0H

ERASE SUSPEND

NO

Toggle Bit checking Q6

not toggled

YES

Read Array or

Program

Reading or

NO

Programming End

YES

Write Data 30H

Delay 400us (note)

Continue Erase

ERASE RESUME

Another

NO

Erase Suspend ?

YES

Note: If the system implements an endless erase suspend/resume loop, or the number of erase suspend/resume is

exceeded 1024 times, then the 400us time delay must be put into consideration.

P/N:PM1200

REV. 1.0, DEC. 20, 2005

30

MX29F400C T/B

TIMING WAVEFORM FOR SECTOR PROTECTION FOR SYSTEM WITHOUT 12V

A1

A6

Toggle bit polling

Verify

5V

OE#

tCEP

WE#

* See the following Note!

CE#

Data

Don't care

(Note 2)

01H

F0H

tOE

A18-A16

Sector Address

Note1: Must issue "unlock for sector protect/unprotect" command before sector protection

for a system without 12V provided.

Note2: Except F0H

P/N:PM1200

REV. 1.0, DEC. 20, 2005

31

MX29F400C T/B

TIMING WAVEFORM FOR CHIP UNPROTECTION FOR SYSTEM WITHOUT 12V

A1

A6

Toggle bit polling

Verify

5V

OE#

tCEP

WE#

* See the following Note!

CE#

Data

Don't care

(Note 2)

F0H

00H

tOE

Note1: Must issue "unlock for sector protect/unprotect" command before sector unprotection

for a system without 12V provided.

Note2: Except F0H

P/N:PM1200

REV. 1.0, DEC. 20, 2005

32

MX29F400C T/B

SECTOR PROTECTION ALGORITHM FOR SYSTEM WITHOUT 12V

START

PLSCNT=1

Write "unlock for sector protect/unprotect"

Command(Table1)

Set Up Sector Addr

(A17,A16,A15,A14,A13,A12)

OE#=VIH,A9=VIH

CE#=VIL,A6=VIL

Activate WE# Pulse to start

Data don't care

Toggle bit checking

Q6 not Toggled

No

Yes

Increment PLSCNT

Set CE#=OE#=VIL

A9=VIH

Read from Sector

Addr=SA, A1=1

No

Data=01H?

Yes

PLSCNT=32?

Yes

Device Failed

Yes

Protect Another

Sector?

No

Write Reset Command

Sector Protection

Complete

P/N:PM1200

REV. 1.0, DEC. 20, 2005

33

MX29F400C T/B

CHIP UNPROTECTION ALGORITHM FOR SYSTEM WITHOUT 12V

START

Protect All Sectors

PLSCNT=1

Write "unlock for sector protect/unprotect"

Command (Table 1)

Set OE#=A9=VIH

CE#=VIL,A6=1

Activate WE# Pulse to start

Data don't care

No

Toggle bit checking

Q6 not Toggled

Increment

PLSCNT

Yes

Set OE#=CE#=VIL

A9=VIH,A1=1

Set Up First Sector Addr

Read Data from Device

No

Data=00H?

Yes

Increment

PLSCNT=1000?

Sector Addr

Yes

Device Failed

No

All sectors have

been verified?

Yes

Write Reset Command

Chip Unprotect

Complete

* It is recommended before unprotect whole chip, all sectors should be protected in advance.

P/N:PM1200

REV. 1.0, DEC. 20, 2005

34

MX29F400C T/B

ID CODE READ TIMING WAVEFORM

VCC

5V

VID

ADD

A9

VIH

VIL

VIH

VIL

ADD

A0

tACC

ADD

A1-A8

VIH

A10-A17 VIL

CE#

VIH

VIL

VIH

VIL

tCE

WE#

OE#

tOE

VIH

VIL

tDF

tOH

VIH

VIL

DATA

Q0-Q15

DATA OUT

23H/ABH (Byte)

C2H/00C2H

2223H/22ABH (Word)

P/N:PM1200

REV. 1.0, DEC. 20, 2005

35

MX29F400C T/B

ERASE AND PROGRAMMING PERFORMANCE(1)

LIMITS

PARAMETER

MIN.

TYP.(2)

MAX.(3)

UNITS

Sector Erase Time

0.7

4

15

32

sec

Chip Erase Time

Byte Programming Time

Word Programming Time

Chip Programming Time

9

300

360

13.5

9

us

11

4.5

3

us

Byte Mode

Word Mode

sec

Erase/Program Cycles

100,000

Cycles

Note: 1.Not 100% Tested, Excludes external system level over head.

2.Typical values measured at 25° C,5V.

3.Maximum values measured at 25°C,4.5V.

LATCH-UP CHARACTERISTICS

MIN.

-1.0V

MAX.

Input Voltage with respect to GND on all pins except I/O pins

Input Voltage with respect to GND on all I/O pins

Current

13.5V

Vcc + 1.0V

+100mA

-1.0V

-100mA

Includes all pins except Vcc. Test conditions: Vcc = 5.0V, one pin at a time.

DATA RETENTION

PARAMETER

MIN.

UNIT

Data Retention Time

20

Years

P/N:PM1200

REV. 1.0, DEC. 20, 2005

36

MX29F400C T/B

ORDERING INFORMATION

PART NO.

AccessTime Operating Current Standby Current Temperature PACKAGE

Remark

(ns)

MAX.(mA)

MAX.(uA)

Range

MX29F400CTMI-55

MX29F400CTMI-70

MX29F400CTMI-90

MX29F400CTTI-55

55

70

90

55

40

5

-40^oC~85^oC 44 Pin SOP

-40^oC~85^oC 48 Pin TSOP

(NormalType)

MX29F400CTTI-70

MX29F400CTTI-90

70

90

40

5

-40^oC~85^oC 48 Pin TSOP

(NormalType)

-40^oC~85^oC 48 Pin TSOP

(NormalType)

MX29F400CBMI-55

MX29F400CBMI-70

MX29F400CBMI-90

MX29F400CBTI-55

55

70

90

55

40

5

-40^oC~85^oC 44 Pin SOP

-40^oC~85^oC 48 Pin TSOP

(NormalType)

MX29F400CBTI-70

MX29F400CBTI-90

70

90

40

5

-40^oC~85^oC 48 Pin TSOP

(NormalType)

-40^oC~85^oC 48 Pin TSOP

(NormalType)

MX29F400CTMI-55G 55

MX29F400CTMI-70G 70

MX29F400CTMI-90G 90

40

5

-40^oC~85^oC 44 Pin SOP PB-free

-40^oC~85^oC 48 Pin TSOP PB-free

(NormalType)

MX29F400CTTI-55G

MX29F400CTTI-70G

MX29F400CTTI-90G

55

70

90

40

5

-40^oC~85^oC 48 Pin TSOP PB-free

(NormalType)

-40^oC~85^oC 48 Pin TSOP PB-free

(NormalType)

MX29F400CBMI-55G 55

MX29F400CBMI-70G 70

MX29F400CBMI-90G 90

MX29F400CBTI-55G 55

40

5

-40^oC~85^oC 44 Pin SOP PB-free

-40^oC~85^oC 48 Pin TSOP PB-free

(NormalType)

MX29F400CBTI-70G 70

MX29F400CBTI-90G 90

40

5

-40^oC~85^oC 48 Pin TSOP PB-free

(NormalType)

-40^oC~85^oC 48 Pin TSOP PB-free

(NormalType)

Note: The Automotive grade is under development.

P/N:PM1200

REV. 1.0, DEC. 20, 2005

37

MX29F400C T/B

PART NAME DESCRIPTION

MX 29 F 400 C T T

I

70 G

OPTION:

G: Lead-free package

blank: normal

SPEED:

55:55ns

70:70ns

90: 90ns

TEMPERATURE RANGE:

I: Industrial (-40˚aC to 85˚ C)

PACKAGE:

M:SOP

T: TSOP

BOOT BLOCK TYPE:

T: Top Boot

B: Bottom Boot

REVISION:

C

DENSITY & MODE:

400: 4M, x8/x16 Boot Sector

TYPE:

F: 5V

DEVICE:

29: Flash

P/N:PM1200

REV. 1.0, DEC. 20, 2005

38

MX29F400C T/B

PACKAGE INFORMATION

P/N:PM1200

REV. 1.0, DEC. 20, 2005

39

MX29F400C T/B

P/N:PM1200

REV. 1.0, DEC. 20, 2005

40

MX29F400C T/B

REVISION HISTORY

Revision No. Description

Page

P1

Date

DEC/20/2005

1.0

1. Removed "Preliminary" title

2. Removed commercial grade

All

3. Added access time: 55ns; Removed access time: 120ns

All

P/N:PM1200

REV. 1.0, DEC. 20, 2005

41

MX29F400C T/B

MACRONIX INTERNATIONALCO., LTD.

Headquarters:

TEL:+886-3-578-6688

FAX:+886-3-563-2888

Europe Office :

TEL:+32-2-456-8020

FAX:+32-2-456-8021

Hong Kong Office :

TEL:+86-755-834-335-79

FAX:+86-755-834-380-78

Japan Office :

Kawasaki Office :

TEL:+81-44-246-9100

FAX:+81-44-246-9105

Osaka Office :

TEL:+81-6-4807-5460

FAX:+81-6-4807-5461

Singapore Office :

TEL:+65-6346-5505

FAX:+65-6348-8096

Taipei Office :

TEL:+886-2-2509-3300

FAX:+886-2-2509-2200

MACRONIX AMERICA, INC.

TEL:+1-408-262-8887

FAX:+1-408-262-8810

http : //www.macronix.com

MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice.

型号	制造商	描述	价格	文档
29F400T-12PC	ETC	4MEGABIT (512K x 8/ 256K x 16) 5VOLT SECTOR ERASE CMOS FLASH MEMORY	获取价格
29F400T-12PI	WINBOND	Flash, 512KX8, 120ns, PDSO44, PLASTIC, SOP-44	获取价格
29F400T-12TC	ETC	4MEGABIT (512K x 8/ 256K x 16) 5VOLT SECTOR ERASE CMOS FLASH MEMORY	获取价格
29F400T-12TI	WINBOND	Flash, 512KX8, 120ns, PDSO48, TSOP-48	获取价格
29F400T-90PC	WINBOND	Flash, 512KX8, 90ns, PDSO44, PLASTIC, SOP-44	获取价格
29F400T-90PI	WINBOND	Flash, 512KX8, 90ns, PDSO44, PLASTIC, SOP-44	获取价格
29F400T-90TC	ETC	4MEGABIT (512K x 8/ 256K x 16) 5VOLT SECTOR ERASE CMOS FLASH MEMORY	获取价格
29F400T-90TI	WINBOND	Flash, 512KX8, 90ns, PDSO48, TSOP-48	获取价格
29F52	FAIRCHILD	8-Bit Registered Transceiver	获取价格
29F524DC	TI	8-BIT, DSP-PIPELINE REGISTER, CDIP28, CERAMIC, DIP-28	获取价格

29F400C-90

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