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UPD16878GS-BGG-A

更新时间：2024-12-04 13:11:23

品牌：NEC

描述：Stepper Motor Controller, 0.3A, MOS, PDSO38, 7.62 MM, PLASTIC, SSOP-38

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概述
规格参数
数据手册

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UPD16878GS-BGG-A 概述

Stepper Motor Controller, 0.3A, MOS, PDSO38, 7.62 MM, PLASTIC, SSOP-38 运动控制电子器件

UPD16878GS-BGG-A 规格参数

是否Rohs认证：	符合	生命周期：	Transferred
零件包装代码：	SSOP	包装说明：	SSOP,
针数：	38	Reach Compliance Code：	compliant
ECCN代码：	EAR99	HTS代码：	8542.39.00.01
风险等级：	5.38	其他特性：	CAN SIMULTANEOUSLY DRIVE TWO STEPPER MOTORS
模拟集成电路 - 其他类型：	STEPPER MOTOR CONTROLLER	JESD-30 代码：	R-PDSO-G38
JESD-609代码：	e6	长度：	12.7 mm
功能数量：	1	端子数量：	38
最高工作温度：	85 °C	最低工作温度：	-10 °C
最大输出电流：	0.3 A	封装主体材料：	PLASTIC/EPOXY
封装代码：	SSOP	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, SHRINK PITCH	峰值回流温度（摄氏度）：	NOT SPECIFIED
认证状态：	Not Qualified	座面最大高度：	1.8 mm
最大供电电压 (Vsup)：	5.5 V	最小供电电压 (Vsup)：	2.7 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	MOS	温度等级：	OTHER
端子面层：	TIN BISMUTH	端子形式：	GULL WING
端子节距：	0.65 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	5.6 mm
Base Number Matches：	1

UPD16878GS-BGG-A 数据手册

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DATA SHEET

MOS INTEGRATED CIRCUIT

PD16878

MONOLITHIC QUAD H BRIDGE DRIVER CIRCUIT

DESCRIPTION

The µPD16878 is a monolithic quad H bridge driver IC that employs a CMOS control circuit and a MOS FET

output circuit. Because it uses MOS FETs in its output stage, this driver IC consumes less power than conventional

driver ICs that use bipolar transistors.

Because the µPD16878 controls a motor by inputting serial data, its package has been shrunk and the number of

pins reduced. As a result, the performance of the application set can be improved and the size of the set has been

reduced.

The µPD16878 employs a current-controlled 64-step micro step driving method that drives stepper motor with low

vibration.

The µPD16878 is housed in a 38-pin plastic shrink SOP to contribute to the miniaturization of the application set.

The µPD16878 can simultaneously drive two stepper motors and is ideal for the mechanisms of camcorders.

FEATURES

• Four H bridge circuits employing power MOS FETs

• Current-controlled 64-step micro step driving

• Motor control by serial data (8 bytes x 8 bits) (original oscillation: 4-MHz input)

Data is input with the LSB first.

EVR reference setting voltage: 100 to 250 mV (@V^REF= 250 mV) ... 4-bit data input (10-mV step)

Chopping frequency: 32 to 124 kHz ... 5-bit data input (4-kHz step)

Original oscillation division or internal oscillation selectable

Number of pulses in 1 V^D: 0 to 126 pulses ... 6 bits + 2-bit data input (2 pulses/step)

Step cycle: 0.25 to 8191.75 µs ... 15-bit data input (0.25- µs step)

• 3-V power supply. Minimum operating voltage: 2.7 V (MIN.)

• Low current consumption I^DD: 3.0 mA (MAX.), I^{DD (RESET)}: 100 µA (MAX.), I^MO(RESET): 1.0 µA (MAX.)

• 38-pin plastic shrink SOP (7.62 mm (300))

ORDERING INFORMATION

Part number

Package

µPD16878GS-BGG

38-pin plastic shrink SOP (7.62 mm (300))

The information in this document is subject to change without notice. Before using this document, please

confirm that this is the latest version.

Not all devices/types available in every country. Please check with local NEC representative for

availability and additional information.

Document No.

Date Published February 2002 N CP(K)

Printed in Japan

S15974EJ1V0DS00 (1st edition)

2002

OSC^IN

OSCOUT

REF

SCLK

SDATA

LATCH

EXP0 EXP1 EXP2 EXP3

17 18 19 21

RESET

VDD

VM1

VM2

VM3

VM4

x 2

SERIAL-PARARELLE DECODER

PULSE GENERATER

EXTOUT SELECTOR

1/N

EVR1

EVR2

EVR1

EVR2

EXT

OSC

SELECTOR

OSC

CURRENT SET

EXT

–

FILTER

LGND

PGND

H BRIDGE

1ch

H BRIDGE

2ch

H BRIDGE

1ch

H BRIDGE

2ch

FIL

FBB

FBD

µPD16878

PIN CONFIGURATION

38-pin plastic shrink SOP (7.62 mm (300))

LGND

RESET

OSC^OUT

OSCIN

COSC

FIL

SCLK

SDATA

LATCH

REF

EXT

FBB

VM2

FBA

VM1

EXP0

EXP1

EXP2

EXT

EXP3

PGND

Data Sheet S15974EJ1V0DS

µPD16878

1. PIN FUNCTIONS

Pin No.

Symbol

Function

LGND

C^OSC

FIL^A

FIL^B

FIL^C

FIL^D

V^REF

V^DD

Control circuit GND pin

Chopping capacitor connection pin

α 1-ch filter capacitor connection pin (1000 pF TYP.)

α 2-ch filter capacitor connection pin (1000 pF TYP.)

β 1-ch filter capacitor connection pin (1000 pF TYP.)

β 2-ch filter capacitor connection pin (1000 pF TYP.)

Reference voltage input pin (250 mV TYP.)

Control circuit supply voltage input pin

Output circuit supply voltage input pin

β 2-ch output pin

V^M3

D²

FB^D

β 2-ch sense resistor connection pin

β 2-ch output pin

D¹

V^M4

Output circuit supply voltage connection pin

β 1-ch output pin

C²

FB^C

β 1-ch sense resistor connection pin

β 1-ch output pin

C¹

EXP0

EXP1

EXP2

PGND

EXP3

EXT^α

V^M1

Output monitor pin (open drain)

Power circuit GND pin

Output monitor pin (open drain)

Logic circuit monitor pin

Output circuit supply voltage input pin

α 1-ch output pin

A¹

FB^A

α 1-ch sense resistor connection pin

α 1-ch output pin

A²

V^M2

Output circuit supply voltage input pin

α 2-ch output pin

B¹

FB^B

α 2-ch sense resistor connection pin

α 2-ch output pin

B²

EXT^β

V^D

Logic circuit monitor pin

Video sync signal input pin

LATCH

SDATA

SCLK

OSC^IN

OSC^OUT

RESET

Latch signal input pin

Serial data input pin

Serial clock input pin

Original oscillation input pin (4 MHz TYP.)

Original oscillation output pin

Reset signal output pin

Data Sheet S15974EJ1V0DS

µPD16878

2. I/O PIN EQUIVALENT CIRCUIT

Pin Name

Equivalent Circuit

Pin Name

Equivalent Circuit

VDD

LATCH

SDATA

SCLK

Pad

OSCIN

RESET

Pull-down

resistor (125 Ω)

VDD

EXP0

EXP1

EXP2

EXP3

Pad

OSC^OUT

EXT_α

EXT

VDD

FIL

Pad

VREF

Buffer

Parasitic diodes

Pad

, A

, B

, C

, D

Data Sheet S15974EJ1V0DS

250 mV

EVR : 1010

CPU

fOSC : 64 kHz

4 MHz

OSC^IN

100 kΩ x 4

OSCOUT

REF

SCLK SDATA LATCH

EXP0 EXP1 EXP2 EXP3

RESET

3.3 V

REGULATOR

VDD

SERIAL-PARARELLE DECODER

PULSE GENERATER

EXTOUT SELECTOR

1/N

EVR1 EVR2

EXT

COSC

SELECTOR

OSC

CURRENT SET

BATTERY

4.8 to 11 V

33 pF

–

FILTER

LGND

PGND

H BRIDGE

1ch

H BRIDGE

2ch

H BRIDGE

1ch

H BRIDGE

2ch

FBA

FILA

FBB

FIL

FBC

FILC

FBD

FILD

6.8 Ω x 2

1000 pF

6.8 Ω

1000 pF

1000 pF x 2

MOTOR 1

MOTOR 2

µPD16878

4. STANDARD CHARACTERISTICS CURVES

vs. T

Characteristics

MO (RESET) vs. V Characteristics

1.4

1.2

1.0

0.8

0.6

0.4

0.2

0.8

0.6

0.4

0.2

T = 25°C,

no load,

after reset

125°C/W

Ambient Temperature T (°C)

100

120

–10

Output Circuit Supply Voltage V

(V)

DD vs. VDD Characteristics

IDD (RESET) vs. VDD Characteristics

200

150

100

T = 25°C,

= 25°C,

operating,

output open

after reset

Control Circuit Supply Volage V^DD(V)

IH/VDD, VIL/VDD vs. VDD Characteristics

IIH/IIL vs. VIN Characteristics

0.8

0.6

0.4

0.2

= 25°C,

TA = 25°C

: VIN = VDD,

IIL

: VIN = 0V

IIH

Control Circuit Supply Volage V^DD(V)

Input Voltage V^IN(V)

Data Sheet S15974EJ1V0DS

µPD16878

OSC vs. VDD Characteristics

STEP vs. VDD Characteristics

= 25°C,

150

140

130

120

110

100

= 25°C,

OSC = 100 pF,

COSC = 100 pF

DATA: all high

Control Circuit Supply Voltage V^DD(V)

VREFVER vs. VDD Characteristics

M (MAX) vs. EVR Characteristics

= 25°C, V = 6 V

= 25°C,

Rs = 6.8 Ω, fOSC = 64 kHz,

L = 25 mH/R = 100 at 1 kHz

VREF = 250 mV

Ω

100

150

200

250

300

Control Circuit Supply Voltage V^DD(V)

Reference Setting Voltage EVR (mV)

ON, tOFF vs. V Characteristics

500

400

300

200

100

= 25°C,

= 100 mA,

FIL : none

tON

tOFF

Output Circuit Supply Voltage V

(V)

Data Sheet S15974EJ1V0DS

µPD16878

5. INTERFACE (I/F) CIRCUIT DATA CONFIGURATION (f^CLK= 4-MHz EXTERNAL CLOCK INPUT)

Input data consists of serial data (8 bytes x 8 bits).

Input serial data with the LSB first, from the 1st byte to 8th byte.

(1) Initial data

(2) Standard data

<1st byte>

Bit

Data

Function

HEADER DATA2

HEADER DATA1

HEADER DATA0

−

Setting

Bit

Data

Function

HEADER DATA2

HEADER DATA1

HEADER DATA0

−

Setting

DATA selection

−

Hi-Z or L

−

Hi-Z or L

1 or 0

EXP3

1 or 0

EXP3

EXP2

EXP1

EXP0

Remark Hi-Z : High impedance,

L : Low level (current sink)

<2nd byte>

Bit

Data

Function

Setting

Bit

Data

1 or 0

Function

α ROTATION

α ENABLE

Setting

α ch CCW/CW

α ch ON/OFF

1 or 0

Start point wait

8 µs to 2.04 ms

α ch

8-bit data

input ^Note

First Point Wait Setting

(1 to 255)

∆t = 8 µs

Number of

6-bit data

input

pulses in 1 VD

Setting (0 to 63)

∆n = 2 pulses ^Note

α Pulse Number

Note Input other than “0”.

Note The number of pulses can be varied in 2-pulse

steps.

<3rd byte>

Bit

Data

Function

Setting

Bit

Data

Function

Setting

15-bit data

Start point drive

wait

α ch pulse

cycle

8-bit data

input ^Note

First Point

8 µs to 2.04 ms

0.25 to 8191.75 µs

Setting

α Pulse Width

Low-order

8-bit data

input

Magnetize Wait Setting

(1 to 255)

∆t = 8 µs

(1 to 32767)

∆t = 0.25 µs

Note Input other than “0”.

Data Sheet S15974EJ1V0DS

µPD16878

<4th byte>

Bit

<4th byte>

Bit

Data

Function

OSCSEL

Setting

Data

Function

Setting

1 or 0

Internal/external

1 or 0

Current Set α

set2/set1

15-bit data

α ch

pulse cycle :

0.25 to 8191.75 µs

Setting

Chopping

frequency :

32 to 124 kHz

Setting

α Pulse Width

High-order

7-bit data

input

5-bit data

input

Chopping

(1 to 32767)

∆t = 0.25 µs

Frequency

(8 to 31)^Note

∆f = 4 kHz

Note The frequency is 0 kHz if 0 to 7 is input.

<5th byte>

Bit

Data

EXT^α

EXT^β

Bit

Data

1 or 0

Function

β ROTATION

β ENABLE

Setting

β ch CCW/CW

β ch ON/OFF

ENABLE α ^Note1

ROTATION α^Note2

Pulse Out α

FF7 α

ENABLE β ^Note1

ROTATION β ^Note2

Pulse Out β

FF7 β

Note 5

1 or 0

β ch

Number of

6-bit data

input

pulses in 1 VD

Setting (1 to 63)

∆n = 2 pulses ^Note

β Pulse Number

FF3 α

Checksum^Note3

Chopping^Note4

FF3 β

FF2 β

FF1 β

Notes 1. H level : Conducts, L level : Stops

2. H level : Reverse (CCW),

Note The number of pulses can be varied in 2-pulse

steps.

L level : Forward (CW)

3. H level : Normal data input,

L level : Abnormal data input

4. Not output in internal oscillation mode.

5. Select one of D0 to D6 and input “1”.

If two or more of D0 to D6 are selected,

they are positively ORed for output.

<6th byte>

Bit

Data

Function

Setting

Bit

Data

Function

Setting

15-bit data

α ch Output current

setting 2 EVR : 100

to 250 mV

4-bit data

input

α ch

β ch pulse

cycle:

Current Set2

Setting (0 to 15) ^Note

0.25 to 8191.75 µs

Setting

β Pulse Width

Low-order

8-bit data

input

α ch Output current

setting 1 EVR : 100

to 250 mV

(1 to 32767)

∆t = 0.25 µs

4-bit data

input

α ch

Current Set1

Setting (0 to 15) ^Note

Note A voltage of about double EVR is output to

the FIL pin.

Data Sheet S15974EJ1V0DS

µPD16878

<7th byte>

Bit

Data

Function

Setting

Data

Function

Setting

1 or 0

Current Set β

set2/set1

β ch Output

15-bit data

4-bit data

input

β ch

current setting 2

β ch pulse

cycle:

Current Set2

EVR: 100 to 250 mV

Setting (0 to 15)^Note

0.25 to 8191.75 µs

Setting

High-order

7-bit data

input

β Pulse Width

β ch Output

4-bit data

input

β ch

current setting 1

(1 to 32767)

∆t = 0.25 µs

Current Set1

EVR: 100 to 250 mV

Setting (0 to 15)^Note

Note A voltage of about double EVR is output to

the FIL pin.

<8th byte>

Bit

Data

1 or 0

Function

Setting

Bit

Data

1 or 0

Function

Setting

1 or 0

Checksum

Checksum ^Note

Checksum

Checksum ^Note

Note Data is input so that the sum of the 1st

through the 8th bytes is 00H.

Data Sheet S15974EJ1V0DS

µPD16878

Data Configuration

Data can be input in either of two ways. Initial data can be input when the power is first applied, or standard data

can be input during normal operation. Input serial data with the LSB first, i.e., starting from the D0 bit (LSB) of the 1st

byte. Therefore, the D7 bit of the 8th byte is the most significant bit (MSB).

When inputting initial data, set a start point wait time that specifies the delay from power application to pulse

output, and the start point drive wait time. At the same time, also set a chopping frequency and a reference voltage

(EVR) that determines the output current of each channel. Because the µPD16878 has an EXT pin for monitoring the

internal operations, the parameter to be monitored can be selected by initial data.

When inputting standard data, input the rotation direction of each channel, the number of pulses, and the data for

the pulse cycle.

Initial data or standard data is selected by using bits D5 to D7 of the 1st byte (see Table 5-1).

Table 5-1. Data Selection Mode (1st byte)

Data type

Initial data

Standard data

Remark If the high-order three bits are high, the initial data is selected;

if they are low, the standard data is selected.

Data other than (0, 0, 0) and (1, 1, 1) must not be input.

Input the serial data during start point wait time.

Details of Data Configuration

How to input initial data and standard data is described below.

(1) Initial data input

<1st byte>

The 1st byte specifies the type of data (initial data or standard data) and determines the presence or absence of

the EXP pin output. Bits D5 to D7 of this byte specify the type of data as shown in Table 5-1, while bits D0 to D3

select the EXP output (open drain).

Table 5-2. 1st Byte Data Configuration

Bit

Data

0 or 1

The EXP pin goes low (current sink) when the input data is “0”, and high (high impedance state) when the input

data is “1”. Pull this pin up to V^DDfor use. Input “0” to bit D4.

Data Sheet S15974EJ1V0DS

µPD16878

<2nd byte>

The 2nd byte specifies the delay between data being read and data being output. This delay is called the start up

wait time, and the motor can be driven from that point at which the start up wait time is “0”. This time is counted at the

rising edge of V^D. The start up wait time can be set to 2.04 ms (when a 4-MHz clock is input), and can be fine-tuned

by means of 8-bit division (8-µs step: with 4-MHz clock). The start up wait time is set to 2.04 ms when all the bits of

the 2nd byte are set to “1”.

Caution Always input data other than “0” to this byte because the start up wait time is necessary for

latching data. If “0” is input to this byte, data cannot be updated. Transfer standard data during the

start up wait time.

<3rd byte>

The 3rd byte specifies the delay between the start point wait time being cleared and the output pulse being

generated. This time is called the start up drive wait time, and the output pulse is generated from the point at which

the start up drive wait time reaches “0”. The start up drive wait time is counted at the falling edge of the start up wait

time. The start up drive wait time can be set to 2.04 ms (with 4-MHz clock) and can be fine-tuned by means of 8-bit

division (8 µs step: with 4-MHz clock). The start up drive wait time is set to 2.04 ms when all the bits of the 3rd byte

are “1”.

Caution Always input data other than “0” to this byte because the start up drive wait time is necessary for

latching data. If “0” is input to this byte, data cannot be updated.

<4th byte>

The 4th byte selects a chopping frequency by using 5-bit data. It also selects whether the chopping frequency is

created by dividing the original oscillation (external clock) or whether the internal oscillator is used. The chopping

frequency is selected by bits D0 to D4. Bit D7 specifies the method used to create the chopping frequency. When this

bit is “0”, the original oscillation (external clock input to OSC^IN) is used; when it is “1”, the internal oscillator is used.

Bits D5 and D6 are fixed to “0”.

The chopping signal is output after the initial data has been input and the first standard data has been latched

(see Timing Chart).

Table 5-3. 4th Byte Data Configuration (Initial data)

Bit

Data

0 or 1

The chopping frequency is set to 0 kHz and to a value in the range of 32 to 124 kHz (in 4-kHz steps), as follows.

Although the chopping frequency is set by 5 bits of data, it is internally configured using 7-bit data (with the low-

order 2 bits fixed to 0).

Data Sheet S15974EJ1V0DS

µPD16878

Bit

f^OSC= 0 kHz

Data

0 or 1

Bit

f^OSC= 0 kHz

f^OSC= 32 kHz

f^OSC= 36 kHz

f^OSC= 124 kHz

Data

0 or 1

Bit

Data

0 or 1

Bit

Data

0 or 1

Bit

Data

0 or 1

<5th byte>

The 5th byte selects a parameter to be output to the EXT pin (logic operation monitor pin). Input data to bits D0 to

D6 of this byte. Bit D7 is fixed to “0”.

There are two EXT pins. EXTα indicates the operating status of α ch, and EXTβ indicates that of β ch. The

relationship between each bit and each EXT pin is as shown in Table 5-4.

Table 5-4. 5th Byte Data Configuration (Initial data)

Bit

Data

EXT^α

Not used

EXT^β

Not used

0 or 1

ENABLE α

ROTATION α

PULSEOUT α

FF7 α

ENABLE β

ROTATION β

PULSEOUT β

FF7 β

FF3 α

FF3 β

CHECKSUM

CHOPPING

FF2 β

FF1 β

The checksum bit is cleared to “0” in the event of an error. Normally, it is “1”.

If two or more signals that output signals to EXTα and EXTβ are selected, they are positively ORed for output.

Caution The CHOPPING signal is not output in internal oscillation mode.

Data Sheet S15974EJ1V0DS

µPD16878

Remark The meanings of the symbols listed in Table 5-4 are as follows:

ENABLE : Output setting (H : Conducts, L : Stops)

ROTATION : Rotation direction (H : Reverse (CCW), L : Forward (CW))

PULSEOUT : Output pulse signal

FF7 : Presence/absence of pulse in LATCH cycle (Outputs H level if output pulse information exists in

standard data.)

FF3 : Pulse gate (output while pulse exists)

FF2 : Outputs H level during start up wait time + start up drive wait time

FF1 : Outputs H level during start up wait time

CHECKSUM : Checksum output (H : when normal data is transmitted,

L : when abnormal data is transmitted)

CHOPPING : Chopping wave output (in original oscillation mode only)

<6th byte>

The 6th byte sets the peak output current value of α ch. The output current is determined by the EVR reference

voltage.

The 250-mV (TYP.) voltage input from an external source to the V^REFpin is internally doubled and input to a 4-bit

D/A converter. By dividing this voltage by 4-bit data, an EVR reference voltage can be set inside the IC within the

range of 200 to 500 mV, in units of 20 mV.

The µPD16878 can set two values of the EVR reference voltage in advance. This is done by using bits D0 to D3

or D4 to D7. Which of the two EVR reference voltage values is to be used is specified by the CURRENT SET bit in

the standard data.

If all the bits of the 6th byte are “0”, the EVR reference voltage of 200 mV is selected; if they are “1”, the EVR

reference voltage of 500 mV is selected.

Table 5-5. 6th Byte Data Configuration (Initial data)

Bit

Data

0 or 1

Remark Bits D4 to D7 : Reference voltage 2 (EVR α²)

Bits D0 to D3 : Reference voltage 1 (EVR α¹)

<7th byte>

The 7th byte specifies the peak output current value of β ch. The output current is determined by the EVR

reference voltage.

The 250-mV (TYP.) voltage input from an external source to the V^REFpin is internally doubled and input to a 4-bit

D/A converter. By dividing this voltage by 4-bit data, an EVR reference voltage can be set inside the IC within a range

of 200 to 500 mV, in units of 20 mV.

The µPD16878 can set two values of the EVR reference voltage in advance. This is done using bits D0 to D3 or

D4 to D7. Which of the two EVR reference voltage values is to be used is specified by the CURRENT SET bit in the

standard data.

If all the bits of the 7th byte are “0”, the EVR reference voltage of 200 mV is selected; if they are “1”, the EVR

reference voltage of 500 mV is selected.

Data Sheet S15974EJ1V0DS

µPD16878

Table 5-6. 7th Byte Data Configuration (Initial data)

Bit

Data

0 or 1

Remark Bits D4 to D7 : Reference voltage 2 (EVR β²)

Bits D0 to D3 : Reference voltage 1 (EVR β¹)

<8th byte>

The 8th byte is checksum data. Normally, the sum of the 8-byte data is 00H.

If the sum is not 00H because data transmission is abnormal, the stepping operation is inhibited and the

checksum output pin (EXT pin) is kept “L”.

(2) Standard data input

<1st byte>

The 1st byte specifies the type of data and whether the EXP pin output is used, such as when the initial data is

input.

Table 5-7. 1st Byte Data Configuration

Bit

Data

0 or 1

The EXP pin goes low (current sink) when the input data is “0”, and high (high impedance state) when the input

data is “1”. Input “0” to bit D4.

<2nd byte>

The 2nd byte specifies the rotation direction of the α channel, enables output of the α channel, and the number of

pulses (126 pulses MAX.) during the 1V^Dperiod (in 1 cycle of FF2) of the α channel.

Bit D7 is used to specify the rotation direction. The rotation is in the forward direction (CW mode) when this bit is

“0”; it is in the reverse direction (CCW mode) when the bit is “1”.

Bit D6 is used to enable the output of the α channel. The α channel enters the high impedance state when this bit

is “0”; it is in conduction mode when the bit is “1”.

The number of pulses is set by bits D0 to D5. It is set by 6 bits in terms of software. However, the actual circuit

uses an 8-bit counter with the low-order two bits fixed to “0”. Therefore, the number of pulses that is actually

generated during start up wait time + start up drive wait (FF2) cycle is the number of pulses input x 2. The number of

pulses can be set to a value in the range of 0 to 126, in units of 2 pulses.

Data Sheet S15974EJ1V0DS

µPD16878

Table 5-8. 2nd Byte Data Configuration (Standard data)

Bit

Data

0 or 1

Rotation direction

<3rd and 4th bytes>

ENABLE

Number of pulses

The 3rd and 4th bytes select the pulse cycle of the α channel and which of the two reference voltages, created in

the initial mode, is to be used (CURRENT SETα).

The pulse cycle is specified using 15 bits : bits D0 (least significant bit) to D7 of the 3rd byte, and bits D0 to D6

(most significant bit) of the 4th byte. The pulse cycle can be set to a value in the range of 0.25 to 8191.75 µs in units

of 0.25 µs (with a 4-MHz clock).

CURRENT SETα is specified by bit D7 of the 4th byte. When this bit is “0”, reference voltage 1 (EVRα¹) is

selected; when it is “1”, reference voltage 2 (EVRα²) is selected. For further information, refer to the description of the

6th byte of the initial data.

Table 5-9. 4th Byte Data Configuration (Standard data)

Table 5-10. 3rd Byte Data Configuration (Standard data)

Bit

Data

0 or 1

CURRENT SETα Most significant

Least significant bit

bit

(Reference) 6th Byte Data Configuration for Initial Data

Bit

0 or 1

Data

0 or 1

Remark Bits D4 to D7 : Reference voltage 2 (EVR α²)

Bits D0 to D3 : Reference voltage 1 (EVR α¹)

<5th byte>

The 5th byte specifies the rotation direction of the β channel, enables output of the β channel, and the number of

pulses (126 pulses MAX.) during the 1V^Dperiod (in one cycle of FF2) of the β channel.

Bit D7 is used to specify the rotation direction. The rotation is in the forward direction (CW mode) when this bit is

“0”; it is in the reverse direction (CCW mode) when the bit is “1”.

Bit D6 is used to enable the output of the β channel. The β channel goes into a high impedance state when this bit

is “0”; it is in the conduction mode when the bit is “1”.

The number of pulses is set by bits D0 to D5. It is set by six bits in terms of software. However, the actual circuit

uses an 8-bit decoder with the low-order two bits fixed to “0”. Therefore, the number of pulses that is actually

generated during start up wait time + start up drive wait (FF2) cycle is the number of pulses input x 2. The number of

pulses can be set in a range of 0 to 126 and in units of 2 pulses.

Data Sheet S15974EJ1V0DS

µPD16878

Table 5-11. 5th Byte Data Configuration (Standard data)

Bit

Data

0 or 1

Rotation direction

<6th and 7th bytes>

ENABLE

Number of pulses

The 6th and 7th bytes select the pulse cycle of the β channel and which of the two reference voltages, created in

the initial mode, is to be used (CURRENT SETβ).

The pulse cycle is specified using 15 bits : bits D0 (least significant bit) to D7 of the 6th byte, and bits D0 to D6

(most significant bit) of the 7th byte. The pulse cycle can be set to a value in the range of 0.25 to 8191.75 µs in units

of 0.25 µs (with a 4-MHz clock).

CURRENT SETβ is specified by bit D7 of the 7th byte. When this bit is “0”, reference voltage 1 (EVRβ¹) is

selected; when it is “1”, reference voltage 2 (EVRβ²) is selected. For further information, refer to the description of the

7th byte of the initial data.

Table 5-12. 7th Byte Data Configuration (Standard data)

Table 5-13. 6th Byte Data Configuration (Standard data)

Bit

Data

0 or 1

CURRENT SETβ Most significant bit

(Reference) 7th Byte Data Configuration for Initial Data

Least significant bit

Bit

0 or 1

Data

0 or 1

Remark Bits D4 to D7 : Reference voltage 2 (EVR β²)

Bits D0 to D3 : Reference voltage 1 (EVR β¹)

<8th byte>

The 8th byte is checksum data. Normally, the sum of the 8-byte data is 00H.

If the sum is not 00H because data transmission is abnormal, the stepping operation is inhibited and the

checksum output pin (EXT pin) is held at “L”.

Data Sheet S15974EJ1V0DS

µPD16878

(Data Update Timing)

The standard data (pulse width, number of pulses, rotation direction, current setting, and ENABLE) of this product

are set and updated at the following latch timing.

Table 5-14. Data Update Timing

ENABLE change

Pulse width

1 → 1

FF2↓

0 → 1

FF2↓

FF1↓

1 → 0

FF2↓

0 → 0

−

Number of pulses

Rotation direction

Current setting

ENABLE

The timing at which data is to be updated differs, as shown in Table 5-14, depending on the enabled status.

For example, suppose the enable signal is currently “0” (output high impedance) and “1” (output conduction) is

input by the next data. In this case, the pulse width, number of pulses, and rotation direction signals are updated at

FF2(upon the completion of start up wait), and the current setting and ENABLE signals are updated at FF1 (upon

completion of start up drive wait).

FF1

Start up wait

FF2

Start up wait +

start up drive wait

Pulse output

Pulse width, number of pulses, and rotation direction

are updated.

Current setting and ENABLE are updated

(ENABLE change: 0 to 1).

(1)

(2)

(3)

LATCH

Initial data

identification

Standard data

identification

I1 data is output.

FF1, FF2 output

Data Sheet S15974EJ1V0DS

µPD16878

(1)

(2)

Not output

(3)

Pulse width

Internal data retained.

Output reset

Updated to S2 data at FF2

Rotation direction

Number of pulses

Internal output retained

Not output

Internal data retained.

Output reset

Current setting

ENABLE

Internal output retained

Not output

Updated to S2 data at either FF1 or FF2

by enable data of (2)

The initial mode of this product is as follows.

The IC operation can be initialized as follows:

(1) Turns ON V^DD.

(2) Make RESET input “L”.

(3) Input serial initial data.

In initial mode, the operating status of the IC is as shown in Table 5-15.

Table 5-15. Operations in Initial Mode

Item

Current consumption

OSC

Specifications

100 µA

Oscillation stops.

Input of external clock is inhibited.

Input inhibited.

V^D

FF1 to FF7

PULSE OUT

EXP0 to EXP3

“L” level

Undefined in the case of (1) above.

Previous value is retained in the case of (2) above.

Can be updated by serial data in the case of (3) above.

Can be accessed after initialization in the case of (1) above.

Can be accessed after RESET has gone “H” in the case of (2) above.

Can be accessed in the case of (3) above.

Serial operation

Step pulse output is inhibited and FF7 is made “L” if the following conditions are satisfied.

(1) If the set number of pulses (2nd/5th: standard data) is 00H.

(2) If the checksum value is other than 00H.

(3) If the start up wait time is set to 1 V^Dor longer.

(4) If the start up wait time + start up drive wait time is set to 1 V^Dor longer.

(5) If start up wait is completed earlier than LATCH (↑).

(6) If V^Dis not input.

Data Sheet S15974EJ1V0DS

µPD16878

Cautions on Correct Use

(1) With this product, input the data for start up wait and start up drive wait. Because the standard data are

set or updated by these wait times, if the start up wait time and start up drive wait time are not input, the

data are not updated.

(2) The start up wait time must be longer than LATCH.

(3) If the rising of the start up drive wait time is the same as the falling of the last output pulse, a count error

occurs, and the IC may malfunction.

(4) Input the initial data in a manner that it does not straddle the video sync signal (V^D). If it does, the initial

data is not latched.

(5) Transmit the standard data during the start up wait time (FF1). If it is input at any other time, the data

may

not be transmitted correctly.

(6) If the LGND potential is undefined, the data may not be input correctly. Keep the LGND potential to the

minimum level. It is recommended that LGND and PGND be divided for connection (single ground) to

prevent the leakage of noise from the output circuit.

Data Sheet S15974EJ1V0DS

µPD16878

6. ELECTRICAL SPECIFICATIONS

Absolute Maximum Ratings (TA = 25°C)

Parameter

Supply voltage

Symbol

Condition

Rating

–0.5 to +6.0

–0.5 to +11.2

–0.5 to V^DD+ 0.5

500

Unit

V^DD

V^M

Input voltage

V^IN

Reference voltage

V^REF

I^M(DC)

I^M(pulse)

H bridge drive current ^{Note 1}

Instantaneous H bridge drive

current ^{Note 1}

PW ≤ 10 ms, Duty ≤ 5%

150

mA/phase

300

Power consumption ^{Note 2}

Peak junction temperature

Storage temperature

P^T

1.0

150

°C

T^CH(MAX.)

T^stg

–55 to +150

Notes 1. Permissible current per phase with the IC mounted on a PCB.

2. When the IC is mounted on a glass epoxy PCB (10 cm x 10 cm x 1 mm).

Caution If the absolute maximum rating of even one of the above parameters is exceeded even

momentarily, the quality of the product may be degraded. Absolute maximum ratings, therefore,

specify the values exceeding which the product may be physically damaged. Be sure to use the

product within the range of the absolute maximum ratings.

Recommended Operating Range

Parameter

Supply voltage

Symbol

MIN.

2.7

4.8

TYP.

250

MAX.

5.5

Unit

V^DD

V^M

Input voltage

V^IN

V^DD+ 0.4

275

Reference voltage

V^REF

225

EXP pin input voltage

EXP pin input current

H bridge drive current

Clock frequency (OSC^IN)

Clock frequency amplitude

Serial clock frequency (SCLK)

Video sync signal width

LATCH signal wait time

SCLK wait time

V^EXPIN

V^DD

I^EXPIN

100

µA

MHz

I^M(DC)

−100

−200

3.9

+100

+200

5.0

I^M(pulse)^{Note 1}

f^CLK^{Note 2}

VfCLK ^{Note 2}

f^SCLK

PW^(VD)^{Note 3}

t^(VD-LATCH)^{Note 4}

t^(SCLK-LATCH)^{Note 4}

t^setup^{Note 4}

t^hold^{Note 4}

f^OSC^{Note 3}

t^RST

0.7 V^DD

V^DD

5.0

MHz

250

400

SDATA setup time

SDATA hold time

Chopping frequency

Reset signal pulse width

Operating temperature

Peak junction temperature

124

kHz

µs

100

−10

T^A

+85

125

°C

T^CH(MAX.)

Notes 1. PW ≤ 10 ms, duty ≤ 5%

2. C^OSC= 33 pF, V^REF= 250 mV

3. f^CLK= 4 MHz

4. Serial data delay time(see the figure on the next page.)

Data Sheet S15974EJ1V0DS

µPD16878

(VD-LATCH)

LATCH

SCLK

64 clocks (8 bits x 8 bytes)

(SCLK-LATCH)

Ignored because LATCH is at H level.

50%

LATCH

SDATA

SCLK

50%

(SCLK-LATCH)

setup

hold

Data Sheet S15974EJ1V0DS

µPD16878

ELECTRICAL CHARACTERISTICS

DC Characteristics (Unless otherwise specified, VDD = 3.3 V, VM = 6.0 V, VREF = 250 mV, TA = 25°C, fCLK = 4 MHz,

C^OSC= 33 pF, CFIL = 1000 pF, EVR = 100 mV (0000))

Parameter

Off V^Mpin current

V^DDpin current

Symbol

I^MO(RESET)

Condition

MIN.

TYP.

MAX.

1.0

Unit

µA

No load, reset period

Output open

I^DD

3.0

V^DDpin current

I^DD(RESET)

V^IH

Reset period

100

High level input voltage

LATCH, SCLK, SDATA, V^D,

RESET, OSCIN

0.7 V^DD

0.9 V^DD

Low level input voltage

Input hysteresis voltage

V^IL

V^H

0.3 V^DD

300

Monitor output voltage 1

(EXT ^α, ^β)

V^OM^α^(H), V^OM^β^(H)5th byte

V^OM^α^(L), V^OM^β^(L)5th byte

0.1 V^DD

V^DD

Monitor output voltage 2

V^OEXP(H)

Pull up (V^DD)

(EXP0 to EXP3 : open drain)

VOEXP(L)

I^OEXP= 100 µA

0.1 V^DD

0.06

High level input current

I^IH

V^IN= V^DD

Low level input current

Reset pin high level input

current

I^IL

V^IN= 0 V

−1.0

µA

I^IH(RST)

V^RST= V^DD

1.0

Reset pin low level input

current

I^IL(RST)

V^RST= 0

−1.0

µA

Input pull down resistor

R^IND

R^ON

LATCH, SCLK, SDATA, V^D

I^M= 100 mA

200

5.0

kΩ

Ω

H bridge ON resistance ^{Note 1}

3.5

Chopping frequency (internal

oscillation: C^OSC= 100 pF)

f^OSC(1)

f^OSC(2)

DATA: 00000 (4th byte)

DATA: 11111 (4th byte)

kHz

100

124

150

250

Step frequency

V^Ddelay time ^{Note 2}

f^STEP

Minimum step

kHz

∆t^VD

Sine wave peak output

current ^{Note 3}

I^M

L = 25 mH/R = 100 Ω (1 kHz)

EVR = 200 mV (1010)

R^S= 6.8 Ω, f^OSC= 64 kHz

EVR = 200 mV (1010)

FIL pin voltage ^{Note 4}

V^EVR

370

400

430

FIL pin step voltage ^{Note 4}

V^EVRSTEP

Minimum step

AC Characteristics (Unless otherwise specified, VDD = 3.3 V, VM = 6.0 V, TA = 25°C, fCLK = 4 MHz)

Parameter

Symbol

Condition

I^M= 100 mA ^{Note 5}

MIN.

TYP.

1.0

MAX.

2.0

Unit

H bridge output circuit turn on t^ONH

time

µs

H bridge output circuit turn off t^OFFH

time

I^M= 100 mA ^{Note 5}

1.0

2.0

µs

Notes 1. Total of ON resistance at top and bottom of output H bridge

2. By OSC^INand V^Dsync circuit

3. FB pin is monitored.

4. FIL pin is monitored. A voltage about twice that of the EVR value is output to the FIL pin.

5. 10 to 90% of the pulse peak value without filter capacitor (C^FIL)

Data Sheet S15974EJ1V0DS

Initialization

RESET

V^D

LATCH

DATA

Initial

Standard

S¹

Standard

EXP : 0

ENABLE: 1

Standard

S⁵

EXP

: 1

EXP : 1

error DATA

I¹

S²

S³

S⁴

Dummy data

ENABLE: 1

EXP: 1

EXP

: 0

EXP

: 1

ENABLE: 0

OSC^OUT

(original oscillation)

Input at rising

edge of RESET

Output by

I1 data

Start point wait

(FF1)

Start point wait +

start point drive wait

(FF2)

Output by

I1 data

Output by S2

data setting

ENABLE OUT^{Note 1}

Output by S5

data setting

Output by chopping

setting of I1 data

Chopping pulse

Output by EXP

setting of S1 data

Output by EXP

setting of S2DATA

Output by EXP

setting of I1 data

EXP0 to EXP3

PULSE OUT

S⁴DATA output

Pulse error

S²DATA output

Enable

Outputs high level while

pulse is being generated

PULSE GATE

(FF3)

Outputs high level for standard data while a

pulse output signal exists (LATCH cycle)

No pulse output because

data is erroneous

PULSE CHECK^{Note 2}

(FF7)

CHECK SUM^{Note 3}

High level because

data is normal.

Low level because

data is abnormal.

Restore to high level because

data is normal.

Notes 1. ENABLE is set at the falling edge of FF1 when the level changes from low

to high, and at the falling edge of FF2 when the level changes from high

to low.

SCLK

SDATA

8th byte

1st byte

2. FF7 is an output signal that is used to check for the presence or absence

of a pulse in the standard data, is updated at the rising edge of LATCH

and reset once at the falling edge of LATCH. If CHECK SUM is other than

“00H”, FF7 goes low, inhibiting pulse output, even if a pulse is generated.

3. CHECK SUM output is updated at the rising edge of LATCH.

(LSB)

Data is held at rising edge of SCLK.

µPD16878

TIMING CHART (2)

CLK

(PULSE OUT)

MOB

(CW mode)

Current direction: A2

H bridge

1ch output status

α , β

Current direction: A1

Current direction: B2

H bridge ,

α β

2ch output status

Current direction: B1

(Expanded view)

CLK

CW mode^Note1

Note1

CW mode

Note2

CCW mode

PULSE OUT

Position No.

CCW

H bridge

1ch output status

CCW

H bridge

2ch output status

Notes1. In CW mode : Position No. is incremented.

2. In CCW mode : Position No. is decremented.

CCW

Remarks 1. The current value of the actual wave is approximated to the value shown on the next page.

2. The C¹, C², D¹, and D²pins of β channel correspond to the A¹, A², B¹, and B²pins of α channel.

3. The CW mode is set if the D7 bit of the 2nd and 5th bytes of the standard data is “0”.

4. The CCW mode is set if the D7 bit of the 2nd and 5th bytes of the standard data is “1”.

Data Sheet S15974EJ1V0DS

µPD16878

RELATION BETWEEN ROTATION ANGLE, PHASE CURRENT, AND VECTOR QUANTITY

(64-DIVISION MICRO STEP)

(Values of µPD16878 for reference)

Step

Rotation angle (θ )

A phase current

TYP.

B phase current

TYP.

100

Vector quantity

TYP.

MIN.

−

MAX.

−

MIN.

−

MAX.

−

θ 0

100

θ 1

5.6

2.5

9.8

17.0

26.5

36.1

45.3

54.1

62.6

68.4

75.7

82.3

88.1

93.2

97.4

100.7

103

−

100

−

100.48

100

θ 2

11.3

16.9

22.5

28.1

33.8

39.4

12.4

22.1

31.3

40.1

48.6

58.4

65.7

72.3

78.1

83.2

87.4

90.7

93.2

−

19.5

29.1

38.3

47.1

55.6

63.4

70.7

77.3

83.1

88.2

92.4

95.7

98.1

100

93.2

90.7

87.4

83.2

78.1

72.3

65.7

58.4

48.6

40.1

31.3

22.1

12.4

2.5

98.1

95.7

92.4

88.2

83.1

77.3

70.7

63.4

55.6

47.1

38.3

29.1

19.5

9.8

103

100.7

97.4

93.2

88.1

82.3

75.7

68.4

62.6

54.1

45.3

36.1

26.5

17.0

−

θ 3

100.02

99.99

99.98

99.97

99.98

99.97

99.98

99.99

100.02

100

θ 4

θ 5

θ 6

θ 7

θ 8

θ 9

50.6

56.3

61.9

67.5

73.1

78.8

84.4

θ 10

θ 11

θ 12

θ 13

θ 14

θ 15

θ 16

100.48

100

−

100

−

Remark These data do not indicate guaranteed values.

Data Sheet S15974EJ1V0DS

µPD16878

7. PACKAGE DRAWING

38-PIN PLASTIC SSOP (7.62 mm (300))

detail of lead end

NOTE

ITEM MILLIMETERS

Each lead centerline is located within 0.10 mm of

its true position (T.P.) at maximum material condition.

12.7 0.3

0.65 MAX.

0.65 (T.P.)

+0.05

0.37

−0.1

0.125 0.075

1.675 0.125

1.55

7.7 0.2

5.6 0.2

1.05 0.2

+0.1

0.2

−0.05

0.6 0.2

0.10

+7°

3°

−3°

P38GS-65-BGG-1

Data Sheet S15974EJ1V0DS

µPD16878

8. RECOMMENDED SOLDERING CONDITIONS

When soldering this product, it is highly recommended to observe the conditions as shown below. If other

soldering processes are used, or if the soldering is performed under different conditions, please make sure to consult

with our sales offices.

For more details, refer to our document “SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL”

(C10535E).

Type of Surface Mount Device

µPD16878GS-BGG: 38-pin plastic shrink SOP (7.62 mm (300))

Process

Soldering conditions

Symbol

Infrared Ray Reflow

Peak temperature: 235°C or below (Package surface temperature),

Reflow time: 30 seconds or less (at 210°C or higher),

Maximum number of reflow processes: 3 time or less,

IR35-00-3

Number of days: None ^Note

Flux: Rosin-based flux with low chlorine content (chlorine 0.2 Wt% or below) is

recommended.

Vapor Phase Soldering Peak temperature: 215°C or below (Package surface temperature),

Reflow time: 40 seconds or less (at 200°C or higher),

VP15-00-3

Maximum number of reflow processes: 3 time or less,

Number of days: None ^Note

Flux: Rosin-based flux with low chlorine content (chlorine 0.2 Wt% or below) is

recommended.

Wave Soldering

Solder temperature: 260°C or below, Flow time: 10 seconds or less,

Maximum number of flow processes: 1 time,

WS60-00-1

Pre-heating temperature: 120°C or below (Package surface temperature),

Flux: Rosin-based flux with low chlorine content (chlorine 0.2 Wt% or below) is

recommended.

Partial Heating Method Pin temperature: 300°C or below,

Heat time: 3 seconds or less (Per each side of the device).

−

Note Number of days the device can be stored after the dry pack has been opened, at conditions of 25°C, 65%RH.

Caution Apply only one kind of soldering condition to a device, except for “partial heating method”, or the

device will be damaged by heat stress.

Data Sheet S15974EJ1V0DS

µPD16878

[MEMO]

Data Sheet S15974EJ1V0DS

µPD16878

NOTES FOR CMOS DEVICES

PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note:

Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and

ultimately degrade the device operation. Steps must be taken to stop generation of static electricity

as much as possible, and quickly dissipate it once, when it has occurred. Environmental control

must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using

insulators that easily build static electricity. Semiconductor devices must be stored and transported

in an anti-static container, static shielding bag or conductive material. All test and measurement

tools including work bench and floor should be grounded. The operator should be grounded using

wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need

to be taken for PW boards with semiconductor devices on it.

HANDLING OF UNUSED INPUT PINS FOR CMOS

Note:

No connection for CMOS device inputs can be cause of malfunction. If no connection is provided

to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence

causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels

of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused

pin should be connected to V^DDor GND with a resistor, if it is considered to have a possibility of

being an output pin. All handling related to the unused pins must be judged device by device and

related specifications governing the devices.

STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note:

Power-on does not necessarily define initial status of MOS device. Production process of MOS

does not define the initial operation status of the device. Immediately after the power source is

turned ON, the devices with reset function have not yet been initialized. Hence, power-on does

not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the

reset signal is received. Reset operation must be executed immediately after power-on for devices

having reset function.

Data Sheet S15974EJ1V0DS

µPD16878

•

The information in this document is current as of January, 2002. The information is subject to

change without notice. For actual design-in, refer to the latest publications of NEC's data sheets or

data books, etc., for the most up-to-date specifications of NEC semiconductor products. Not all

products and/or types are available in every country. Please check with an NEC sales representative

for availability and additional information.

•

No part of this document may be copied or reproduced in any form or by any means without prior

written consent of NEC. NEC assumes no responsibility for any errors that may appear in this document.

NEC does not assume any liability for infringement of patents, copyrights or other intellectual property rights of

third parties by or arising from the use of NEC semiconductor products listed in this document or any other

liability arising from the use of such products. No license, express, implied or otherwise, is granted under any

patents, copyrights or other intellectual property rights of NEC or others.

•

Descriptions of circuits, software and other related information in this document are provided for illustrative

purposes in semiconductor product operation and application examples. The incorporation of these

circuits, software and information in the design of customer's equipment shall be done under the full

responsibility of customer. NEC assumes no responsibility for any losses incurred by customers or third

parties arising from the use of these circuits, software and information.

While NEC endeavours to enhance the quality, reliability and safety of NEC semiconductor products, customers

agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. To minimize

risks of damage to property or injury (including death) to persons arising from defects in NEC

semiconductor products, customers must incorporate sufficient safety measures in their design, such as

redundancy, fire-containment, and anti-failure features.

NEC semiconductor products are classified into the following three quality grades:

"Standard", "Special" and "Specific". The "Specific" quality grade applies only to semiconductor products

developed based on a customer-designated "quality assurance program" for a specific application. The

recommended applications of a semiconductor product depend on its quality grade, as indicated below.

Customers must check the quality grade of each semiconductor product before using it in a particular

application.

"Standard": Computers, office equipment, communications equipment, test and measurement equipment, audio

and visual equipment, home electronic appliances, machine tools, personal electronic equipment

and industrial robots

"Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster

systems, anti-crime systems, safety equipment and medical equipment (not specifically designed

for life support)

"Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life

support systems and medical equipment for life support, etc.

The quality grade of NEC semiconductor products is "Standard" unless otherwise expressly specified in NEC's

data sheets or data books, etc. If customers wish to use NEC semiconductor products in applications not

intended by NEC, they must contact an NEC sales representative in advance to determine NEC's willingness

to support a given application.

(Note)

(1) "NEC" as used in this statement means NEC Corporation and also includes its majority-owned subsidiaries.

(2) "NEC semiconductor products" means any semiconductor product developed or manufactured by or for

NEC (as defined above).

M8E 00. 4

UPD16878GS-BGG-A 相关器件

型号	制造商	描述	价格	文档
UPD16878GS-BGG-E1-A	RENESAS	IC,MOTOR CONTROLLER,CMOS/MOS,SSOP,38PIN	获取价格
UPD16878GS-BGG-E2-A	RENESAS	IC,MOTOR CONTROLLER,CMOS/MOS,SSOP,38PIN	获取价格
UPD16879	NEC	MONOLITHIC QUAD H BRIDGE DRIVER CIRCUIT	获取价格
UPD16879GS-BGG	NEC	MONOLITHIC QUAD H BRIDGE DRIVER CIRCUIT	获取价格
UPD16879GS-BGG-A	RENESAS	IC,MOTOR CONTROLLER,CMOS,SSOP,38PIN	获取价格
UPD16879GS-BGG-E2-A	RENESAS	IC,MOTOR CONTROLLER,CMOS,SSOP,38PIN	获取价格
UPD168807K9-4EG-E1-A	RENESAS	1.9A SWITCHING CONTROLLER, 1500kHz SWITCHING FREQ-MAX, PQCC48, 6 X 6 MM, 0.40 MM PITCH, PLASTIC, VQFN-48	获取价格
UPD16882	NEC	MONOLITHIC CD-ROM/DVD-ROM 3-PHASE SPINDLE MOTOR DRIVER	获取价格
UPD16882GS	NEC	MONOLITHIC CD-ROM/DVD-ROM 3-PHASE SPINDLE MOTOR DRIVER	获取价格
UPD16882GS-A	RENESAS	IC,MOTOR CONTROLLER,CMOS/MOS,SOP,30PIN	获取价格