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NHD-0220FZ-SYG-GBW

更新时间：2025-06-11 20:28:59

品牌：NEWHAVEN

描述：LCD MOD CHAR 2X20 Y/G TRANSFL

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概述
数据手册

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NHD-0220FZ-SYG-GBW 概述

LCD MOD CHAR 2X20 Y/G TRANSFL

NHD-0220FZ-SYG-GBW 数据手册

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User’s Guide

NHD-0220FZ-SYG-GBW

LCM

(Liquid Crystal Display Module)

RoHS Compliant

NHD- Newhaven Display

0220- 2 Lines x 20 Characters

FZ-

Version Line

Transflective

SYG- Side Yellow/Green LED B/L

G-

B-

W-

STN-Gray

6:00 View

Wide Temperature (-20 ~ +70c)

For product support, contact

Newhaven Display International

2511 Technology Drive, #101

Elgin, IL 60124

Tel: (847) 844-8795 Fax: (847) 844-8796

June 5, 2008

DOCUMENT REVISION HISTORY

Version

DATE

DESCRIPTION

CHANGED BY

First issue

Apr-06-2006

CONTENTS

Item

Page

Functions & Features

Mechanical specifications

Dimensional Outline

Absolute maximum ratings

Block diagram

Pin description

Contrast adjust

Optical characteristics

Electrical characteristics

Timing Characteristics

Instruction description

Display character address code:

character pattern

7-8

9-12

14--21

Quality Specifications

ꢀꢁ&EATURES

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ꢄꢁ "UILTꢅIN CONTROLLER ꢆ+3ꢇꢇꢈꢈ5 OR EQUIVALENTꢉ

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ꢍꢁ ꢀꢎꢀꢈ DUTY CYCLEꢏꢀꢎꢂBIAS

ꢂꢁ "+, TO BE DRIVEN BY PINꢀꢐ PINꢄꢐ OR PINꢀꢂꢐ PINꢀꢈ OR !ꢐ +

ꢈꢁ ꢄꢇCHARACTERS ꢑꢄLINES DISPLAY

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&34. POSITIVE

34. 'RAY

ꢈ /ꢒCLOCK

2EFLECTIVE

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34. 9ELLOWꢎ'REEN

ꢀꢄ /ꢒCLOCK

34.ꢅ"LUE

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"ACKLIGHT 4YPE

4RANSFLECTIVE

4RANSMISSIVE

ꢍꢁꢄ6 INPUT

)NTERNAL 0OWER

##&,

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ꢊꢁꢊ INPUT

9ELLOWꢅ'REEN

3UPER 7IDE

"ACKLIGHT #OLOR

4EMPERATURE 2ANGE

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4OUCH SCREEN

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#HARACTER PITCH

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ꢈꢂꢁꢇMMꢆ,ꢉꢑꢄꢇꢁꢇMMꢆ7ꢉꢑ -AXꢃꢁꢂꢆ(ꢉMM

ꢍꢈꢁꢇMMꢆ,ꢉꢑꢀꢇꢁꢇMMꢆ7ꢉ

ꢀꢁꢃꢂMMꢆ,ꢉꢑꢊꢁꢄꢊMMꢆ7ꢉ

ꢄꢁꢀꢂMMꢆ,ꢉꢑꢍꢁꢀꢓMMꢆ7ꢉ

!PPROXꢁ

ꢀ

4.Absolute maximum ratings

Item

Symbol

Standard

Unit

Power voltage

DD-VSS

7.0

VDD

+70

+80

Input voltage

Operating temperature range

Storage temperature range

5.Block diagram

VIN

VOP

VST

VSS

-20

-30

6.Interface pin description

External

Pin no.

Symbol

Function

connection

Signal ground for LCM (GND)

Power supply for logic (+5V) for LCM

Contrast adjust

Power supply

R/W

MPU

Read/write select signal

Operation (data read/write) enable signal

Four low order bi-directional three-state data bus lines.

Used for data transfer between the MPU and the LCM.

These four are not used during 4-bit operation.

Four high order bi-directional three-state data bus lines.

Used for data transfer between the MPU

7~10

DB0~DB3

MPU

11~14

DB4~DB7

MPU

LED+

LED-

Power supply for LED backlight(+4.2V)

Power supply

Power supply for LED backlight(0V)

7.Contrast adjust

DD~V0: LCD Driving voltage

VR: 10k~20k

8.Optical characteristics

TN type display module (Ta=25k, VDD=5.0V)

Item

Symbol

Condition

Min.

Typ.

120

Max.

Unit

Viewing angle

ꢀ

-25

deg

ꢁ

-30

Contrast ratio

Response time (rise)

150

Response time (fall)

STN type display module (Ta=25k, VDD=5.0V)

Item

Symbol

Condition

Min.

Typ.

Max.

Unit

Viewing angle

ꢀ

-60

deg

-40

ꢁ

150

250

Contrast ratio

Response time (rise)

Response time (fall)

9.Electrical characteristics

DC characteristics

Parameter

Symbol

Conditions

Min.

Typ.

Max.

Unit

Supply voltage for LCD

Input voltage

Ta =25k

4.7

4.6

5.0

DD-V

5.5

3.0

1.0

VDD

0.6

Supply current

Ta=25k, VDD=5.0V

Input leakage current

“H” level input voltage

“L” level input voltage

“H” level output voltage

“L” level output voltage

Backlight supply voltage

Backlight supply current

LKG

2.2

2.4

Twice initial value or less

LOH=-0.25mA

LOH=1.6mA

0.4

4.2

F= 4.2V

10.Timing Characteristics

Write cycle (Ta=25k, VDD=5.0V)

Parameter

Enable cycle time

Enable pulse width

Enable rise/fall time

RS; R/W setup time

Symbol

Test pin

Min.

500

300

Typ.

Max.

Unit

tr, tf

tsu1

100

RS; R/W

RS; R/W address hold

th1

time

Read data output delay

Read data hold time

tsu2

th2

DB0~DB7

Write mode timing diagram

VIH1

VIL1

th1

tsu1

VIL1

VIH1

VIL1

tsu2

th2

VIH1

VIL1

VIH1

VIL1

VALID DATA

Read cycle (Ta=25k, VDD=5.0V)

Parameter

Enable cycle time

Enable pulse width

Enable rise/fall time

RS; R/W setup time

Symbol

Test pin

Min.

500

300

Typ.

Max.

Unit

tr, tf

tsu

100

RS; R/W

RS; R/W address hold

time

Read data output delay

Read data hold time

tdh

DB0~DB7

Read mode timing diagram

VIH1

VIL1

tsu

VIL1

VIH1

VIL1

VIH1

VIL1

tdh

VIH1

VIL1

VIH1

VIL1

VALID DATA

11.Instruction description

11.1Outline

To overcome the speed difference between the internal clock of KS0066U and the MPU clock, KS0066U

performs internal operations by storing control in formations to IR or DR. The internal operation is determined

according to the signal from MPU, composed of read/write and data bus (Refer to Table7).

Instructions can be divided largely into four groups:

1) KS0066U function set instructions (set display methods, set data length, etc.)

2) Address set instructions to internal RAM

3) Data transfer instructions with internal RAM

4) Others

The address of the internal RAM is automatically increased or decreased by 1.

Note: during internal operation, busy flag (DB7) is read “High”.

Busy flag check must be preceded by the next instruction.

11.2 Instruction Table

Instruction code

Execution

time (fosc=

270 KHZ

Instruction

Description

RS R/W DB7 DB6

DB4 DB3 DB2

DB0

Write “20H” to DDRA and set

DDRAM address to “00H” from

Set DDRAM address to “00H”

From AC and return cursor to

Its original position if shifted.

The contents of DDRAM are

not changed.

Clear

1.53ms

Display

Return

Home

1.53ms

39us

Assign cursor moving direction

And blinking of entire display

Entry mode

Set

Display ON/

OFF control

I/D SH

Set display (D), cursor (C), and

Blinking of cursor (B) on/off

Control bit.

Set cursor moving and display

Shift control bit, and the

Direction, without changing of

DDRAM data.

Set interface data length (DL:

Cursor or

39us

S/C R/L

Display shift

Function

set

Bit/4-bit), numbers of display

Line (N: =2-line/1-line) and,

Display font type (F: 5x11/5x8)

Set CGRAM address in

address

Set

39us

CGRAM

Address

Set

AC5 AC4 AC3 AC2 AC1 AC0

Counter.

Set DDRAM address in

address

Counter.

DDRAM

Address

AC6 AC5 AC4 AC3 AC2 AC1 AC0

Whether during internal

Operation or not can be known

By reading BF. The contents of

Address counter can also be

read.

Read busy

Flag and

Address

0us

BF AC6 AC5 AC4 AC3 AC2 AC1 AC0

Write data into internal RAM

(DDRAM/CGRAM).

Write data

Address

Read data

From RAM

43us

D7 D6 D5 D4 D3 D2 D1 D0

Read data from internal RAM

(DDRAM/CGRAM).

NOTE:

When an MPU program with checking the busy flag (DB7) is made, it must be necessary 1/2fosc is

necessary for executing the next instruction by the falling edge of the “E” signal after the busy flag (DB7) goes

to “Low”.

11.3Contents

1) Clear display

R/W

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

Clear all the display data by writing “20H” (space code) to all DDRAM address, and set DDRAM address

to “00H” into AC (address counter).

Return cursor to the original status, namely, bring the cursor to the left edge on the fist line of the display.

Make the entry mode increment (I/D=“High”).

2) Return home

R/W

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

Return home is cursor return home instruction.

Set DDRAM address to “00H” into the address counter.

Return cursor to its original site and return display to its original status, if shifted.

Contents of DDRAM does not change.

3) Entry mode set

R/W

DB7

DB6

DB5

DB4

DB3

DB2

DB1

I/D

DB0

Set the moving direction of cursor and display.

I/D: increment / decrement of DDRAM address (cursor or blink)

When I/D=“high”, cursor/blink moves to right and DDRAM address is increased by 1.

When I/D=“Low”, cursor/blink moves to left and DDRAM address is increased by 1.

*CGRAM operates the same way as DDRAM, when reading from or writing to CGRAM.

SH: shift of entire display

When DDRAM read (CGRAM read/write) operation or SH=“Low”, shifting of entire display is not performed. If

SH =“High” and DDRAM write operation, shift of entire display is performed according to I/D value. (I/D=“high”.

shift left, I/D=“Low”. Shift right).

4) Display ON/OFF control

R/W

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

Control display/cursor/blink ON/OFF 1 bit register.

D: Display ON/OFF control bit

When D=“High”, entire display is turned on.

When D=“Low”, display is turned off, but display data remains in DDRAM.

C: cursor ON/OFF control bit

When D=“High”, cursor is turned on.

When D=“Low”, cursor is disappeared in current display, but I/D register preserves its data.

B: Cursor blink ON/OFF control bit

When B=“High”, cursor blink is on, which performs alternately between all the “High” data and display

characters at the cursor position.

When B=“Low”, blink is off.

5) Cursor or display shift

R/W

DB7

DB6

DB5

DB4

DB3

S/C

DB2

R/L

DB1

DB0

Shifting of right/left cursor position or display without writing or reading of display data.

This instruction is used to correct or search display data.

During 2-line mode display, cursor moves to the 2nd line after the 40th digit of the 1st line.

Note that display shift is performed simultaneously in all the lines.

When display data is shifted repeatedly, each line is shifted individually.

When display shift is performed, the contents of the address counter are not changed.

Shift patterns according to S/C and R/L bits

S/C

R/L

Operation

Shift cursor to the left, AC is decreased by 1

Shift cursor to the right, AC is increased by 1

Shift all the display to the left, cursor moves according to the display

Shift all the display to the right, cursor moves according to the display

6) Function set

R/W

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

DL: Interface data length control bit

When DL=“High”, it means 8-bit bus mode with MPU.

When DL=“Low”, it means 4-bit bus mode with MPU. Hence, DL is a signal to select 8-bit or 4-bit bus mode.

When 4-but bus mode, it needs to transfer 4-bit data twice.

N: Display line number control bit

When N=“Low”, 1-line display mode is set.

When N=“High”, 2-line display mode is set.

F: Display line number control bit

When F=“Low”, 5x8 dots format display mode is set.

When F=“High”, 5x11 dots format display mode.

7) Set CGRAM address

R/W

DB7

DB6

DB5

AC5

DB4

AC4

DB3

AC3

DB2

AC2

DB1

AC1

DB0

AC0

Set CGRAM address to AC.

The instruction makes CGRAM data available from MPU.

8) Set DDRAM address

R/W

DB7

DB6

AC6

DB5

AC5

DB4

AC4

DB3

AC3

DB2

AC2

DB1

AC1

DB0

AC0

Set DDRAM address to AC.

This instruction makes DDRAM data available form MPU.

When 1-line display mode (N=LOW), DDRAM address is form “00H” to “4FH”.In 2-line display mode (N=High),

DDRAM address in the 1st line form “00H” to “27H”, and DDRAM address in the 2nd line is from “40H” to

“67H”.

9) Read busy flag & address

R/W

DB7

DB6

AC6

DB5

AC5

DB4

AC4

DB3

AC3

DB2

AC2

DB1

AC1

DB0

AC0

This instruction shows whether KS0066U is in internal operation or not.

If the resultant BF is “High”, internal operation is in progress and should wait BF is to be LOW, which by then

the nest instruction can be performed. In this instruction you can also read the value of the address counter.

10) Write data to RAM

R/W

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

Write binary 8-bit data to DDRAM/CGRAM.

The selection of RAM from DDRAM, and CGRAM, is set by the previous address set instruction (DDRAM

address set, CGRAM address set).

RAM set instruction can also determine the AC direction to RAM.

After write operation. The address is automatically increased/decreased by 1, according to the entry mode.

11) Read data from RAM

R/W

DB7

DB6

DB5

DB4

DB3

DB2

DB1

DB0

Read binary 8-bit data from DDRAM/CGRAM.

The selection of RAM is set by the previous address set instruction. If the address set instruction of RAM

is not performed before this instruction, the data that has been read first is invalid, as the direction of AC is not

yet determined. If RAM data is read several times without RAM address instructions set before, read operation,

the correct RAM data can be obtained from the second. But the first data would be incorrect, as there is no

time margin to transfer RAM data.

In case of DDRAM read operation, cursor shift instruction plays the same role as DDRAM address set

instruction, it also transfers RAM data to output data register.

After read operation, address counter is automatically increased/decreased by 1 according to the entry

mode.

After CGRAM read operation, display shift may not be executed correctly.

NOTE: In case of RAM write operation, AC is increased/decreased by 1 as in read operation.

At this time, AC indicates next address position, but only the previous data can be read by the read

instruction.

12.Display character address code:

10 11 12 13 14 15 16 17 18 19 20

00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13

40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53

13.Standard character pattern

14.QUALITY SPECIFICATIONS

14.1 Standard of the product appearance test

Manner of appearance test: The inspection should be performed in using 20W x 2 fluorescent lamps.

Distance between LCM and fluorescent lamps should be 100 cm or more. Distance between LCM and

inspector eyes should be 30 cm or more.

Viewing direction for inspection is 45° from vertical against LCM.

Fluorescent

Lamps

30cm

min

100cm _min

LCD

LCM

Definition of zone:

A Zone

B Zone

A Zone: Active display area (minimum viewing area).

B Zone: Non-active display area (outside viewing area).

14.2 Specification of quality assurance

AQL inspection standard

Sampling method: MIL-STD-105E, Level II, single sampling

Defect classification (Note: * is not including)

Classify

Major

Item

Note

AQL

0.65

Display state

Short or open circuit

LC leakage

Flickering

No display

Wrong viewing direction

Contrast defect (dim, ghost)

Back-light

1,8

Non-display

Flat cable or pin reverse

Wrong or missing component

Background color deviation

Black spot and dust

Line defect, Scratch

Rainbow

Minor

Display

state

1.0

Chip

Pin hole

Protruded

Polarizer

Soldering

Wire

Bubble and foreign material

Poor connection

Position, Bonding strength

TAB

Note on defect classification

No.

Item

Criterion

Not allow

Short or open circuit

LC leakage

Flickering

No display

Wrong viewing direction

Wrong Back-light

Contrast defect

Refer to approval sample

Background

deviation

color

Point defect,

Black spot, dust

(including Polarizer)

Point

Size

Accpetable Qty.

Disregard

φ<0.10

0.10<φ0.20

0.20<φ0.25

0.25<φ0.30

φ>0.30

φ = (X+Y)/2

Unitꢀmm

Line defect,

Scratch

Line

Acceptable Qty.

---

Disregard

0.015W

3.0L 0.03W

2.0L 0.05W

1.0L

0.1ꢀW

0.05<W

---

Applied as point defect

Unit: mm

Not more than two color changes across the viewing area.

Rainbow

Item

Criterion

Chip

Acceptable criterion

Remark:

0.5mm

9/2

X: Length

direction

Y: Short

direction

Z: Thickness

direction

Acceptable criterion

t: Glass

thickness

0.5mm

W: Terminal

Width

Acceptable criterion

shall not reach to ITO

Acceptable criterion

Disregard

0.2

Acceptable criterion

ꢁ

ꢂ

t/3

No.

Item

Criterion

Segment

pattern

(1) Pin hole

φ < 0.10mm is acceptable.

W = Segment width

φ = (X+Y)/2

Point Size

φꢃꢄꢅW

Acceptable Qty

Disregard

ꢃꢄꢅW< φꢃꢄꢂW

φꢀꢃꢄꢂW

Unit: mm

Back-light

Soldering

(1) The color of backlight should correspond its

specification.

(2) Not allow flickering

(1) Not allow heavy dirty and solder ball on PCB.

(The size of dirty refer to point and dust defect)

(2) Over 50% of lead should be solderedon Land.

Lead

Land

50% lead

10 Wire

(1) Copper wire should not be rusted

(2) Not allow crack on copper wire connection.

(3) Not allow reversing the position of the flat cable.

(4) Not allow exposed copper wire inside the flat cable.

(1) Not allow screw rust or damage.

11* PCB

(2) Not allow missing or wrong putting of component.

Item

Criterion

Protruded

W: Terminal Width

Acceptable criteria:

Y ≤ 0.4

TAB

1. Position

ITO

W11/3W

H11/3H

TAB

TAB bonding strength test

TAB

P (=F/TAB bonding width) 650gf/cm ,(speed rate: 1mm/min)

5pcs per SOA (shipment)

Total no. of acceptable

Defect

A. Zone

Maximum 2 minor non-conformities per one unit.

Defect distance: each point to be separated over 10mm

B. Zone

It is acceptable when it is no trouble for quality and assembly

in customer’s end product.

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