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NJU7384V

更新时间：2024-12-03 13:08:59
品牌：NJRC
描述：Stepper Motor Controller, 0.7A, CMOS, PDSO32, SSOP-32

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NJU7384V 概述

Stepper Motor Controller, 0.7A, CMOS, PDSO32, SSOP-32 运动控制电子器件

NJU7384V 规格参数

生命周期：Active零件包装代码：SSOP
包装说明：SSOP-32针数：32
Reach Compliance Code：compliant风险等级：5.74
Is Samacsys：N模拟集成电路 - 其他类型：STEPPER MOTOR CONTROLLER
JESD-30 代码：R-PDSO-G32长度：11 mm
功能数量：1端子数量：32
最高工作温度：85 °C最低工作温度：-40 °C
最大输出电流：0.7 A封装主体材料：PLASTIC/EPOXY
封装代码：LSSOP封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, LOW PROFILE, SHRINK PITCH认证状态：Not Qualified
座面最大高度：1.45 mm最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：3 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
宽度：5.6 mmBase Number Matches：1

NJU7384V 数据手册

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NJU7384  
Pulse Input Bipolar Stepper Motor Driver  
■GENERAL DESCRIPTION  
■PACKAGE OUTLINE  
NJU7384 is a bipolar drive stepping motor driver.  
The control method used is a simple pulse train input control  
(STEP & DIR) method of programming. Also, low power  
consumption was realized as a result of the adoption of a highly  
efficient CMOS.  
As the control functions, the external input RESET and ENABLE  
functions are used, and as the protective function, a thermal  
shutdown (TSD) is incorporated.  
The package uses the low thermal resistance SSOP32 which  
can withstand a high output current.  
NJU7384V  
■FEATURES  
• Operating Voltage  
3.0 to 5.5V（Logic : VDD）  
4.0 to 8.0V（H bridge : VMM）  
700mA/ch  
• Maximum Output Current  
• Pulse Input (STEP＆DIR) Control  
• Half / Full Step Change Function  
• Thermal Shutdown Circuit  
• Thermal Shutdown Alarm Output  
• RESET Function  
• ENABLE Function  
• CMOS Technology  
• Package Outline  
SSOP32  
■BLOCK DIAGLAM  
VDD  
VMM1  
OUTA1  
OUTA2  
STEP  
DIR  
PGNG1  
VMM2  
HSM  
OUTB1  
OUTB2  
RESET  
ENABLE  
GND  
PGND2  
TSD  
ALARM  
TSD  
Ver.2007-08-20  
- 1 -  
NJU7384  
■PIN FUNCTION  
1. NC  
2. NC  
3. NC  
4. VDD  
5. NC  
6. STEP  
7. DIR  
8. HSM  
9. RESET  
10. ENABLE  
11. TSD ALARM  
12. NC  
32. VMM1  
31. VMM1  
1
2
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
3
30. OUTA1  
29. OUTA1  
28. OUTA2  
27. OUTA2  
26. PGND1  
25. PGND1  
24. PGND2  
23. PGND2  
22. OUTB2  
21. OUTB2  
20. OUTB1  
19. OUTB1  
18. VMM2  
4
5
6
7
8
9
10  
11  
12  
13  
14  
15  
16  
13. GND  
14. NC  
15. NC  
16. NC  
17. VMM2  
■PIN DESCRIPTION  
PIN No.  
SYMBOL  
FUNCTION  
NOTE  
1,2,3  
NC  
VDD  
Non connection pins  
-
4
5
6
Logic Power-Supply input pin  
Non connection pin  
-
NC  
-
STEP  
Pulse signal input pin for motor  
rotation control pin  
1 pulse input ⇒ 1 clock motion  
7
8
9
DIR  
HSM  
Forward / Reverse rotation control  
Full / Half step mode control pin  
Phase initialize signal input pin  
“H”= Forward (CW), ”L”= Reverse (CCW)  
“H”= Full step, ”L”= Half step  
“H”= Normal operation,  
RESET  
”L”= Phase initialize  
10  
11  
ENABLE  
Output signal all off control signal “H”= Normal operation,  
input pin  
”L”= Output all off  
TSD  
ALARM  
NC  
TSD alarm output pin  
TSD operating =”L” signal output  
12  
13  
Non connection pins  
Logic ground (GND) pin  
Non connection pins  
H bridge power-supply pins  
Output pin B1  
-
GND  
-
14,15,16  
17,18  
19,20  
21,22  
23,24  
25,26  
27,28  
29,30  
31,32  
NC  
-
VMM2  
Connect to motor power-supply  
OUTB1  
OUTB2  
PGND2  
PGND1  
OUTA2  
OUTA1  
VMM1  
-
Output pin B2  
-
H bridge ground (GND) pin  
H bridge ground (GND) pin  
Output pin A2  
-
-
-
Output pin A1  
-
H bridge power-supply pins  
Connect to motor power-supply  
* Short all logic ground terminals and the H bridge ground terminal externally.  
* Short all H bridge power supply voltage terminals externally.  
* Fix the potential of unused logic input terminals externally.  
Ver.2007-08-20  
- 2 -  
NJU7384  
■ABSOLUTEMAXIMUMRATINGS  
(Ta=25°C)  
PARAMETER  
RATINGS  
SYMBOL(unit)  
NOTE  
Logic Power Supply Voltage  
H Bridge Power Supply Voltage  
Logic Input Voltage  
Motor Output Current (Max)  
Logic Input Current  
Operating Temperature Range  
Operating Junction Temperature Range  
Storage Temperature Rnage  
Power Dissipation  
+7.0  
+9.0  
VDD (V)  
VMM (V)  
VID (V)  
*1)  
-
-
-
-
-
-
-
-0.3  
~
VDD  
700  
IOPEAK(mA/ch)  
IIPEAK (mA)  
Topr (°C)  
Tj(°C)  
Tstg(°C)  
PD (mW)  
10  
-40  
~
+85  
-40  
-50  
~
~
+150  
+150  
1175  
*2)  
*
1) : VDD ≤ VMM  
*
2) : EIAJ/JEDEC STD 2 Layer substrate  
■RECOMMENDEDOPERATINGCONDITIONS  
(Ta=25°C)  
NOTE  
VDD ≤ VMM  
PARAMETER  
Logic Power Supply Voltage  
Range  
SYMBOL  
VDD  
MIN.  
3.0  
TYP.  
5.0  
MAX.  
5.5  
UNIT  
V
H Bridge Power Supply  
VMM  
4.0  
6.0  
8.0  
V
-
Voltage Range  
Logic H Input Voltage  
Logic L Input Voltage  
STEP-ON Time  
VIH  
VIL  
3.5  
0
-
-
-
-
-
-
VDD  
V
1.2  
V
tONMIN  
tOFFMIN  
tDS  
10  
10  
1
-
-
-
-
µs  
µs  
µs  
µs  
VDD=5.0V,  
No load  
STEP-OFF Time  
Data Setup Time  
Hold Time  
tDH  
1
Input Clock Frequency  
fCLK  
-
-
50  
kHz  
Ver.2007-08-20  
- 3 -  
NJU7384  
■ELECTRICALCHARACTERISTICS  
(Ta=25°C, VDD=5V, VMM=6V)  
PARAMETER  
■General  
SYMBOL  
CONDITION  
MIN.  
TYP.  
MAX.  
UNIT  
STEP, DIR, HSM, RESET,  
ENABLE=”5V”, No Load,  
VDD Meas.  
I DD  
-
-
0.3  
0.3  
0.6  
0.6  
mA  
mA  
Operating Current  
STEP, DIR, HSM, RESET,  
ENABLE=”5V”, No load,  
I MM  
VMM Meas.  
Thermal Shutdown  
Operating Temperature  
Thermal Shutdown  
Hysteresis  
TTSD  
THYS  
-
-
-
180  
30  
-
-
°C  
°C  
-
■Input (STEP, DIR, HSM, ENABLE, RESET Terminals)  
STEP, DIR, HSM, ENABLE,  
IIH  
IIL  
-
-
-
1
-
µA  
µA  
RESET =”5V”  
STEP, DIR, HSM, ENABLE,  
RESET =”0V”  
Logic Input Current  
-1  
■H Bridge (Output)  
H Output Voltage  
L Output Voltage  
Io=+400mA  
Io= -400mA  
5.5  
-
5.7  
0.2  
-
V
V
VOH  
VOL  
0.4  
Upper Side Output ON  
Resistance  
Io=400mA  
-
0.75  
1.25  
Ω
Ω
ROH  
Under Side Output ON  
Resistance  
Io=400mA  
-
-
-
0.50  
1.0  
1.00  
-
ROL  
Output Leak Current  
IO LEAK  
µA  
■Signal Output  
TSD Alarm L Output  
Voltage  
TSD Pull-up Resistance  
No external pull-up resistance  
-
VTSD  
RTSD  
-
-
-
0.3  
-
V
10  
kΩ  
Ver.2007-08-20  
- 4 -  
NJU7384  
■TIMING CONDITION  
tONMIN  
tOFFMIN  
50%  
STEP  
t DS  
tDH  
DIR,HSM,  
RESET,  
ENABLE  
■TRUTH TABLE  
LOGIC IN  
MODE  
H
L
OPERATE  
Hi Z  
VDD  
DIR  
H
L
CW  
CCW  
H
L
FULL STEP  
HALF STEP  
OPERATE  
RESET  
OPERATE  
Hi Z  
HSM  
H
L
RESET  
H
L
ENABLE  
*VMM : Motor voltage supply  
*OPERATE : Follow the input logic  
*Hi Z : Output all off (A1, A2, B1,B2)  
■EXCITATION SEQUENCE  
Condition: FULL STEP, HSM=ENABLE=RESET  
Condition: HALF STEP, HSM=LOW, ENABLE=RESET=HIGH  
0
L
H
L
H
-
1
H
L
L
H
+
-
2
H
L
3
L
H
H
L
-
Pulse  
OUTA1  
OUTA2  
OUTB1  
OUTB2  
IA  
Pulse  
OUTA1  
OUTA2  
OUTB1  
OUTB2  
IA  
0
L
H
L
H
-
1
Hi Z  
Hi Z  
L
2
H
L
L
H
+
-
3
H
4
H
L
5
Hi Z  
Hi Z  
H
6
L
H
H
L
-
7
L
L
H
H
L
Hi Z  
Hi Z  
+
H
L
Hi Z  
Hi Z  
-
H
L
0
+
+
0
+
+
IB  
-
-
0
+
+
0
IB  
-
+
DIR=HIGH CW  
DIR=LOW CCW  
DIR=HIGH CW  
DIR=LOW CCW  
* Regarding the current flow direction, the direction A1→A2 and B1→B2 is indicated as +, and the direction A2→A1 and  
B2→B1 is indicated as –.  
Ver.2007-08-20  
- 5 -  
NJU7384  
■POWER SUPPLY ON/OFF TIMING  
Regarding the switch-on sequence of the logic power supply VDD and the motor power supply VMM, input VDD after  
MM has risen. The recommended sequence is shown below.  
V
ON  
OFF  
VDD VMM  
VDD VMM  
≤
≤
VMM  
VDD  
The RESET signal is "L" level in the range of turning ON . And Phase logic is initialized.  
RESET  
The STEP terminal is a negative edge active.  
If STEP input terminal is no Signal. It signal level is fixed at H level.  
“ “  
STEP  
HSM/DIR  
ENABLE  
IA  
IB  
Excitation phase backup section  
Phase logic initialization section  
■RECOMMENDED STEP MODE CHANGEOVER (HSM)  
The current flowing through the stepping motor must be controlled continuously so that a mis-step does not occur.  
Also, the following precautions must be observed concerning changing of the setting of the HSM input.  
(1) A mis-step does not occur during changeover from a full step to a half step  
(2) Regarding changeover from a half step to a full step,  
(a) A mis-step does not occur during changeover from a half step (excitation sequence 0, 2, 4, 6) to a full step.  
(b) A mis-step occurs during changeover from a half step (excitation sequence 1, 3, 5, 7) to a full step.  
For the above reason, it is recommended that mode changeover from a half step to a full step be carried out during  
the period when the RESET input is “L” logic.  
Ver.2007-08-20  
- 6 -  
NJU7384  
■TIMING CHART  
• Fixed mode (Full step / Forward direction)  
Condition : DIR=”H”, HSM=”H”  
VMM, VDD  
DIR  
HSM  
excitation sequence No  
0
1
2
3
4
.
STEP  
RESET  
ENABLE  
IA  
IB  
Ver.2007-08-20  
- 7 -  
NJU7384  
• Direction change (Full step / Forward direction ⇒ Reverse direction)  
Condition : DIR=”H” ⇒ ”L”, HSM=”H”  
VMM, VDD  
DIR  
HSM  
excitation sequence No  
0
1
2
1
0
3
2
1
.
STEP  
RESET  
ENABLE  
IA  
IB  
Ver.2007-08-20  
- 8 -  
NJU7384  
• Step mode change (Full step ⇒ Half step)  
Condition : DIR=”H”, HSM=”H” ⇒ ”L”  
VMM, VDD  
DIR  
HALF STEP sequence  
HSM  
excitation sequence No  
5
6
7
0
1
3
4
5
6
7
0
.
0
1
2
0
1
2
STEP  
RESET  
ENABLE  
IA  
IB  
Ver.2007-08-20  
- 9 -  
NJU7384  
■APPLICATION CIRCUIT  
VMM(+6V)  
VDD(+5V)  
+
+
GND(VMM  
)
VDD  
µ-COM  
VMM1  
CMOS,TTL-LS  
Input/Output Device  
STEPPER  
M
OUTA1  
STEP  
DIR  
STEP  
OUTA2  
PGND1  
CW/CCW  
HSM  
FULL/HALF  
VMM2  
OUTB1  
RESET  
RESET  
OUTB2  
PGND2  
ENA BLE  
GND  
NORMAL/INHIBIT  
TSD ALARM  
THERMAL SENSOR  
TSD  
GND(VDD  
)
GND(VMM)  
[CAUTION]  
The specifications on this databook are only  
given for information , without any guarantee  
as regards either mistakes or omissions. The  
application circuits in this databook are  
described only to show representative usages  
of the product and not intended for the  
guarantee or permission of any right including  
the industrial rights.  
Ver.2007-08-20  
- 10 -  

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