首页 > 驱动程序和接口 > MOSFET 驱动器 > LM5109A

LM5109A

更新时间：2025-07-01 08:35:56

品牌：NSC

描述：L5109又名:LM5109，封装上丝印是L5109

PDF下载

中文翻译

免费 PCB/SMT

概述
数据手册

如果您发现信息不准确，欢迎纠错

LM5109A 概述

L5109又名:LM5109，封装上丝印是L5109 L5109又名： LM5109 ，封装上丝印是L5109

LM5109A 数据手册

通过下载LM5109A数据手册来全面了解它。这个PDF文档包含了所有必要的细节，如产品概述、功能特性、引脚定义、引脚排列图等信息。

PDF下载

April 2006

LM5109A

High Voltage 1A Peak Half Bridge Gate Driver

n Bootstrap supply voltage to 108V DC

n Fast propagation times (30 ns typical)

n Drives 1000 pF load with 15ns rise and fall times

n Excellent propagation delay matching (2 ns typical)

n Supply rail under-voltage lockout

General Description

The LM5109A is a cost effective, high voltage gate driver

designed to drive both the high-side and the low-side

N-Channel MOSFETs in a synchronous buck or a half bridge

configuration. The floating high-side driver is capable of

working with rail voltages up to 90V. The outputs are inde-

pendently controlled with TTL compatible input thresholds.

The robust level shift technology operates at high speed

while consuming low power and providing clean level tran-

sitions from the control input logic to the high-side gate

driver. Under-voltage lockout is provided on both the low-

side and the high-side power rails. The device is available in

the SOIC-8 and the thermally enhanced LLP-8 packages.

n Low power consumption

n Pin compatible with ISL6700

Typical Applications

n Current Fed push-pull converters

n Half and Full Bridge power converters

n Solid state motor drives

n Two switch forward power converters

Features

Package

n Drives both a high-side and low-side N-Channel

MOSFET

n SOIC-8

n LLP-8 (4 mm x 4 mm)

n 1A peak output current (1.0A sink / 1.0A source)

Independent TTL compatible inputs

Simplified Block Diagram

20170201

FIGURE 1.

DS201702

www.national.com

Connection Diagrams

20170202

20170203

FIGURE 2.

Ordering Information

Ordering Number

Package Type

NSC Package Drawing

M08A

Supplied As

LM5109AMA

SOIC-8

95 Units in anti static rails

2500 Units on Tape & Reel

1000 Units on Tape & Reel

4500 Units on Tape & Reel

LM5109AMAX

LM5109ASD

SOIC-8

M08A

LLP-8

SDC08A

LM5109ASDX

LLP-8

SDC08A

Pin Descriptions

Pin #

Name

Description

Application Information

SO-8

LLP-8

V_DD

Positive gate drive supply

High side control input

Low side control input

Locally decouple to V_SSusing low ESR/ESL capacitor located

as close to IC as possible.

The HI input is compatible with TTL input thresholds. Unused

HI input should be tied to ground and not left open

The LI input is compatible with TTL input thresholds. Unused

LI input should be tied to ground and not left open.

All signals are referenced to this ground.

V_SS

Ground reference

Low side gate driver output

High side source connection

Connect to the gate of the low-side N-MOS device.

Connect to the negative terminal of the bootstrap capacitor

and to the source of the high-side N-MOS device.

Connect to the gate of the high-side N-MOS device.

High side gate driver output

High side gate driver positive Connect the positive terminal of the bootstrap capacitor to HB

supply rail

and the negative terminal of the bootstrap capacitor to HS.

The bootstrap capacitor should be placed as close to IC as

possible.

Note: For LLP-8 package it is recommended that the exposed pad on the bottom of the package be soldered to ground plane on the PCB and the ground

plane should extend out from underneath the package to improve heat dissipation.

www.national.com

Absolute Maximum Ratings (Note 1)

Storage Temperature Range

ESD Rating HBM (Note 2)

−55˚C to +150˚C

1.5 kV

If Military/Aerospace specified devices are required,

please contact the National Semiconductor Sales Office/

Distributors for availability and specifications.

Recommended Operating

Conditions

V_DDto V_SS

-0.3V to 18V

−0.3V to 18V

HB to HS

V_DD

8V to 14V

LI or HI to V_SS

LO to V_SS

−0.3V to V_DD+0.3V

V_HS−0.3V to V_HB+0.3V

−5V to 90V

HS (Note 6)

−1V to 90V

V_HS+8V to V_HS+14V

HO to V_SS

HS Slew Rate

Junction Temperature

50 V/ns

HS to V_SS(Note 6)

HB to V_SS

−40˚C to +125˚C

108V

Junction Temperature

-40˚C to +150˚C

Electrical Characteristics

Specifications in standard typeface are for T_J= +25˚C, and those in boldface type apply over the full operating junction tem-

perature range. Unless otherwise specified, V_DD= V_HB= 12V, V_SS= V_HS= 0V, No Load on LO or HO (Note 4).

Symbol

Parameter

Conditions

Min

Typ

Max

Units

SUPPLY CURRENTS

I_DD

V_DDQuiescent Current

LI = HI = 0V

f = 500 kHz

LI = HI = 0V

f = 500 kHz

0.3

1.8

0.6

2.9

0.2

2.8

µA

I_DDO

I_HB

V_DDOperating Current

Total HB Quiescent Current

Total HB Operating Current

HB to V_SSCurrent, Quiescent

HB to V_SSCurrent, Operating

0.06

1.4

I_HBO

I_HBS

I_HBSO

V_HS= V_HB= 90V

f = 500 kHz

0.1

0.5

INPUT PINS LI and HI

V_IL

V_IH

R_I

Low Level Input Voltage Threshold

0.8

100

6.0

5.7

1.8

200

High Level Input Voltage Threshold

Input Pulldown Resistance

2.2

500

kΩ

UNDER VOLTAGE PROTECTION

V_DDR

V_DDH

V_HBR

V_HBH

V_DDRising Threshold

V_DDThreshold Hysteresis

HB Rising Threshold

V_DDR= V_DD- V_SS

V_HBR= V_HB- V_HS

6.7

0.5

6.6

0.4

7.4

7.1

HB Threshold Hysteresis

LO GATE DRIVER

V_OLLLow-Level Output Voltage

I_LO= 100 mA

V_OHL= V_LO– V_SS

I_LO= −100 mA,

V_OHL= V_DD– V_LO

V_LO= 0V

0.38

0.72

0.65

1.20

V_OHL

High-Level Output Voltage

I_OHL

I_OLL

Peak Pullup Current

1.0

Peak Pulldown Current

V_LO= 12V

HO GATE DRIVER

V_OLHLow-Level Output Voltage

I_HO= 100 mA

V_OLH= V_HO– V_HS

I_HO= −100 mA

V_OHH= V_HB– V_HO

V_HO= 0V

0.38

0.72

0.65

1.20

V_OHH

High-Level Output Voltage

I_OHH

I_OLH

Peak Pullup Current

1.0

Peak Pulldown Current

V_HO= 12V

THERMAL RESISTANCE

θ_JAJunction to Ambient

SOIC-8 (Note 3), (Note 5)

LLP-8 (Note 3), (Note 5)

160

˚C/W

www.national.com

Switching Characteristics

Specifications in standard typeface are for T_J= +25˚C, and those in boldface type apply over the full operating junction tem-

perature range. Unless otherwise specified, V_DD= V_HB= 12V, V_SS= V_HS= 0V, No Load on LO or HO.

Symbol

LM5109A

t_LPHL

Parameter

Conditions

Min

Typ

Max

Units

Lower Turn-Off Propagation Delay (LI

Falling to LO Falling)

t_HPHL

t_LPLH

t_HPLH

t_MON

t_MOFF

Upper Turn-Off Propagation Delay (HI

Falling to HO Falling)

Lower Turn-On Propagation Delay (LI

Rising to LO Rising)

Upper Turn-On Propagation Delay (HI

Rising to HO Rising)

Delay Matching: Lower Turn-On and

Upper Turn-Off

Delay Matching: Lower Turn-Off and

Upper Turn-On

t_RC, t_FC

t_PW

Either Output Rise/Fall Time

Minimum Input Pulse Width that

Changes the Output

C_L= 1000 pF

Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the component may occur. Operating Ratings are conditions under which operation of

the device is guaranteed. Operating Ratings do not imply guaranteed performance limits. For guaranteed performance limits and associated test conditions, see the

Electrical Characteristics tables.

Note 2: The human body model is a 100 pF capacitor discharged through a 1.5kΩ resistor into each pin.

Note 3: 4 layer board with Cu finished thickness 1.5/1/1/1.5 oz. Maximum die size used. 5x body length of Cu trace on PCB top. 50 x 50mm ground and power

planes embedded in PCB. See Application Note AN-1187.

Note 4: Min and Max limits are 100% production tested at 25˚C. Limits over the operating temperature range are guaranteed through correlation using Statistical

Quality Control (SQC) methods. Limits are used to calculate National’s Average Outgoing Quality Level (AOQL).

Note 5: The θ is not a constant for the package and depends on the printed circuit board design and the operating conditions.

Note 6: In the application the HS node is clamped by the body diode of the external lower N-MOSFET, therefore the HS voltage will generally not exceed -1V.

However in some applications, board resistance and inductance may result in the HS node exceeding this stated voltage transiently.

If negative transients occur on HS, the HS voltage must never be more negative than V - 15V. For example, if V = 10V, the negative transients at HS must not

exceed -5V.

www.national.com

Typical Performance Characteristics

V_DDOperating Current vs Frequency

HB Operating Current vs Frequency

20170204

20170205

Operating Current vs Temperature

Quiescent Current vs Temperature

20170206

20170207

Quiescent Current vs Voltage

Propagation Delay vs Temperature

20170209

20170208

www.national.com

Typical Performance Characteristics (Continued)

LO and HO High Level Output Voltage vs Temperature

LO and HO Low Level Output Voltage vs Temperature

20170210

20170211

Undervoltage Rising Thresholds vs Temperature

Undervoltage Hysteresis vs Temperature

20170214

20170215

Input Thresholds vs Temperature

Input Thresholds vs Supply Voltage

20170217

20170216

www.national.com

Timing Diagram

20170218

FIGURE 3.

and involves high peak current. Minimizing this loop

length and area on the circuit board is important to

ensure reliable operation.

Layout Considerations

Optimum performance of high and low-side gate drivers

cannot be achieved without taking due considerations during

circuit board layout. The following points are emphasized:

HS Transient Voltages Below

Ground

The HS node will always be clamped by the body diode of

the lower external FET. In some situations, board resis-

tances and inductances can cause the HS node to tran-

siently swing several volts below ground. The HS node can

swing below ground provided:

1. Low ESR / ESL capacitors must be connected close to

the IC between VDD and VSS pins and between HB and

HS pins to support high peak currents being drawn from

VDD and HB during the turn-on of the external MOS-

FETs.

2. To prevent large voltage transients at the drain of the top

MOSFET, a low ESR electrolytic capacitor and a good

quality ceramic capacitor must be connected between

the MOSFET drain and ground (VSS).

1. HS must always be at a lower potential than HO. Pulling

HO more than -0.3V below HS can activate parasitic

transistors resulting in excessive current flow from the

HB supply, possibly resulting in damage to the IC. The

same relationship is true with LO and VSS. If necessary,

a Schottky diode can be placed externally between HO

and HS or LO and GND to protect the IC from this type

of transient. The diode must be placed as close to the IC

pins as possible in order to be effective.

3. In order to avoid large negative transients on the switch

node (HS) pin, the parasitic inductances between the

source of the top MOSFET and the drain of the bottom

MOSFET (synchronous rectifier) must be minimized.

4. Grounding considerations:

a) The first priority in designing grounding connections is

to confine the high peak currents that charge and dis-

charge the MOSFET gates to a minimal physical area.

This will decrease the loop inductance and minimize

noise issues on the gate terminals of the MOSFETs. The

gate driver should be placed as close as possible to the

MOSFETs.

2. HB to HS operating voltage should be 15V or less.

Hence, if the HS pin transient voltage is -5V, VDD should

be ideally limited to 10V to keep HB to HS below 15V.

3. Low ESR bypass capacitors from HB to HS and from

VDD to VSS are essential for proper operation. The

capacitor should be located at the leads of the IC to

minimize series inductance. The peak currents from LO

and HO can be quite large. Any series inductances with

the bypass capacitor will cause voltage ringing at the

leads of the IC which must be avoided for reliable

operation.

b) The second consideration is the high current path that

includes the bootstrap capacitor, the bootstrap diode,

the local ground referenced bypass capacitor, and the

low-side MOSFET body diode. The bootstrap capacitor

is recharged on a cycle-by-cycle basis through the boot-

strap diode from the ground referenced VDD bypass

capacitor. The recharging occurs in a short time interval

www.national.com

Physical Dimensions inches (millimeters) unless otherwise noted

Controlling dimension is inch. Values in [ ] are millimeters.

Notes: Unless otherwise specified.

1. Standard lead finish to be 200 microinches/5.08 micrometers minimum lead/tin (solder) on copper.

2. Dimension does not include mold flash.

3. Reference JEDEC registration MS-012, Variation AA, dated May 1990.

SOIC-8 Outline Drawing

NS Package Number M08A

www.national.com

Physical Dimensions inches (millimeters) unless otherwise noted (Continued)

Notes: Unless otherwise specified.

1. For solder thickness and composition, see “Solder Information” in the packaging section of the National Semiconductor web

page (www.national.com).

2. Maximum allowable metal burr on lead tips at the package edges is 76 microns.

3. No JEDEC registration as of May 2003.

LLP-8 Outline Drawing

NS Package Number SDC08A

National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves

the right at any time without notice to change said circuitry and specifications.

For the most current product information visit us at www.national.com.

LIFE SUPPORT POLICY

NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS

WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT AND GENERAL COUNSEL OF NATIONAL SEMICONDUCTOR

CORPORATION. As used herein:

1. Life support devices or systems are devices or systems

which, (a) are intended for surgical implant into the body, or

(b) support or sustain life, and whose failure to perform when

properly used in accordance with instructions for use

provided in the labeling, can be reasonably expected to result

in a significant injury to the user.

2. A critical component is any component of a life support

device or system whose failure to perform can be reasonably

expected to cause the failure of the life support device or

system, or to affect its safety or effectiveness.

BANNED SUBSTANCE COMPLIANCE

National Semiconductor manufactures products and uses packing materials that meet the provisions of the Customer Products

Stewardship Specification (CSP-9-111C2) and the Banned Substances and Materials of Interest Specification (CSP-9-111S2) and contain

no ‘‘Banned Substances’’ as defined in CSP-9-111S2.

Leadfree products are RoHS compliant.

National Semiconductor

Americas Customer

Support Center

National Semiconductor

Europe Customer Support Center

Fax: +49 (0) 180-530 85 86

National Semiconductor

Asia Pacific Customer

Support Center

National Semiconductor

Japan Customer Support Center

Fax: 81-3-5639-7507

Email: new.feedback@nsc.com

Tel: 1-800-272-9959

Email: europe.support@nsc.com

Deutsch Tel: +49 (0) 69 9508 6208

English Tel: +44 (0) 870 24 0 2171

Français Tel: +33 (0) 1 41 91 8790

Email: ap.support@nsc.com

Email: jpn.feedback@nsc.com

Tel: 81-3-5639-7560

www.national.com

LM5109A 相关器件

型号	制造商	描述	价格	文档
LM5109AMA	NSC	High Voltage 1A Peak Half Bridge Gate Driver	获取价格
LM5109AMA	TI	LM5109A High Voltage 1A Peak Half Bridge Gate Driver	获取价格
LM5109AMA/NOPB	TI	High Voltage 1A Peak Half Bridge Gate Driver	获取价格
LM5109AMA/NOPB	NSC	IC 1 A HALF BRDG BASED MOSFET DRIVER, PDSO8, LEAD FREE, MS-012AA, SOIC-8, MOSFET Driver	获取价格
LM5109AMAX	NSC	High Voltage 1A Peak Half Bridge Gate Driver	获取价格
LM5109AMAX	TI	LM5109A High Voltage 1A Peak Half Bridge Gate Driver	获取价格
LM5109AMAX/NOPB	TI	1-A, 100-V half bridge gate driver with 8-V UVLO 8-SOIC -40 to 125	获取价格
LM5109ASD	NSC	High Voltage 1A Peak Half Bridge Gate Driver	获取价格
LM5109ASD	TI	LM5109A High Voltage 1A Peak Half Bridge Gate Driver	获取价格
LM5109ASD/NOPB	TI	1-A, 100-V half bridge gate driver with 8-V UVLO 8-WSON -40 to 125	获取价格