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1338

更新时间：2025-03-22 08:28:47

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描述：Real-Time Clock With Battery Backed Non-Volatile RAM

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1338 概述

Real-Time Clock With Battery Backed Non-Volatile RAM

1338 数据手册

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Real-Time Clock with Battery

Backed Non-Volatile RAM

1338

Datasheet

Description

Features

The 1338 is a serial real-time clock (RTC) device that

consumes ultra-low power and provides a full binary-coded

decimal (BCD) clock/calendar with 56 bytes of battery

backed Non-Volatile Static RAM. The clock/calendar

provides seconds, minutes, hours, day, date, month, and

year information. The clock operates in either the 24-hour

or 12-hour format with AM/PM indicator. The end of the

month date is automatically adjusted for months with fewer

than 31 days, including corrections for leap year. Access to

the clock/calendar registers is provided by an I²C interface

capable of operating in fast I²C mode. Built-in Power-sense

circuitry detects power failures and automatically switches

to the backup supply, maintaining time and date operation.

• Real-Time Clock (RTC) counts seconds, minutes, hours,

day, date, month, and year with leap-year compensation

valid up to 2100

• 56-byte battery-backed Non-Volatile RAM for data

storage

• Fast mode I²C serial interface

• Automatic power-fail detect and switch circuitry

• Programmable square-wave output

• Packaged in 8-pin MSOP, 8-pin SOIC, or 16-pin SOIC

(surface-mount package with an integrated crystal)

• Industrial temperature range (-40°C to +85°C)

Typical Applications

• Telecom (Routers, Switches, Servers)

• Handheld (GPS, Point of Sale POS Terminals)

• Consumer Electronics (Set-Top Box, Digital Recording,

Network Applications, Digital Photo Frames)

• Office (Fax/Printers, Copiers)

• Medical (Glucometer, Medicine Dispensers)

• Other (Thermostats, Vending Machines, Modems, Utility

Meters)

Block Diagram

Crystal inside package

for 16-pin SOIC ONLY

1Hz / 4.096kHz /

8.192kHz / 32.768kHz

32.768kHz

Oscillator and

Divider

MUX/

Buffer

SQW/OUT

VCC

GND

V_BAT

Power

Control

Logic

Clock, Calendar

Counter

SCL

SDA

I²C

Interface

56 Byte

RAM

1 Byte 7 Bytes

Control

Buffer

February 3, 2023

1338 Datasheet

Pin Assignment (8-pin MSOP/8-pin SOIC)

Pin Assignment (16-pin SOIC)

SCL

SDA

VCC

SQW/OUT

GND

V_BAT

SQW/OUT

SCL

IDT

1338

VCC

V_BAT

GND

IDT

1338C

SDA

Pin Descriptions

Number

Name

Pin Description/Function

8MSOP, 16SOIC

8SOIC

—

Connections for standard 32.768kHz quartz crystal. The internal oscillator circuitry is designed

for operation with a crystal having a specified load capacitance (CL) of 12.5pF. An external

32.768kHz oscillator can also drive the IDT1338. In this configuration, the X1 pin is connected to

the external oscillator signal and the X2 pin is left floating.

V_BAT

Backup Supply Input for Lithium Coin Cell or Other Energy Source. Battery voltage must be held

between the minimum and maximum limits for proper operation. Diodes placed in series

between the backup source and the V_BATpin may prevent proper operation. If a backup supply

is not required, V_BATmust be connected to ground.

GND

SDA

Connect to ground.

Serial data input/output. SDA is the input/output pin for the I²C serial interface. It is an open-drain

output and requires an external pull-up resistor (2kOhm typical).

SCL

Serial clock input. SCL is used to synchronize data movement on the serial interface. It is an

open-drain output and requires an external pull-up resistor (2kOhm typical)

SQW/OUT Square-Wave/Output driver. When enabled and the SQWE bit set to 1, the SQW/OUT pin

outputs one of four square-wave frequencies (1Hz, 4kHz, 8kHz, 32kHz). It is an open drain

output and requires an external pull-up resistor (10K ohm typical). Operates when the device is

powered with VCC or V_BAT

V_CC

Device power supply. When voltage is applied within specified limits, the device is fully

accessible by I²C and data can be written and read.

—

4 – 13

No connect. These pins are unused and must be connected to ground for proper operation.

February 3, 2023

1338 Datasheet

Typical Operating Circuit

CRYSTAL

V_CC

10k

SCL

SQW/OUT

CPU

IDT1338

V_BAT

SDA

GND

Detailed Description

The following sections discuss in detail the Oscillator

block, Power Control block, Clock/Calendar Register

Block and Serial I²C block.

Oscillator Block

Selection of the right crystal, correct load capacitance

and careful PCB layout are important for a stable crystal

oscillator. Due to the optimization for the lowest possible

current in the design for these oscillators, losses caused

by parasitic currents can have a significant impact on the

overall oscillator performance. Extra care needs to be

taken to maintain a certain quality and cleanliness of the

PCB.

Crystal Selection

The key parameters when selecting a 32 kHz crystal to

work with 1338 RTC are:

In the above figure, X1 and X2 are the crystal pins of our

device. Cin1 and Cin2 are the internal capacitors which

include the X1 and X2 pin capacitance. Cex1 and Cex2

are the external capacitors that are needed to tune the

crystal frequency. Ct1 and Ct2 are the PCB trace

capacitances between the crystal and the device pins.

CS is the shunt capacitance of the crystal (as specified in

the crystal manufacturer's datasheet or measured using a

network analyzer). Cex1 and Cex2 are not needed if the

crystal circuit uses the recommended crystal with

specified load capacitance (CL) of 12.5pF.

• Recommended Load Capacitance

• Crystal Effective Series Resistance (ESR)

• Frequency Tolerance

Effective Load Capacitance

Please see diagram below for effective load capacitance

calculation. The effective load capacitance (CL) should

match the recommended load capacitance of the crystal

in order for the crystal to oscillate at its specified parallel

resonant frequency with 0ppm frequency error.

Note: 1338CSRI integrates a standard 32.768 kHz

crystal in the package and contributes an additional

frequency error of 10ppm at nominal V_CC(+3.3 V) and

T_A=+25°C.

February 3, 2023

1338 Datasheet

ESR (Effective Series Resistance)

PCB Layout

Choose the crystal with lower ESR. A low ESR helps the

crystal to start up and stabilize to the correct output

frequency faster compared to high ESR crystals.

Frequency Tolerance

The frequency tolerance for 32kHz crystals should be

specified at nominal temperature (+25°C) on the crystal

manufacturer datasheet. The crystals used with 1338

typically have a frequency tolerance of ±20ppm at +25°C.

Specifications for a typical 32kHz crystal used with our

device are shown in the table below.

PCB Assembly, Soldering and Cleaning

Parameter

Nominal Freq.

Symbol Min

Typ

Max Units

Board-assembly production process and assembly

quality can affect the performance of the 32kHz oscillator.

Depending on the flux material used, the soldering

process can leave critical residues on the PCB surface.

High humidity and fast temperature cycles that cause

humidity condensation on the printed circuit board can

create process residuals. These process residuals cause

the insulation of the sensitive oscillator signal lines

towards each other and neighboring signals on the PCB

to decrease. High humidity can lead to moisture

condensation on the surface of the PCB and, together

with process residuals, reduce the surface resistivity of

the board. Flux residuals on the board can cause leakage

current paths, especially in humid environments.

Thorough PCB cleaning is therefore highly recommended

in order to achieve maximum performance by removing

flux residuals from the board after assembly. In general,

reduction of losses in the oscillator circuit leads to better

safety margin and reliability.

f_O

ESR

C_L

32.768

kHz

Series Resistance

Load Capacitance

110

k

12.5

PCB Design Consideration

• Signal traces between the device pins and the crystal

must be kept as short as possible. This minimizes

parasitic capacitance and sensitivity to crosstalk and

EMI. Note that the trace capacitances play a role in the

effective crystal load capacitance calculation.

• Data lines and frequently switching signal lines should be

routed as far away from the crystal connections as

possible. Crosstalk from these signals may disturb the

oscillator signal.

• Reduce the parasitic capacitance between X1 and X2

signals by routing them as far apart as possible.

• The oscillation loop current flows between the crystal and

the load capacitors. This signal path (crystal to CL1 to

CL2 to crystal) should be kept as short as possible and

ideally be symmetric. The ground connections for both

capacitors should be as close together as possible.

Never route the ground connection between the

capacitors all around the crystal, because this long

ground trace is sensitive to crosstalk and EMI.

• To reduce the radiation / coupling from oscillator circuit,

an isolated ground island on the GND layer could be

made. This ground island can be connected at one point

to the GND layer. This helps to keep noise generated by

the oscillator circuit locally on this separated island. The

ground connections for the load capacitors and the

oscillator should be connected to this island.

February 3, 2023

1338 Datasheet

Table 1. Power Control

Supply Condition

Power Control

A precise, temperature-compensated voltage reference

and a comparator circuit provides power-control function

that monitors the V_CClevel. The device is fully accessible

and data can be written and read when V_CCis greater

than V_PF. However, when V_CCfalls below V_PF, the internal

clock registers are blocked from any access. If V_PFis

less than V_BAT, the device power is switched from V_CCto

V_BATwhen V_CCdrops below V_PF. If V_PFis greater than

V_BAT, the device power is switched from V_CCto V_BAT

when V_CCdrops below V_BAT. The registers are

Read/Write Powered

Access

V_BAT

V_CC

V_CC< V_PF, V_CC< V_BAT

V_CC< V_PF, V_CC> V_BAT

V_CC> V_PF, V_CC< V_BAT

V_CC> V_PF, V_CC> V_BAT

Yes

maintained from the V_BATsource until V_CCis returned to

nominal levels (Table 1). After V_CCreturns above V_PF

read and write access is allowed after t_REC(see the

“Power-Up/Down Timing” diagram).

Power-up/down Timing

Table 2. Power-up/down Characteristics

Ambient Temperature -40 to +85C

Parameter

Symbol

t_REC

Conditions

Min.

Typ.

Max.

Unit

µs

Recovery at Power-up

(Note 1)

V_CCFall Time; V_PF(MAX)to V_PF(MIN)

t_VCCF

1338-18 (Note 2)

1338-31 (Note 2)

V_CCRise Time; V_PF(MIN)to V_PF(MAX)

t_VCCR

Note 1: This delay applies only if the oscillator is running. If the oscillator is disabled or stopped, no power-up delay

occurs.

Note 2: Measured at typical VBAT level.

February 3, 2023

1338 Datasheet

RTC and RAM Address Map

The address map for the RTC and RAM registers shown in Table 3. The RTC registers and control register are located

in address locations 00H to 07H The RAM registers are located in address locations 08H to 3FH. During a multibyte

access, when the register pointer reaches 3FH (the end of RAM space) it wraps around to location 00H (the beginning

of the clock space). On an I²C START, STOP, or register pointer incrementing to location 00H, the current time and date

is transferred to a second set of registers. The time and date in the secondary registers are read in a multibyte data

transfer, while the clock continues to run. This eliminates the need to re-read the registers in case of an update of the

main registers during a read.

Table 3. RTC and RAM Address Map

Address

00H

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Function

Seconds

Minutes

Range

00 - 59

10 seconds

10 minutes

AM/PM

Seconds

01H

Minutes

Hour

1 - 12

+ AM/PM

00 - 23

02H

12/24

10 hour

Hours

10 hour

03H

04H

05H

06H

07H

Day

Date

1 - 7

10 date

Date

Month

Year

01 - 31

01 - 12

00 - 99

10 month

Month

10 year

Year

OUT

OSF

SQWE

RS1

RS0

Control

RAM 56 x 8

08H -

3FH

00H - FFH

Note: Bits listed as “0” should always be written and read as 0.

Clock and Calendar

Table 3 shows the address map of the RTC registers. The

time and date information is obtained by reading the

appropriate register bytes. The time and calendar are set

or initialized by writing the appropriate register bytes. The

contents of the time and calendar registers are in the

BCD format. Bit 7 of Register 0 is the clock halt (CH) bit.

When this bit is set to 1, the oscillator is disabled. When

cleared to 0, the oscillator is enabled. The clock can be

halted whenever the timekeeping functions are not

required, which decreases V_BATcurrent.

The countdown chain is reset whenever the seconds

acknowledge pulse from the device. To avoid rollover

issues, once the countdown chain is reset, the remaining

time and date registers must be written within one

second. If enabled, the 1Hz square-wave output

transitions high 500ms after the seconds data transfer,

provided the oscillator is already running.

Note that the initial power-on state of all registers,

unless otherwise specified, is not defined. Therefore,

it is important to enable the oscillator (CH = 0) during

initial configuration.

The day-of-week register increments at midnight. Values

that correspond to the day of week are user-defined but

must be sequential (i.e., if 1 equals Sunday, then 2

equals Monday, and so on). Illogical time and date entries

result in undefined operation.

The IDT1338 runs in either 12-hour or 24-hour mode. Bit

6 of the hours register is defined as the 12-hour or

24-hour mode-select bit. When high, the 12-hour mode is

selected. In the 12-hour mode, bit 5 is the AM/PM bit,

with logic high being PM. In the 24-hour mode, bit 5 is the

second 10-hour bit (20–23 hours). If the 12/24-hour mode

select is changed, the hours register must be

When reading or writing the time and date registers,

secondary (user) buffers are used to prevent errors when

the internal registers update. When reading the time and

date registers, the user buffers are synchronized to the

internal registers on any start or stop, and when the

address pointer rolls over to zero.

re-initialized to the new format.

February 3, 2023

1338 Datasheet

On an I²C START, the current time is transferred to a

second set of registers. The time information is read from

these secondary registers, while the clock continues to

run. This eliminates the need to re-read the registers in

case of an update of the main registers during a read.

Table 4. Control Register (07H)

The control register controls the operation of the SQW/OUT pin and provides oscillator status.

Bit #

Name

POR

Bit 7

OUT

Bit 6

Bit 5

OSF

Bit 4

SQWE

Bit 3

Bit 2

Bit 1

RS1

Bit 0

RS0

Bit 7: Output Control (OUT). Controls the output level of the SQW/OUT pin when the square-wave output is disabled. If SQWE

= 0, the logic level on the SQW/OUT pin is 1 if OUT = 1; it is 0 if OUT = 0.

Bit 5: Oscillator Stop Flag (OSF). A logic 1 in this bit indicates that the oscillator has stopped or was stopped for some time

period and can be used to judge the validity of the clock and calendar data. This bit is edge triggered, and is set to logic 1 when

the internal circuitry senses the oscillator has transitioned from a normal run state to a STOP condition. The following are

examples of conditions that may cause the OSF bit to be set:

1) The first time power is applied.

2) The voltage present on VCC and VBAT are insufficient to support oscillation.

3) The CH bit is set to 1, disabling the oscillator.

4) External influences on the crystal (i.e., noise, leakage, etc.).

This bit remains at logic 1 until written to logic 0. This bit can only be written to logic 0. Attempting to write OSF to logic 1 leaves

the value unchanged.

Bit 4: Square-Wave Enable (SQWE). When set to logic 1, this bit enables the oscillator output to operate with either VCC or

_BATapplied. The frequency of the square-wave output depends upon the value of the RS0 and RS1 bits.

Bits 1 and 0: Rate Select (RS1 and RS0). These bits control the frequency of the square-wave output when the square-wave

output has been enabled. The table below lists the square-wave frequencies that can be selected with the RS bits.

Table 5. Square Wave Output

OUT

RS1

RS0

SQW Output

SQWE

1Hz

4.096kHz

8.192kHz

32.768kHz

February 3, 2023

1338 Datasheet

I²C Serial Data Bus

Acknowledge: Each receiving device, when addressed,

is obliged to generate an acknowledge after the reception

of each byte. The master device must generate an extra

clock pulse that is associated with this acknowledge bit.

The 1338 supports the I²C bus protocol. A device that

sends data onto the bus is defined as a transmitter and a

device receiving data as a receiver. The device that

controls the message is called a master. The devices that

are controlled by the master are referred to as slaves.

The bus must be controlled by a master device that

generates the serial clock (SCL), controls the bus

access, and generates the START and STOP conditions.

The 1338 operates as a slave on the I²C bus. Within the

bus specifications, a standard mode (100kHz maximum

clock rate) and a fast mode (400kHz maximum clock

rate) are defined. The 1338 works in both modes.

Connections to the bus are made via the open-drain I/O

lines SDA and SCL.

A device that acknowledges must pull down the SDA line

during the acknowledge clock pulse in such a way that

the SDA line is stable LOW during the HIGH period of the

acknowledge related clock pulse. Of course, setup and

hold times must be taken into account. A master must

signal an end of data to the slave by not generating an

acknowledge bit on the last byte that has been clocked

out of the slave. In this case, the slave must leave the

data line HIGH to enable the master to generate the

STOP condition.

Timeout: Timeout is where a slave device resets its

interface whenever Clock goes low for longer than the

timeout, which is typically 35msec. This added logic

deals with slave errors and recovering from those errors.

When timeout occurs, the slave interface should

re-initialize itself and be ready to receive a

The following bus protocol has been defined (see the

“Data Transfer on I²C Serial Bus” figure):

• Data transfer may be initiated only when the bus is not

busy.

• During data transfer, the data line must remain stable

whenever the clock line is HIGH. Changes in the data line

while the clock line is HIGH are interpreted as control

signals.

communication from the master, but it will expect a Start

prior to any new communication.

Accordingly, the following bus conditions have been

defined:

Bus not busy: Both data and clock lines remain HIGH.

Start data transfer: A change in the state of the data

line, from HIGH to LOW, while the clock is HIGH, defines

a START condition.

Stop data transfer: A change in the state of the data

line, from LOW to HIGH, while the clock line is HIGH,

defines the STOP condition.

Data valid: The state of the data line represents valid

data when, after a START condition, the data line is

stable for the duration of the HIGH period of the clock

signal. The data on the line must be changed during the

LOW period of the clock signal. There is one clock pulse

per bit of data.

Each data transfer is initiated with a START condition and

terminated with a STOP condition. The number of data

bytes transferred between START and STOP conditions

is not limited, and is determined by the master device.

The information is transferred byte-wise and each

receiver acknowledges with a ninth bit.

February 3, 2023

1338 Datasheet

Data Transfer on I²C Serial Bus

Depending upon the state of the R/W bit, two types of

data transfer are possible:

1338 address, which is 1101000, followed by the

direction bit (R/W), which is 0 for a write. After receiving

and decoding the slave address byte the slave outputs an

acknowledge on the SDA line. After the 1338

acknowledges the slave address + write bit, the master

transmits a register address to the 1338. This sets the

acknowledging the transfer. The master may then

transmit zero or more bytes of data, with the 1338

acknowledging each byte received. The address pointer

increments after each data byte is transferred. The

master generates a STOP condition to terminate the data

write.

1) Data transfer from a master transmitter to a slave

receiver. The first byte transmitted by the master is the

slave address. Next follows a number of data bytes. The

slave returns an acknowledge bit after each received

byte. Data is transferred with the most significant bit

(MSB) first.

2) Data transfer from a slave transmitter to a master

receiver. The first byte (the slave address) is transmitted

by the master. The slave then returns an acknowledge

bit. This is followed by the slave transmitting a number of

data bytes. The master returns an acknowledge bit after

all received bytes other than the last byte. At the end of

the last received byte, a “not acknowledge” is returned.

The master device generates all of the serial clock pulses

and the START and STOP conditions. A transfer is ended

with a STOP condition or with a repeated START

condition. Since a repeated START condition is also the

beginning of the next serial transfer, the bus is not

released. Data is transferred with the most significant bit

(MSB) first.

2) Slave Transmitter Mode (Read Mode): The first byte

is received and handled as in the slave receiver mode.

However, in this mode, the direction bit indicates that the

transfer direction is reversed. Serial data is transmitted

on SDA by the 1338 while the serial clock is input on

SCL. START and STOP conditions are recognized as the

beginning and end of a serial transfer (see the “Data

Read–Slave Transmitter Mode” figure). The slave

address byte is the first byte received after the START

condition is generated by the master. The slave address

byte contains the 7-bit 1338 address, which is 1101000,

followed by the direction bit (R/W), which is 1 for a read.

After receiving and decoding the slave address byte the

slave outputs an acknowledge on the SDA line. The 1338

then begins to transmit data starting with the register

address pointed to by the register pointer. If the register

pointer is not written to before the initiation of a read

mode the first address that is read is the last one stored

in the register pointer. The address pointer is

The 1338 can operate in the following two modes:

1) Slave Receiver Mode (Write Mode): Serial data and

clock are received through SDA and SCL. After each byte

is received an acknowledge bit is transmitted. START

and STOP conditions are recognized as the beginning

and end of a serial transfer. Address recognition is

performed by hardware after reception of the slave

address and direction bit (see the “Data Write–Slave

Receiver Mode” figure). The slave address byte is the

first byte received after the START condition is generated

by the master. The slave address byte contains the 7-bit

incremented after each byte is transferred. The 1338

must receive a “not acknowledge” to end a read.

February 3, 2023

1338 Datasheet

Data Write – Slave Receiver Mode

Data Read (from current Pointer location) – Slave Transmitter Mode

Data Read (Write Pointer, then Read) – Slave Receive and Transmit

February 3, 2023

1338 Datasheet

Handling, PCB Layout, and Assembly

The IDT1338 package contains a quartz tuning-fork crystal. Pick-and-place equipment may be used, but precautions

should be taken to ensure that excessive shocks are avoided. Ultrasonic cleaning equipment should be avoided to

prevent damage to the crystal.

Avoid running signal traces under the package, unless a ground plane is placed between the package and the signal

line. All NC (no connect) pins must be connected to ground.

Moisture-sensitive packages are shipped from the factory dry-packed. Handling instructions listed on the package label

must be followed to prevent damage during re-flow. Refer to the IPC/JEDEC J-STD-020 standard for moisture-sensitive

device (MSD) classifications.

Absolute Maximum Ratings

Stresses above the ratings listed below can cause permanent damage to the 1338. These ratings, which are standard

values for Renesas commercially rated parts, are stress ratings only. Functional operation of the device at these or any

other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods can affect product reliability. Electrical parameters are

guaranteed only over the recommended operating temperature range.

Item

Voltage Range on Any Pin Relative to Ground

Storage Temperature

Rating

-0.3V to +6.0V

-55 to +125C

260C

Soldering Temperature

Recommended DC Operating Conditions

(V_CC= V_CC(MIN)to V_CC(MAX), TA = -40°C to +85°C, unless otherwise noted. Typical values are at V_CC= 3.3V,

TA = +25°C, unless otherwise noted.) (Note 1)

Parameter

Symbol

T_A

Min.

-40

Typ.

Max.

+85

Unit

Ambient Operating Temperature

V_BATInput Voltage, Note 2

Pull-up Resistor Voltage (SQW/OUT), Note 2

Logic 1, Note 2

C

V_BAT

V_PU

1.3

3.0

3.7

5.5

V_IH

0.8V_CC

-0.3

V_CC+ 0.3

+0.2V_CC

Logic 0, Note 2

V_IL

Supply Voltage

1338-18

V_PF

1.8

3.3

5.5

V_CC

1338-31

Power Fail Voltage

1338-18

1.40

2.45

1.62

2.7

1.71

2.97

V_PF

1338-31

February 3, 2023

1338 Datasheet

DC Electrical Characteristics

(V_CC= V_CC(MIN)to V_CC(MAX), TA = -40°C to +85°C, unless otherwise noted. Typical values are at V_CC= 3.3V,

TA = +25°C, unless otherwise noted.) (Note 1)

Parameter

Symbol

I_LI

Conditions

Min.

Typ. Max. Unit

Input Leakage

Note 3

Note 4

µA

I/O Leakage

I_LO

V_CC> 2V; V_OL= 0.4V

V_CC< 2V; V_OL= 0.2V_CC

V_CC> 2V; V_OL= 0.4V

1.71V < V_CC< 2V;

3.0

SDA Logic 0 Output

I_OLSDA

SQW/OUT Logic 0 Output

I_OLSQWV_OL= 0.2V_CC

1.3V < V_CC< 1.71V;

V_OL= 0.2V_CC

250

µA

1338-18

7.5

Active Supply Current (Note 5)

I_CCA

1338-31; V_CC< 3.63V

1338-31; 3.63V < V_CC< 5.5V

1338-18

Standby Current (Note 6)

I_CCS

1338-31; V_CC< 3.63 V

1338-31; 3.63V < V_CC< 5.5V

µA

V_BATLeakage Current (V_CCActive)

I_BATLKG

100

DC Electrical Characteristics

(V_CC= 0V, TA = -40°C to +85°C, unless otherwise noted. Typical values are at V_BAT= 3.0V, TA = +25°C, unless

otherwise noted.) (Note 1)

Parameter

Symbol

Conditions

Min.

Typ.

Max.

Unit

V_BATCurrent (OSC ON); V_BAT= 3.7V, I_BATOSC1Note 7

SQW/OUT OFF

800

1200

V_BATCurrent (OSC ON); V_BAT= 3.7V, I_BATOSC2Note 7

SQW/OUT ON

1025

120

1400

300

V_BATData-Retention Current

(OSC OFF); V_BAT= 3.7V

I_BATDATNote 7

February 3, 2023

1338 Datasheet

AC Electrical Characteristics

(V_CC= V_CC(MIN)to V_CC(MAX), TA = -40°C to +85°C) (Note 1)

Parameter

Symbol

Conditions

Fast Mode

Min.

Typ. Max. Unit

SCL Clock Frequency

f_SCL

100

400

100

kHz

Standard Mode

Fast Mode

Bus Free Time Between a STOP and

START Condition

t_BUF

1.3

µs

Standard Mode

4.7

Hold Time (Repeated) START

Condition, Note 8

t_HD:STAFast Mode

Standard Mode

Fast Mode

0.6

4.0

Low Period of SCL Clock

t_LOW

1.3

Standard Mode

Fast Mode

4.7

High Period of SCL Clock

t_HIGH

0.6

Standard Mode

4.0

Setup Time for a Repeated START

Condition

t_SU:STAFast Mode

Standard Mode

t_HD:DATFast Mode

Standard Mode

t_SU:DATFast Mode

Standard Mode

Fast Mode

0.6

4.7

Data Hold Time (Notes 9, 10)

0.9

Data Setup Time (Note 11)

100

250

Rise Time of Both SDA and SCL

Signals (Note 12)

t_R

20 + 0.1C_B

0.6

300

1000

300

Standard Mode

Fast Mode

Fall Time of Both SDA and SCL Signals

(Note 12)

t_F

Standard Mode

300

Setup Time for STOP Condition

t_SU:STOFast Mode

Standard Mode

4.0

Capacitive Load for Each Bus Line

(Note 12)

C_B

400

I/O Capacitance (SDA, SCL)

C_I/O

t_OSF

Note 13

Note 14

Oscillator Stop Flag (OSF) Delay

100

WARNING: Negative undershoots below -0.3V while the device is in battery-backed mode may cause loss

of data.

Note 1: Limits at -40°C are guaranteed by design and are not production tested.

Note 2: All voltages referenced to ground.

Note 3: SCL only.

Note 4: SDA and SQW/OUT.

Note 5: I_CCA—SCL clocking at max frequency = 400kHz.

Note 6: Specified with the I²C bus inactive.

Note 7: Measured with a 32.768kHz crystal on X1 and X2.

Note 8: After this period, the first clock pulse is generated.

Note 9: A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the V_IHMINof

the SCL signal) to bridge the undefined region of the falling edge of SCL.

February 3, 2023

1338 Datasheet

Note 10: The maximum t_HD:DATneed only be met if the device does not stretch the LOW period (t_LOW) of the SCL

signal.

Note 11: A fast-mode device can be used in a standard-mode system, but the requirement t_SU:DAT> to 250ns must

then be met. This is automatically the case if the device does not stretch the LOW period of the SCL signal. If such

a device does stretch the LOW period of the SCL signal, it must output the next data bit to the SDA line t_R(MAX)

t_SU:DAT= 1000 + 250 = 1250 ns before the SCL line is released.

Note 12: C_B—total capacitance of one bus line in pF.

Note 13: Guaranteed by design. Not production tested.

Note 14: The parameter t_OSFis the period of time the oscillator must be stopped for the OSF flag to be set over the

voltage range of 0.0V < V_CC< V_CCMAX and 1.3V < V_BACKUP< 3.7V.

Timing Diagram

February 3, 2023

1338 Datasheet

Typical Operating Characteristics

IBAT vs VBAT

(IDT1338-31)

Icc vs Vcc

(IDT1338-31)

734

694

654

614

574

534

494

SQWE=1

SQWE=0

SCL=400kHz

SCL=0Hz

1.3

1.8

2.3

2.8

3.3

2.7

3.2

3.7

4.2

4.7

5.2

VBat (V)

Vcc (V)

Oscillator Frequency vs Supply Voltage

IBAT vs Temperature

32767.950000

32767.900000

32767.850000

32767.800000

32767.750000

800

700

600

500

400

SQWE=1

SQWE=0

Freq

-40

-20

2.7

3.2

3.7

4.2

4.7

5.2

Temperature (C)

Oscillator Supply Voltage (V)

February 3, 2023

1338 Datasheet

Thermal Characteristics for 8MSOP

Parameter

Symbol

Conditions

Min.

Typ. Max. Unit

Thermal Resistance Junction to

Ambient

_JA

Still air

C/W

Thermal Resistance Junction to Case

_JC

C/W

Thermal Characteristics for 8SOIC

Parameter

Symbol

_JA

Typ. Max. Unit

Thermal Resistance Junction to

Ambient

Still air

150

140

120

C/W

_JA

1 m/s air flow

3 m/s air flow

_JA

Thermal Resistance Junction to Case

_JC

Thermal Characteristics for 16SOIC

Parameter

Symbol

_JA

Conditions

Min.

Typ. Max. Unit

Thermal Resistance Junction to

Ambient

Still air

120

115

105

C/W

_JA

1 m/s air flow

3 m/s air flow

_JA

Thermal Resistance Junction to Case

_JC

February 3, 2023

1338 Datasheet

Marking Diagram (8MSOP)

Marking Diagram (16SOIC)

38GI

YYWW$

IDT

1338AC-31

SRGI

YYWW**$

IDT1338-31DVGI

Marking Diagram (8SOIC)

IDT1338AC-31SRGI

IDT1338

-31DCGI

YYWW$

IDT1338

-18DCGI

YYWW$

IDT

1338AC-18

SRGI

YYWW**$

IDT1338-31DCGI

IDT1338-18DCGI

IDT1338AC-18SRGI

Notes:

1. ‘$’ is the assembly mark code.

2. ‘**’ is the lot sequence.

3. ‘YYWW’ is the last two digits of the year and week that

the part was assembled.

4. “G” denotes RoHS compliant package.

5. “I” denotes industrial grade.

6. Bottom marking: Lot number.

February 3, 2023

1338 Datasheet

Package Outline Drawings

The package outline drawings are appended at the end of this document and are accessible from the link below. The

package information is the most current data available.

8MSOP (TSSOP)

www.renesas.com/us/en/document/psc/dvdvg-package-outline-30-x-30-mm-body-tssop

8SOIC

www.renesas.com/us/en/document/psc/package-outline-drawing-package-code-dcg8d1-8-soic-482-x-381-x-172-mm-b

ody-127mm-pitch

16SOIC

www.renesas.com/us/en/document/psc/sop16-package-outline-drawing-300-mil-body-127-mm-pitch-psg16d1

Ordering Information

Part / Order Number

1338-18DCGI

Shipping Packaging

Tubes

Package

8-pin SOIC

16-pin SOIC

8-pin MSOP

8-pin SOIC

16-pin SOIC

Temperature

-40 to +85 C

1338-18DCGI8

1338AC-18SRGI

1338AC-18SRGI8

1338-31DVGI

1338-31DVGI8

1338-31DCGI

1338-31DCGI8

1338AC-31SRGI

1338AC-31SRGI8

Tape and Reel

Tubes

Tape and Reel

Tubes

Tape and Reel

Tubes

Tape and Reel

Tubes

Tape and Reel

The 1338 packages are RoHS compliant. Packages without the integrated crystal are Pb-free; packages that include the

integrated crystal (as designated with a “C” before the dash number) may include lead that is exempt under RoHS

requirements. The lead finish is JESD91 category e3.

“A” is the device revision designator and will not correlate to the datasheet revision.

February 3, 2023

1338 Datasheet

Revision History

Date

Description of Change

February 3, 2023

Updated POD links in Package Outline Drawings.

September 30, 2020 • Updated Effective Load Capacitance section; added last sentence of “Cex1...of 12.5pF”.

• Rebranded/reformatted datasheet to Renesas.

November 12, 2014

Updated device markings.

March 10, 2014

Changed tVCCF min value from 300µs to 3ms. Added associated note.

February 07, 2013

1. Changed the Vih Min value to 0.8Vcc and the Vil Max value to +0.2Vcc on page 11. This is based on new

data taken on TSMC samples (old data was from Fab 4).

2. The IBATDAT current on page 12 should change from 10nA to 120nA (Typ) and from 100nA to 300nA (Max)

per latest Characterization data from TSMC.

December 10, 2012

Updated orderable parts - added “G” to 16-pin SOIC parts with SRI/SRI8. New part numbers for 16-pin SOIC

will read as SRGI and SRGI8.

September 20, 2012 1. Moved all from Fab4 to TSMC. QA requested change in the marking of only the 16-pin SOIC device with

internal crystal to add “A” due to the fact that TSMC uses a different crystal than Fab4. Notification of a change

in orderables was initiated with PCN A1208-06.

2. Updated 16-pin SOIC marking diagram and ordering information to include “A”.

October 17, 2011

Added separate item for tVCCF in “Power-up/Down Conditions” table for 1338-31; 300µs min.

September 22, 2011 Changed “V_CCFall Time; V_PF(MAX)to V_PF(MIN)” spec from 300µs Min. to 1ms Min. (Table 2,

“Power-Up/Down Characteristics).

April 13, 2011

March 29, 2010

Updated Supply Current specifications.

Added “Timeout” paragraph on page 8.

November 10, 2009

December 02, 2008

November 13, 2008

November 10, 2008

May 9, 2008

Added “Handling, PCB Layout, and Assembly” section.

Updated Typical Operating Characteristics graphs; added marking diagrams.

Updated graphs in “Typical Operating Characteristics; added “Typical Operating Circuit” diagram.

Updated Block Diagram; Typical Operating Characteristics charts.

The part number for 16pin RoHS complaint part has now changed from 1338C-31SOGI to 1338C-31SRI and

the 1338C-18SOGI changed to 1338C-18SRI.

April 03, 2004

March 28, 2008

January 29, 2008

Combined -3 and -33 parts to -31.

Added new note to Part Ordering information pertaining to RoHS compliance and Pb-free devices.

New device. Preliminary release.

February 3, 2023

Package Outline Drawing

Package Code: DCG8D1

8-SOIC 4.82 x 3.81 x 1.72 mm Body, 1.27mm Pitch

PSC-4068-01, Revision: 02, Date Created: Jun 21, 2022

0.010

-A-

See Detail A

5.00

4.80

4.00

3.81

6.30

5.79

-B-

0.48

x45°

0.25

Index Area

Top View

Side View

15°

5°

1.75

1.50

0° Min

R0.07 Min

1.80

1.24

-C-

0.254

Gage Plane

Seating Plane

0.004 C

1.27

0.25

0.10

0.51

0.30

1.27

0.41

1.04 Ref

Side View

3.81

Detail A

(Rotated 90° CW)

0.61

0.38

1.27

With Plating

0.51

0.30

0.25

0.10

0.25

0.10

0.48

0.28

Base Metal

7.16

6.96

3.81

3.61

Section A-A

NOTES:

1. JEDEC compatible.

2. All dimensions are in mm and angles are in degrees.

3. Use ±0.05 mm for the non-toleranced dimensions.

4. Foot length is measured at gauge plane 0.25 mm

above seating plane.

RECOMMENDED LAND PATTERN

(PCB Top View, SMD Design)

SOP16, Package Outline Drawing

300 Mil Body, 1.27 mm Pitch

PSG16D1, PSC-4007-01, Rev 01, Page 1

Package Revision History

Date Created Rev no.

Nov 4, 2021 Rev 01

Feb 25, 2016 Rev 00

Description

Added Land Pattern

Initial Release

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