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K6R4016C1D-TP8

更新时间：2025-06-11 02:23:53

品牌：SAMSUNG

描述：256Kx16 Bit High Speed Static RAM(5.0V Operating). Operated at Commercial and Industrial Temperature Ranges.

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K6R4016C1D-TP8 概述

256Kx16 Bit High Speed Static RAM(5.0V Operating). Operated at Commercial and Industrial Temperature Ranges. 256Kx16位高速静态RAM （ 5.0V工作）。工作在商用和工业温度范围。

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PRELIMPreliminaryPPPPPPPPPINARY

CMOS SRAM

K6R4016C1D

Document Title

256Kx16 Bit High Speed Static RAM(5.0V Operating).

Operated at Commercial and Industrial Temperature Ranges.

Revision History

Rev No.

Rev. 0.0

Rev. 0.1

Rev. 0.2

History

Draft Data

Remark

Initial release with Preliminary.

Package dimension modify on page 11.

Change Icc, Isb and Isb1

September. 7. 2001

Septermber.28. 2001

November, 3, 2001

Preliminary

Item

10ns

90mA

Current

65mA

55mA

45mA

85mA

75mA

65mA

20mA

5mA

ICC(Commercial)

12ns

15ns

10ns

12ns

15ns

80mA

70mA

115mA

100mA

85mA

ICC(Industrial)

ISB

ISB1(Normal)

30mA

10mA

Rev. 0.3

Rev. 0.4

1. Correct AC parameters : Read & Write Cycle

2. Corrrect Power part : Delete "P-Industrial,Low Power" part

3. Delete Data Retention Characteristics

November, 23, 2001

December, 18, 2001

Preliminary

1. Delete 15ns speed bin.

2. Change Icc for Industrial mode.

Item

85mA

75mA

Current

75mA

10ns

12ns

ICC(Industrial)

65mA

Rev. 1.0

Rev. 2.0

1. Final datasheet release.

2. Delete 12ns speed bin.

July, 09, 2002

June. 20, 2003

Final

1. Add the Lead Free Package type.

The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the

specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any ques-

tions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.

Rev 2.0

June 2003

- 1 -

PRELIMPreliminaryPPPPPPPPPINARY

CMOS SRAM

K6R4016C1D

4Mb Async. Fast SRAM Ordering Information

Org.

Part Number

VDD(V)

Speed ( ns )

PKG

Temp. & Power

K6R4004C1D-J(K)C(I) 10

K6R4004V1D-J(K)C(I) 08/10

K6R4008C1D-J(K,T,U)C(I) 10

3.3

8/10

J : 32-SOJ

1M x4

K : 32-SOJ(LF) C : Commercial Temperature

,Normal Power Range

J : 36-SOJ

K : 36-SOJ(LF)

T : 44-TSOP2

U : 44-TSOP2(LF)

I : Industrial Temperature

512K x8

,Normal Power Range

K6R4008V1D-J(K,T,U)C(I) 08/10

3.3

8/10

L : Commercial Temperature

,Low Power Range

P : Industrial Temperature

,Low Power Range

J : 44-SOJ

K6R4016C1D-J(K,T,U,E)C(I) 10

K : 44-SOJ(LF)

T : 44-TSOP2

U: 44-TSOP2(LF)

E : 48-TBGA

256K x16

K6R4016V1D-J(K,T,U,E)C(I,L,P) 08/10

3.3

8/10

Rev 2.0

June 2003

- 2 -

PRELIMPreliminaryPPPPPPPPPINARY

CMOS SRAM

K6R4016C1D

256K x 16 Bit High-Speed CMOS Static RAM

FEATURES

GENERAL DESCRIPTION

• Fast Access Time 10ns(Max.)

• Low Power Dissipation

Standby (TTL) : 20mA(Max.)

The K6R4016C1D is a 4,194,304-bit high-speed Static Ran-

dom Access Memory organized as 262,144 words by 16 bits.

The K6R4016C1D uses 16 common input and output lines and

has an output enable pin which operates faster than address

access time at read cycle. Also it allows that lower and upper

byte access by data byte control(UB, LB). The device is fabri-

cated using SAMSUNG¢s advanced CMOS process and

designed for high-speed circuit technology. It is particularly well

suited for use in high-density high-speed system applications.

The K6R4016C1D is packaged in a 400mil 44-pin plastic SOJ

or TSOP(II) forward or 48 T BGA.

(CMOS) : 5mA(Max.)

Operating K6R4016C1D-10 : 65mA(Max.)

• Single 5.0V±10% Power Supply

• TTL Compatible Inputs and Outputs

• Fully Static Operation

- No Clock or Refresh required

• Three State Outputs

• Center Power/Ground Pin Configuration

• Data Byte Control : LB : I/O1~ I/O8, UB : I/O9~ I/O16

• Standard Pin Configuration

K6R4016C1D-J : 44-SOJ-400

K6R4016C1D-K : 44-SOJ-400(Lead-Free)

K6R4016C1D-T : 44-TSOP2-400BF

K6R4016C1D-U : 44-TSOP2-400BF (Lead-Free)

K6R4016C1D-E : 48-TBGA with 0.75 Ball pitch

(7mm X 9mm)

• Operating in Commercial and Industrial Temperature range.

FUNCTIONAL BLOCK DIAGRAM

Clk Gen.

Pre-Charge Circuit

Memory Array

1024 Rows

256 x 16 Columns

Data

Cont.

I/O Circuit &

Column Select

I/O1~I/O 8

Data

Cont.

I/O9~I/O 16

Gen.

CLK

A10 A11 A12 A13 A14 A15 A16 A17

Rev 2.0

June 2003

- 3 -

PRELIMPreliminaryPPPPPPPPPINARY

CMOS SRAM

K6R4016C1D

PIN CONFIGURATION (Top View)

44 A17

43 A16

42 A15

41 OE

N.C

I/O1

I/O9

I/O10

Vcc

40 UB

I/O1

I/O2

I/O3

39 LB

I/O2

Vss

I/O3

I/O4

I/O5

I/O6

N.C

I/O11

I/O12

I/O13

I/O14

38 I/O 16

37 I/O 15

36 I/O 14

35 I/O 13

34 Vss

33 Vcc

32 I/O 12

31 I/O 11

30 I/O 10

29 I/O 9

28 N.C

27 A14

26 A13

25 A12

24 A11

23 A10

A17

N.C

A14

A12

I/O4 10

Vcc 11

Vss 12

I/O5 13

I/O6 14

I/O7 15

I/O8 16

WE 17

A5 18

SOJ/

TSOP2

Vcc

I/O7

I/O8

N.C

A16

A15

A13

A10

Vss

I/O15

I/O16

N.C

A11

A6 19

A7 20

48-TBGA

A8 21

A9 22

PIN FUNCTION

Pin Name

A0 - A17

Pin Function

Address Inputs

Write Enable

Chip Select

Output Enable

Lower-byte Control(I/O1~I/O8)

Upper-byte Control(I/O9~I/O16)

Data Inputs/Outputs

Power(+5.0V)

I/O1 ~ I/O16

VCC

VSS

Ground

N.C

No Connection

ABSOLUTE MAXIMUM RATINGS*

Parameter

Voltage on Any Pin Relative to VSS

Voltage on VCC Supply Relative to VSS

Power Dissipation

Symbol

VIN, VOUT

VCC

Rating

Unit

-0.5 to VCC+0.5

-0.5 to 7.0

1.0

°C

Storage Temperature

TSTG

-65 to 150

0 to 70

Operating Temperature

Commercial

Industrial

-40 to 85

* Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and

functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied.

Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Rev 2.0

June 2003

- 4 -

PRELIMPreliminaryPPPPPPPPPINARY

CMOS SRAM

K6R4016C1D

RECOMMENDED DC OPERATING CONDITIONS*(TA=0 to 70°C)

Parameter

Symbol

Min

Typ

Max

Unit

Supply Voltage

VCC

4.5

5.0

5.5

Ground

VSS

Input High Voltage

Input Low Voltage

VIH

2.2

VCC+0.5***

0.8

VIL

-0.5**

The above parameters are also guaranteed at industrial temperature range.

** VIL(Min) = -2.0V a.c(Pulse Width £ 8ns) for I £ 20mA.

*** VIH(Max) = VCC + 2.0V a.c (Pulse Width £ 8ns) for I £ 20mA.

DC AND OPERATING CHARACTERISTICS*(TA=0 to 70°C, Vcc=5.0V±10%, unless otherwise specified)

Parameter

Symbol

Test Conditions

Min

Max

Unit

Input Leakage Current

Output Leakage Current

ILI

VIN=VSS to VCC

-2

ILO

CS =VIH or OE=VIH or WE=VIL

VOUT=VSS to VCC

-2

Operating Current

Standby Current

ICC

Min. Cycle, 100% Duty

CS =VIL, VIN=VIH orVIL, IOUT=0mA

Com.

Ind.

10ns

ISB

Min. Cycle, CS=VIH

ISB1

f=0MHz, CS ³ VCC-0.2V,

VIN³ VCC-0.2V or VIN£0.2V

Output Low Voltage Level

Output High Voltage Level

VOL

VOH

IOL=8mA

IOH=-4mA

0.4

2.4

* The above parameters are also guaranteed at industrial temperature range.

CAPACITANCE*(TA=25°C, f=1.0MHz)

Item

Symbol

Test Conditions

VI/O=0V

TYP

Max

Unit

Input/Output Capacitance

Input Capacitance

CI/O

CIN

VIN=0V

* Capacitance is sampled and not 100% tested.

Rev 2.0

June 2003

- 5 -

PRELIMPreliminaryPPPPPPPPPINARY

CMOS SRAM

K6R4016C1D

AC CHARACTERISTICS(TA=0 to 70°C, VCC=5.0V±10%, unless otherwise noted.)

TEST CONDITIONS*

Parameter

Value

Input Pulse Levels

0V to 3V

3ns

Input Rise and Fall Times

Input and Output timing Reference Levels

Output Loads

1.5V

See below

* The above test conditions are also applied at industrial temperature range.

Output Loads(B)

for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ

Output Loads(A)

+5.0V

RL = 50W

DOUT

480W

VL = 1.5V

DOUT

30pF*

ZO = 50W

255W

5pF*

* Capacitive Load consists of all components of the

test environment.

* Including Scope and Jig Capacitance

READ CYCLE*

K6R4016C1D-10

Parameter

Symbol

Unit

Min

Max

Read Cycle Time

tRC

tAA

Address Access Time

Chip Select to Output

tCO

tOE

tLZ

Output Enable to Valid Output

Chip Enable to Low-Z Output

Output Enable to Low-Z Output

Chip Disable to High-Z Output

Output Disable to High-Z Output

Output Hold from Address Change

Chip Selection to Power Up Time

Chip Selection to Power DownTime

tOLZ

tHZ

tOHZ

tOH

tPU

tPD

* The above parameters are also guaranteed at industrial temperature range.

Rev 2.0

June 2003

- 6 -

PRELIMPreliminaryPPPPPPPPPINARY

CMOS SRAM

K6R4016C1D

WRITE CYCLE*

K6R4016C1D-10

Parameter

Symbol

Unit

Min

Max

Write Cycle Time

tWC

tCW

tAS

Chip Select to End of Write

Address Set-up Time

Address Valid to End of Write

Write Pulse Width(OE High)

Write Pulse Width(OE Low)

Write Recovery Time

tAW

tWP

tWP1

tWR

tWHZ

tDW

tDH

Write to Output High-Z

Data to Write Time Overlap

Data Hold from Write Time

End of Write to Output Low-Z

tOW

* The above parameters are also guaranteed at industrial temperature range.

TIMING DIAGRAMS

TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH, UB, LB=VIL)

tRC

Address

tAA

tOH

Data Out

Previous Valid Data

Valid Data

TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)

tRC

Address

tAA

tCO

tHZ(3,4,5)

tBHZ(3,4,5)

tBA

UB, LB

tBLZ(4,5)

tOHZ

tOE

tOLZ

tOH

tLZ(4,5)

Data out

High-Z

Valid Data

Rev 2.0

June 2003

- 7 -

PRELIMPreliminaryPPPPPPPPPINARY

CMOS SRAM

K6R4016C1D

NOTES(READ CYCLE)

1. WE is high for read cycle.

2. All read cycle timing is referenced from the last valid address to the first transition address.

3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or VOL

levels.

4. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ (Min.) both for a given device and from device to

device.

5. Transition is measured ±200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested.

6. Device is continuously selected with CS=VIL.

7. Address valid prior to coincident with CS transition low.

8. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.

TIMING WAVEFORM OF WRITE CYCLE(1) (OEClock)

tWC

Address

tAW

tWR(5)

tCW(3)

tBW

UB, LB

tAS(4)

tWP(2)

tDW

tDH

High-Z

Data in

Data out

Valid Data

tOHZ(6)

TIMING WAVEFORM OF WRITE CYCLE(2) (OE=Low fixed)

tWC

Address

tAW

tWR(5)

tCW(3)

tBW

UB, LB

tWP1(2)

tAS(4)

tDW

tDH

High-Z

Valid Data

Data in

(9)

(10)

tWHZ(6)

tOW

High-Z

Data out

Rev 2.0

June 2003

- 8 -

PRELIMPreliminaryPPPPPPPPPINARY

CMOS SRAM

K6R4016C1D

TIMING WAVEFORM OF WRITE CYCLE(3) (CS=Controlled)

tWC

Address

tAW

tWR(5)

tCW(3)

tBW

UB, LB

tAS(4)

tWP(2)

tDW

tDH

High-Z

Data in

Valid Data

tLZ

tWHZ(6)

High-Z

High-Z(8)

Data out

TIMING WAVEFORM OF WRITE CYCLE(4) (UB, LBControlled)

tWC

Address

tAW

tCW(3)

tWR(5)

tBW

UB, LB

tAS(4)

tWP(2)

tDH

tDW

High-Z

Data in

Valid Data

tBLZ

tWHZ(6)

High-Z(8)

High-Z

Data out

NOTES(WRITE CYCLE)

1. All write cycle timing is referenced from the last valid address to the first transition address.

2. A write occurs during the overlap of a low CS,WE,LB and UB. A write begins at the latest transition CS going low and WE

going low ; A write ends at the earliest transition CS going high or WE going high. tWP is measured from the beginning of write

to the end of write.

3. tCW is measured from the later of CS going low to end of write.

4. tAS is measured from the address valid to the beginning of write.

5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.

6. If OE, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase

of the output must not . be applied because bus contention can occur.

7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.

8. If CS goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state.

9. Dout is the read data of the new address.

10. When CS is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be

applied.

Rev 2.0

June 2003

- 9 -

PRELIMPreliminaryPPPPPPPPPINARY

CMOS SRAM

K6R4016C1D

FUNCTIONAL DESCRIPTION

I/O Pin

Mode

Supply Current

I/O1~I/O8

High-Z

I/O9~I/O16

High-Z

Not Select

ISB, ISB1

ICC

Output Disable

High-Z

Read

Write

DOUT

High-Z

DOUT

DIN

High-Z

DOUT

High-Z

DIN

ICC

High-Z

DIN

* X means Don¢t Care.

Rev 2.0

June 2003

- 10

PRELIMPreliminaryPPPPPPPPPINARY

CMOS SRAM

K6R4016C1D

PACKAGE DIMENSIONS

44-SOJ-400

Units:millimeters/Inches

#44

#23

9.40 ± 0.25

0.370 ±0.010

11.18 ± 0.12

0.440± 0.005

+0.10

0.20

-0.05

0.008^+0.004

- 0.002

#22

28.98

1.141

0.69

0.027

MAX

MIN

25.58 ± 0.12

1.125 ± 0.005

1.19

0.047

1.27

(

)

3.76

0.148

MAX

(

)

0.050

0.10

MAX

0.004

+0.10

0.43

0.017

- 0.002

-0.05

+0.004

+0.10

-0.05

0.71

0.95

0.0375

1.27

0.050

(

)

0.028 ^+0.004

-0.002

44-TSOP2-400BF

Units:millimeters/Inches

0~8°

0.25

0.010

TYP

#23

#44

0.45 ~0.75

0.018 ~ 0.030

11.76 ±0.20

0.463 ±0.008

0.50

0.020

(

)

#22

18.81

0.741

MAX

+ 0.075

- 0.035

+ 0.003

- 0.001

0.125

0.005

18.41 ± 0.10

0.725 ±0.004

1.00 ± 0.10

0.039 ±0.004

1.20

0.047

MAX

0.10

0.004

MAX

+0.10

- 0.05

+ 0.004

- 0.002

0.05

0.002

0.30

MIN

0.80

0.0315

0.805

0.032

(

)

0.012

Rev 2.0

June 2003

- 11

PRELIMPreliminaryPPPPPPPPPINARY

CMOS SRAM

K6R4016C1D

PACKAGE DIMENSIONS

Units : millimeter.

Top View

Bottom View

A1 INDEX MARK

0.50

#A1

B/2

Detail A

Side View

Min

Typ

0.75

7.00

3.75

9.00

5.25

0.45

0.90

0.55

0.35

Max

6.90

Notes.

7.10

1. Bump counts: 48(8row x 6column)

2. Bump pitch : (x,y)=(0.75 x 0.75)(typ.)

3. All tolerence are +/-0.050 unless

otherwise specified.

8.90

9.10

4. Typ : Typical

0.40

0.80

0.50

1.00

5. Y is coplanarity: 0.08(Max)

0.30

0.40

0.08

Rev 2.0

June 2003

- 12

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