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M464S1724IUS

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品牌：SAMSUNG

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M464S1724IUS 概述

SDRAM Product Guide SDRAM产品指南

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General Information

SDRAM

SDRAM Product Guide

November 2007

Memory Division

November 2007

General Information

SDRAM

A. SDRAM Component Ordering Information

K 4 S X X X X X X X - X X X X

Speed

Temperature & Power

Package Type

Revision

Interface (VDD, VDDQ)

Bank

SAMSUNG Memory

DRAM

Product

Density & Refresh

Organization

1. SAMSUNG Memory : K

2. DRAM : 4

8. Revision

M : 1st Gen.

: 11th Gen.

A : 2nd Gen.

B : 3rd Gen.

C : 4th Gen.

D : 5th Gen.

E : 6th Gen.

K : 12th Gen

N : 14th Gen

3. Product

: 7th Gen

S : SDRAM

H : 9th Gen

4. Density & Refresh

16 : 16Mb, 4K/64ms

64 : 64Mb, 4K/64ms

28 : 128Mb, 4K/64ms

56 : 256Mb, 8K/64ms

51 : 512Mb, 8K/64ms

9. Package Type

U : TSOP II (Lead-free)

: TSOP II

V : sTSOP II (Lead-free)

N : sTSOP II

(Lead-free & Halogen-free)

: TSOP II

Note 1: All of Lead-free or Halogen-free product are in

compliance with RoHS

5. Organization

10. Temperature & Power

04 : x 4

06 : x 4 Stack (Flex frame)

07 : x 8 Stack (Flex frame)

08 : x 8

C : Commercial Temp.( 0°C ~ 70°C) & Normal Power

L : Commercial Temp.( 0°C ~ 70°C) & Low Power

I : Industrial Temp.( -40°C ~ 85°C) & Normal Power

P : Industrial Temp.( -40°C ~ 85°C) & Low Power

16 : x16

32 : x32

6. Bank

11. Speed (Default CL= 3)

2 : 2 Banks

3 : 4 Banks

75 : 7.5ns, PC133 (133MHz CL=3)

60 : 6.0ns (166MHz CL=3)

50 : 5.0ns (200MHz CL=3)

7. Interface ( VDD, VDDQ)

2 : LVTTL (3.3V, 3.3V)

November 2007

General Information

SDRAM

B. SDRAM Component Product Guide

Package & Power

Density

Bank

Part Number

Org.

Interface

Refresh

Power (V)

Package

Avail.

Speed

UC75

UL75

K4S640832K

K4S641632K

K4S640832N

K4S641632N

K4S280432I

8M x 8

4M x 16

8M x 8

EOL

64Mb K-die

4Banks

LVTTL

4K/64ms

3.3 ± 0.3V

Lead-free 54pin TSOP(II)

DEC. ’08

UC50/C60/C75

UL50/L60/L75

LC75

LL75

Lead-free & Halogen-

free

4Q’07

64Mb N-die

128Mb I-die

4Banks

LVTTL

4K/64ms

3.3 ± 0.3V

LC50/C60/C75

LL50/L60/L75

54pin TSOP(II)

4M x 16

32M x 4

16M x 8

8M x 16

32M x 4

16M x 8

8M x 16

64M x 4

32M x 8

16M x 16

64M x 4

32M x 8

16M x 16

128M x 4

64M x 8

32M x 16

UC75

UL75

UC75

UL75

EOL

4Banks K4S280832I

K4S281632I

Lead-free 54pin TSOP(II)

AUG. ’08

UC60/C75

UL60/L75

C75

K4S280432K

UL75

Lead-free & Halogen-

free

UC75

UL75

4Banks

LVTTL

4K/64ms

8K/64ms

3.3 ± 0.3V

Now

128Mb K-die

256Mb H-die

K4S280832K

K4S281632K

K4S560432H

54pin TSOP(II)

UC60/C75

UL60/L75

UC75

UL75

UC75

UL75

EOL

4Banks K4S560832H

K4S561632H

Lead-free 54pin TSOP(II)

SEP. ’08

UC60/C75

UL60/L75

C75

K4S560432J

UL75

Lead-free & Halogen-

free

UC75

UL75

4Banks

Now

256Mb J-die

K4S560832J

K4S561632J

K4S510432D

54pin TSOP(II)

UC60/C75

UL60/L75

UC75

UL75

UC75

UL75

512Mb D-die

Note 1 :

4Banks K4S510832D

K4S511632D

Lead-free 54pin TSOP(II)

UC75

UL75

Note 3 :

U : TSOP(II) (Lead-free)

L : TSOP(II) (Lead-free & Halogen-free)

Speed

Description

7.5ns, PC133 (133Mhz @ CL=3)

6.0 ns (166Mhz @ CL=3)

5.0 ns (200Mhz @ CL=3)

Note 2 :

Temperature and Power Description

Temperature, Normal Power

* All products have backward compatibility with PC100.

Temperature, Low Power

- Commercial Temp (0°C < Ta < 70°C)

Note 4 : 128Mb K-die SDR and 256Mb J-die SDR DRAMs support Lead-free & Halogen-free package with Lead-free package code(-U)

November 2007

General Information

SDRAM

C. Industrial Temperature SDRAM Component Product Guide

Package & Power

Density

Bank

Part Number

Org.

Interface

Refresh

Power (V)

Package

Avail.

& Speed

64Mb

K-die

4Banks

UI60/I75

EOL

KS641632K

4M x 16

8M x 16

16M x 16

LVTTL

4K/64ms

8K/64ms

Lead-free 54pin TSOP(II)

3.3 ± 0.3V

UP60/P75

DEC.’08

64Mb

N-die

LI60/I75

Lead-free & Halogen-free

54pin TSOP(II)

4Banks KS641632N

4Banks K4S281632I

4Banks K4S281632K

4Banks K4S561632H

4Banks K4S561632J

1Q’08

LP60/P75

128Mb

I-die

UI60/I75

EOL

Lead-free 54pin TSOP(II)

Lead-free & Halogen-free

UP60/P75

AUG.’08

128Mb

K-die

I60/I75

Now

UP60/P75

54pin TSOP(II)

256Mb

H-die

UI60/I75

EOL

Lead-free 54pin TSOP(II)

UP60/P75

SEP.’08

256Mb

J-die

Lead-free & Halogen-free

I60/I75

Now

UP60/P75

54pin TSOP(II)

Note 1 :

Note 3 :

U : TSOP(II) (Lead-free)

L : TSOP(II) (Lead-free & Halogen-free)

Speed

Description

7.5ns, PC133 (133Mhz @ CL=3)

6.0 ns (166Mhz @ CL=3)

5.0 ns (200Mhz @ CL=3)

Note 2 :

Temperature and Power Description

Industrial Temperature, Normal Power

Industrial Temperature, Low Power

- Industrial Temp (-40°C < Ta < 85°C)

Note 4 : 128Mb K-die SDR and 256Mb J-die SDR DRAMs support Lead-free & Halogen-free package with Lead-free package code(-U)

November 2007

General Information

SDRAM

D. SDRAM Module Ordering Information

M X X X S X X X X X X X - X X X

Memory Module

DIMM Configuration

Speed

Power

Data bits

PCB revision & Type

Feature

Depth

Package

Component Revision

Refresh, # of Banks in Comp. & Interface

Composition Component

1. Memory Module : M

7. Composition Component

: x 4

: x 8

: x16

2. DIMM Configuration

: x 4 Stack (Flexframe)

: x 8 Stack (Flexframe)

3 : DIMM

4 : SODIMM

3. Data Bits

8. Component Revision

63 : x63 PC100 / PC133 µSODIMM

1st Gen.

3rd Gen.

5th Gen.

7th Gen.

11h Gen.

2nd Gen.

4th Gen.

6th Gen.

9h Gen.

with SPD for 144pin

64 : x64 PC100 / PC133 SODIMM

with SPD for 144pin (Intel/JEDEC)

66 : x64 Unbuffered DIMM

with SPD for 144pin/168pin (Intel/JEDEC)

74 : x72 /ECC Unbuffered DIMM

with SPD for 168pin (Intel/JEDEC)

77 : x72 /ECC PLL + Register DIMM

with SPD for 168pin (Intel PC100)

90 : x72 /ECC PLL + Register DIMM

with SPD for 168pin (JEDEC PC133)

9. Package

: TSOP(II)

(400mil)

: sTSOP(II)

: TSOP(II) Lead-free (400mil)

: sTSOP(II) Lead-free (400mil)

4. Feature

S : SDRAM

10. PCB Revision & Type

5. Depth

Mother PCB

2nd Rev.

Low Profile DIMM S : 4Layer PCB.

1 : 1st Rev.

3 : 3rd Rev.

09 : 8M (for 128Mb/512Mb)

16 : 16M

32 : 32M

64 : 64M

28 : 128M

56 : 256M

17 : 16M (for 128Mb/512Mb)

33 : 32M (for 128Mb/512Mb)

65 : 64M (for 128Mb/512Mb)

29 : 128M (for 128Mb/512Mb)

59 : 256M (for 128Mb/512Mb)

11. Power

C : Commercial Normal

: Commercial Low

( 0°C ~ 70°C)

6. Refresh, # of Banks in comp. & Interface

4K/ 64ms Ref., 4Banks & LVTTL

8K/ 64ms Ref., 4Banks & LVTTL

12. Speed (Default CL= 3 )

7A : PC133 (133MHz CL=3/PC100 CL2)

November 2007

General Information

SDRAM

E. SDRAM Module Product Guide

Comp.

Power Internal External

Org.

Density

Part No.

Speed

Composition

Feature

Avail.

Version

(V)

Banks

168pin PC133 Registered DIMM

32Mx72

64Mx72

256MB M390S3253HU1

C7A

32M x 8 * 9 pcs

64M x 4 * 18 pcs

256Mb

H-die

DS, 1500mil

DS, 1700mil

DS, 1200mil

EOL

M390S6450HU1

512MB

3.3 V

JUN.’08

M390S6450HUU

168pin PC133 Unbuffered DIMM

8Mx64

64MB M366S0924IUS

M366S1723IUS

C7A

8M x 16 * 4 pcs

16M x 8 * 8 pcs

128Mb

I-die

SS, 1000mil

SS, 1375mil

EOL

JUN.’08

EOL

16Mx64

M366S1654HUS

128MB

C7A

16M x 16 * 4 pcs

256Mb

H-die

SS, 1000mil

JUN.’08

M366S1654JUS

C7A

16M x 16 * 4 pcs

16M x 8 * 9 pcs

16M x 8 * 16 pcs

16M x 8 * 18 pcs

32M x 8 * 8 pcs

256Mb

128Mb

256Mb

J-die

I-die

J-die

SS, 1000mil

SS, 1375mil

DS, 1375mil

SS, 1375mil

Now

16Mx72

32Mx64

32Mx72

32Mx64

M374S1723IUS

3.3V

EOL

M366S3323IUS

JUN.’08

256MB M374S3323IUS

M366S3253JUS

Now

EOL

M366S6453HUS

512MB

C7A

32M x 8 * 16 pcs

256Mb

H-die

J-die

DS, 1375mil

JUN.’08

64Mx64

M366S6453JUS

32M x 8 * 16 pcs

256Mb

Now

144pin PC133 SODIMM

EOL

M464S1724IUS

128MB

L7A

8M x 16 * 8 pcs

16M x 16 * 8 pcs

32M x 8 * 16 pcs

128Mb

I-die

DS, 1250mil

JUN.’08

16Mx64

32Mx64

64Mx64

M464S1724KUS

128Mb

256Mb

K-die

H-die

J-die

H-die

J-die

Now

EOL

M464S3254HUS

256MB

JUN.’08

3.3V

M464S3254JUS

Now

EOL

M464S6453HV0

512MB

JUN.’08

M464S6453JV0

Now

November 2007

General Information

SDRAM

F. Package Dimension

Unit : mm

#54

#28

#27

(1.50)

+0.075

- 0.035

0.125

22.22 ± 0.10

(10°)

0.10 MAX

[

(10°)

0.80TYP

[0.80 ± 0.08]

0.075 MAX

[

+0.10

0.35

- 0.05

(0.71)

0.25TYP

NOTE

1. ( ) IS REFERENCE

2. [ ] IS ASS’Y OUT QUALITY

(0° ∼ 8°)

54Pin TSOP(II) Package Dimension

November 2007

General Information

SDRAM

For further information,

semiconductor@samsung.com

November 2007

M464S1724IUS 相关器件

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