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530GC127M000DGR

更新时间：2025-07-06 03:18:26

品牌：SILICON

描述：CMOS Output Clock Oscillator, 127MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

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530GC127M000DGR 概述

CMOS Output Clock Oscillator, 127MHz Nom, ROHS COMPLIANT, SMD, 6 PIN

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Si530/531

REVISION D

CRYSTAL OSCILLATOR (XO) (10 MHZ TO 1.4 GHZ)

Features

Si5602



Available with any-rate output



Internal fixed crystal frequency

ensures high reliability and low

aging

Available CMOS, LVPECL,

LVDS, and CML outputs

3.3, 2.5, and 1.8 V supply options

Industry-standard 5 x 7 mm

package and pinout

frequencies from 10 MHz to 945 MHz

and select frequencies to 1.4 GHz



3rd generation DSPLL with superior

jitter performance



3x better frequency stability than

SAW-based oscillators



Pb-free/RoHS-compliant

Ordering Information:

Applications

See page 7.



SONET/SDH

Networking

SD/HD video



Test and measurement

Clock and data recovery

FPGA/ASIC clock generation

Pin Assignments:

See page 6.

Description

(Top View)

The Si530/531 XO utilizes Silicon Laboratories’ advanced DSPLL circuitry

to provide a low jitter clock at high frequencies. The Si530/531 is available

with any-rate output frequency from 10 to 945 MHz and select frequencies to

1400 MHz. Unlike a traditional XO, where a different crystal is required for

each output frequency, the Si530/531 uses one fixed crystal to provide a

wide range of output frequencies. This IC based approach allows the crystal

resonator to provide exceptional frequency stability and reliability. In addition,

DSPLL clock synthesis provides superior supply noise rejection, simplifying

the task of generating low jitter clocks in noisy environments typically found in

communication systems. The Si530/531 IC based XO is factory configurable

for a wide variety of user specifications including frequency, supply voltage,

output format, and temperature stability. Specific configurations are factory

programmed at time of shipment, thereby eliminating long lead times

associated with custom oscillators.

V_DD

CLK–

CLK+

GND

Si530 (LVDS/LVPECL/CML)

V_DD

Functional Block Diagram

GND

CLK

V_DD

CLK– CLK+

Si530 (CMOS)

V_DD

Any-rate

10–1400 MHz

DSPLL^®

Clock

Synthesis

Fixed

Frequency

CLK–

CLK+

GND

Si531 (LVDS/LVPECL/CML)

GND

Rev. 1.2 5/11

Si530/531

1. Electrical Specifications

Table 1. Recommended Operating Conditions

Parameter

Symbol

Test Condition

3.3 V option

2.5 V option

1.8 V option

Min

2.97

2.25

1.71

Typ

3.3

2.5

1.8

Max

3.63

2.75

1.89

Units

Supply Voltage

Supply Current

Output enabled

LVPECL

CML

—

121

108

111

LVDS

CMOS

Tristate mode

—

0.75 x V

—

Output Enable (OE)²

0.5

Operating Temperature Range

–40

ºC

Notes:

1. Selectable parameter specified by part number. See Section 3. "Ordering Information" on page 7 for further details.

2. OE pin includes a 17 k pullup resistor to V_DD

Table 2. CLK± Output Frequency Characteristics

Parameter

Symbol

Test Condition

LVPECL/LVDS/CML

CMOS

Min

Typ

—

Max

945

160

Units

MHz

Nominal Frequency^1,2

—

Initial Accuracy

Measured at +25 °C at time of

shipping

f_i

—

±1.5

—

ppm

Temperature Stability^1,3

–7

–20

–50

—

+20

+50

Aging

Frequency drift over first year

—

±3

ppm

f_a

Frequency drift over 20 year

life

±10

Notes:

1. See Section 3. "Ordering Information" on page 7 for further details.

2. Specified at time of order by part number. Also available in frequencies from 970 to 1134 MHz and 1213 to 1417 MHz.

3. Selectable parameter specified by part number.

4. Time from powerup or tristate mode to f_O.

Rev. 1.2

Si530/531

Table 2. CLK± Output Frequency Characteristics (Continued)

Parameter

Total Stability

Symbol

Test Condition

Min

—

Typ

—

Max

±20

Units

ppm

Temp stability = ±7 ppm

Temp stability = ±20 ppm

Temp stability = ±50 ppm

—

±31.5

±61.5

—

Powerup Time⁴

t_OSC

—

Notes:

1. See Section 3. "Ordering Information" on page 7 for further details.

2. Specified at time of order by part number. Also available in frequencies from 970 to 1134 MHz and 1213 to 1417 MHz.

3. Selectable parameter specified by part number.

4. Time from powerup or tristate mode to f_O.

Table 3. CLK± Output Levels and Symmetry

Parameter

Symbol

Test Condition

mid-level

Min

V_DD– 1.42

1.1

Typ

—

Max

V_DD– 1.25

1.9

Units

LVPECL Output Option¹

V_OD

V_SE

swing (diff)

—

V_PP

swing (single-ended)

mid-level

0.55

—

0.95

LVDS Output Option²

CML Output Option²

1.125

1.20

1.275

swing (diff)

V_OD

V_O

0.5

—

0.7

0.9

—

V_PP

2.5/3.3 V option mid-level

1.8 V option mid-level

– 1.30

—

– 0.36

—

2.5/3.3 V option swing (diff)

1.8 V option swing (diff)

1.10

0.35

0.8 x V_DD

—

1.50

1.90

0.50

V_DD

0.4

350

—

V_PP

V_OD

0.425

—

CMOS Output Option³

Rise/Fall time (20/80%)

Symmetry (duty cycle)

V_OH

V_OL

= 32 mA

I_OL= 32 mA

—

t_R,t_F

LVPECL/LVDS/CML

—

CMOS with C = 15 pF

—

LVPECL:

V_DD– 1.3 V

SYM

(diff)

LVDS:

CMOS:

—

1.25 V (diff)

V_DD/2

Notes:

1. 50  to V_DD– 2.0 V.

2. R_term= 100  (differential).

3. C_L= 15 pF

Rev. 1.2

Si530/531

Table 4. CLK± Output Phase Jitter

Parameter

Symbol

Test Condition

Min

—

Typ

0.25

0.26

0.36

0.34

0.62

0.61

Max

0.40

0.37

0.50

0.42

—

Units

Phase Jitter (RMS)¹

for F_OUT> 500 MHz

_J

12 kHz to 20 MHz (OC-48)

50 kHz to 80 MHz (OC-192)

12 kHz to 20 MHz (OC-48)

—

Phase Jitter (RMS)¹

for F_OUTof 125 to 500 MHz

—

50 kHz to 80 MHz (OC-192)

—

Phase Jitter (RMS)

for F_OUTof 10 to 160 MHz

CMOS Output Only

12 kHz to 20 MHz (OC-48)

—

50 kHz to 20 MHz

—

Notes:

1. Refer to AN256 for further information.

2. Max offset frequencies: 80 MHz for FOUT > 250 MHz, 20 MHz for 50 MHz < FOUT <250 MHz,

2 MHz for 10 MHz < FOUT <50 MHz.

Table 5. CLK± Output Period Jitter

Parameter

Period Jitter*

Symbol

Test Condition

RMS

Min

—

Typ

Max

—

Units

PER

Peak-to-Peak

—

*Note: Any output mode, including CMOS, LVPECL, LVDS, CML. N = 1000 cycles. Refer to AN279 for further information.

Table 6. CLK± Output Phase Noise (Typical)

Offset Frequency (f)

120.00 MHz

LVDS

156.25 MHz

LVPECL

622.08 MHz

LVPECL

Units

100 Hz

1 kHz

10 kHz

100 kHz

1 MHz

–112

–122

–132

–137

–144

–150

n/a

–105

–122

–128

–135

–144

–147

n/a

–97

–107

–116

–121

–134

–146

–148

dBc/Hz

10 MHz

100 MHz

Rev. 1.2

Si530/531

Table 7. Environmental Compliance

The Si530/531 meets the following qualification test requirements.

Parameter

Mechanical Shock

Conditions/Test Method

MIL-STD-883, Method 2002

MIL-STD-883, Method 2007

MIL-STD-883, Method 2003

MIL-STD-883, Method 1014

MIL-STD-883, Method 2036

J-STD-020, MSL1

Mechanical Vibration

Solderability

Gross & Fine Leak

Resistance to Solder Heat

Moisture Sensitivity Level

Contact Pads

Gold over Nickel

Table 8. Absolute Maximum Ratings¹

Parameter

Maximum Operating Temperature

Supply Voltage, 1.8 V Option

Symbol

Rating

Units

ºC

AMAX

–0.5 to +1.9

–0.5 to +3.8

Supply Voltage, 2.5/3.3 V Option

Input Voltage (any input pin)

–0.5 to V + 0.3

ºC

Storage Temperature

–55 to +125

2500

ESD Sensitivity (HBM, per JESD22-A114)

Soldering Temperature (Pb-free profile)²

Soldering Temperature Time @ T_PEAK(Pb-free profile)²

Notes:

ESD

260

ºC

PEAK

20–40

seconds

1. Stresses beyond those listed in Absolute Maximum Ratings may cause permanent damage to the device. Functional

operation or specification compliance is not implied at these conditions. Exposure to maximum rating conditions for

extended periods may affect device reliability.

2. The device is compliant with JEDEC J-STD-020C. Refer to Si5xx Packaging FAQ available for download at

www.silabs.com/VCXO for further information, including soldering profiles.

Rev. 1.2

Si530/531

2. Pin Descriptions

(Top View)

V_DD

CLK–

CLK+

CLK–

CLK+

GND

CLK

Si531

Si530

LVDS/LVPECL/CML

CMOS

Table 9. Pinout for Si530 Series

LVDS/LVPECL/CML Function

Symbol

OE (CMOS only)*

CMOS Function

Output enable

No connection

0 = clock output disabled (outputs tristated)

1 = clock output enabled

Output enable

(LVPECL,LVDS, 0 = clock output disabled (outputs tristated)

No connection

CML)*

1 = clock output enabled

Electrical and Case Ground

Oscillator Output

GND

Electrical and Case Ground

Oscillator Output

CLK+

CLK–

Complementary Output

Power Supply Voltage

No connection

Power Supply Voltage

*Note: OE includes a 17 k pullup resistor to V_DD

Table 10. Pinout for Si531 Series

Symbol

LVDS/LVPECL/CML Function

Output enable

OE (LVPECL, LVDS, CML)* 0 = clock output disabled (outputs tristated)

1 = clock output enabled

No connection

GND

No connection

Electrical and Case Ground

Oscillator Output

CLK+

CLK–

Complementary output

Power Supply Voltage

*Note: OE includes a 17 k pullup resistor to V_DD

Rev. 1.2

Si530/531

3. Ordering Information

The Si530/531 XO supports a variety of options including frequency, temperature stability, output format, and V

Specific device configurations are programmed into the Si530/531 at time of shipment. Configurations can be

specified using the Part Number Configuration chart below. Silicon Laboratories provides a web browser-based

part number configuration utility to simplify this process. Refer to www.silabs.com/VCXOPartNumber to access this

tool and for further ordering instructions. The Si530 and Si531 XO series are supplied in an industry-standard,

RoHS compliant, 6-pad, 5 x 7 mm package. The Si531 Series supports an alternate OE pinout (pin #1) for the

LVPECL, LVDS, and CML output formats. See Tables 9 and 10 for the pinout differences between the Si530 and

Si531 series.

53x

XXXMXXX

Tape & Reel Packaging

Blank = Trays

530 or 531 XO

Product Family

Operating Temp Range (°C)

-40 to +85°C

1^stOption Code

V_DDOutput Format Output Enable Polarity

Part Revision Letter

Frequency (e.g., 622M080 is 622.080 MHz)

3.3 LVPECL

3.3 LVDS

3.3 CMOS

3.3 CML

High

Low

Available frequency range is 10 to 945 MHz, 970 to 1134 MHz, and

1213 to 1417 MHz. The position of “M” shifts to denote higher or lower

frequencies. If the frequency of interest requires greater than 6 digit

resolution, a six digit code will be assigned for the specific frequency.

2.5 LVPECL

2.5 LVDS

2.5 CMOS

2.5 CML

2^ndOption Code

1.8 CMOS

1.8 CML

Code Temperature Stability (ppm, max, ±) Total Stablility (ppm, max, ±)

61.5

31.5

3.3 LVPECL

3.3 LVDS

3.3 CMOS

3.3 CML

2.5 LVPECL

2.5 LVDS

2.5 CMOS

2.5 CML

1.8 CMOS

1.8 CML

Note:

CMOS available to 160 MHz.

Example P/N: 530AB622M080DGR is a 5 x 7 XO in a 6 pad package. The frequency is 622.080 MHz, with a 3.3 V supply, LVPECL output,

and Output Enable active high polarity. Temperature stability is specifed as ±20 ppm. The part is specified for –40 to +85 °C ambient

temperature range operation and is shipped in tape and reel format.

Figure 1. Part Number Convention

Rev. 1.2

Si530/531

4. Outline Diagram and Suggested Pad Layout

Figure 2 illustrates the package details for the Si530/531. Table 11 lists the values for the dimensions shown in the

illustration.

Figure 2. Si530/531 Outline Diagram

Table 11. Package Diagram Dimensions (mm)

Dimension

Min

1.45

1.2

Nom

1.65

Max

1.85

1.6

1.4

0.60 TYP.

7.00 BSC.

6.2

6.10

6.30

2.54 BSC.

5.00 BSC.

4.40

4.30

1.07

4.50

1.47

1.27

1.815 BSC.

0.7 REF.

—

aaa

bbb

ccc

ddd

—

0.15

0.10

—

Rev. 1.2

Si530/531

5. Si530/Si531 Mark Specification

Figure 3 illustrates the mark specification for the Si530/Si531. Table 12 lists the line information.

Figure 3. Mark Specification

Table 12. Si53x Top Mark Description

Line

Position

Description

1–10

“SiLabs"+ Part Family Number, 53x (First 3 characters in part number where x = 0

indicates a 530 device and x = 1 indicates a 531 device).

1–10

Si530, Si531: Option1 + Option2 + Freq(7) + Temp

Si532, Si533, Si534, Si530/Si531 w/ 8-digit resolution:

Option1 + Option2 + ConfigNum(6) + Temp

Trace Code

Position 1

Pin 1 orientation mark (dot)

Product Revision (D)

Position 2

Tiny Trace Code (4 alphanumeric characters per assembly release instructions)

Year (least significant year digit), to be assigned by assembly site (ex: 2007 = 7)

Calendar Work Week number (1–53), to be assigned by assembly site

“+” to indicate Pb-Free and RoHS-compliant

Position 3–6

Position 7

Position 8–9

Position 10

Rev. 1.2

Si530/531

6. 6-Pin PCB Land Pattern

Figure 4 illustrates the 6-pin PCB land pattern for the Si530/531. Table 13 lists the values for the dimensions shown

in the illustration.

Figure 4. Si530/531 PCB Land Pattern

Table 13. PCB Land Pattern Dimensions (mm)

Dimension

Min

Max

5.08 REF

2.54 BSC

4.15 REF

0.84

2.00

—

8.20 REF

7.30 REF

1.70 TYP

2.15 REF

—

6.78

6.30

Notes:

1. Dimensioning and tolerancing per the ANSI Y14.5M-1994 specification.

2. Land pattern design based on IPC-7351 guidelines.

3. All dimensions shown are at maximum material condition (MMC).

4. Controlling dimension is in millimeters (mm).

Rev. 1.2

Si530/531

Revision 1.1 to Revision 1.2

DOCUMENT CHANGE LIST

Revision 0.4 to Revision 0.5

 Updated 2.5 V/3.3 V and 1.8 V CML output level

specifications for Table 3 on page 3.

 Updated Table 1, “Recommended Operating

 Added footnotes clarifying max offset frequency test

Conditions,” on page 2.

conditions for Table 4 on page 4.

Added maximum supply current specifications.

Specified relationship between temperature at startup

and operation temperature.

 Added CMOS phase jitter specs to Table 4 on

page 4.

 Removed the words "Differential Modes:

LVPECL/LVDS/CML" in the footnote referring to

AN256 in Table 4 on page 4.

 Updated Table 4, “CLK± Output Phase Jitter,” on

page 4 to include maximum rms jitter generation

specifications and updated typical rms jitter

specifications.

 Separated 1.8 V, 2.5 V/3.3 V supply voltage

specifications in Table 8 on page 5.

 Added Table 6, “CLK± Output Phase Noise

 Updated and clarified Table 8 on page 5 to include

the "Moisture Sensitivity Level" and "Contact Pads"

rows.

(Typical),” on page 4.

 Added Output Enable active polarity as an option in

Figure 1, “Part Number Convention,” on page 7.

 Updated Figure 3 on page 9 and Table 12 on page 9

to reflect specific marking information. Previously,

Figure 3 was generic.

Revision 0.5 to Revision 1.0

 Updated Note 3 in Table 1, “Recommended

Operating Conditions,” on page 2.

 Updated Figure 1, “Part Number Convention,” on

page 7.

Revision 1.0 to Revision 1.1

 Updated Table 1, “Recommended Operating

Conditions,” on page 2.

Device maintains stable operation over –40 to +85 ºC

operating temperature range.

Supply current specifications updated for revision D.

 Updated Table 2, “CLK± Output Frequency

Characteristics,” on page 2.

Added specification for ±20 ppm lifetime stability

(±7 ppm temperature stability) XO.

 Updated Table 3, “CLK± Output Levels and

Symmetry,” on page 3.

Updated LVDS differential peak-peak swing

specifications.

 Updated Table 4, “CLK± Output Phase Jitter,” on

page 4.

 Updated Table 5, “CLK± Output Period Jitter,” on

page 4.

Revised period jitter specifications.

 Updated Table 8, “Absolute Maximum Ratings ,” on

page 5 to reflect the soldering temperature time at

260 ºC is 20–40 sec per JEDEC J-STD-020C.

 Updated 3. "Ordering Information" on page 7.

Changed ordering instructions to revision D.

 Added 5. "Si530/Si531 Mark Specification" on page

Rev. 1.2

Si530/531

CONTACT INFORMATION

Silicon Laboratories Inc.

400 West Cesar Chavez

Austin, TX 78701

Tel: 1+(512) 416-8500

Fax: 1+(512) 416-9669

Toll Free: 1+(877) 444-3032

Please visit the Silicon Labs Technical Support web page:

https://www.silabs.com/support/pages/contacttechnicalsupport.aspx

and register to submit a technical support request.

The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice.

Silicon Laboratories assumes no responsibility for errors and omissions, and disclaims responsibility for any consequences resulting from

the use of information included herein. Additionally, Silicon Laboratories assumes no responsibility for the functioning of undescribed features

or parameters. Silicon Laboratories reserves the right to make changes without further notice. Silicon Laboratories makes no warranty, rep-

resentation or guarantee regarding the suitability of its products for any particular purpose, nor does Silicon Laboratories assume any liability

arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation conse-

quential or incidental damages. Silicon Laboratories products are not designed, intended, or authorized for use in applications intended to

support or sustain life, or for any other application in which the failure of the Silicon Laboratories product could create a situation where per-

sonal injury or death may occur. Should Buyer purchase or use Silicon Laboratories products for any such unintended or unauthorized ap-

plication, Buyer shall indemnify and hold Silicon Laboratories harmless against all claims and damages.

Silicon Laboratories and Silicon Labs are trademarks of Silicon Laboratories Inc.

Other products or brandnames mentioned herein are trademarks or registered trademarks of their respective holders

Rev. 1.2

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