SI8902B-A01-GSR
更新时间：2024-09-15 19:01:47
品牌：SILICON
描述：ADC, Successive Approximation, 10-Bit, 1 Func, 3 Channel, Serial Access, CMOS, PDSO16, SOIC-16
概述
规格参数
数据手册
替代型号SI8902B-A01-GSR 概述
ADC, Successive Approximation, 10-Bit, 1 Func, 3 Channel, Serial Access, CMOS, PDSO16, SOIC-16 AD转换器 模数转换器
SI8902B-A01-GSR 规格参数
| 是否Rohs认证： | 符合 | 生命周期： | Active |
| 包装说明： | SOIC-16 | Reach Compliance Code： | compliant |
| HTS代码： | 8542.39.00.01 | 风险等级： | 5.17 |
| 最大模拟输入电压： | 3.6 V | 最小模拟输入电压： | |
| 转换器类型： | ADC, SUCCESSIVE APPROXIMATION | JESD-30 代码： | R-PDSO-G16 |
| 长度： | 10.3 mm | 最大线性误差 (EL)： | 0.0977% |
| 模拟输入通道数量： | 3 | 位数： | 10 |
| 功能数量： | 1 | 端子数量： | 16 |
| 最高工作温度： | 85 °C | 最低工作温度： | -40 °C |
| 输出位码： | BINARY | 输出格式： | SERIAL |
| 封装主体材料： | PLASTIC/EPOXY | 封装代码： | SOP |
| 封装等效代码： | SOP16,.4 | 封装形状： | RECTANGULAR |
| 封装形式： | SMALL OUTLINE | 峰值回流温度（摄氏度）： | NOT SPECIFIED |
| 电源： | 3/3.3,3/5 V | 认证状态： | Not Qualified |
| 座面最大高度： | 2.65 mm | 子类别： | Other Converters |
| 标称供电电压： | 3.3 V | 表面贴装： | YES |
| 技术： | CMOS | 温度等级： | INDUSTRIAL |
| 端子形式： | GULL WING | 端子节距： | 1.27 mm |
| 端子位置： | DUAL | 处于峰值回流温度下的最长时间： | NOT SPECIFIED |
| 宽度： | 7.5 mm | Base Number Matches： | 1 |
SI8902B-A01-GSR 数据手册
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PDF下载Si8900/1/2
ISOLATED MONITORING ADC
Features
ADC
3 input channels
Temperature range:
–40 to +85 °C
10-bit resolution
>60-year life at rated working
2 µs conversion time
Isolated serial I/O port
voltage
CSA component notice 5A
UART (Si8900)
approval
I2C/SMbus (Si8901)
2.5 MHz SPI port (Si8902)
Transient immunity:
45 kV/µs (typ)
IEC 60950, 61010, 60601
VDE/IEC 60747-5-2
UL1577 recognized
Ordering Information:
Up to 5 kVrms for 1 minute
See page 25.
Applications
Pin Assignments
I s o la t e d d a t a a c q u is it io n
AC mains monitor
Solar inverters
Isolated temp/humidity sensing
Switch mode power systems
Telemetry
VDDA
VREF
AIN0
VDDB
NC
Description
NC
AIN1
Rx
Si8900
Si8901
Si8902
The Si8900/1/2 series of isolated monitoring ADCs are useful as linear
signal galvanic isolators, level shifters, and/or ground loop eliminators in
many applications including power-delivery systems and solar inverters.
These devices integrate a 10-bit SAR ADC subsystem, supervisory state
Tx
AIN2
NC
NC
RST
VDDB
GNDB
GNDA
2
machine and isolated UART (Si8900), I C/SMbus port (Si8901), or SPI
Port (Si8902) in a single package. Based on Silicon Labs’ proprietary
CMOS isolation technology, ordering options include a choice of 2.5 or
5 kV isolation ratings. All products are safety certified by UL, CSA, and
VDE. The Si8900/1/2 devices offer a typical common-mode transient
immunity performance of 45 kV/µs for robust performance in noisy and
high-voltage environments. Devices in this family are available in 16-pin
SOIC wide-body packages.
VDDA
VREF
AIN0
VDDB
NC
NC
AIN1
SCL
SDA
NC
AIN2
RST
RSDA
GNDA
VDDB
GNDB
Safety Approval
UL 1577 recognized
U p t o 5 k V r m s f o r 1 m i n u t e
CSA component notice 5A
approval
VDE certification conformity
VDDA
RST
VDDB
NC
IED 60747-5-2 (VDE 0884 Part 2)
NC
SDO
SCLK
SDI
VREF
AIN0
AIN1
AIN2
GNDA
IEC 60950, 61010, 60601
EN
VDDB
GNDB
Rev. 1.1 10/12
Copyright © 2012 by Silicon Laboratories
Si8900/1/2
Si8900/1/2
2
Rev. 1.1
Si8900/1/2
TABLE OF CONTENTS
Section
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Regulatory Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
4. ADC Data Transmission Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
4.1. UART (Si8900) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
2
4.2. I C/SMBus (Si8901) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
4.3. SPI Port (Si8902) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
4.4. Master Controller Firmware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
5. Si8900/1/2 Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
6. Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
6.1. Isolated Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
6.2. Device Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
6.3. Application Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
7. Device Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23
8. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25
9. Package Outline: 16-Pin Wide Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26
10. Land Pattern: 16-Pin Wide-Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28
11. Top Marking: 16-Pin Wide Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
11.1. Si8900/1/2 Top Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
11.2. Top Marking Explanation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32
Rev. 1.1
3
Si8900/1/2
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Symbol
Condition
Min
2.7
—
Typ
—
Max
3.6
Unit
V
Input Side Supply Voltage
Input Side Supply Current
V
With respect to GND1
DDA
DDA
I
V
= 3.3 V, Si890x active
10
13.3
11.4
5.5
mA
DDA
V
= 3.3 V, Si890x idle
—
8.6
—
DDA
Output Side Supply Voltage
Output Side Supply Current
V
With respect to GND2
= 3.3 V to 5.5 V, Si890x active
2.7
—
V
DDB
I
V
4.4
3.3
—
5.8
mA
DDB
DDB
V
= 3.3 V to 5.5 V, Si890x idle
—
3.9
DDB
Operating Temperature
T
–40
+85
°C
A
Table 2. Electrical Specifications
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
ADC
Resolution
R
10
bits
LSB
LSB
Integral Nonlinearity
INL
DNL
VREF = 2.4 V
—
—
±0.5
±0.5
±1
±1
Differential Nonlinearity
VREF = 2.4 V,
Guaranteed Monotonic
Offset Error
OFS
FSE
–2
–2
—
0
0
0
+2
+2
—
LSB
LSB
ppm/°C
V
Full Scale Error
Offset Tempco
T
45
OS
Input Voltage Range
Sampling Capacitance
Input MUX Impedance
V
C
V
REF
IN
—
—
—
5
5
—
pF
IN
R
—
—
k
MUX
Power Supply
Rejection
PSRR
–70
dB
Reference Voltage
V
Default V
= V
0
—
12
2
V
V
REF
REF
DDA
DDA
VREF Supply Current
ADC Conversion Time
I
—
—
µA
µs
VREF
t
CONV
4
Rev. 1.1
Si8900/1/2
Table 2. Electrical Specifications (Continued)
Parameter
Symbol
Test Condition
Min
Typ
Max
Unit
Reset and Undervoltage Lockout
Power-on RESET
Voltage Threshold High
VRSTH
—
1.7
—
—
—
—
1.8
—
1
V
V
Power-on RESET
Voltage Threshold Low
VRSTL
VDDA Power-On Reset Ramp
Time
tRAMP Time from VDDA = 0 V
to VDDA > VRST
ms
Power-On Reset
Delay Time
tPOR
tRAMP < 1 ms
0.3
ms
Output Side UVLO Threshold
UVLO
H
—
—
2.3
—
—
V
Output side UVLO
Hysteresis
100
mV
Digital Inputs
Logic High Level Input Voltage
Logic Low Level Input Voltage
Logic Input Current
V
0.7 x V
—
—
—
—
0.6
+10
—
V
V
IH
DDB
V
IL
I
VIN = 0 V or V
–10
—
µA
pF
IN
DD
Input Capacitance
C
15
IN
Digital Outputs
Logic High Level Output Voltage
V
V
= 5 V,
= –4 mA
V –0.4
DDB
4.8
—
—
—
V
V
V
OH
DDB
I
OH
V
= 3.3 V,
= –4 mA
3.1
—
DDB
I
OH
Logic Low Level Output Voltage
V
V
= 3.3 to 5 V,
= 4 mA
0.2
85
0.4
—
OL
DDB
I
OL
Digital Output Series Impedance
Serial Ports
R
—
OUT
UART Bit Rate
60
—
—
—
234
240
kbps
kbps
2
SMBus/I C Bit Rate
Slave
Address = 1111000x
SPI Port
—
—
2.5
Mbps
Rev. 1.1
5
Si8900/1/2
Table 2. Electrical Specifications (Continued)
Parameter
SPI Port Timing
Symbol
Test Condition
Min
Typ
Max
Unit
EN Falling Edge to SCLK Rising
Edge
t
80
—
—
ns
SE
Last Clock Edge to /EN Rising
EN Falling to SDO Valid
EN Rising to SDO High-Z
SCLK High Time
t
80
—
—
—
—
—
—
—
—
—
160
160
—
ns
ns
ns
ns
ns
ns
ns
SD
t
SEZ
SDZ
CKH
t
—
t
200
200
80
SCLK Low Time
t
—
CKL
SDI Valid to SCLK Sample Edge
t
—
SIS
SCLK Sample Edge to SDI
Change
t
80
—
SIH
SCLK Shift Edge to SDO
Change
t
—
—
160
ns
SOH
EN
tSE
tCKL
tSD
SCLK
tCLKH
tSIS
tSIH
SDI
tSOH
tSEZ
tSDZ
SDO
Figure 1. SPI Port Timing Characteristics
6
Rev. 1.1
Si8900/1/2
Table 3. Thermal Characteristics
Parameter
Symbol
Test Condition
WB SOIC-16 NB SOIC-16
100 105
Unit
IC Junction-to-Air Thermal
Resistance
ºC/W
JA
500
450
370
VDD1, VDD2 = 2.70 V
400
300
200
100
0
VDD1, VDD2 = 3.6 V
220
VDD1, VDD2 = 5.5 V
0
50
100
150
200
Temperature (ºC)
Figure 2. (WB SOIC-16) Thermal Derating Curve, Dependence of Safety Limiting Values
with Case Temperature per DIN EN 60747-5-2
500
430
V
DD1, VDD2 = 2.70 V
400
300
200
100
0
360
VDD1, VDD2 = 3.6 V
210
VDD1, VDD2 = 5.5 V
0
50
100
150
200
Temperature (ºC)
Figure 3. (NB SOIC-16) Thermal Derating Curve, Dependence of Safety Limiting Values
with Case Temperature per DIN EN 60747-5-2
Rev. 1.1
7
Si8900/1/2
Table 4. Absolute Maximum Ratings
Parameter
Storage Temperature
Symbol
Min
–65
–40
–0.5
–0.5
–0.5
—
Typ
—
—
—
—
—
—
—
—
Max
150
Unit
°C
°C
V
T
STG
Ambient Temperature under Bias
Input-Side Supply Voltage
Output-Side Supply Voltage
Input/Output Voltage
T
85
A
V
6.0
DDA
DDB
V
6.0
V
V
VDD +0.5
10
V
I
Output Current Drive
I
mA
°C
O
Lead Solder Temperature (10 s)
Maximum Isolation Voltage
—
260
—
6500
V
RMS
*Note: Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be
restricted to conditions as specified in the operational sections of this data sheet. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
8
Rev. 1.1
Si8900/1/2
2. Regulatory Information
The Si8900/1/2 family is certified by Underwriters Laboratories, CSA International, and VDE. Table 5 summarizes
the certification levels supported.
Table 5. Regulatory Information
CSA
The Si89xx is certified under CSA Component Acceptance Notice 5A. For more details, see File 232873.
61010-1: Up to 600 VRMS reinforced insulation working voltage; up to 600 VRMS basic insulation working voltage.
60950-1: Up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage.
60601-1: Up to 125 VRMS reinforced insulation working voltage; up to 380 VRMS basic insulation working voltage.
VDE
The Si89xx is certified according to IEC 60747-5-2. For more details, see File 5006301-4880-0001.
60747-5-2: Up to 1200 Vpeak for basic insulation working voltage.
60950-1: Up to 600 VRMS reinforced insulation working voltage; up to 1000 VRMS basic insulation working voltage.
UL
The Si89xx is certified under UL1577 component recognition program. For more details, see File E257455.
Rated up to 5000 VRMS isolation voltage for basic protection.
Rev. 1.1
9
Si8900/1/2
3. Functional Description
The Si8900/1/2 (Figure 4) are isolated monitoring ADCs that convert linear input signals into digital format and
transmit the resulting data through an on-chip isolated serial port to an external master processor (typically a
microcontroller). The Si890x access protocol is simple: The master configures and controls the start of ADC
conversion by writing a configuration register (CNFG_0) Command Byte to the Si890x. The master then acquires
ADC conversion data by reading the Si890x serial port. Devices in this series differ only in the type of serial port.
2
Options include a UART with on-chip baud rate generator that operates at 234 kbps max (Si8900), an SMBus/I C
port that operates at 240 kbps max (Si8901), and an SPI Port that operates at 2.5 MHz max (Si8902).
The integrated ADC subsystem consists of a three-channel analog input multiplexer (MUX) followed by a series
gain amplifier (selectable 1x or 0.5x gain) and 10-bit SAR ADC. Serial-port-accessible ADC options allow the user
to select an internal or external voltage reference, set the programmable gain amplifier (PGA), and select the ADC
MUX address. The master can configure the Si890x to return ADC data on-demand (Demand Mode) or
continuously (Burst Mode). For more information, see "CNFG_0 Command Byte" on page 18.
VDDA
VDDB
AIN0
AIN1
Tx
Rx
10‐Bit
ADC
Tx Data
MUX
PGA
UART
AIN2
VREF
VREF
All
Blocks
GNDB
ADC Subsystem
ISOLATION
State Machine/
User Registers
RST
GNDA
Si8900
VDDA
VDDB
AIN0
AIN1
SDA
SCL
SMBus/
I2C
10‐Bit
ADC
Tx Data
MUX
PGA
All
Blocks
AIN2
VREF
GNDB
ADC Subsystem
VREF
RST
ISOLATION
State Machine/
User Registers
RSDA
GNDA
Si8901
VDDA
VDDB
SCK
SDI
AIN0
AIN1
10‐Bit
ADC
Tx Data
MUX
PGA
SPI Port
SDO
EN
AIN2
VREF
VREF
All
Blocks
ADC Subsystem
GND2
ISOLATION
RST
State Machine/
User Registers
GND1
Si8902
Figure 4. Si8900/1/2 Block Diagrams
10
Rev. 1.1
Si8900/1/2
4. ADC Data Transmission Modes
The master can access ADC read-only registers ADC_H and ADC_L using either Demand Mode or Burst Mode. In
Demand Mode (MODE = 1), the master triggers individual A/D conversions “on-demand”. In Burst Mode
(MODE = 0), the Si890x performs ADC conversions continuously.
Master to Slave
Slave to Master
Master writes CNFG_0
Command Byte to Si8900 Rx
CNFG_0
Command
Byte
tCONV
MODE = 1
CNFG_0
Command
ADC_H
ADC_L
Byte
Master reads updated CNFG_0 and ADC
Data From Si8900 (Tx output)
B) Si8900 Demand Mode ADC Read
Master to Slave
Slave to Master
Master writes Slave Address and
CNFG_0 Command Byte to Si8901 SDA
CNFG_0
Command
Slave
Address
Slave Address
Byte
tCONV
CNFG_0
MODE = 1
Command
ADC_H
ADC_L
Byte
Master reads Slave Address, updated CNFG_0
and ADC Data from Si8901 (SDA pin)
C) Si8901 Demand Mode ADC Read
Master writes CNFG_0
Command Byte to Si8902 SDI
Master to Slave
Slave to Master
CNFG_0
Command
Byte
tCONV
MODE = 1
CNFG_0
Command
Byte
ADC_H
ADC_L
The master must wait 8µS
(track‐and‐hold time) before
reading ADC data packet.
Master reads updated CNFG_0 and
ADC Data from Si8902 SDO
D) Si8902 Demand Mode ADC Read
Figure 5. ADC Demand Mode Operation
Referring to Figure 5A, a Demand Mode ADC read is initiated when the master writes a Command Byte to the
Si8900. (The Command Byte is a copy of the CNFG_0 register that has been properly configured by the master.)
Upon receipt of the Command Byte, the Si8900 updates its CNFG_0 register and triggers the start of an ADC
conversion, at which time the master may immediately begin reading ADC conversion data from the Si8900 UART.
The ADC conversion data packet contains a copy of the Command Byte for verification and two-bytes of ADC
conversion data. The Si8901 (Figure 5B) ADC read transaction is identical to that of the Si8900 with the exception
2
of the added I C/SMBus Slave Address byte (Si8901 Slave Address is 0xF0). The Si8902 Demand Mode ADC
read transaction (Figure 5C) is the same as that of the Si8900, except the master must wait 8 µs after the
transmission of the Command Byte before reading the Si8902 SPI port because byte transmission time is two
times shorter versus the Si8900/01.
Rev. 1.1
11
Si8900/1/2
The Burst Mode ADC transactions for the Si8900 (Figure 6A) and Si8901 (Figure 6B) are substantially the same. A
Burst Mode ADC read is initiated when the master writes a CNFG_0 (MODE = 0) Command Byte to the Si8900/1,
which updates the CNFG_0 register and triggers the ADC continuously. Like the Demand Mode example, the
Si8901 has a Slave Address byte prior to the CNFG_0 Command Byte. When using the Si8901, the master must
2
write the I C port address prior to reading the serial port. The Si8902 Burst Mode (Figure 6C) is similar to that of
the Si8900/1, except the master must wait 8 µs before reading the first Burst Mode ADC data packet. After reading
the first Burst Mode ADC data packet, the master may read all ADC data packets that follow without delay.
Master writes CNFG_0
Command Byte to Si8900 Rx
CNFG_0
Command
Byte 0
MODE = 0
Master to Slave
Slave to Master
tCONV
tCONV
CNFG_0
Command
Byte
tCONV
ADC_H
Data
ADC_H
Data
ADC_L
Data
ADC_L
Data
Master reads updated CNFG_0 Command Byte and ADC data from Si8900 Tx
A) Si8900 ADC Burst Mode (MODE = 0)
Master writes Slave Address & CNFG_0
Command Byte to Si8901 SDA
CNFG_0
Command
Byte 0
Slave Addrress
Write
MODE = 0
tCONV
tCONV
tCONV
CNFG_0
Command
Byte
Master to Slave
ADC_H
Data
ADC_H
Data
Slave Address
Read
ADC_L
Data
ADC_L
Data
Slave to Master
Master reads Slave Address, updated CNFG_0 and ADC data from Si8901 SDA
B) Si8901 ADC Burst Mode (MODE = 0)
Master writes CNFG_0 Command
Byte to Si8902 SDI
CNFG_0
Command
Byte
Master to Slave
Slave to Master
tCONV
tCONV
tCONV
MODE = 0
CNFG_0
Command
Byte
ADC_H
Data
ADC_H
Data
ADC_L
Data
ADC_L
Data
Master reads updated CNFG_0 and ADC data from Si8902 SDO
C) Si8902 ADC Burst Mode (MODE = 0)
Figure 6. ADC Burst Mode Operation
12
Rev. 1.1
Si8900/1/2
4.1. UART (Si8900)
The UART is a two-wire interface (Tx, Rx) and operates as an asynchronous, full-duplex serial port with internal
auto baud rate generator that measures the period of incoming data stream and automatically adjusts the internal
baud rate generator to match. The auto baud rate detection and matching optimizes UART timing for minimum bit
error rate. For more information, see “AN635: AC Line Monitoring Using the Si890x Family of Isolated ADCs”.
There are a total of 10 bits per data read/write: One start bit, eight data bits (LSB first), and one stop bit with data
transmitted LSB first as shown in Figure 7. Figure 8A and Figure 8B show master/Si8900 ADC read transactions
for Demand Mode and Burst Mode, respectively.
MARK
SPACE
Start Bit
D5
D6
D7
D2
D4
D0
D1
D3
STOP BIT
BIT TIMES
BIT SAMPLING
Figure 7. UART Data Byte
Master to Slave
Slave to Master
CNFG_0 Write Command Byte
S
‐
1
1
P
D0 D1 D2 D3 D4 D5 D6 D7
ADC Data
S
1
1
P
S
0
1
P
S
0
0 S
‐
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
CNFG_0 Read Data
D0 D1 D2 D3 D4 D5 D6 D7
CNFG_0 Write Command Byte
A) Si8900 Demand Mode ADC Read
S
‐
1
1
P
D0 D1 D2 D3 D4 D5 D6 D7
Periodic ADC Data
1
1
S
P
S
0 1 P S 0
0 P S
0 1 P S 0
0 P S
‐
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
CNFG_0 Read Data
D0 D1 D2 D3 D4 D5 D6 D7
D0 D1 D2 D3 D4 D5 D6 D7
B) Si8900 Burst Mode ADC Read
Figure 8. Si8900 ADC Read Operation
Rev. 1.1
13
Si8900/1/2
2
4.2. I C/SMBus (Si8901)
2
The I C/SMBus serial port is a two-wire serial bus where data line SDA is bidirectional and clock line SCL is
2
unidirectional. Reads and writes to this interface by the master are byte-oriented, with the I C/SMBus master
controlling the serial data rates up to 240 kbps. The SDA and SCL lines must be pulled high through pull-up
resistors of 5 k or less. An Si8901 ADC read transaction begins with a START condition (“S” or Repeated START
condition “SR”), which is defined as a high-to-low transition on SDA while SCL is high (Figure 9). The master
terminates a transmission with a STOP condition (P), defined as a low-to-high transition on SDA while SCL is high.
The data on SDA must remain stable during the high period of the SCL clock pulse because such changes in either
line will be interpreted as a control command (e.g., S, P SR). SDA and SCL idle in the high state when the bus is
not busy. Acknowledge bits (Figure 10) provide detection of successful data transfers, whereas unsuccessful
transfers conclude with a not-acknowledge bit (NACK). Both the master and the Si8901 generate ACK and NACK
bits. An ACK bit is generated when the receiving device pulls SDA low before the rising edge of the acknowledged
related (ninth) SCL pulse and maintains it low during the high period of the clock pulse. A NACK bit is generated
when the receiver allows SDA to be pulled high before the rising edge of the acknowledged related SCL pulse and
maintains it high during the high period of the clock pulse. An unsuccessful data transfer occurs if a receiving
device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master
2
attempts communication at a later time. Figure 11A shows the I C Slave Address Byte and CNFG_0 byte for the
Si8901. Figure 11B and Figure 11C show master/Si8901 ADC read transactions for Demand Mode and Burst
Mode, respectively.
SR
P
S
SDA
SCL
Figure 9. Start and Stop Conditions
Not Acknowledge (NACK)
S
SDA
SCL
Acknowledge (ACK)
9
1
2
Figure 10. Acknowledge Cycle
14
Rev. 1.1
Si8900/1/2
Master to Slave
Slave to Master
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
S
1
1
‐
s6 s5 s4 s3 s2 s1 s0
A
A P
Si8901 CNFG_0 Write Data
Si8901 Slave Address
A) Si8901 CNFG_0 Write
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
S
1
1
‐
s6 s5 s4 s3 s2 s1 s0
A
A
P
Si8901 Write
Slave Address
Si8901 CNFG_0 Write Data
ADC Data
D7 D6 D5 D4 D3 D2 D1 D0
s6 s5 s4 s3 s2 s1 s0
D7 D6 D5 D4 D3 D2 D1 D0
Si8901 Slave Address = 0xF0
S
S
1
1
‐
1
0
0
0
A
A
A P
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Si8901 Read
Slave Address
Si8901 CNFG_0 Read Data
B) Si8901 Demand Mode ADC Read
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
s6 s5 s4 s3 s2 s1 s0
Si8901 Slave Address
S
1
1
‐
A
A P
Si8901 CNFG_0 Write Data
Periodic ADC Data
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
S
S
1
1
‐
1
0
0
0
A
s6 s5 s4 s3 s2 s1 s0
A
A
P
D7 D6 D5 D4 D3 D2 D1 D0
D7 D6 D5 D4 D3 D2 D1 D0
Si8901 Read
Slave Address
Si8901 CNFG_0
Read Data
C) Si8901 Burst Mode ADC Read
Figure 11. Si8901 ADC Read Operation
MASTER
Si8902
MOSI
MISO
SDI
SPI Shift Register
7 6 5 4 3 2 1 0
SPI Shift Register
7 6 5 4 3 2 1 0
SDO
/EN
Receive Buffer
Receive Buffer
Baud Rate
Generator
SCLK
SCLK
EN or Px.y
Figure 12. Master Connection to Si8902
Rev. 1.1
15
Si8900/1/2
4.3. SPI Port (Si8902)
EN
SCLK
SDI
MSB
MSB
Bit 6
Bit 6
Bit 5
Bit 5
Bit 4
Bit 4
Bit 3
Bit 3
Bit 2
Bit 2
Bit 1
Bit 1
Bit 0
Bit 0
SDO
Figure 13. Si8902 Data/Clock Timing
The Serial Peripheral Interface (SPI port) is a slave mode, full-duplex, synchronous, 4-wire serial bus that connects
to the master as shown in Figure 12. The master's clock and data timing must match the Si8902 timing shown
Figure 12 (for more information about clock and data timing, please see the “SPI Port” section of Table 2 on
page 6).
As shown in Figure 13, an SPI bus transaction begins with the master driving EN low and maintaining this state for
the duration of the read transaction(s). The master transmits data from its master-out/slave-in terminal (MOSI) to
the Si8902 serial read/write input terminal (SDI). The Si8902 transmits data to the master from its serial data-out
terminal (SDO) to the master-in/slave-out terminal (MISO), and data transfer ends when the master returns /EN to
the high state. Figure 14A shows the Si8902 CNFG_0 Command Byte format, while Figures 14B and 14C show
Si8902 Demand Mode and Burst Mode ADC reads.
16
Rev. 1.1
Si8900/1/2
D7 D6 D5 D4 D3 D2 D1 D0
Master to Slave
Slave to Master
1
1
‐
CNFG_0 Write
Command Byte
D7 D6 D5 D4 D3 D2 D1 D0
A) Si8902 CNFG_0 Command Byte
1
1
‐
CNFG_0 Write
Command Byte
8µS
Delay
D7 D6 D5 D4 D3 D2 D1 D0
1
1
‐
1
0
0
0
D7 D6 D5 D4 D3 D2 D1 D0
ADC Data
D7 D6 D5 D4 D3 D2 D1 D0
Si8902 CNFG_0 Read Byte
B) Si8902 ADC Demand Mode Read
D7 D6 D5 D4 D3 D2 D1 D0
1
1
‐
CNFG_0 Write
Command Byte
8µS
Delay
D7
1
D0 D7
D0 D7
D0 D7
D0 D7
D0
1
‐
1 0
0
0 1 0
0
0
Si8902 CNFG_0
Read Byte
Periodic ADC Data
C) Si8902 ADC Burst Mode Read
Figure 14. Si8902 ADC Read Operation
4.4. Master Controller Firmware
The user's master controller must include firmware to manage the Si890x Demand and Burst operating modes and
serial port control. In some cases, the master controller may also require a firmware moving average function to
reduce noise. For more information on master controller firmware, see “AN637: Si890x Master Controller
Recommendations”, available for download at www.silabs.com/isolation.
Rev. 1.1
17
Si8900/1/2
5. Si8900/1/2 Configuration Registers
CNFG_0 Command Byte
Bit
D7
1
D6
1
D5
MX1
R/W
1
D4
MX0
R/W
1
D3
VREF
R/W
1
D2
—
D1
MODE
R/W
1
D0
PGA
R/W
1
Name
Type
R/W
1
R/W
1
R/W
1
Default
Bit
7:6
5:4
Name
Function
1,1
Internal use. These bits are always set to 1.
MX1, MX0 ADC MUX Address.
ADC MUX address selection is controlled by MX1, MX0 as follows:
MX1
MX0
Selected ADC MUX Channel
1
1
0
0
1
0
1
0
Not Used
AIN2
AIN1
AIN0
3
VREF
ADC Voltage Reference Source
VDD is selected as the reference voltage when this bit is set to 1. An externally con-
nected voltage reference generator is selected when this bit is reset to 0.
2
1
—
Not used.
MODE
ADC Read Mode
ADC Demand Mode read is enabled when this bit is 1, and Burst Mode is enabled
when this bit is 0. For more information on Demand and Burst mode operation,
please see "ADC Data Transmission Modes" on page 11.
0
PGA
PGA Gain Set
PGA gain is 1 when this bit is set to 1. PGA gain is 0.5 when this bit is reset to 0.
18
Rev. 1.1
Si8900/1/2
ADC_H Byte
Bit
D7
1
D6
0
D5
MX1
R
D4
MX0
R
D3
D9
R
D2
D8
R
D1
D7
R
D0
D6
R
Name
Type
R
R
Default
—
—
—
—
—
—
—
—
Bit
7:6
5:4
Name
Function
1,0
Internal use. These bits are always set to 1,0.
MX1, MX0 ADC MUX Address
ADC input MUX address for the converted data in ADC_H, ADC_L.
3:0
D9: D6
ADC conversion data bits D9:D6
Most significant 4 bits of ADC conversion data.
ADC_L Byte
Bit
D7
0
D6
D5
R
D5
D4
R
D4
D3
R
D3
D2
R
D2
D1
R
D1
D0
R
D0
0
Name
Type
R
R
Default
—
—
—
—
—
—
—
—
Bit
7
Name
0
Function
Internal use. This bit is always set to 0.
6:1
D5:D0
ADC Conversion Data Bits D5:D0
Least significant 6 bits of ADC conversion data.
0
0
Internal use. This bit is always set to 0.
Rev. 1.1
19
Si8900/1/2
6. Applications
6.1. Isolated Outputs
The Si890x serial outputs are internally isolated from the device input side. To ensure safety in the end-user
application, high voltage circuits (i.e., circuits with >30 VAC) must be physically separated from the safety extra-low
voltage circuits (i.e., circuits with <30 VAC) by a certain distance (creepage/clearance). If a component straddles
this isolation barrier, it must meet those creepage/clearance requirements and also provide a sufficiently large
high-voltage breakdown protection rating (commonly referred to as working voltage protection). Tables published in
the component standards (UL1577, IEC60747, CSA 5A) are readily accepted by certification bodies to provide
proof for end-system specifications requirements. Refer to the end-system specification (61010-1, 60950-1, 60601-
1, etc.) requirements before starting any circuit design that uses galvanic isolation. To enhance the robustness of a
design, it is further recommended that the user also include 100 resistors in series with the Si890x inputs and
outputs if the system is excessively noisy. The nominal impedance of an isolated Si890x output channel is
approximately 50 and is a combination of the value of the on-chip series termination resistor and channel
resistance of the output driver FET. When driving loads where transmission line effects are a factor, output pins
should be appropriately terminated with controlled-impedance PCB traces.
The Si890x supply inputs must be bypassed with a parallel combination of 10 µF and 0.1 µF capacitors at VDDA
and VDDB as shown in Figure 15A. The capacitors should be placed as close to the package as possible. The
Si890x uses the VDDA supply as its internal ADC voltage reference by default. A precision external reference can
be installed as shown in Figure 15A and must be bypassed with a parallel combination of 0.1 µF and 4.7 µF
capacitors. (Note that the CNFG_0 VREF bit must be set to 0 when using the external reference.) The Si890x has
an on-chip power on reset circuit (POR) that maintains the device in its reset state until VDDA has stabilized. A
2 k pull-up resistor on RST is strongly recommended to reduce the possibility of external noise coupling into the
reset input. The Si8901 will also require a 5 k pull-up resistor to VDDA on the RSDA input.
2.7 V to 3.6 V
2.5 V to 5.5 V
Board Edge
0.1 µF
0.1 µF
Si890x
10 µF
10 µF
VDDA
VDDB
VDDA
VREF
Si890x
VREF
VDDA
4.7 µF
0.1 µF
5 K
2 K
GNDA
GNDB
RST
RSDA
GNDA
Optional External VREF
8 mm
(min)
GNDB
GNDA
GNDB
Si8901
Only
Board Edge
Keep‐out Area
(No metal in this area)
A
B
Figure 15. Si890x Installation
Figure 15B shows the required PCB ground configuration, where an 8 mm (min) “keep-out area” is provided to
ensure adequate creepage and clearance distances between the two grounds. PCB metal traces cannot be
present or cross through the keep-out area on the PCB top, bottom, or internal layer.
20
Rev. 1.1
Si8900/1/2
6.2. Device Reset
During power-up, the Si890x is held in the reset state by the internal power-on reset signal (POR) until VDDA
settles above VRST. When this condition is met, a delay is initiated that maintains the Si890x in the reset state for
time period tPOR, after which the reset signal is driven high allowing the Si890x to start-up. Note the maximum
allowable VDD ramp time (i.e. time from 0 V to VDDA settled above VRST) is 1 ms. Slower ramp times may cause
the Si890x to be released from reset before VDDA reaches the VRST level.
Figure 16 shows typical VDDA monitor reset timing where the internal reset is driven low (Si890x in reset) when
VDDA falls below VRST (e.g., during a power down or VDDA brownout). The internal reset is released to its high
state when VDDA again settles above VRST. External circuitry can also be used to force a reset event by driving
the external RST input low. A 2 k pull-up resistor on RST is recommended to avoid erroneous reset events from
external noise coupling to the RST input.
VDDA
VRSTH
VRSTL
VDDA(min)
Internal
RESET
tPOR
VDDA
Monitor
Reset
Power‐On Reset
Figure 16. Si890x Power-on and Monitor Reset
Rev. 1.1
21
Si8900/1/2
6.3. Application Example
Figure 17 shows the Si8900 operating as a single-phase ac line voltage and current monitor. The VDDA dc bias
circuit uses a low-cost 3.3 V linear regulator referenced to the neutral (white wire). The ac current is measured on
ADC input AIN0. The ac line voltage is scaled by resistors R17 and R18 and level-shifted by the 1.5 V VREF. AC
line current is measured using differential amplifier U1 connected across shunt resistor R1. Data is transferred to
the external controller or processor via the isolated UART.
Single‐Phase
AC Line
1.5 V
R2
R3
R4
Si8900
R1
AIN0
AIN1
R6
C2
U1
Low Cost
Dual OpAmp
R5
R7
R17
R11
C3
R18
R8
TX
RX
R9
R10
1.5 V
External
Master Controller
C1
R12
D1
U2
3.3 V
LDO
VDDA
GNDA
VDDB
GNDB
R14
C5
C4
R13
Output Side
Bias Supply
1.5 V
R15
Figure 17. AC Line Monitor Application Example
22
Rev. 1.1
Si8900/1/2
7. Device Pin Assignments
VDDA
VREF
AIN0
VDDA
VREF
AIN0
VDDA
RST
VDDB
NC
VDDB
NC
VDDB
NC
NC
NC
NC
SDO
AIN1
VREF
AIN0
AIN1
AIN2
GNDA
AIN1
Rx
SCL
SDA
NC
SCLK
Si8900
Si8901
Si8902
Tx
AIN2
SDI
AIN2
NC
RST
NC
EN
RST
RSDA
GNDA
VDDB
GNDB
VDDB
GNDB
VDDB
GNDB
GNDA
Figure 18. Si8900/1/2 Pinout (16SOW)
Table 6. Si8900/1/2 Pin Assignments
Description
Pin
Si8900 Si8901 Si8902
Pin
Pin
Pin
1
2
VDDA
Input side VDD bias voltage (typically 3.3 V)
VREF
RST Si8900/1: External voltage reference input.
Si8902: Active low reset.
3
4
5
6
7
AIN0
AIN1
AIN2
NC
AIN0
NC Si8900: ADC analog input channel 0.
Si8901: ADC analog input channel 0.
Si8902: No connection
AIN1 VREF Si8900: ADC analog input channel 1.
Si8901: ADC analog input channel 1.
Si8902: External VREF in.
AIN2
AIN0 Si8900: ADC analog input channel 2.
Si8901: ADC analog input channel 2.
Si8902: ADC analog input channel 0.
RST
AIN1 Si8900: No Connection.
Si8901: Active low reset.
Si8902: ADC analog input channel 1.
RST
RSDA AIN2 Si8900: Active low reset.
Si8901: RSDA bias resistor (typically 5 k).
Si8902: ADC analog input channel 2.
8
GNDA
GNDB
VDDB
Input side ground
9
Output side ground
10
11
12
Output side VDD bias voltage (2.7 V to 5.5 V)
EN Si8900/1: No connection. Si8902: SPI Port Enable.
SDI Si8900: UART unidirectional transmit output.
NC
Tx
SDA
2
Si8901: I C Bidirectional data input/output.
Si8902: SPI port Serial data in.
Rev. 1.1
23
Si8900/1/2
Table 6. Si8900/1/2 Pin Assignments (Continued)
Pin
Si8900 Si8901 Si8902
Description
Pin
Pin
Pin
13
Rx
SCL
SCLK Si8900: UART unidirectional receive input.
2
Si8901: I C port unidirectional serial clock input.
Si8902: SPI port unidirectional serial clock input.
14
NC
SDO Si8900/1: No connection.
Si8902: SPI port Serial data out (SDO)
15
16
NC
No connection
VDDB
Si8900/1/2: Output side VDD bias voltage (2.7 V to 5.5 V).
24
Rev. 1.1
Si8900/1/2
8. Ordering Guide
Table 7. Product Ordering Information1,2,3
Part Number (OPN)
Serial Port
Package
Isolation Rating
Temp Range
Si8900B-A01-GS
Si8900D-A01-GS
Si8901B-A01-GS
Si8901D-A01-GS
Si8902B-A01-GS
Si8902D-A01-GS
Notes:
UART
UART
WB SOIC
WB SOIC
WB SOIC
WB SOIC
WB SOIC
WB SOIC
2.5 kV
5.0 kV
2.5 kV
5.0 kV
2.5 kV
5.0 kV
–40 to +85 °C
–40 to +85 °C
–40 to +85 °C
–40 to +85 °C
–40 to +85 °C
–40 to +85 °C
2
I C/SMBus
2
I C/SMBus
SPI Port
SPI Port
1. Add an “R” suffix to the part number to specify the tape and reel option. Example: “Si8900AB-A-ISR”.
2. All packages are RoHS-compliant.
3. Moisture sensitivity level is MSL3 for wide-body SOIC-16 package with peak reflow temperatures of 260 °C according
to the JEDEC industry standard classifications and peak solder temperatures.
Rev. 1.1
25
Si8900/1/2
9. Package Outline: 16-Pin Wide Body SOIC
Figure 19 illustrates the package details for the Si8900/1/2 Digital Isolator. Table 8 lists the values for the
dimensions shown in the illustration.
Figure 19. 16-Pin Wide Body SOIC
26
Rev. 1.1
Si8900/1/2
Table 8. Package Diagram Dimensions
Millimeters
Symbol
Min
—
Max
A
A1
A2
b
2.65
0.30
—
0.10
2.05
0.31
0.20
0.51
0.33
c
D
10.30 BSC
10.30 BSC
7.50 BSC
1.27 BSC
E
E1
e
L
0.40
0.25
0°
1.27
0.75
8°
h
θ
aaa
bbb
ccc
ddd
eee
fff
—
0.10
0.33
0.10
0.25
0.10
0.20
—
—
—
—
—
Notes:
1. All dimensions shown are in millimeters (mm) unless otherwise
noted.
2. Dimensioning and Tolerancing per ANSI Y14.5M-1994.
3. This drawing conforms to JEDEC Outline MS-013, Variation AA.
4. Recommended reflow profile per JEDEC J-STD-020C specification
for small body, lead-free components.
Rev. 1.1
27
Si8900/1/2
10. Land Pattern: 16-Pin Wide-Body SOIC
Figure 20 illustrates the recommended land pattern details for the Si8900/1/2 in a 16-pin wide-body SOIC. Table 9
lists the values for the dimensions shown in the illustration.
Figure 20. 16-Pin SOIC Land Pattern
Table 9. 16-Pin Wide Body SOIC Land Pattern Dimensions
Dimension
Feature
Pad Column Spacing
Pad Row Pitch
Pad Width
(mm)
9.40
1.27
0.60
1.90
C1
E
X1
Y1
Pad Length
Notes:
1. This Land Pattern Design is based on IPC-7351 pattern SOIC127P1032X265-16AN
for Density Level B (Median Land Protrusion).
2. All feature sizes shown are at Maximum Material Condition (MMC) and a card
fabrication tolerance of 0.05 mm is assumed.
28
Rev. 1.1
Si8900/1/2
11. Top Marking: 16-Pin Wide Body SOIC
11.1. Si8900/1/2 Top Marking
Si890XY
YYWWRTTTTT
e4
TW
11.2. Top Marking Explanation
Si890 = Isolator product series
X = Serial Port
Base Part Number
0 = UART
1 = I C
Ordering Options
2
Line 1 Marking:
2 = SPI
Y = Insulation rating
(See Ordering Guide for more
information).
B = 2.5 kV; D = 5.0 kV
YY = Year
WW = Workweek
Assigned by assembly subcontractor. Corresponds to the
year and workweek of the mold date.
Line 2 Marking:
Line 3 Marking:
Manufacturing code from assembly house
“R” indicates revision
RTTTTT = Mfg Code
Circle = 1.7 mm Diameter
(Center-Justified)
“e4” Pb-Free Symbol
TW = Taiwan
Country of Origin ISO Code
Abbreviation
Rev. 1.1
29
Si8900/1/2
DOCUMENT CHANGE LIST
Revision 0.5 to Revision 1.0
No changes.
Revision 1.0 to Revision 1.1
Removed “pending” throughout.
Changed AN638 reference to AN637.
Updated "Top Marking: 16-Pin Wide Body SOIC" on
page 29.
30
Rev. 1.1
Si8900/1/2
NOTES:
Rev. 1.1
31
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thereof, "the world’s most energy friendly microcontrollers", Ember®, EZLink®, EZMac®, EZRadio®, EZRadioPRO®, DSPLL®, ISOmodem ®, Precision32®, ProSLIC®, SiPHY®,
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SI8902B-A01-GSR 替代型号
| 型号 | 制造商 | 描述 | 替代类型 | 文档 |
| Si8902B-A01-GS | SILICON | ISOLATED MONITORING ADC | 完全替代 |
|
| SI8900B-A01-GS | SILICON | ADC, Successive Approximation, 10-Bit, 1 Func, 3 Channel, Serial Access, CMOS, PDSO16, SOI | 完全替代 |
|
SI8902B-A01-GSR 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| Si8902D-A01-GS | SILICON | ISOLATED MONITORING ADC | 获取价格 |
|
| SI8902D-A01-GSR | SILICON | ADC, Successive Approximation, 10-Bit, 1 Func, 3 Channel, Serial Access, CMOS, PDSO16, SOIC-16 | 获取价格 |
|
| SI8902EDB | VISHAY | Bi-Directional N-Channel 20-V (D-S) MOSFET | 获取价格 |
|
| SI8902EDB-T1 | VISHAY | TRANSISTOR 2 CHANNEL, N-CHANNEL, Si, SMALL SIGNAL, MOSFET, MICRO FOOT, CSP-6, FET General Purpose Small Signal | 获取价格 |
|
| SI8902EDB-T2-E1 | VISHAY | Bi-Directional N-Channel 20-V (D-S) MOSFET | 获取价格 |
|
| SI8902EDB_06 | VISHAY | Bi-Directional N-Channel 20-V (D-S) MOSFET | 获取价格 |
|
| SI8902EDB_08 | VISHAY | Bi-Directional N-Channel 20-V (D-S) MOSFET | 获取价格 |
|
| SI8904EDB | VISHAY | Bi-Directional N-Channel 30-V (D-S) MOSFET | 获取价格 |
|
| SI8904EDB-T2-E1 | VISHAY | Small Signal Field-Effect Transistor, N-Channel, Metal-oxide Semiconductor FET | 获取价格 |
|
| SI8904EDB-T2-E3 | VISHAY | TRANSISTOR 2 CHANNEL, N-CHANNEL, Si, SMALL SIGNAL, MOSFET, 2 X 3 MM, MICRO FOOT, CSP-6, FET General Purpose Small Signal | 获取价格 |
|
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