E-L6258EA
更新时间：2025-01-13 05:55:35
描述：PWM controlled high current DMOS universal motor driver
概述
规格参数
数据手册E-L6258EA 概述
PWM controlled high current DMOS universal motor driver PWM控制大电流DMOS通用电机驱动器 运动控制电子器件
E-L6258EA 规格参数
| 生命周期： | Active | 零件包装代码： | SSOP |
| 包装说明： | ROHS COMPLIANT, SSOP-36 | 针数： | 36 |
| Reach Compliance Code： | not_compliant | ECCN代码： | EAR99 |
| HTS代码： | 8542.39.00.01 | Factory Lead Time： | 16 weeks |
| 风险等级： | 2.15 | 模拟集成电路 - 其他类型： | STEPPER MOTOR CONTROLLER |
| JESD-30 代码： | R-PDSO-G36 | JESD-609代码： | e3 |
| 长度： | 15.9 mm | 湿度敏感等级： | 3 |
| 功能数量： | 1 | 端子数量： | 36 |
| 最高工作温度： | 125 °C | 最低工作温度： | -40 °C |
| 最大输出电流： | 2 A | 封装主体材料： | PLASTIC/EPOXY |
| 封装代码： | HSSOP | 封装等效代码： | SSOP36,.56 |
| 封装形状： | RECTANGULAR | 封装形式： | SMALL OUTLINE, HEAT SINK/SLUG, SHRINK PITCH |
| 峰值回流温度（摄氏度）： | 245 | 电源： | 5,40 V |
| 认证状态： | Not Qualified | 座面最大高度： | 3.6 mm |
| 子类别： | Motion Control Electronics | 最大供电电压 (Vsup)： | 5.25 V |
| 最小供电电压 (Vsup)： | 4.75 V | 标称供电电压 (Vsup)： | 5 V |
| 表面贴装： | YES | 技术： | BCDMOS |
| 温度等级： | AUTOMOTIVE | 端子面层： | Matte Tin (Sn) - annealed |
| 端子形式： | GULL WING | 端子节距： | 0.65 mm |
| 端子位置： | DUAL | 处于峰值回流温度下的最长时间： | 30 |
| 宽度： | 11 mm | Base Number Matches： | 1 |
E-L6258EA 数据手册
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PDF下载L6258EA
PWM controlled
high current DMOS universal motor driver
Features
■ Able to drive both windings of a bipolar stepper
motor or two DC motors
■ Output current up to 1.5A each winding
■ Wide voltage range: 12V to 40V
■ Four quadrant current control, ideal for
microstepping and dc motor control
■ Precision PWM control
PowerSO36
■ No need for recirculation diodes
■ TTL/CMOS compatible inputs
■ Cross conduction protection
■ Thermal shutdow
The power stage is a dual DMOS full bridge
capable of sustaining up to 40V, and includes the
diodes for current recirculation.The output current
capability is 1.5A per winding in continuous mode,
with peak start-up current up to 2A. A thermal
protection circuitry disables the outputs if the chip
temperature exceeds the safe limits.
■ Extended low operating temperature range:
-40°C
Description
L6258EA is a dual full bridge for motor control
applications realized in BCD technology, with the
capability of driving both windings of a bipolar
stepper motor or bidirectionally control two DC
motors.
L6258EA and a few external components form a
complete control and drive circuit. It has high
efficiency phase shift chopping that allows a very
low current ripple at the lowest current control
levels, and makes this device ideal for steppers as
well as for DC motors.
Table 1.
Device summary
Order code
Package
PowerSO36
Packing
E-L6258EA
Tube
December 2007
Rev 5
1/32
www.st.com
1
Contents
L6258EA
Contents
1
2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1
2.2
2.3
2.4
2.5
2.6
2.7
Reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Input logic (I0 - I1 - I2 - I3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Phase input ( PH ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Triangular generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Charge pump circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Current control loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Current control loop compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3
4
PWM current control loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.1
3.2
3.3
3.4
3.5
Open loop transfer function analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Power amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Load attenuation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Error amplifier and sense amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Effect of the Bemf on the current control loop stability . . . . . . . . . . . . . . . 22
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
4.1
4.2
4.3
Interference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Motor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Notes on PCB design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
5
6
7
Operation mode time diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
2/32
L6258EA
List of tables
List of tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Device summary. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Absolute maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Current levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Charge pump capacitor's values. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3/32
List of figures
L6258EA
List of figures
Figure 1.
Figure 2.
Figure 3.
Figure 4.
Figure 5.
Figure 6.
Figure 7.
Figure 8.
Figure 9.
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin connection (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Power bridge configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Current control loop block diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Output comparator waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Ax bode plot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Aloop bode plot (uncompensated) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Aloop bode plot (compensated) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure 10. Electrical model of the load. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure 11. Typical application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure 12. Full step operation mode timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 13. Half step operation mode timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 14. 4 bit microstep operation mode timing diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 15. PowerSO36 mechanical data & package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
4/32
L6258EA
1
Block diagram
Block diagram
Figure 1.
Block diagram
R1 1M
RC1
CC1
CBOOT
VS
CP
VCP2
EA_IN1
EA_OUT1
VBOOT
TRI_0
+
VCP1
OUT1A
CHARGE
PUMP
C
ERROR
AMP
-
POWER
BRIDGE
1
VR
+
-
VREF1
I3_1
+
-
OUT1B
INPUT
&
TRI_180
C
SENSE1B
SENSE
AMP
I2_1
DAC
VR GEN
DAC
Rs
I1_1
I0_1
PH_1
SENSE1A
DISABLE
THERMAL
PROT.
VDD(5V)
VR (VDD/2)
VS
VREF1
I3_2
ERROR
AMP
TRI_0
VR
+
-
OUT2A
INPUT
&
SENSE
AMP
+
-
C
C
I2_2
POWER
BRIDGE
2
I1_2
+
-
OUT2B
I0_2
SENSE2B
PH_2
TRI_180
Rs
TRI_CAP
CFREF
TRI_0
TRIANGLE
GENERATOR
TRI_180
SENSE2A
GND
EA_IN2
EA_OUT2
D96IN430D
RC2
CC2
R2 1M
Table 2.
Parameter
Vs
Absolute maximum rating
Description
Value
Unit
Supply voltage
45
7
V
V
VDD
Vref1/Vref2
IO
Logic supply voltage
Reference voltage
2.5
2
V
Output current (peak)(1)
Output current (continuous)
Logic input voltage range
Bootstrap supply
A
IO
1.5
A
Vin
-0.3 to 7
60
V
Vboot
Vboot - Vs
Tj
V
Maximum Vgate applicable
Junction temperature
Storage temperature range
15
V
150
°C
°C
Tstg
-55 to 150
1. This current is intended as not repetitive current for max. 1 second.
5/32
Block diagram
Figure 2.
L6258EA
Pin connection (top view)
PWR_GND
1
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
PWR_GND
SENSE1
OUT1B
I3_1
2
PH_1
I1_1
3
4
I0_1
5
I2_1
OUT1A
DISABLE
TRI_CAP
VDD
6
VS
7
EA_OUT1
EA_IN1
VREF1
8
9
GND
10
11
12
13
14
15
16
17
18
SIG_GND
VREF2
VCP1
VCP2
VBOOT
VS
EA_IN2
EA_OUT2
I2_2
OUT2A
I0_2
I3_2
OUT2B
SENSE2
PWR_GND
I1_2
PH_2
PWR_GND
D96IN432F
Table 3.
Pin #
Pin functions
Name
Description
Ground connection (1). They also conduct heat from die to
printed circuit copper.
1, 36
2, 17
PWR_GND
PH_1, PH_2
These TTL compatible logic inputs set the direction of
current flow through the load. A high level causes current to
flow from OUTPUT A to OUTPUT B.
Logic input of the internal DAC (1). The output voltage of the
DAC is a percentage of the Vref voltage applied according to
the thruth Table 5 on page 12.
3
I1_1
4
5
I0_1
See pin 3
OUT1A
Bridge output connection (1)
Disables the bridges for additional safety during switching.
When not connected the bridges are enabled
6
7
DISABLE
TRI_cap
Triangular wave generation circuit capacitor. The value of
this capacitor defines the output switching frequency
6/32
L6258EA
Block diagram
Table 3.
Pin #
Pin functions (continued)
Name
Description
8
VDD (5V)
GND
Supply voltage input for logic circuitry
9
Power ground connection of the internal charge pump circuit
Charge pump oscillator output
10
11
12
VCP1
VCP2
Input for external charge pump capacitor
VBOOT
Overvoltage input for driving of the upper DMOS
Supply voltage input for output stage. They are shorted
internally
13, 31
14
VS
OUT2A
Bridge output connection (2)
Logic input of the internal DAC (2). The output voltage of the
DAC is a percentage of the VRef voltage applied according
to the truth Table 5 on page 12.
15
I0_2
16
I1_2
See pin 15
Ground connection. They also conduct heat from die to
printed circuit copper
18, 19
20, 35
21
PWR_GND
SENSE2, SENSE1 Negative input of the transconductance input amplifier (2, 1)
Bridge output connection and positive input of the
tranconductance (2)
OUT2B
22
23
24
25
I3_2
I2_2
See pin 15
See pin 15
EA_OUT_2
EA_IN_2
Error amplifier output (2)
Negative input of error amplifier (2)
Reference voltages for the internal DACs, determining the
output current value. Output current also depends on the
logic inputs of the DAC and on the sensing resistor value
26, 28
VREF2, VREF1
27
29
30
32
33
SIG_GND
EA_IN_1
EA_OUT_1
I2_1
Signal ground connection
Negative input of error amplifier (1)
Error amplifier output (1)
See pin 3
I3_1
See pin 3
Bridge output connection and positive input of the
tranconductance (1)
34
OUT1B
Note:
The number in parenthesis shows the relevant Power Bridge of the circuit. Pins 18, 19, 1
and 36 are connected together.
7/32
Block diagram
Figure 3.
L6258EA
Thermal characteristics
Power Dissipated T Ambient Thermal J-A resistance
Conditions
(W)
(˚C)
(˚C/W)
5.3
70
15
pad layout + ground layers + 16 via hol
PCB ref.: 4 LAYER cm 12 x 12
4.0
2.3
70
70
20
35
pad layout + ground layers
PCB ref.: 4 LAYER cm 12 x 12
pad layout + 6cm2 on board heat sink
PCB ref.: 2 LAYER cm 12 x 12
D02IN1370
12
10
8
15˚C/W
20˚C/W
35˚C/W
6
4
2
0
-40
-20
0
20
40
60
80
100
120
140
160
D04IN1525A
Ambient Temperature (˚C)
Table 4.
Electrical characteristics
(V = 40V; V = 5V; T = 25°; unless otherwise specified.)
S
DD
j
Parameter
Description
Test condition
Min.
Typ.
Max. Unit
VS
Supply voltage
12
40
V
V
V
VDD
Logic supply voltage
Storage voltage
4.75
VS+6
5.25
VBOOT
VS = 12 to 40V
VS+12
Max drop across sense
resistor
VSense
1.25
V
VS(off)
VDD(off)
IS(on)
IS(off)
IDD
Power off reset
Off threshold
Off threshold
6
7.2
4.1
15
7
V
Power off reset
3.3
V
VS quiescent current
VS quiescent current
VDD operative current
Both bridges ON, no load
Both bridges OFF
mA
mA
mA
15
8/32
L6258EA
Block diagram
Max. Unit
Table 4.
Electrical characteristics (continued)
(V = 40V; V = 5V; T = 25°; unless otherwise specified.)
S
DD
j
Parameter
Description
Test condition
Min.
Typ.
ΔTSD-H Shut down hysteresis
25
°C
°C
TSD
Thermal shutdown
150
Triangular oscillator
frequency(1)
fosc
CFREF = 1nF
12.5
15
18.5 KHz
TRANSISTORS
IDSS
Rds(on)
Vf
Leakage current
OFF State
ON state
If =1.0A
500
0.75
1.4
μA
W
V
On resistance
0.6
1
Flywheel diode voltage
CONTROL LOGIC
Vin(H)
Vin(L)
Iin
lnput voltage
All Inputs
All inputs
2
0
VDD
0.8
V
V
Input voltage
Input current (2)
-150
-10
0
+10
μA
μA
V
0 < Vin < 5V
Idis
Disable pin input current
Reference voltage
Vref terminal input current
+150
(3)
Vref1 ref2
/
Operating
Vref = 1.25
Iref
-2
5
μA
FI =
PWM loop transfer ratio
DAC full scale precision
2
V
/V
ref sense
VFS
Vref = 2.5V I0/I1/I2/I3 = L
1.23
-30
1.34
+30
V
Vref = 2.5V I0/I1/I2/I3 = H
mV
Voffset
Current loop offset
Vref = 2V I0/I1/I2/I3 = H;
Tj = -40 to 125°C
-60
-2
+60
+2
mV
%
Normalized @ full scale
value
DAC factor ratio
SENSE AMPLIFIER
lnput common mode
Vcm
-0.7
VS+0.7
0
V
voltage range
Iinp
Input bias
sense1/sense2
Open loop
-200
μA
ERROR AMPLIFIER
GV
SR
Open loop voltage gain
70
0.2
400
dB
Output slew rate
V/μs
kHz
GBW
Gain bandwidth product
1. Chopping frequency is twice fosc value.
2. This is true for all the logic inputs except the disable input.
3. If Tj is inside the range -40 to -10°C then Vref max is 2V+0.5V·(Tj + 40°C)/30°C. If Tj is greater than -10°C
then Vref max is 2.5V.
9/32
Functional description
L6258EA
2
Functional description
The circuit is intended to drive both windings of a bipolar stepper motor or two DC motors.
The current control is generated through a switch mode regulation.
With this system the direction and the amplitude of the load current are depending on the
relation of phase and duty cycle between the two outputs of the current control loop.
The L6258EA power stage is composed by power DMOS in bridge configuration as it is
shown in Figure 4, where the bridge outputs OUT_A and OUT_B are driven to V with an
s
high level at the inputs IN_A and IN_B while are driven to ground with a low level at the
same inputs.
The zero current condition is obtained by driving the two half bridge using signals IN_A and
IN_B with the same phase and 50% of duty cycle.
In this case the outputs of the two half bridges are continuously switched between power
supply (V ) and ground, but keeping the differential voltage across the load equal to zero.
s
In Figure 4 is shown the timing diagram of the two outputs and the load current for this
working condition.
Following we consider positive the current flowing into the load with a direction from OUT_A
to OUT_B, while we consider negative the current flowing into load with a direction from
OUT_B to OUT_A.
Now just increasing the duty cycle of the IN_A signal and decreasing the duty cycle of IN_B
signal we drive positive current into the load.
In this way the two outputs are not in phase, and the current can flow into the load trough the
diagonal bridge formed by T1 and T4 when the output OUT_A is driven to V and the output
s
OUT_B is driven to ground, while there will be a current recirculation into the higher side of
the bridge, through T1 and T2, when both the outputs are at Vs and a current recirculation
into the lower side of the bridge, through T3 and T4, when both the outputs are connected to
ground.
Since the voltage applied to the load for recirculation is low, the resulting current discharge
time constant is higher than the current charging time constant during the period in which
the current flows into the load through the diagonal bridge formed by T1 and T4. In this way
the load current will be positive with an average amplitude depending on the difference in
duty cycle of the two driving signals.
In Figure 4 is shown the timing diagram in the case of positive load current
On the contrary, if we want to drive negative current into the load is necessary to decrease
the duty cycle of the IN_A signal and increase the duty cycle of the IN_B signal. In this way
we obtain a phase shift between the two outputs such to have current flowing into the
diagonal bridge formed by T2 and T3 when the output OUT_A is driven to ground and
output OUT_B is driven to Vs, while we will have the same current recirculation conditions of
the previous case when both the outputs are driven to Vs or to ground.
So, in this case the load current will be negative with an average amplitude always
depending by the difference in duty cycle of the two driving signals.
In Figure 4 is shown the timing diagram in the case of negative load current.
Figure 5 shows the device block diagram of the complete current control loop.
10/32
L6258EA
Functional description
2.1
Reference voltage
The voltage applied to VREF pin is the reference for the internal DAC and, together with the
sense resistor value, defines the maximum current into the motor winding according to the
following relation:
V
0,5 ⋅ V
1
FI
REF
REF
----- -------------
I
= ----------------------------- =
⋅
MAX
R
R
S
S
where R = sense resistor value
s
Figure 4.
Power bridge configuration
VS
IN_A
IN_B
T1
T2
OUT_B
LOAD
OUT_A
T3
T4
OUTA
OUTB
Iload
Fig. 1A
Fig. 1B
Fig. 1C
0
OUTA
OUTB
Iload
0
OUTA
OUTB
0
Iload
D97IN624
11/32
Functional description
L6258EA
Figure 5.
Current control loop block diagram
POWER AMPL.
VS
OUTA
LOAD
RL
-
Tri_0
INPUT TRANSCONDUCTANCE
AMPL.
+
ERROR AMPL.
VR
LL
VS
+
-
ia
VREF
I0
RS
-
ic
+
+
Tri_180
I1
DAC
VDAC
-
I2
OUTB
Rc
Cc
I3
PH
ib
Gin=1/Ra
-
VSENSE
+
D97IN625
Gs=1/Rb
SENSE TRANSCONDUCTANCE
AMPL.
2.2
Input logic (I0 - I1 - I2 - I3)
The current level in the motor winding is selected according to this table:
Table 5.
I3
Current levels
I2
Current level
% of IMAX
I1
I0
H
H
H
H
H
H
H
H
L
H
H
H
H
L
H
H
L
H
L
No Current
9.5
H
L
19.1
L
28.6
H
H
L
H
L
38.1
L
47.6
L
H
L
55.6
L
L
63.5
H
H
H
H
H
L
H
L
71.4
L
77.8
L
H
82.5
12/32
L6258EA
Functional description
Table 5.
I3
Current levels (continued)
Current level
% of IMAX
I2
I1
I0
L
L
L
L
L
H
L
L
L
L
L
H
H
L
L
H
L
88.9
92.1
95.2
98.4
100
H
L
L
2.3
2.4
Phase input ( PH )
The logic level applied to this input determines the direction of the current flowing in the
winding of the motor.
High level on the phase input causes the motor current flowing from OUT_A to OUT_B
through the load.
Triangular generator
This circuit generates the two triangular waves TRI_0 and TRI_180 internally used to
generate the duty cycle variation of the signals driving the output stage in bridge
configuration.
The frequency of the triangular wave defines the switching frequency of the output, and can
be adjusted by changing the capacitor connected at TR1_CAP pin:
K
C
F
= ---
ref
-5
where: K = 1.5 x 10
2.5
Charge pump circuit
To ensure the correct driving of the high side drivers a voltage higher than Vs is supplied on
the Vboot pin. This boostrap voltage is not needed for the low side power DMOS transistors
because their sources terminals are grounded. To produce this voltage a charge pump
method is used. It is made by using two external capacitors; one connected to the internal
oscillator (CP) and the other (Cboot) to storage the overvoltage needed for the driving the
gates of the high side DMOS. The value suggested for the capacitors are:
Table 6.
Charge pump capacitor's values
Component name
Component's function
Value
Unit
Cboot
CP
Storage capacitor
Pump capacitor
100
10
nF
nF
13/32
Functional description
L6258EA
2.6
Current control loop
The current control loop is a transconductance amplifier working in PWM mode.
The motor current is a function of the programmed DAC voltage.
To keep under control the output current, the current control modulates the duty cycle of the
two outputs OUT_A and OUT_B, and a sensing resistor Rs is connected in series with the
motor winding in order to produce a voltage feedback compared with the programmed
voltage of the DAC.
The duty cycle modulation of the two outputs is generated comparing the voltage at the
outputs of the error amplifier, with the two triangular wave references.
In order to drive the output bridge with the duty cycle modulation explained before, the
signals driving each output (OUTA & OUTB) are generated by the use of the two
comparators having as reference two triangular wave signals Tri_0 and Tri_180 of the same
amplitude, the same average value (in our case Vr), but with a 180° of phase shift each
other.
The two triangular wave references are respectively applied to the inverting input of the first
comparator and to the non inverting input of the second comparator.
The other two inputs of the comparators are connected together to the error amplifier output
voltage resulting by the difference between the programmed DAC. The reset of the
comparison between the mentioned signals is shown in Figure 6.
Figure 6.
Output comparator waveforms
Tri_0
Error Ampl.
Output
Tri_180
First Comp.
Output
Second Comp.
Output
In the case of V
equal to zero, the transconductance loop is balanced at the value of Vr,
DAC
so the outputs of the two comparators are signals having the same phase and 50% of duty
cycle.
As we have already mentioned, in this situation, the two outputs OUT_A and OUT_B are
simultaneously driven from V to ground; and the differential voltage across the load in this
s
case is zero and no current flows in the motor winding.
14/32
L6258EA
Functional description
With a positive differential voltage on V
positively unbalanced respected Vr.
(see Figure 5, the transconductance loop will be
DAC
In this case being the error amplifier output voltage greater than Vr, the output of the first
comparator is a square wave with a duty cycle higher than 50%, while the output of the
second comparator is a square wave with a duty cycle lower than 50%.
The variation in duty cycle obtained at the outputs of the two comparators is the same, but
one is positive and the other is negative with respect to the 50% level.
The two driving signals, generated in this case, drive the two outputs in such a way to have
switched current flowing from OUT_A through the motor winding to OUT_B.
With a negative differential voltage V
unbalanced respected Vr.
, the transconductance loop will be negatively
DAC
In this case the output of the first comparator is a square wave with a duty cycle lower than
50%, while the output of the second comparator is a square wave with a duty cycle higher
than 50%.
The variation in the duty cycle obtained at the outputs of the two comparators is always of
the same.
The two driving signals, generated in this case, drive the the two outputs in order to have the
switched current flowing from OUT_B through the motor winding to OUT_A.
2.7
Current control loop compensation
In order to have a flexible system able to drive motors with different electrical characteristics,
the non inverting input and the output of the error amplifier ( EA_OUT ) are available.
Connecting at these pins an external RC compensation network it is possible to adjust the
gain and the bandwidth of the current control loop.
15/32
PWM current control loop
L6258EA
3
PWM current control loop
3.1
Open loop transfer function analysis
Block diagram: refer to Figure 5.
Input parameters:
●
●
●
●
●
●
●
●
●
●
●
●
V = 24V
S
L = 12mH
L
R = 12Ω
L
R = 0.33Ω
S
R = to be calculated
C
C = to be calculated
C
Gs transconductance gain = 1/Rb
Gin transconductance gain = 1/Ra
Ampl. of the Tria_0_180 ref. = 1.6V (peak to peak)
R = 40KΩ
a
R = 20KΩ
b
V = Internal reference equal to V /2 (Typ. 2.5V)
r
DD
these data refer to a typical application, and will be used as an example during the analysis
of the stability of the current control loop.
The block diagram shows the schematics of the L6258 internal current control loop working
in PWM mode; the current into the load is a function of the input control voltage V
the relation between the two variables is given by the following formula:
, and
DAC
I
· R · G = V
· G
DAC in
LOAD
S
S
1
1
-------
-------
I
⋅ R
⋅
= V
⋅
LOAD
DAC
S
R
R
b
a
R
V
b
DAC
----------------------
--------------
I
= V
⋅
= 0,5 ⋅
(A)
LOAD
DAC
R ⋅ R
R
S
a
s
where:
V
is the control voltage defining the load current value
DAC
G
G
is the gain of the input transconductance amplifier ( 1/Ra )
is the gain of the sense transconductance amplifier ( 1/Rb )
in
s
R
is the resistor connected in series to the output to sense the load current
s
In this configuration the input voltage is compared with the feedback voltage coming from
the sense resistor, then the difference between this two signals is amplified by the error
amplifier in order to have an error signal controlling the duty cycle of the output stage
keeping the load current under control.
It is clear that to have a good performance of the current control loop, the error amplifier
must have an high DC gain and a large bandwidth.
16/32
L6258EA
PWM current control loop
Gain and bandwidth must be chosen depending on many parameters of the application, like
the characteristics of the load, power supply etc..., and most important is the stability of the
system that must always be guaranteed.
To have a very flexible system and to have the possibility to adapt the system to any
application, the error amplifier must be compensated using an RC network connected
between the output and the negative input of the same.
For the evaluation of the stability of the system, we have to consider the open loop gain of
the current control loop:
Aloop = ACerr · ACpw · ACload · ACsense
where AC... is the gain of the blocks that refers to the error, power and sense amplifier plus
the attenuation of the load block.
The same formula in dB can be written in this way:
Aloop = ACerr + ACpw + ACload + ACsense
dB
dB
dB
dB
dB
So now we can start to analyse the dynamic characteristics of each single block, with
particular attention to the error amplifier.
3.2
Power amplifier
The power amplifier is not a linear amplifier, but is a circuit driving in PWM mode the output
stage in full bridge configuration.
The output duty cycle variation is given by the comparison between the voltage of the error
amplifier and two triangular wave references Tri_0 and Tri_180. Because all the current
control loop is referred to the Vr reference, the result is that when the output voltage of the
error amplifier is equal to the Vr voltage the two output Out_A and Out_B have the same
phase and duty cycle at 50%; increasing the output voltage of the error amplifier above the
Vr voltage, the duty cycle of the Out_A increases and the duty cycle of the Out_B decreases
of the same percentage; on the contrary decreasing the voltage of the error amplifier below
the Vr voltage, the duty cycle of the Out_A decreases and the duty cycle of the Out_B
increases of the same percentage.
The gain of this block is defined by the amplitude of the two triangular wave references;
more precisely the gain of the power amplifier block is a reversed proportion of the
amplitude of the two references.
In fact a variation of the error amplifier output voltage produces a larger variation in duty
cycle of the two outputs Out_A and Out_B in case of low amplitude of the two triangular
wave references.
The duty cycle has the max value of 100% when the input voltage is equal to the amplitude
of the two triangular references.
The transfer function of this block consist in the relation between the output duty cycle and
the amplitude of the triangular references.
Vout = 2 · V · (0.5 - DutyCycle)
S
ΔV
2 ⋅ V
out
S
----------------
ACpw
= 20 ⋅ log
= ------------------------------------------------------
Triangular Amplitude
dB
ΔV
in
17/32
PWM current control loop
L6258EA
2 ⋅ 24
----------------
= 29,5dB
ACpw
= 20 ⋅ log
dB
1,6
Moreover, having the two references Tri_0 and Tri_180 a triangular shape it is clear that the
transfer function of this block is a linear constant gain without poles and zeros.
3.3
Load attenuation
The load block is composed by the equivalent circuit of the motor winding (resistance and
inductance) plus the sense resistor.
We will considered the effect of the Bemf voltage of the motor in the next chapter.
The input of this block is the PWM voltage of the power amplifier and as output we have the
voltage across the sense resistor produced by the current flowing into the motor winding.
The relation between the two variable is:
V
out
----------------------
V
=
⋅ R
sense
S
R + R
L
S
so the gain of this block is:
V
R
sense
S
ACload = --------------------- = ----------------------
v
R + R
out
L
S
R
S
----------------------
ACload
= 20 ⋅ log
dB
R + R
L
S
0,33
12 + 0,33
------------------------
Aload
= 20 ⋅ log
= –31,4dB
dB
where:
R = equivalent resistance of the motor winding
L
R = sense resistor
S
Because of the inductance of the motor L , the load has a pole at the frequency:
L
1
Fpole = -----------------------------------
L
L
--------------------
2π ⋅
R + R
L
S
1
Fpole = ---------------------------------------------- = 163Hz
–3
12 ⋅ 10
--------------------------
6,28 ⋅
12 + 0,33
18/32
L6258EA
PWM current control loop
Before analysing the error amplifier block and the sense transconductance block, we have to
do this consideration:
Aloop = Ax + Bx
dB
dB
dB
Ax| = ACpw| + ACload|
dB
dB
dB
and
Bx| = ACerr| + ACsense|
dB
dB
dB
this means that Ax|dB is the sum of the power amplifier and load blocks;
Ax| = (29,5) + (-31.4) = -1.9dB
dB
The BODE analysis of the transfer function of Ax is:
Figure 7.
Ax bode plot
The Bode plot of the Ax|dB function shows a DC gain of -1.9dB and a pole at 163Hz.
It is clear now that (because of the negative gain of the Ax function), Bx function must have
an high DC gain in order to increment the total open loop gain increasing the bandwidth too.
3.4
Error amplifier and sense amplifier
As explained before the gain of these two blocks is:
Bx = ACerr + ACsense
dB
dB
dB
Being the voltage across the sense resistor the input of the Bx block and the error amplifier
voltage the output of the same, the voltage gain is given by:
1
Rb
-------
ib = Vsense ⋅ Gs = Vsense ⋅
19/32
PWM current control loop
L6258EA
1
Zc
------
Verr_out = -(ic · Zc) so ic = -(Verr_out ·
)
because ib = icwe have:
1
Rb
1
Zc
-------
------
Vsense ·
= -(Verr_out ·
)
Verr_out
Vsense Rb
Zc
Bx = –----------------------- = –-------
In the case of no external RC network is used to compensate the error amplifier, the typical
open loop transfer function of the error plus the sense amplifier is something with a gain
around 80dB and a unity gain bandwidth at 400kHz. In this case the situation of the total
transfer function Aloop, given by the sum of the Ax and Bx is:
dB
dB
Figure 8.
Aloop bode plot (uncompensated)
The BODE diagram shows together the error amplifier open loop transfer function, the Ax
function and the resultant total Aloop given by the following equation:
Aloop = AxdB + Bx
dB
dB
The total Aloop has an high DC gain of 78.1dB with a bandwidth of 15KHz, but the problem
in this case is the stability of the system; in fact the total Aloop cross the zero dB axis with a
slope of -40dB/decade.
Now it is necessary to compensate the error amplifier in order to obtain a total Aloop with an
high DC gain and a large bandwidth. Aloop must have enough phase margin to guarantee
the stability of the system.
A method to reach the stability of the system, using the RC network showed in the block
diagram, is to cancel the load pole with the zero given by the compensation of the error
amplifier.
The transfer function of the Bx block with the compensation on the error amplifier is:
20/32
L6258EA
PWM current control loop
1
------------------------------
Rc – j
Zc
Rb
2π ⋅ f ⋅ Cc
Bx = –------- = –---------------------------------------------
Rb
In this case the Bx block has a DC gain equal to the open loop and equal to zero at a
frequency given by the following formula:
1
Fzero = ------------------------------------
2π ⋅ Rc ⋅ Cc
In order to cancel the pole of the load, the zero of the Bx block must be located at the same
frequency of 163Hz; so now we have to find a compromise between the resistor and the
capacitor of the compensation network.
Considering that the resistor value defines the gain of the Bx block at the zero frequency, it
is clear that this parameter will influence the total bandwidth of the system because,
annulling the load pole with the error amplifier zero, the slope of the total transfer function is
-20dB/decade.
So the resistor value must be chosen in order to have an error amplifier gain enough to
guarantee a desired total bandwidth.
In our example we fix at 35dB the gain of the Bx block at zero frequency, so from the
formula:
Rc
Rb
-------
= 20 ⋅ log
Bx_gain
@ zero freq.
where: Rb = 20kΩ
we have: Rc = 1.1MΩ
Therefore we have the zero with a 163Hz the capacitor value:
1
1
Cc = --------------------------------------------- = ---------------------------------------------------------------- = 880pF
2π ⋅ Fzero ⋅ Rc –6
6,28 ⋅ 163 ⋅ 1,1 ⋅ 10
Now we have to analyse how the new Aloop transfer function with a compensation network
on the error amplifier is.
The following bode diagram shows:
–
–
–
the Ax function showing the position of the load pole
the open loop transfer function of the Bx block
the transfer function of the Bx with the RC compensation network on the error
amplifier
–
the total Aloop transfer function that is the sum of the Ax function plus the transfer
function of the compensated Bx block.
21/32
PWM current control loop
Figure 9. Aloop bode plot (compensated)
L6258EA
We can see that the effect of the load pole is cancelled by the zero of the Bx block ; the total
Aloop cross a the 0dB axis with a slope of -20dB/decade, having in this way a stable system
with an high gain at low frequency and a bandwidth of around 8KHz.
To increase the bandwidth of the system, we should increase the gain of the Bx block,
keeping the zero in the same position. In this way the result is a shift of the total Aloop
transfer function up to a greater value.
3.5
Effect of the Bemf on the current control loop stability
In order to evaluate what is the effect of the Bemf voltage of the stepper motor we have to
look at the load block:
22/32
L6258EA
PWM current control loop
Figure 10. Electrical model of the load
OUT+
Bemf
R
L
L
L
to Sense
Amplifier
R
S
OUT-
The schematic now shows the equivalent circuit of the stepper motor including a sine wave
voltage generator of the Bemf. The Bemf voltage of the motor is not constant, its value
changes depending on the speed of the motor.
Increasing the motor speed the Bemf voltage increases:
Bemf = Kt · ω
where:
Kt is the motor constant
ωis the motor speed in radiant per second
The formula defining the gain of the load considering the Bemf of the stepper motor
becomes:
R
S
----------------------
(V – Bemf) ⋅
S
R + R
Vsense
Vout
L
S
ACload = --------------------- = ---------------------------------------------------------------
V
S
V
– Bemf
R
S
S
---------------------------- ----------------------
Acload =
⋅
V
R + R
S
L
S
V
– Bemf
R
⎛
⎜
⎝
⎞
⎟
⎠
S
S
---------------------------- ----------------------
ACload
= 20 ⋅ log
⋅
dB
V
R + R
S
L
S
we can see that the Bemf influences only the gain of the load block and does not introduce
any other additional pole or zero, so from the stability point of view the effect of the Bemf of
the motor is not critical because the phase margin remains the same.
Practically the only effect of the Bemf is to limit the gain of the total Aloop with a consequent
variation of the bandwidth of the system.
23/32
Application information
L6258EA
4
Application information
A typical application circuit is shown in Figure 11.
Note:
For avoid current spikes on falling edge of DISABLE a "DC feedback" would be added to the
ERROR Amplifier. (R1-R2 on Figure 11).
4.1
Interference
Due to the fact that the circuit operates with switch mode current regulation, to reduce the
effect of the wiring inductance a good capacitor (100nF) can be placed on the board near
the package, between the power supply line (pin 13,31) and the power ground (pin
1,36,18,19) to absorb the small amount of inductive energy.
It should be noted that this capacitor is usually required in addition to an electrolytic
capacitor, that has poor performance at the high frequencies, always located near the
package, between power supply voltage (pin 13,31) and power ground (pin 1,36,18,19), just
to have a current recirculation path during the fast current decay or during the phase
change.
The range value of this capacitor is between few µF and 100µF, and it must be chosen
depending on application parameters like the motor inductance and load current amplitude.
A decoupling capacitor of 100nF is suggested also between the logic supply and ground.
The EA_IN1 and EA_IN2 pins carry out high impedance lines and care must be taken to
avoid coupled noise on this signals. The suggestion is to put the components connected to
this pins close to the L6258, to surround them with ground tracks and to keep as far as
possible fast switching outputs of the device. Remember also an 1 Mohm resistor between
EA_INx and EA_OUTx to avoid output current spike during supply startup/shutdown.
A non inductive resistor is the best way to implement the sensing. Whether this is not
possible, some metal film resistor of the same value can be paralleled.
The two inputs for the sensing of the winding motor current (SENSE_A & SENSE_B) should
be connected directly on the sensing resistor Rs terminals, and the path lead between the
Rs and the two sensing inputs should be as short as possible.
Note:
Connect the DISABLE pin to a low impedance (< 300 Ω ) voltage source to reduce at
minimum the interference on the output current due to capacitive coupling of OUT1A (pin5)
and DISABLE (pin 6).
24/32
L6258EA
Application information
Figure 11. Typical application circuit
0.33
VCP1
10
21
20
OUT2B
10nF
VCP2
11
SENSE2
STEPPER
MOTOR
VBOOT
12
M
OUT2A
100nF
VS
14
35
34
5
12mH 10Ω
VS
13,31
7
SENSE1
TRI_CAP
0.33
1nF
OUT1B
OUT1A
GND
L6258EA
PH1
I0_1
2
9
SOP36
PACKAGE
4
I1_1
3
I2_1
PWR_GND
1,36
18,19
32
33
17
15
16
23
22
I3_1
PH2
VDD
8
VDD(5V)
VREF
I0_2
SIG_GND
I1_2
27
I2_2
I3_2
28
26
24
VREF1
VREF2
DISABLE
6
29
30
25
EA_IN1
EA_OUT1
1M
EA_IN2
EA_OUT2
1M
820pF
820pF
D97IN626E
R1 1M
R2 1M
4.2
Motor selection
Some stepper motor have such high core losses that they are not suitable for switch mode
current regulation. Furthermore, some stepper motors are not designed for continuous
operating at maximum current. Since the circuit can drive a constant current through the
motor, its temperature might exceed, both at low and high speed operation.
25/32
Application information
L6258EA
4.3
Notes on PCB design
We recommend to observe the following layout rules to avoid application problems with
ground and anomalous recirculation current.
The by-pass capacitors for the power and logic supply must be kept as near as possible to
the IC.
It's important to separate on the PCB board the logic and power grounds and the internal
charge pump circuit ground avoiding that ground traces of the logic signals cross the ground
traces of the power signals.
Because the IC uses the board as a heat sink, the dissipating copper area must be sized in
accordance with the required value of R
.
thj-amb
26/32
L6258EA
Operation mode time diagrams
5
Operation mode time diagrams
Figure 12. Full step operation mode timing diagram
(Phase - DAC input and motor current)
Position
0
1
2
3
0
1
2
3
0
FULL Step Vector
5V
Phase
1
Ph1
0
5V
1
0
Phase
2
0
5V
I0_1
Ph2
Ph2
0
5V
I1_1
I2_1
I3_1
I0_2
I1_2
I2_2
I3_2
0
DAC 1
Inputs
2
3
5V
0
Ph1
5V
0
Current
level% of IMAX
I3
I2
I1
I0
5V
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
100
98.4
DAC 2
Inputs
5V
95.2
0
5V
92.1
88.9
0
0
0
82.5
77.8
71.4
95.2%
19.1%
63.5
Motor drive
Current 1
55.6
47.6
95.2%
19.1%
38.1
Motor drive
Current 2
28.6
0
19.1
D97IN629A
9.5
No Current
27/32
Operation mode time diagrams
L6258EA
Figure 13. Half step operation mode timing diagram
(Phase - DAC input and motor current)
0
1
2
3
4
5
6
7
5V
0
Phase 1
Phase 2
5V
0
Half Step Vector
Ph1
2
5V
0
I0_1
5V
0
3
1
DAC 1
Inputs
I1_1
I2_1
I3_1
5V
0
5V
0
Ph2
4
0 Ph2
5V
0
I0_2
I1_2
I2_2
I3_2
5V
0
DAC 2
Inputs
5
7
5V
0
6
5V
0
Ph1
100%
71.4%
Current
level% of IMAX
I3
I2
I1
I0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
100
98.4
0
95.2
Motor drive
Current 1
92.1
88.9
-71.4%
-100%
100%
82.5
77.8
71.4
71.4%
63.5
55.6
47.6
Motor drive
Current 2
38.1
0
28.6
19.1
9.5
-71.4%
-100%
No Current
D97IN627C
28/32
L6258EA
Operation mode time diagrams
Figure 14. 4 bit microstep operation mode timing diagram
(Phase - DAC input and motor current)
Position
0
4
8 12 16 20 24 28 32 36 40 44 48 52 56 60 64
Micro Step Vector
5V
Ph1
16
0
Phase
1
5V
24
8
0
Phase
5V
2
I0_1
I1_1
I2_1
I3_1
I0_2
I1_2
I2_2
I3_2
Ph2 32
0 Ph2
0
5V
0
DAC 1
Inputs
40
56
5V
48
0
Ph1
5V
0
5V
0
DAC 2
Inputs
Current
level% of IMAX
I3
I2
I1
I0
5V
0
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
100
98.4
5V
95.2
0
92.1
88.9
0
82.5
100%
95.2%
82.5%
63.5%
47.6%
38.1%
77.8
71.4
Motor drive
Current 1
19.1%
63.5
0
0%
55.6
47.6
38.1
28.6
19.1
Motor drive
Current 2
9.5
0
No Current
D97IN628A
29/32
Package information
L6258EA
6
Package information
In order to meet environmental requirements, ST offers these devices in ECOPACK®
packages. These packages have a Lead-free second level interconnect. The category of
second Level Interconnect is marked on the package and on the inner box label, in
compliance with JEDEC Standard JESD97. The maximum ratings related to soldering
conditions are also marked on the inner box label.
ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
Figure 15. PowerSO36 mechanical data & package dimensions
mm
inch
DIM.
MIN.
TYP. MAX. MIN.
3.60
TYP. MAX.
0.1417
0.0118
0.1299
0.0039
0.0150
0.0126
0.6299
0.3858
0.5709
0.4370
0.1142
0.2441
0.0256
0.4350
0.0039
0.6260
0.0433
0.0433
OUTLINE AND
MECHANICAL DATA
A
a1
a2
a3
b
0.10
0.30 0.0039
3.30
0
0.10
0.22
0.23
15.80
9.40
13.90
10.90
0.38 0.0087
0.32 0.0091
16.00 0.6220
9.80 0.3701
14.5 0.5472
11.10 0.4291
2.90
c
D
D1
E
E1
E2
E3
e
5.80
6.20 0.2283
0.65
e3
G
11.05
0
0.10
H
15.50
15.90 0.6102
1.10
h
L
0.8
1.10 0.0315
10˚ (max)
8˚ (max)
N
s
PowerSO-36
Note: “D and E1” do not include mold flash or protusions.
- Mold flash or protusions shall not exceed 0.15mm (0.006”)
- Critical dimensions are "a3", "E" and "G".
0096119 C
30/32
L6258EA
Revision history
7
Revision history
Table 7.
Date
Document revision history
Revision
Changes
11-May-2004
29-Jun-2004
1
2
First Issue
Updated the table 1: Order Codes
Changed on the page 5 the fosc parameter max. value from 17.5 to
18.5kHz
24-Sep-2004
23-Mar-2005
3
4
Add. note at the bottom of Table 2: Absolute maximum rating.
Document reformatted.
03-Dec-2007
5
Modified the ACpw formula in Section 3.2 on page 17.
Added the disable note in Section 4.1 on page 24.
31/32
L6258EA
Please Read Carefully:
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32/32
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