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BQ25505RGRR

更新时间：2025-01-16 12:52:17
品牌：TI
描述：Ultra Low Power Boost Charger with Battery Management and Autonomous Power Multiplexor

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BQ25505RGRR 概述

Ultra Low Power Boost Charger with Battery Management and Autonomous Power Multiplexor 超低功耗升压充电器与电池管理和自治权力多路复用器 电池管理芯片 电源管理电路

BQ25505RGRR 规格参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active包装说明：HVQCCN,
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01Factory Lead Time：6 weeks
风险等级：1.64模拟集成电路 - 其他类型：BATTERY CHARGE CONTROLLER
控制技术：PULSE FREQUENCY MODULATION最大输入电压：5.1 V
最小输入电压：0.1 VJESD-30 代码：S-PQCC-N20
JESD-609代码：e4长度：3.5 mm
湿度敏感等级：2功能数量：1
端子数量：20最高工作温度：125 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：HVQCCN封装形状：SQUARE
封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度（摄氏度）：260
座面最大高度：0.9 mm表面贴装：YES
切换器配置：BOOST最大切换频率：1000 kHz
温度等级：AUTOMOTIVE端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：NO LEAD端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：3.5 mmBase Number Matches：1

BQ25505RGRR 数据手册

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bq25505  
www.ti.com  
SLUSBJ3B –AUGUST 2013–REVISED JANUARY 2014  
Ultra Low Power Boost Charger with Battery Management and Autonomous Power  
Multiplexor for Primary Battery in Energy Harvester Applications  
Check for Samples: bq25505  
1
FEATURES  
•
Ultra Low Power With High Efficiency DC/DC  
Boost Charger  
–
Integrated MPPT for optimal energy  
extraction from a variety of energy  
harvesters  
–
–
Cold-Start Voltage: VIN ≥ 330 mV  
•
Gate Drivers for Primary (Non-rechargeable)  
and Secondary (rechargeable) Storage  
Element Multiplexing  
Continuous Energy Harvesting From Input  
Sources as low as 100 mV  
–
–
Ultra Low Quiescent Current of 325 nA  
–
–
Autonomous switching based on VBAT_OK  
Input Voltage Regulation Prevents  
Break-before-make prevents system rail  
droop  
Collapsing High Impedance Input Sources  
–
Ship Mode with < 5 nA From Battery  
•
Energy Storage  
APPLICATIONS  
–
Energy can be Stored to Re-Chargeable Li-  
ion Batteries, Thin-film Batteries, Super-  
Capacitors, or Conventional Capacitors  
•
•
•
•
•
•
•
•
•
•
Energy Harvesting  
Solar Charger  
Thermal Electric Generator (TEG) Harvesting  
Wireless Sensor Networks (WSN)  
Industrial Monitoring  
•
•
Battery Charging and Protection  
–
–
Internally Set Undervoltage Level  
User Programmable Overvoltage Level  
Environmental Monitoring  
Battery Good Output Flag  
Bridge and Structural Health Monitoring (SHM)  
Smart Building Controls  
–
–
Programmable Threshold and Hysteresis  
Warn Attached Microcontrollers of Pending  
Loss of Power  
Portable and Wearable Health Devices  
Entertainment System Remote Controls  
–
Can be Used to Enable/Disable System  
Loads  
•
Programmable Maximum Power Point Tracking  
(MPPT)  
DESCRIPTION  
The bq25505 is the first of a new family of intelligent integrated energy harvesting Nano-Power management  
solutions that are well suited for meeting the special needs of ultra low power applications. The product is  
specifically designed to efficiently acquire and manage the microwatts (µW) to miliwatts (mW) of power  
generated from a variety of DC sources like photovoltaic (solar) or thermal electric generators (TEGs). The  
bq25505 is a highly efficient boost charger targeted toward products and systems, such as wireless sensor  
networks (WSN) which have stringent power and operational demands. The design of the bq25505 starts with a  
DCDC boost charger that requires only microwatts of power to begin operating.  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
PRODUCTION DATA information is current as of publication date.  
Copyright © 2013–2014, Texas Instruments Incorporated  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
 
 
bq25505  
SLUSBJ3B –AUGUST 2013–REVISED JANUARY 2014  
www.ti.com  
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam  
during storage or handling to prevent electrostatic damage to the MOS gates.  
DESCRIPTION (CONTINUED)  
Once started, the boost charger can effectively extract power from low voltage output harvesters such as TEGs  
or single or dual cell solar panels. The boost charger can be started with VIN as low as 330 mV, and once  
started, can continue to harvest energy down to VIN = 100 mV.  
The bq25505 implements a programmable maximum power point tracking (MPPT) sampling network to optimize  
the transfer of power into the device. Sampling of the VIN_DC open circuit voltage is programmed using external  
resistors, and that sample voltage is held with an external capacitor. For example solar cells that operate at  
maximum power point (MPP) of 80% of their open circuit voltage, the resistor divider can be set to 80% of the  
VIN_DC voltage and the network will control the VIN_DC to operate near that sampled reference voltage.  
Alternatively, an external reference voltage can be provide by a MCU to produce a more complex MPPT  
algorithm.  
The bq25505 was designed with the flexibility to support a variety of energy storage elements. The availability of  
the sources from which harvesters extract their energy can often be sporadic or time-varying. Systems will  
typically need some type of energy storage element, such as a re-chargeable battery, super capacitor, or  
conventional capacitor. The storage element will make certain constant power is available when needed for the  
systems. The storage element also allows the system to handle any peak currents that can not directly come  
from the input source. To prevent damage to the storage element, both maximum and minimum voltages are  
monitored against the internally programmed undervoltage (UV) and user programmable overvoltage (OV) levels.  
To further assist users in the strict management of their energy budgets, the bq25505 toggles the battery good  
flag to signal an attached microprocessor when the voltage on an energy storage battery or capacitor has  
dropped below a pre-set critical level. This should trigger the shedding of load currents to prevent the system  
from entering an undervoltage condition. The OV and battery good thresholds are programmed independently.  
In addition to the boost charging front end, bq25505 provides the system with an autonomous power multiplexor  
gate drive. The gate drivers allow two storage elements to be multiplexed autonomously in order to provide a  
single power rail to the system load. This multiplexor is based off the VBAT_OK threshold which is resistor  
programmable by the user. This allows the user to set the level when the system is powered by the energy  
harvester storage element, e.g. rechargable battery or super capacitor or a primary non-rechargeable battery  
(e.g. two AA batteries). This type of hybrid system architecture allows for the run-time of a typical battery  
powered systems to be extended based on the amount of energy available from the harvester. If there is not  
sufficient energy to run the system due to extended "dark time", the primary battery is autonomously switched to  
the main system rail within 8 µsec in order to provide uninterrupted operation.  
All the capabilities of bq25505 are packed into a small foot-print 20-lead 3.5 mm x 3.5 mm QFN package.  
2
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bq25505  
www.ti.com  
SLUSBJ3B –AUGUST 2013–REVISED JANUARY 2014  
TYPICAL APPLICATION SCHEMATIC  
CSTOR  
CBYP  
+
SEC_BAT  
(rechargeable)  
VSTOR  
VBAT_SEC  
VOC_SAMP  
L1  
VBAT_PRI  
LBOOST  
TPS62736  
Ideal Diode OR  
+
VREF_SAMP  
PRI_BAT  
Boost  
Controller  
CIN  
+
VBAT_OK  
Solar  
Cell  
CREF  
System  
Load  
VB_PRI_ON  
-
VSS  
MPPT  
VB_SEC_ON  
VIN_DC  
Cold Start  
Nano-Power  
Management  
VSTOR  
VBAT_SEC  
Host  
GPIO1  
GPIO2  
EN  
VBAT_OK  
bq25505  
ROV2  
ROV1  
ROK3  
ROK2  
ROK1  
For Ordering Information, see the Package Option Addendum at the end of the data sheet.  
Copyright © 2013–2014, Texas Instruments Incorporated  
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bq25505  
SLUSBJ3B –AUGUST 2013–REVISED JANUARY 2014  
www.ti.com  
ABSOLUTE MAXIMUM RATINGS(1)  
over operating free-air temperature range (unless otherwise noted)  
VALUE  
MIN  
UNIT  
MAX  
VIN_DC, VOC_SAMP, VREF_SAMP, VBAT_OV, VB_PRI_ON,  
Input voltage  
VB_SEC_ON, VBAT_PRI, VBAT_SEC, VRDIV, OK_HYST, OK_PROG,  
–0.3  
5.5  
V
VBAT_OK, VSTOR, LBST(2)  
Peak Input Power, PIN_PK  
510  
125  
150  
mW  
°C  
Operating junction temperature range, TJ  
Storage temperature range, TSTG  
–40  
–65  
°C  
(1) Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings  
only and functional operation of the device at these or any other conditions beyond those indicated under “recommended operating  
conditions” is not implied. Exposure to absolute–maximum–rated conditions for extended periods may affect device reliability.  
(2) All voltage values are with respect to VSS/ground terminal.  
THERMAL INFORMATION  
bq25505  
THERMAL METRIC(1)(2)  
UNITS  
RGR (20 PINS)  
θJA  
Junction-to-ambient thermal resistance  
34.6  
49.0  
12.5  
0.5  
θJCtop  
θJB  
Junction-to-case (top) thermal resistance  
Junction-to-board thermal resistance  
°C/W  
ψJT  
Junction-to-top characterization parameter  
Junction-to-board characterization parameter  
Junction-to-case (bottom) thermal resistance  
ψJB  
12.6  
1.0  
θJCbot  
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.  
(2) For thermal estimates of this device based on PCB copper area, see the TI PCB Thermal Calculator.  
spacing  
RECOMMENDED OPERATING CONDITIONS  
MIN NOM  
MAX  
5.1  
UNIT  
V
VIN(DC)  
DC input voltage into VIN_DC(1)  
Battery voltage range(2)  
0.1  
2
VBAT_SEC,  
VBAT_PRI  
5.5  
V
CIN  
Input capacitance  
4.7  
4.7  
µF  
µF  
CSTOR  
Storage capacitance  
CBAT  
Battery pin capacitance or equivalent battery capacity  
Sampled reference storage capacitance  
Total resistance for setting for MPPT reference.  
Total resistance for setting the VBAT_OK threshold voltage.  
Total resistance for setting VBAT_OV threshold voltage.  
Input inductance  
100  
µF  
CREF  
9
18  
10  
20  
13  
13  
11  
22  
15  
15  
nF  
ROC1 + ROC2  
MΩ  
MΩ  
MΩ  
µH  
°C  
ROK 1 + ROK 2 + ROK3  
11  
ROV1 + ROV2  
11  
L1  
TA  
TJ  
22  
Operating free air ambient temperature  
Operating junction temperature  
–40  
–40  
85  
105  
°C  
(1) Maximum input power ≤ 400 mW. Cold start has been completed  
(2) VBAT_OV setting must be higher than VIN_DC  
4
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bq25505  
www.ti.com  
SLUSBJ3B –AUGUST 2013–REVISED JANUARY 2014  
ELECTRICAL CHARACTERISTICS  
Over recommended temperature range, typical values are at TA = 25°C. Unless otherwise noted, specifications apply for  
conditions of VSTOR = 4.2 V. External components, CIN = 4.7 µF, L1 = 22 µH, CSTOR= 4.7 µF  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX UNIT  
BOOST CHARGER  
VIN(DC)  
DC input voltage into VIN_DC  
Cold-start completed  
100  
5100  
285  
mV  
mA  
I-CHG(CBC_LIM)  
Cycle-by-cycle current limit of charger  
0.5V < VIN < 4.0 V; VSTOR = 4.2  
V
230  
PIN  
Input power range for normal charging  
VBAT_OV > VSTOR >  
VSTOR_CHGEN  
0.005  
1.6  
510  
400  
1.9  
mW  
mV  
V
VIN(CS)  
Minimum input voltage for cold start circuit to  
start charging VSTOR  
VBAT_SEC < VBAT_UV; VSTOR  
= 0 V; 0°C < TA < 85°C  
330  
1.73  
5
VSTOR_CHGEN  
PIN(CS)  
Voltage on VSTOR when cold start operation  
ends and normal charger operation commences  
Minimum cold-start input power for VSTOR to  
reach VSTOR(CHGEN) and allow normal charging  
to commence  
VSTOR < VSTOR(CHGEN)  
µW  
tBAT_HOT_PLUG  
Time for which switch between VSTOR and  
VBAT_SEC closes when battery is hot plugged  
into VBAT_SEC  
Battery resistance = 300 Ω,  
Battery voltage = 3.3V  
50  
325  
1
ms  
nA  
QUIESCENT and LEAKAGE CURRENTS  
IQ  
EN = GND - Full operating mode  
VIN_DC = 0V; VSTOR = 2.1V; TJ  
= 25°C  
400  
700  
5
VIN_DC = 0V; VSTOR = 2.1V;  
–40°C < TJ < 85°C  
EN = VBAT_SEC - Ship mode  
EN = VBAT_SEC - Ship mode  
VBAT_SEC = VBAT_PRI = 2.1 V;  
TJ = 25°C; VSTOR = VIN_DC = 0  
V
VBAT_SEC = VBAT_PRI = 2.1 V;  
–40°C < TJ < 85°C; VSTOR =  
VIN_DC = 0 V  
20  
5
I-BATPRI(LEAK)  
VBAT_PRI = VBAT_SEC = 2.1 V;  
TJ = 25°C; VIN_DC = 0 V; VSTOR  
floating  
1
nA  
nA  
VBAT_PRI = VBAT_SEC = 2.1 V;  
–40°C < TJ < 85°C; VIN_DC = 0 V;  
VSTOR floating  
20  
MOSFET RESISTANCES  
RDS(ON)-BAT  
ON resistance of switch between VBAT_SEC and VBAT_SEC = 4.2 V  
VSTOR  
0.95  
1.50  
Ω
RDS(ON)_CHG  
Charger low side switch ON resistance  
Charger high side switch ON resistance  
Charger low side switch ON resistance  
Charger high side switch ON resistance  
Maximum charger switching frequency  
VBAT_SEC = 4.2 V  
0.70  
2.30  
0.80  
3.70  
1.0  
0.90  
3.00  
1.00  
4.80  
Ω
Ω
VBAT_SEC = 2.1 V  
Ω
Ω
fSW  
MHz  
C
TTEMP_SD  
Junction temperature when charging is  
discontinued  
VBAT_OV > VSTOR > 1.8V  
125  
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bq25505  
SLUSBJ3B –AUGUST 2013–REVISED JANUARY 2014  
www.ti.com  
ELECTRICAL CHARACTERISTICS (continued)  
Over recommended temperature range, typical values are at TA = 25°C. Unless otherwise noted, specifications apply for  
conditions of VSTOR = 4.2 V. External components, CIN = 4.7 µF, L1 = 22 µH, CSTOR= 4.7 µF  
PARAMETER  
TEST CONDITIONS  
MIN  
TYP  
MAX UNIT  
BATTERY MANAGEMENT  
VBAT_OV  
Programmable voltage range for overvoltage  
threshold  
VBAT_SEC increasing  
2.2  
5.5  
45  
V
VBAT_OV_HYST  
VDELTA  
Battery over-voltage hysteresis (internal)  
VBAT_SEC decreasing; VBAT_OV  
= 5.25V  
24  
mV  
mV  
VBAT_OV - VIN(DC)  
Main boost charger on; MPPT not  
sampling VOC  
400  
VBAT_UV  
Under-voltage threshold  
VBAT_SEC decreasing  
VBAT_SEC increasing  
VBAT_SEC increasing  
1.91  
1.95  
15  
2
V
mV  
V
VBAT_UV_HYST  
VBAT_OK_HYST  
Battery under-voltage hysteresis (internal)  
32  
Programmable voltage range of digital signal  
indicating VSTOR (=VBAT_SEC) is OK  
VBAT_UV  
VBAT_UV  
VBAT_  
OV  
VBAT_OK_PROG  
Programmable voltage range of digital signal  
indicating VSTOR (=VBAT_SEC) is OK  
VBAT_SEC decreasing  
VBAT_  
OK_HYST –  
50  
mV  
VBAT_ACCURACY  
VBAT_OK(H)  
Overall Accuracy for threshold values VBAT_OV, Selected resistors are 0.1%  
-2  
2
%
VBAT_OK  
tolerance  
VBAT_OK (High) threshold voltage  
Load = 10 µA  
VSTOR –  
200  
mV  
mV  
VBAT_OK(L)  
VBAT_OK (Low) threshold voltage  
Load = 10 µA  
100  
0.3  
ENABLE THRESHOLDS  
EN(H)  
Voltage for EN high setting. Relative to  
VBAT_SEC.  
VBAT_SEC = 4.2V  
VBAT_SEC = 4.2V  
VBAT_SEC  
– 0.2  
V
V
EN(L)  
Voltage for EN low setting  
BIAS and MPPT CONTROL STAGE  
VOC_SAMPLE  
VOC_STLG  
Time period between two MPPT samples  
16  
s
Settling time for MPPT sample measurement of  
VIN_DC open circuit voltage  
Device not switching  
256  
ms  
VIN_REG  
MPPT_80  
MPPT_50  
VBIAS  
Regulation of VIN_DC during charging  
0.5 V < VIN < 4 V; IIN(DC) = 10  
mA  
10%  
Voltage on VOC_SAMP to set MPPT threshold to  
0.80 of open circuit voltage of VIN_DC  
VSTOR –  
0.015  
V
mV  
V
Voltage on VOC_SAMP to set MPPT threshold to  
0.50 of open circuit voltage of VIN_DC  
15  
Internal reference for the programmable voltage  
thresholds  
VSTOR ≥ VSTOR_CHGEN  
1.205  
1.21  
5
1.217  
MULTIPLEXOR  
tDEAD  
Dead time between VB_SEC_ON and  
VB_PRI_ON  
8(1)  
us  
(1) Specified by design.  
6
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bq25505  
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SLUSBJ3B –AUGUST 2013–REVISED JANUARY 2014  
DEVICE INFORMATION  
RGT PACKAGE  
(TOP VIEW)  
20  
19  
18  
17  
16  
1
2
3
4
5
15  
VSS  
VIN_DC  
VSS  
14 VBAT_PRI  
bq25505  
RGR  
3.5x3.5mm  
13  
VOC_SAMP  
VREF_SAMP  
EN  
VBAT_OK  
12  
OK_PROG  
11  
OK_HYST  
6
7
8
9
10  
Figure 1. bq25505 3.5mm x 3.5mm QFN-20 Package  
PIN FUNCTIONS  
PIN  
NAME  
VSS  
I/O TYPE  
DESCRIPTION  
NO.  
1
Input  
Input  
General ground connection for the device  
2
VIN_DC  
DC voltage input from energy harvesters. Connect at least a 4.7 µF capacitor as close as possible  
between this pin and pin 1.  
3
VOC_SAMP  
VREF_SAMP  
Input  
Sampling pin for MPPT network. Connect to VSTOR to sample at 80% of input soure open circuit  
voltage. Connect to GND for 50% or connect to the mid-point of external resistor divider between  
VIN_DC and GND.  
Sample and hold circuit output for the reference set by the MPPT per VOC_SAMP. Connect a 0.01 µF  
capacitor from this pin to GND.  
4
Input  
5
6
7
EN  
Input  
Input  
Active low digital programming input for enabling/disabling the IC. Connect to GND to enable the IC.  
Connect to VSS via the IC's PowerPad.  
NC  
VBAT_OV  
Connect to the mid-point of external resistor divider between VRDIV and GND for setting the  
VBAT_SEC overvoltage threshold.  
8
9
VRDIV  
Output  
Output  
Output  
Input  
Connect high side of resistor divider networks to this biasing voltage.  
VB_SEC_ON  
VB_PRI_ON  
OK_HYST  
Active low push-pull driver for the secondary (rechargeable) energy storage PMOS FET.  
Active low push-pull driver for the primary (non-rechargeable) energy storage PMOS FET.  
10  
11  
Connect to the mid-point of external resistor divider between VRDIV and GND for setting the  
VBAT_OK hysteresis threshold.  
12  
OK_PROG  
Input  
Connect to the mid-point of external resistor divider between VRDIV and GND for setting the  
VBAT_OK threshold.  
13  
14  
15  
16  
17  
18  
VBAT_OK  
VBAT_PRI  
VSS  
Output  
Input  
Supply  
Input  
Input  
I/O  
Digital output for battery good indicator. Internally referenced to the VSTOR voltage.  
Primary (non-rechargeable) energy storage element HiZ sense input.  
Signal ground connection for the device.  
NC  
Connect to ground using the IC's PowerPad.  
NC  
Connect to ground using the IC's PowerPad.  
VBAT_SEC  
Connect a secondary (rechargeable) storage element with at least 100uF of equivalent capacitance to  
this pin.  
19  
20  
VSTOR  
Output  
Input  
Connection for the output of the boost charger. Connect at least a 4.7 µF capacitor in parallel with a  
0.1 µF capacitor as close as possible to between this pin and pin 1 (VSS).  
LBOOST  
Inductor connection for the boost charger switching node. Connect a 22 µH inductor between this pin  
and pin 2 (VIN_DC).  
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SLUSBJ3B –AUGUST 2013–REVISED JANUARY 2014  
www.ti.com  
TYPICAL APPLICATION CIRCUITS  
VBAT_OV = 3.11 V, VBAT_OK = 2.39 V, VBAT_OK_HYST = 2.80 V, MPPT (VOC) = 80%  
L1 = 22 µH, CIN = CSTOR = 4.7 µF, CBYP=0.1 µF, CREF = 10 nF  
ROK1 = 5.62 MΩ, ROK2 = 5.49 MΩ, ROK3 = 1.87 MΩ, ROV1 = 7.5 MΩ, ROV2 = 5.36 MΩ  
CSTOR  
CBYP  
+
SEC_BAT  
(rechargeable)  
VSTOR  
VBAT_SEC  
VOC_SAMP  
LBOOST  
L1  
VBAT_PRI  
TPS62736  
Ideal Diode OR  
+
VREF_SAMP  
PRI_BAT  
Boost  
Controller  
CIN  
+
-
VBAT_OK  
Solar  
Cell  
CREF  
System  
Load  
VB_PRI_ON  
VSS  
MPPT  
VB_SEC_ON  
VIN_DC  
Cold Start  
Nano-Power  
Management  
VSTOR  
VBAT_SEC  
Host  
GPIO1  
GPIO2  
EN  
VBAT_OK  
bq25505  
ROV2  
ROV1  
ROK3  
ROK2  
ROK1  
Figure 2. Typical Solar Application Circuit with Primary and Secondary Batteries  
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VBAT_OV = 4.18V, VBAT_OK = 3.5 V, VBAT_OK_HYST = 3.7 V, MPPT (VOC) = 50%  
L1 = 22 µH, CIN = CSTOR = 4.7 µF, CBYP=0.1 µF, CREF = 10 nF  
ROK1 = 4.22 MΩ, ROK2 = 8.06 MΩ, ROK3 = 0.698 MΩ, ROV1 = 6.04 MΩ, ROV2 = 7.87 MΩ  
TPS62736  
CSTOR  
CBYP  
+
SEC_BAT  
System  
Load  
VSTOR  
VBAT_SEC  
VOC_SAMP  
LBOOST  
L1  
VBAT_PRI  
Ideal Diode OR  
VREF_SAMP  
Boost  
Controller  
CIN  
VBAT_OK  
TEG  
CREF  
VB_PRI_ON  
VSS  
MPPT  
VB_SEC_ON  
VIN_DC  
Cold Start  
Nano-Power  
Management  
VSTOR VBAT_SEC  
Host  
GPIO1  
GPIO2  
EN  
VBAT_OK  
bq25505  
ROV2  
ROV1  
ROK3  
ROK2  
ROK1  
Figure 3. Typical TEG Application Circuit without a Primary Battery  
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VBAT_OV = 3.31 V, VBAT_OK = 2.82 V, VBAT_OK_HYST = 3.12 V, MPPT (VOC) = 40%  
L1 = 22 µH, CIN = CSTOR = 4.7 µF, CBYP=0.1 µF, CREF = 10 nF  
ROK1 = 4.99 MΩ, ROK2 = 6.65 MΩ, ROK3 = 1.24 MΩ, ROV1 = 6.98 MΩ, ROV2 = 5.76 MΩ  
ROC1 = 8.06 MΩ, ROC2 = 12 MΩ  
CSTOR  
CBYP  
+
SEC_BAT  
(rechargeable)  
ROC2  
VOC_SAMP  
LBOOST  
ROC1  
VSTOR  
VBAT  
L1  
VBAT_PRI  
TPS62736  
MA4X79600LCT-ND  
Ideal Diode OR  
+
VREF_SAMP  
Vibration  
Element  
PRI_BAT  
Boost  
Controller  
VBAT_OK  
CIN  
CREF  
System  
Load  
VB_PRI_ON  
MA4X79600LCT-ND  
VSS  
MPPT  
VB_SEC_ON  
VIN_DC  
Cold Start  
Nano-Power  
Management  
VSTOR  
VBAT_SEC  
Host  
GPIO1  
GPIO2  
EN  
VBAT_OK  
bq25505  
ROV2  
ROV1  
ROK3  
ROK2  
ROK1  
Figure 4. Typical Piezoelectric Application Circuit with Primary and Secondary Batteries  
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HIGH-LEVEL FUNCTIONAL BLOCK DIAGRAM  
VSTOR  
LBST  
VBAT_SEC  
VBAT_PRI  
PFM Boost  
Charger  
Controller  
VOR  
CKT  
VSS  
VSS  
Cold-start  
Unit  
VB_PRI_ON  
VB_SEC_ON  
Enable  
Enable  
VIN_DC  
Interrupt  
VBAT_OK  
OK_PROG  
VOC_SAMP  
VREF_SAMP  
BAT_SAVE  
+
MPPT  
Controller  
+
Battery Threshold  
Control  
OT  
VREF  
OK  
OK_HYST  
Temp  
Sensing  
Element  
VREF  
Bias Reference &  
Oscillator  
VREF  
VBAT_UV  
VBAT_OV  
VRDIV  
EN  
Figure 5. High-Level Functional Diagram  
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TYPICAL CHARACTERISTICS  
Table of Graphs  
Unless otherwise noted, graphs were taken using with CIN = 4.7µF, L1 = Coilcraft 22µH LPS4018, CSTOR =  
4.7µF, VBAT_OV=4.2V  
FIGURE  
IN= 10 µA  
Figure 6  
Figure 7  
Figure 8  
Figure 9  
Figure 10  
Figure 11  
Figure 12  
vs. Input Voltage  
vs. Input Current  
IN= 100 µA  
IIN = 10 mA  
VIN = 2.0 V  
VIN = 1.0 V  
VIN = 0.5 V  
VIN = 0.2 V  
Charger Efficiency (η)(1)  
EN = VBAT_SEC (Active  
Mode)  
Figure 13  
Figure 14  
Figure 15  
VBAT_SEC Quiescent Current  
VBAT_PRI Leakage Current  
vs. VBAT_SEC Voltage  
vs. VBAT_PRI Voltage  
EN = GND (Ship Mode)  
EN = VBAT_SEC (Ship  
Mode)  
Startup by Taking EN Low (from  
Ship mode)  
VBAT = 3.4-V charged Li coin cell; VIN_DC = 1.0 V  
power supply; MPPT=50%; ZIN = 100Ω  
Figure 16  
Figure 17  
Figure 18  
Figure 19  
Figure 20  
VBAT = 3.2-V charged Li coin cell; VIN_DC = 2.0 V VOC_SAMP = VSTOR to  
power supply; ZIN = 100Ω  
MPPT Operation  
GND to VSTOR  
R(VSTOR) = open to 84  
Ω to open  
50mA Load Transient on VSTOR  
VBAT = 4.2V charged 0.5 F; VIN_DC = 1.5 V  
power supply; MPPT=80%; ZIN = 75Ω  
50mA Load Transient on VSTOR  
with Sampling  
R(VSTOR) = open to 84  
Ω to open  
Charger Operational Waveform  
During 50mA Load Transient  
R(VSTOR) = 84 Ω  
VRDIV Waveform over Two Periods  
VRDIV Waveform  
Figure 21  
Figure 22  
VSTOR = 4.2V  
VSTOR ramped from 0 V to 4.2 V to 0 V with  
function generator  
VBAT_OK Operation  
Figure 23  
Multiplexor Output (VOR) as  
VBAT_SEC Crosses VBAT_OK  
Threshold  
VBAT_SEC = 0.5 F super  
capacitor; 1kΩ load on  
VOR  
VSTOR ramped from 0 V to 4.2 V to 0 V with  
function generator; VBAT_PRI = 3.6V power supply  
Figure 24  
Multiplexor Signals When  
VBAT_SEC > VBAT_OK Threshold  
VB_PRI_ON goes high; VB_SEC_ON goes low  
VB_PRI_ON goes low; VB_SEC_ON goes low  
Figure 25  
Figure 26  
Figure 27  
Multiplexor Signals When  
VBAT_SEC < VBAT_OK Threshold  
VIN_DC = sourcemeter with compliance = 1.2 V  
and ISC = 1.0 mA  
VBAT_SEC = 120 mF  
super capacitor  
Charging a Super Cap on VBAT  
(1) See SLUA691 for an explanation on how to take these measurements. Because the MPPT feature cannot be disabled on the bq25505,  
these measurements need to be taken in the middle of the 16 s sampling period.  
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Spacer  
100  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
100  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
I
= 10PA  
IN  
I
= 100 PA  
IN  
VSTOR = 2.0 V  
VSTOR = 3.0 V  
VSTOR = 5.5 V  
VSTOR = 2.0 V  
VSTOR = 3.0 V  
0
0.2 0.4 0.6 0.8  
1
1.2 1.4 1.6 1.8  
2
2.2 2.4 2.6 2.8  
3
0
0.2 0.4 0.6 0.8  
1
1.2 1.4 1.6 1.8 2 2.2 2.4 2.6 2.8 3  
Input Voltage (V)  
Input Voltage (V)  
Figure 6. Charger Efficiency vs Input Voltage  
Figure 7. Charger Efficiency vs Input Voltage  
100  
90  
80  
70  
60  
50  
40  
30  
20  
100.00  
90.00  
80.00  
70.00  
60.00  
50.00  
40.00  
I
= 10 mA  
V
= 2 V  
IN  
IN  
VSTOR = 2.0 V  
VSTOR = 3.0 V  
VSTOR = 5.5 V  
VSTOR = 2.2 V  
VSTOR = 3.0 V  
VSTOR = 5.5 V  
0
0.2 0.4 0.6 0.8  
1
1.2 1.4 1.6 1.8  
2
2.2 2.4 2.6 2.8  
3
0.01  
0.1  
1
10  
100  
Input Voltage (V)  
Input Current (mA)  
Figure 8. Charger Efficiency vs Input Voltage  
Figure 9. Charger Efficiency vs Input Current  
100.00  
90.00  
80.00  
70.00  
60.00  
50.00  
40.00  
30.00  
20.00  
100  
90  
80  
70  
60  
50  
40  
30  
20  
V
= 0.5 V  
IN  
V
= 1 V  
IN  
VSTOR = 2.0 V  
VSTOR = 3.0 V  
VSTOR = 5.5 V  
VSTOR = 1.8 V  
VSTOR = 3.0 V  
VSTOR = 5.5 V  
0.01  
0.1  
1
Input Current (mA)  
10  
100  
0.01  
0.1  
1
10  
100  
Input Current (mA)  
Figure 10. Charger Efficiency vs Input Current  
Figure 11. Charger Efficiency vs Input Current  
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100  
90  
1400  
1200  
1000  
800  
600  
400  
200  
0
TA = -40C, VBAT_PRI = 2V  
TA = -40C, VBAT_PRI = 5.5V  
TA = 25C, VBAT_PRI = 2V  
TA = 25C, VBAT_PRI = 5.5V  
TA = 85C, VBAT_PRI = 2V  
TA = 85C, VBAT_PRI = 5.5V  
V
= 0.2 V  
IN  
80  
70  
60  
50  
40  
30  
20  
VSTOR = 3.0 V  
VSTOR = 2.0 V  
VSTOR = 5.5 V  
0.0  
0.1  
1.0  
10.0  
100.0  
2
2.5  
3
3.5  
4
4.5  
5
5.5  
Input Current (mA)  
VBAT_SEC Voltage (V)  
Figure 12. Charger Efficiency vs Input Current  
Figure 13. Quiescent Current vs VBAT_SEC Voltage: Active  
Mode  
250  
200  
150  
100  
50  
35  
TA = -40C, VBAT_PRI = 2V  
TA = -40C, VBAT_PRI = 5.5V  
TA = 25C, VBAT_PRI = 2V  
TA = 25C, VBAT_PRI = 5.5V  
TA = 85C, VBAT_PRI = 2V  
TA = 85C, VBAT_PRI = 5.5V  
TA = 85C, VBAT_SEC = 2V  
30  
TA = 85C, VBAT_SEC = 5.5V  
TA = 25C, VBAT_SEC = 5.5V  
25  
20  
15  
10  
5
TA = 25C, VBAT_SEC = 2V  
TA = -40C, VBAT_SEC = 2V  
TA = -40C, VBAT_SEC = 5.5V  
0
0
-5  
2
2.5  
3
3.5  
4
4.5  
5
5.5  
2
3
4
5
6
VBAT_SEC Voltage (V)  
VBAT_PRI Voltage (V)  
Figure 14. Quiescent Current vs VBAT_SEC Voltage: Ship  
Mode  
Figure 15. VBAT_PRI Leakage Current vs VBAT_PRI  
Voltage  
Figure 16. Startup by Taking EN Low (from Ship mode)  
Figure 17. MPPT Operation  
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Figure 18. 50 mA Load Transient on VSTOR  
Figure 19. 50 mA Load Transient on VSTOR - Zoom Out  
Figure 20. Charger Operational Waveforms During 50 mA  
Load Transient  
Figure 21. VRDIV Waveform over Two Periods  
Figure 22. VRDIV Waveform  
Figure 23. VBAT_OK Operation  
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Figure 24. Multiplexor Output (VOR) as VBAT_SEC Crosses  
VBAT_OK Threshold  
Figure 25. MUX Signals When VBAT_SEC > VBAT_OK  
Threshold  
Figure 26. MUX Signals When VBAT_SEC < VBAT_OK  
threshold  
Figure 27. Charging a Super Cap on VBAT_SEC  
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DETAILED DESCRIPTION  
Boost Charger Overview  
The bq25505 is based on an ultra low quiescent current, efficient synchronous boost charger. The boost charger  
is intended to be powered from a high impedance DC source, such as a solar panel, TEG or piezoelectric  
module; therefore, it regulates its input voltage (VIN_DC) in order to prevent the input source from collapsing.  
The boost charger monitors its output voltage (VSTOR) and stops switching when VSTOR reaches a resistor  
programmable threshold level. The boost charger is based on a switching regulator architecture which maximizes  
efficiency while minimizing start-up and operation power. It uses pulse frequency modulation (PFM) to maintain  
efficiency, even under light load conditions. In addition, the boost charger implements battery protection features  
so that either rechargeable batteries or capacitors can be used as energy storage elements at the rechargeable  
storage element output (VBAT_SEC). Figure 5 is a high-level functional block diagram which highlights most of  
the major functional blocks inside the bq25505.  
Enable Controls  
There is one enable pin implemented in bq25505 in order to maximize the flexibility of control for the system.  
When taken high, the EN pin shuts down the IC completely including the boost charger and battery management  
circuitry. It also turns off the PFET that connects VBAT_SEC to VSTOR. This can be described as ship mode,  
because it will put the IC in the lowest leakage state and provide a long storage period without discharging the  
battery on VBAT_SEC. If there is no need to control EN, it is recommended that this pin be tied to VSS, or  
system ground.  
Startup Operation  
The bq25505 has two circuits for boosting the input voltage, a low-power cold-start circuit, drawing power  
exclusively from VIN_DC when ≥ VIN(CS), and the high efficiency main boost charger, with the bias rails drawing  
power from VSTOR when ≥ VSTOR_CHGEN and the power stage drawing power from VIN_DC when ≥ VIN(DC)  
minimum. When EN = 0 and VSTOR ≤ VSTOR_CHGEN, there are two options for charging the VSTOR  
capacitor, CSTOR, to VSTOR_CHGEN for the main boost charger to turn on. The first option, shown in  
Figure 28, is to allow the cold start circuit to charge VSTOR to VSTOR_CHGEN. Due to the body diode of the  
PFET connecting VSTOR and VBAT_SEC, the cold start circuit must charge both the capacitor on CSTOR and  
the storage element connected to VBAT_SEC up to VSTOR_CHGEN. When a rechargeable battery with an  
open protector is attached, the charge time is typically short due to the minimum charge needed to close the  
FET. When large, discharged super capacitors are attached, the charge time can be signficant. The second  
option, shown in Figure 29, is to connect a storage element, charged above VSTOR_CHGEN, to VBAT_SEC.  
Assuming the voltages on VSTOR and VBAT_SEC are both below 100mV, when a charged storage element is  
attached (i.e. hot-plugged) to VBAT_SEC, the IC turns on the internal PFET between the VSTOR and  
VBAT_SEC pins for tBAT_HOT_PLUG in order to charge CSTOR to VSTOR_CHGEN. If a system load tied to  
VSTOR prevents the storage element from charging VSTOR within tBAT_HOT_PLUG, it is recommended to add an  
external PFET between the system load and VSTOR. An inverted VBAT_OK signal can be used to drive the gate  
of this system-isolating PFET. Once the VSTOR pin voltage reaches the internal under voltage threshold  
(VBAT_UV), the internal PFET stays on and the main boost charger begins to charge the storage element if  
there is sufficient power available at the VIN_DC pin, as explained below. If VSTOR does not reach VBAT_UV  
within 50ms, then the PFET turns off and the cold-start circuit turns on, also as explained below.  
Boost Charger Cold-Start Operation (VSTOR < VSTOR_CHGEN and VIN_DC > VIN(CS) )  
If the attached storage element does not charge CSTOR above VSTOR_CHGEN, VIN_DC ≥ VIN(CS), the cold-  
start circuit turns on. The cold-start circuit is essentially an unregulated boost converter with lower efficiency  
compared to the main boost charger. The energy harvester must supply sufficient power for the IC to exit cold  
start. See the Energy Harvester Selection applications section for guidance.  
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When the CSTOR voltage reaches VSTOR_CHGEN, the main boost charger starts up. The VSTOR voltage from  
the main boost charger is compared against the battery undervoltage threshold (VBAT_UV). When the VBAT_UV  
threshold is reached, the PMOS switch between VSTOR and VBAT_SEC turns on, which allows the energy  
storage element attached to VBAT_SEC to charge up. Cold start is not as efficient as the main boost regulator. If  
sufficient input power is not available, it is possible that the cold start circuit continuously runs and the VSTOR  
output does not increase above VSTOR_CHGEN for the main boost conveter to start up. The battery  
management thresholds are explained later is this section. See the Energy Harvester Selection applications  
section for guidance on minimum input power requirements.  
Main Boost Charger Operation (VSTOR > VSTOR_CHGEN and VIN_DC > VIN(DC) )  
The main boost charger charges the storage element attached to VBAT_SEC with the energy available from the  
high impedance input source. For the first 32 ms (typical) after the main charger is turned on (assuming EN is  
low), the charger is disabled to let the input rise to its open-circuit voltage. This sample period is required to get  
the reference voltage which will be used for the remainder of the charger operation till the next MPPT sampling  
cycle. The boost charger employs pulse frequency modulation (PFM) mode of control to regulate the voltage at  
VIN_DC close to the desired reference voltage. The reference voltage is set by the MPPT control scheme as  
described in the next section. Input voltage regulation is obtained by transferring charge from the input to VSTOR  
only when the input voltage is higher than the voltage on pin VREF_SAMP. The current through the inductor is  
controlled through internal current sense circuitry. The peak current in the inductor is dithered internally to pre-  
determined levels in order to maintain high efficiency of the charger across a wide input current range. The  
charger transfers up to a maximum of 100 mA average input current (230mA typical peak inductor current). The  
boost charger is disabled when the voltage on VSTOR reaches the user set VBAT_OV threshold to protect the  
battery connected at VBAT_SEC from overcharging. In order for the battery to charge to VBAT_OV, the input  
power must exceed the power needed for the load on VSTOR. See the Energy Harvester Selection applications  
section for guidance on minimum input power requirements.  
Maximum Power Point Tracking  
Maximum power point tracking (MPPT) is implemented in order to maximize the power extracted from an energy  
harvester source. The boost converter indirectly modulates the impedance of main boost charger by regulating  
the charger's input voltage, as sensed by the VIN_DC pin, to the sampled reference voltage, as stored on the  
VREF_SAMP pin. The MPPT circuit obtains a new reference voltage 16 s (typical) by periodically disabling the  
charger for 256 ms (typical) and sampling a fraction of the open-circuit voltage. For solar harvesters, the  
maximum power point is typically 70%-80% and for thermoelectric harvesters, the MPPT is typically 50%. Tying  
VOC_SAMP to VSTOR internally sets the MPPT regulation point to 80% of VOC. Tying VOC_SAMP to GND  
internally sets the MPPT regulation point to 50% of VOC. If input source does not have either 80% or 50% of  
VOC as its MPP point, the exact ratio for MPPT can be optimized to meet the needs of the input source being  
used by connecting external resistors ROC1 and ROC2 between VRDIV and GND with mid-point at VOC_SAMP.  
The reference voltage is set by the following expression:  
æ
ç
è
ö
÷
ø
ROC1  
VREF_SAMP = VIN_DC(OpenCircuit)  
ROC1 + ROC2  
(1)  
Storage Element / Battery Management  
In this section the battery management functionality of the bq25505 integrated circuit (IC) is presented. The IC  
has internal circuitry to manage the voltage across the storage element and to optimize the charging of the  
storage element. For successfully extracting energy from the source, two different threshold voltages must be  
programmed using external resistors, namely battery good threshold (VBAT_OK) and over voltage (OV)  
threshold. The two user programmable threshold voltages and the internally set undervoltage threshold  
determine the IC's region of operation. Figure 28 and Figure 29 show plots of the voltage at the VSTOR pin and  
the various threshold voltages for two use cases 1) when a depleted battery on VBAT_SEC is attached and the  
charger enters cold start and 2) when a battery at VBAT_SEC charged above VBAT_UV is attached. For the  
best operation of the system, the VBAT_OK should be used to determine when a load can be applied or  
removed. A detailed description of the three voltage thresholds and the procedure for designing the external  
resistors for setting the three voltage thresholds are described next.  
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5.5V  
VBAT_OV  
BOOST CHARGER OFF  
VSTOR=VBAT_SEC  
MAIN BOOST  
CHARGER  
ON  
VBAT_OK_HYST  
VBAT_OK  
VBAT_UV  
VBAT_OK  
VSTOR  
VSTOR_CHGEN  
0V  
VDIODE  
VBAT_SEC  
COLD START ON  
VIN_DC > 330mV  
time  
Figure 28. Charger Operation after a Depleted Storage Element is Attached  
5.5V  
BOOST CHARGER OFF  
VBAT_OV  
VSTOR=VBAT_SEC  
VBAT_OK_HYST  
MAIN BOOST  
CHARGER  
VBAT_OK  
ON  
VBAT_OK  
VBAT_UV  
0V  
time  
Attach Storage Element  
Figure 29. Charger Operation after a Partially Charged Storage Element is Attached  
When no input source is attached, the VSTOR node should be discharged to ground before attaching a storage  
element. Hot-plugging a storage element that is charged (e.g., the battery protector PFET is closed) and with the  
VSTOR node above ground results in the PFET between VSTOR and VBAT_SEC remaining off until an input  
source is attached. In addition, if a system load attached to VSTOR has fast transients that could pull VSTOR  
below VBAT_UV, the internal PFET switch will turn off in order to recharge the CSTOR capacitor to  
VSTOR_CHGEN. See the application section for guidance on sizing the VSTOR and/or VBAT_SEC capacitance  
to account for transients. If the voltage applied at VIN_DC is greater than VSTOR or VBAT_SEC then current  
may flow until the voltage at the input is reduced or the voltage at VSTOR and VBAT_SEC rise. This is  
considered an abnormal condition and the boost charger does not operate.  
Battery Undervoltage Protection  
To prevent rechargeable batteries from being deeply discharged and damaged, and to prevent completely  
depleting charge from a capacitive storage element, the IC has an internally set undervoltage (VBAT_UV)  
threshold plus an internal hysteresis voltage (VBAT_UV_HYST). The VBAT_UV threshold voltage when the  
battery voltage is decreasing is internally set to 1.95V (typical). The undervoltage threshold when battery voltage  
is increasing is given by VBAT_UV plus VBAT_UV_HYST. For most applications, the system load should be  
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connected to the VSTOR pin while the storage element should be connected to the VBAT_SEC pin. Once the  
VSTOR pin voltage goes above the VBAT_UV_HYST threshold, the VSTOR pin and the VBAT_SEC pins are  
shorted. The switch remains closed until the VSTOR pin voltage falls below VBAT_UV. The VBAT_UV threshold  
should be considered a fail safe to the system; therefore the system load should be removed or reduced based  
on the VBAT_OK threshold which should be set above the VBAT_UV threshold.  
Battery Overvoltage Protection  
To prevent rechargeable batteries from being exposed to excessive charging voltages and to prevent over  
charging a capacitive storage element, the over-voltage (VBAT_OV) threshold level must be set using external  
resistors. This is also the voltage value to which the charger will regulate the VSTOR/VBAT_SEC pin when the  
input has sufficient power. The VBAT_OV threshold when the battery voltage is rising is given by Equation 2:  
æ
ö
÷
ø
ROV2  
ROV1  
3
VBAT_OV = VBIAS 1 +  
ç
2
è
(2)  
The sum of the resistors is recommended to be no higher than 13 MΩ that is, ROV1 + ROV2 = 13 MΩ. The  
overvoltage threshold when battery voltage is decreasing is given by OV_HYST. It is internally set to the over  
voltage threshold minus an internal hysteresis voltage denoted by VBAT_OV_HYST. Once the voltage at the  
battery exceeds VBAT_OV threshold, the boost charger is disabled. The charger starts again once the battery  
voltage falls below the VBAT_OV_HYST level. When there is excessive input energy, the VBAT pin voltage will  
ripple between the VBAT_OV and the VBAT_OV_HYST levels. SLUC484 provides help on sizing and selecting  
the resistors.  
CAUTION  
If VIN_DC is higher than VSTOR and VSTOR is higher than VBAT_OV, the input  
VIN_DC is pulled to ground through a small resistance to stop further charging of the  
attached battery or capacitor. It is critical that if this case is expected, the impedance of  
the source attached to VIN_DC be higher than 20 Ω and not a low impedance source.  
Battery Voltage in Operating Range (VBAT_OK Output)  
The IC allows the user to set a programmable voltage independent of the overvoltage and undervoltage settings  
to indicate whether the VSTOR voltage (and therefore the VBAT_SEC voltage when the PFET between the two  
pins is turned on) is at an acceptable level. When the battery voltage is decreasing the threshold is set by  
Equation 3:  
æ
ö
÷
ø
ROK2  
ROK1  
VBAT_OK_PROG = VBIAS 1 +  
ç
è
(3)  
When the battery voltage is increasing, the threshold is set by Equation 4:  
æ
ö
÷
ø
ROK2 + ROK3  
VBAT_OK_HYST = VBIAS 1 +  
ç
ROK1  
è
(4)  
The sum of the resistors is recommended to be no higher than approximately i.e., ROK1 + ROK2 + ROK3= 13 MΩ.  
The logic high level of this signal is equal to the VSTOR voltage and the logic low level is ground. The logic high  
level has ~20 KΩ internally in series to limit the available current to prevent MCU damage until it is fully powered.  
The VBAT_OK_PROG threshold must be greater than or equal to the UV threshold. For the best operation of the  
system, the VBAT_OK should be setup to drive an external PFET between VSTOR and the system load in order  
to determine when the load can be applied or removed to optimize the storage element capacity. SLUC484  
provides help on sizing and selecting the resistors.  
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Push-Pull Multiplexor Drivers  
There are two push-pull drivers intended to mulitplex between a primary non-rechargeable connected at  
VBAT_PRI and secondary storage element connected on VBAT_SEC based on the VBAT_OK signal. When the  
VBAT_OK signal goes high, indicating that the secondary rechargeable battery at VBAT_SEC is above the  
VBAT_OK_HYST threshold, the VB_PRI_ON output goes high followed by the VB_SEC_ON signal going low in  
order to connect VBAT_SEC to the system output (referred to as the VOR node). When VBAT_OK goes low,  
indicating that the secondary rechargeable battery at VBAT_SEC is below the VBAT_OK threshold, the  
VB_SEC_ON output goes high followed by the VB_PRI_ON signal going low in order to connect VBAT_PRI to  
the system. The drivers are designed to support up to 2 nF of gate capacitance and to drive a PMOS FET. The  
switching characteristics follow a break-before-make model, wherein during a transition, the drivers both go high  
for a typical dead time of 5 us before one of the signals goes low. The figure below shows the FET gate voltages  
for the transition from the secondary battery being connected to the system to the primary battery being  
connected.  
VB_PRI_ON  
10ꢀsec  
85%  
85%  
VB_SEC_ON  
Figure 30. Break-Before-Make Operation of VB_PRI_ON and VB_SEC_ON  
Steady State Operation and Cycle by Cycle Behavior  
Steady state operation for the boost charger is shown in Figure 20. These plots highlight the inductor current  
waveform, the VSTOR voltage ripple, and the LBOOST switching nodes. The charger uses hysteretic control and  
pulse frequency modulation (PFM) switching in order to maintain high efficiency at light load. As long as the  
VIN_DC voltage is above the MPPT regulation set point (i.e. voltage at VREF_SAMP), the boost charger's low-  
side power FET turns on and draws current until it reaches its respective peak current limit. These switching  
bursts continue until VSTOR reaches the VBAT_OV threshold. This cycle-by-cycle minor switching frequency is a  
function of each converter's inductor value, peak current limit and voltage levels on each side of each  
inductor. Once the VSTOR capacitor, CSTOR, droops below a minimum value, the hysteretic switching repeats.  
Nano-Power Management and Efficiency  
The high efficiency of the bq25505 charger is achieved via the proprietary Nano-Power management circuitry  
and algorithm. This feature essentially samples and holds all references (except for VBAT_UV) in order to reduce  
the average quiescent current. That is, the internal circuitry is only active for a short period of time and then off  
for the remaining period of time at the lowest feasible duty cycle. A portion of this feature can be observed in  
Figure 21 where the VRDIV node is monitored. Here the VRDIV node provides a connection to the VSTOR  
voltage (first pulse) and then generates the reference levels for the VBAT_OV and VBAT_OK resistor dividers for  
a short period of time. The divided down values at each pin are sampled and held for comparison against VBIAS  
as part of the hysteretic control. Since this biases a resistor string, the current through these resistors is only  
active when the Nano-Power management circuitry makes the connection—hence reducing the overall quiescent  
current due to the resistors. This process repeats every 64 ms.  
The bq25505's boost charger efficiency is shown for various input power levels in Figure 6 through Figure 12. All  
data points were captured by averaging the overall input current. This must be done due to the periodic biasing  
scheme implemented via the Nano-Power management circuitry. In order to properly measure the resulting input  
current when calculating the output to input efficiency, the input current efficiency data was gathered using a  
source meter set to average over at least 50 samples.  
Thermal Shutdown  
Rechargeable Li-ion batteries need protection from damage due to operation at elevated temperatures. The  
application should provide this battery protection and ensure that the ambient temperature is never elevated  
greater than the expected operational range of 85°C.  
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The bq25505 uses an integrated temperature sensor to monitor the junction temperature of the device. The  
temperature threshold for thermal protection is set to 125°C. Once the temperature threshold is exceeded, the  
boost charger is disabled and charging ceases. Once the temperature of the device drops below this threshold,  
the boost charger and buck converter resumes operation. To avoid unstable operation near the overtemp  
threshold, a built-in hysteresis of approximately 5°C has been implemented. Care should be taken to not over  
discharge the battery in this condition since the boost charger is disabled. However, if the supply voltage drops to  
the VBAT_UV setting, then the switch between VBAT_SEC and VSTOR will open and protect the battery even if  
the device is in thermal shutdown.  
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APPLICATION INFORMATION  
Energy Harvester Selection  
The energy harvesting source (e.g., solar panel, TEG, vibration element) must provide a minimum level of power  
for the IC to operate as designed. The IC's minimum input power required to exit cold start can be estimated as:  
PIN > [(I-STR_ELM_LEAK@1.8V X 1.8V) + (1.8V2 / RSTOR(CS))] / 0.05  
where I-STR_ELM_LEAK@1.8V is the storage element leakage current at 1.8V and  
RSTOR(CS) is the equivalent resitive load on VSTOR during cold start and 0.05 is an estimate of the worst case  
efficiency of the cold start circuit.  
Once the IC is out of cold start and the system load has been activated (e.g., using the VBAT_OK signal), the  
energy harvesting element must provide the main boost charger with at least enough power to meet the average  
system load. Assuming RSTOR(AVG) represents the average resistive load on VSTOR, the simplified equation  
below gives an estimate of the IC's minimum input power needed during system operation:  
PIN X ηEST > PLOAD = (VBAT_OV2 / RSTOR(AVG) + VBAT_OV * I-STR_ELM_LEAK@VBAT_OV  
)
where ηEST can be derived from the datasheet efficiency curves for the given input voltage and current and  
VBAT_OV. The simplified equation above assumes that, while the harvester is still providing power, the system  
goes into low power or sleep mode long enough to charge the storage element so that it can power the system  
when the harvester eventually is down. Refer to SLUC463 for a design example that sizes the energy harvester.  
Storage Element Selection  
In order for the charge management circuitry to protect the storage element from over-charging or discharging,  
the storage element must be connected to VBAT pin and the system load tied to the VSTOR pin. Many types of  
elements can be used, such as capacitors, super capacitors or various battery chemistries. A storage element  
with 100uF equivalent capacitance is required to filter the pulse currents of the PFM switching charger. The  
equivalent capacitance of a battery can be computed as computed as:  
CEQ = 2 x mAHrBAT(CHRGD) x 3600 s/Hr / VBAT(CHRGD)  
In order for the storage element to be able to charge VSTOR capacitor (CSTOR) within the tVB_HOT_PLUG (50 ms  
typical) window at hot-plug; therefore preventing the IC from entering cold start, the time constant created by the  
storage element's series resistance (plus the resistance of the internal PFET switch) and equivalent capacitance  
must be less than tVB_HOT_PLUG . For example, a battery's resistance can be computed as:  
RBAT = VBAT / IBAT(CONTINUOUS) from the battery specifications.  
The storage element must be sized large enough to provide all of the system load during periods when the  
harvester is no longer providing power. The harvester is expected to provide at least enough power to fully  
charge the storage element while the system is in low power or sleep mode. Assuming no load on VSTOR (i.e.,  
the system is in low power or sleep mode), the following equation estimates charge time from voltage VBAT1 to  
VBAT2 for given input power is:  
PIN x ηEST X tCHRG = 1/2 X CEQ X (VBAT22 - VBAT12)  
Refer to SLUC463 for a design example that sizes the storage element.  
Note that if there are large load transients or the storage element has significant impedance then it may be  
necessary to increase the CSTOR capacitor from the 4.7uF minimum or add additional capacitance to VBAT in  
order to prevent a droop in the VSTOR voltage. See below for guidance on sizing capacitors.  
Inductor Selection  
The boost charger needs an appropriately sized inductor for proper operation. The inductor's saturation current  
should be at least 25% higher than the expected peak inductor currents recommended below if system load  
transients on VSTOR are expected. Since this device uses hysteretic control, the boost charger is considered  
naturally stable systems (single order transfer function).  
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For the boost charger to operate properly, an inductor of appropriate value must be connected between  
LBOOST, pin 20, and VIN_DC, pin 2. The boost charger internal control circuitry is designed to control the  
switching behavior with a nominal inductance of 22 µH ± 20%. The inductor must have a peak current capability  
of > 300 mA with a low series resistance (DCR) to maintain high efficiency.  
A list of inductors recommended for this device is shown in Table 1.  
Table 1.  
Inductance (µH)  
Dimensions (mm)  
4.0x4.0x1.7  
Part Number  
LPS4018-223M  
744031220  
Manufacturer  
Coilcraft  
22  
22  
3.8x3.8x1.65  
Wuerth  
Capacitor Selection  
In general, all the capacitors need to be low leakage. Any leakage the capacitors have will reduce efficiency,  
increase the quiescent current and diminish the effectiveness of the IC for energy harvesting.  
VREF_SAMP Capacitance  
The MPPT operation depends on the sampled value of the open circuit voltage and the input regulation follows  
the voltage stored on the CREF capacitor. This capacitor is sensitive to leakage since the holding period is  
around 16 seconds. As the capacitor voltage drops due to any leakage, the input regulation voltage also drops  
preventing proper operation from extraction the maximum power from the input source. Therefore, it is  
recommended that the capacitor be an X7R or COG low leakage capacitor.  
VIN_DC Capacitance  
Energy from the energy harvester input source is initially stored on a capacitor, CIN, connected to VIN_DC, pin  
2, and VSS, pin 1. For energy harvesters which have a source impedance which is dominated by a capacitive  
behavior, the value of the harvester capacitor should scaled according to the value of the output capacitance of  
the energy source, but a minimum value of 4.7 µF is recommended.  
VSTOR Capacitance  
Operation of the bq25505 requires two capacitors to be connected between VSTOR, pin 19, and VSS, pin 1. A  
high frequency bypass capacitor of at 0.01 µF should be placed as close as possible between VSTOR and VSS.  
In addition, a low ESR capacitor of at least 4.7 µF should be connected in parallel.  
Additional Capacitance on VSTOR or VBAT_SEC  
If there are large, fast system load transients and/or the storage element has high resistance, then the CSTOR  
capacitors may momentarily discharge below the VBAT_UV threshold in response to the transient. This causes  
the bq25505 to turn off the PFET switch between VSTOR and VBAT_SEC and turn on the boost charger. The  
CSTOR capacitors may further discharge below the VSTOR_CHGEN threshold and cause the bq25505 to enter  
Cold Start. For instance, some Li-ion batteries or thin-film batteries may not have the current capacity to meet the  
surge current requirements of an attached low power radio. To prevent VSTOR from drooping, either increasing  
the CSTOR capacitance or adding additional capacitance in parallel with the storage element is recommended.  
For example, if boost charger is configured to charge the storage element to 4.2 V and a 500 mA load transient  
of 50 µs duration infrequently occurs, then, solving I = C x dv/dt for CSTOR gives:  
CSTOR ≥ 500 mA x 50 µs/(4.2 V – 1.8 V) = 10.5 µF  
(5)  
Note that increasing CSTOR is the recommended solution but will cause the boost charger to operate in the less  
efficient cold start mode for a longer period at startup compared to using CSTOR = 4.7 µF. If longer cold start run  
times are not acceptable, then place the additional capacitance in parallel with the storage element.  
For a recommended list of standard components, see the EVM User’s guide (SLUUAA8).  
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LAYOUT CONSIDERATIONS  
As for all switching power supplies, the PCB layout is an important step in the design, especially at high peak  
currents and high switching frequencies. If the layout is not carefully done, the boost charger could show stability  
problems as well as EMI problems. Therefore, use wide and short traces for the main current path and for the  
power ground paths. The input and output capacitors as well as the inductors should be placed as close as  
possible to the IC. For the boost charger, first priority are the output capacitors, including the 0.1 uF bypass  
capacitor (CBYP), followed by CSTOR, which should be placed as close as possible between VSTOR, pin 19,  
and VSS, pin 1. Next, the input capacitor, CIN, should be placed as close as possible between VIN_DC, pin 2,  
and VSS, pin 1. Last in priority is the boost charger inductor, L1, which should be placed close to LBOOST, pin  
20, and VIN_DC, pin 2. It is best to use vias and bottom traces for connecting the inductors to their respective  
pins instead of the capacitors.  
To minimize noise pickup by the high impedance voltage setting nodes (VBAT_OV, OK_PROG, OK_HYST), the  
external resistors should be placed so that the traces connecting the midpoints of each divider to their respective  
pins are as short as possible. When laying out the non-power ground return paths (e.g. from resistors and  
CREF), it is recommended to use short traces as well, separated from the power ground traces and connected to  
VSS pin 15. This avoids ground shift problems, which can occur due to superimposition of power ground current  
and control ground current. The PowerPad should not be used as a power ground return path.  
The remaining pins are either NC pins, that should be connected to the PowerPad as shown below, or digital  
signals with minimal layout restrictions. See the EVM user's guide for an example layout (SLUUAA8).  
In order to maximize efficiency at light load, the use of voltage level setting resistors > 1 MΩ is recommended. In  
addition, the sample and hold circuit output capacitor on VREF_SAMP must hold the voltage for 16 s. During  
board assembly, contaminants such as solder flux and even some board cleaning agents can leave residue that  
may form parasitic resistors across the physical resistors/capacitors and/or from one end of a resistor/capacitor  
to ground, especially in humid, fast airflow environments. This can result in the voltage regulation and threshold  
levels changing significantly from those expected per the installed components. Therefore, it is highly  
recommended that no ground planes be poured near the voltage setting resistors or the sample and hold  
capacitor. In addition, the boards must be carefully cleaned, possibly rotated at least once during cleaning, and  
then rinsed with de-ionized water until the ionic contamination of that water is well above 50 Mohm. If this is not  
feasible, then it is recommended that the sum of the voltage setting resistors be reduced to at least 5X below the  
measured ionic contamination.  
THERMAL CONSIDERATIONS  
Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires  
special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added  
heat sinks and convection surfaces, and the presence of other heat-generating components affect the power-  
dissipation limits of a given component.  
Three basic approaches for enhancing thermal performance are listed below.  
•
•
•
Improving the power-dissipation capability of the PCB design  
Improving the thermal coupling of the component to the PCB  
Introducing airflow in the system  
For more details on how to use the thermal parameters in the Thermal Table, check the Thermal Characteristics  
Application Note (SZZA017) and the IC Package Thermal Metrics Application Note (SPRA953).  
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REVISION HISTORY  
Changes from Original (August 2013) to Revision A  
Page  
•
Changed from Product Preview to Production Data ............................................................................................................. 1  
Changes from Revision A (September 2013) to Revision B  
Page  
•
•
Changed Feature: Continuous Energy Harvesting From Input Sources as low as 120 mV To: Continuous Energy  
Harvesting From Input Sources as low as 100 mV .............................................................................................................. 1  
Changed text in the Description From: can continue to harvest energy down to VIN = 120 mV. To: can continue to  
harvest energy down to VIN = 100 mV. ................................................................................................................................. 2  
•
•
Changed Peak Input Power in the Absolute Maximum Ratings table From: MAX = 400 mW To: MAX = 510 mW ............ 4  
Changed VIN(DC) in the Recommended Operating Conditions table From: MIN = 0.12 V MAX = 4 V To: MIN = 0.1  
V MAX = 5.1 V ...................................................................................................................................................................... 4  
•
Changed VINDC in the Electrical Characteristics table From: MIN = 120 MAX = 4000 mV To: MIN = 100 mV MAX =  
5100 mV ................................................................................................................................................................................ 5  
•
•
•
Changed PIN in the Electrical Characteristics table From: MAX = 400 mW To: MAX = 510 mW ....................................... 5  
Added VDELTA, VBAT_OV - VIN(DC to the ELECTRICAL CHARACTERISTICS table ..................................................... 6  
Changed "Refer to SLUC41 for a design example" To: "Refer to SLUC463 for a design example" in the Energy  
Harvester Selection section ................................................................................................................................................ 23  
•
Changed "Refer to SLUC41 for a design example" To: "Refer to SLUC463 for a design example" in the Storage  
Element Selection section .................................................................................................................................................. 23  
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PACKAGE OPTION ADDENDUM  
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9-Dec-2013  
PACKAGING INFORMATION  
Orderable Device  
BQ25505RGRR  
BQ25505RGRT  
Status Package Type Package Pins Package  
Eco Plan  
Lead/Ball Finish  
MSL Peak Temp  
Op Temp (°C)  
Device Marking  
Samples  
Drawing  
Qty  
(1)  
(2)  
(6)  
(3)  
(4/5)  
ACTIVE  
VQFN  
VQFN  
RGR  
20  
20  
3000  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU  
Level-2-260C-1 YEAR  
BQ505  
BQ505  
ACTIVE  
RGR  
250  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU  
Level-2-260C-1 YEAR  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability  
information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that  
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between  
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight  
in homogeneous material)  
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.  
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation  
of the previous line and the two combined represent the entire Device Marking for that device.  
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish  
value exceeds the maximum column width.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
9-Dec-2013  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
Addendum-Page 2  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
9-Dec-2013  
TAPE AND REEL INFORMATION  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
(mm) W1 (mm)  
BQ25505RGRR  
BQ25505RGRT  
VQFN  
VQFN  
RGR  
RGR  
20  
20  
3000  
250  
330.0  
180.0  
12.4  
12.4  
3.75  
3.75  
3.75  
3.75  
1.15  
1.15  
8.0  
8.0  
12.0  
12.0  
Q1  
Q1  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
9-Dec-2013  
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
SPQ  
Length (mm) Width (mm) Height (mm)  
BQ25505RGRR  
BQ25505RGRT  
VQFN  
VQFN  
RGR  
RGR  
20  
20  
3000  
250  
367.0  
210.0  
367.0  
185.0  
35.0  
35.0  
Pack Materials-Page 2  
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BQ25505RGRR CAD模型

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    • BQ25505RGRR 替代型号

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    BQ25600C TI 用于并联充电应用的 I2C 单节 3A 降压电池充电器 获取价格
    BQ25600CYFFR TI 用于并联充电应用的 I2C 单节 3A 降压电池充电器 | YFF | 30 | -40 to 85 获取价格
    BQ25600CYFFT TI 用于并联充电应用的 I2C 单节 3A 降压电池充电器 | YFF | 30 | -40 to 85 获取价格
    BQ25600D TI 具有电源路径、USB 检测和 OTG 且采用 WCSP 封装的 I2C 单节 3A 降压电池充电器 获取价格

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