首页 > 暂无类别数据 > LMZ10503TZX-ADJ/NOPB

LMZ10503TZX-ADJ/NOPB

更新时间：2025-06-11 12:35:44
品牌：TI
描述：LMZ10503 3A SIMPLE SWITCHER® Power Module with 5.5V Maximum Input Voltage

PDF下载

中文翻译

CAD模型

免费 PCB/SMT

LMZ10503TZX-ADJ/NOPB 概述

LMZ10503 3A SIMPLE SWITCHER® Power Module with 5.5V Maximum Input Voltage LMZ10503 SIMPLE 3A SWITCHER®电源模块与5.5V最大输入电压 DC/DC转换器 开关式稳压器或控制器

LMZ10503TZX-ADJ/NOPB 规格参数

是否无铅： 不含铅是否Rohs认证： 不符合
生命周期：Active零件包装代码：SFM
包装说明：PFM-7针数：7
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8504.40.95.80Factory Lead Time：6 weeks
风险等级：0.85Is Samacsys：N
其他特性：ALSO OPERATES IN ADJUSTABLE MODE FROM 0.8 TO 5 V模拟集成电路 - 其他类型：SWITCHING REGULATOR
控制模式：VOLTAGE-MODE控制技术：PULSE WIDTH MODULATION
最大输入电压：5.5 V最小输入电压：2.95 V
标称输入电压：3.3 VJESD-30 代码：R-PSSO-G7
JESD-609代码：e3长度：10.16 mm
湿度敏感等级：3功能数量：1
端子数量：7最高工作温度：125 °C
最低工作温度：-40 °C最大输出电流：6.7 A
最大输出电压：5 V最小输出电压：0.8 V
封装主体材料：PLASTIC/EPOXY封装代码：HSOP
封装等效代码：SMSIP7H,.55,50封装形状：RECTANGULAR
封装形式：SMALL OUTLINE, HEAT SINK/SLUG峰值回流温度（摄氏度）：245
认证状态：Not Qualified座面最大高度：4.82 mm
子类别：Switching Regulator or Controllers表面贴装：YES
切换器配置：BUCK最大切换频率：1160 kHz
温度等级：AUTOMOTIVE端子面层：Matte Tin (Sn)
端子形式：GULL WING端子节距：1.27 mm
端子位置：SINGLE处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：9.85 mmBase Number Matches：1

LMZ10503TZX-ADJ/NOPB 数据手册

通过下载LMZ10503TZX-ADJ/NOPB数据手册来全面了解它。这个PDF文档包含了所有必要的细节，如产品概述、功能特性、引脚定义、引脚排列图等信息。

PDF下载
LMZ10503  
www.ti.com  
SNVS641H –JANUARY 2010–REVISED APRIL 2013  
LMZ10503 3A SIMPLE SWITCHER® Power Module with 5.5V Maximum Input Voltage  
Check for Samples: LMZ10503  
1
FEATURES  
PERFORMANCE BENEFITS  
2
•
Integrated Shielded Inductor  
•
•
Operates at High Ambient Temperatures  
•
Flexible Startup Sequencing using External  
Soft-Start, Tracking, and Precision Enable  
High Efficiency up to 96% Reduces System  
Heat Generation  
•
Protection Against In-Rush Currents and  
Faults Such as Input UVLO and Output Short-  
Circuit  
•
•
Low Radiated Emissions (EMI) Complies with  
EN55022 Class B Standard  
(2)  
Low Output Voltage Ripple of 10 mV Allows  
for Powering Noise-Sensitive Transceiver and  
Signaling ICs  
•
•
•
-40°C to +125°C Junction Temperature  
Operating Range  
Single Exposed pad and Standard Pinout for  
Easy Mounting and Manufacturing  
•
Fast Transient Response for Powering FPGAs  
and ASICs  
Pin-to-Pin Compatible with  
–
–
LMZ10504 (4A/20W max)  
LMZ10505 (5A/25W max)  
ELECTRICAL SPECIFICATIONS  
•
•
•
•
•
15W Maximum Total Output Power  
Up to 3A Output Current  
•
Fully Enabled for WEBENCH® and Power  
Designer  
Input Voltage Range 2.95V to 5.5V  
Output Voltage Range 0.8V to 5V  
APPLICATIONS  
±1.63% Feedback Voltage Accuracy Over  
Temperature  
•
Point-of-Load Conversions from 3.3V and 5V  
Rails  
•
Efficiency up to 96%  
•
•
Space Constrained Applications  
Extreme Temperatures/no Air Flow  
Environments  
DESCRIPTION  
The LMZ10503 SIMPLE SWITCHER® power module  
is a complete, easy-to-use DC-DC solution capable of  
driving up to a 3A load with exceptional power  
conversion efficiency, output voltage accuracy, line  
and load regulation. The LMZ10503 is available in an  
•
Noise Sensitive Applications (i.e. Transceiver,  
Medical)  
innovative  
package  
that  
enhances  
thermal  
performance and allows for hand or machine  
soldering.  
Figure 1. PFM 7 Pin Package  
10.16 x 13.77 x 4.57 mm (0.4 x 0.39 x 0.18 in)  
(1)  
θJA = 20°C/W, θJC = 1.9°C/W  
RoHS Compliant  
(1) θ JA measured on a 2.25” x 2.25” (5.8 cm x 5.8 cm) four layer  
board, with one ounce copper, thirty six 10mil thermal vias, no  
air flow, and 1W power dissipation. Refer to PCB Layout  
Diagrams or Evaluation Board Application Note: AN-2022  
(SNVA421).  
(2) EN 55022:2006, +A1:2007, FCC Part 15 Subpart B: 2007.  
See Table 9 and layout for information on device under test.  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
All trademarks are the property of their respective owners.  
2
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2010–2013, Texas Instruments Incorporated  
LMZ10503  
SNVS641H –JANUARY 2010–REVISED APRIL 2013  
www.ti.com  
DESCRIPTION (CONTINUED)  
The LMZ10503 can accept an input voltage rail between 2.95V and 5.5V and deliver an adjustable and highly  
accurate output voltage as low as 0.8V. One megahertz fixed frequency PWM switching provides a predictable  
EMI characteristic. Two external compensation components can be adjusted to set the fastest response time,  
while allowing the option to use ceramic and/or electrolytic output capacitors. Externally programmable soft-start  
capacitor facilitates controlled startup. The LMZ10503 is a reliable and robust solution with the following features:  
lossless cycle-by-cycle peak current limit to protect for over current or short-circuit fault, thermal shutdown, input  
under-voltage lock-out, and pre-biased startup.  
System Performance  
Current Derating (VOUT = 3.3V)  
Efficiency (VOUT = 3.3V)  
Figure 2.  
Figure 3.  
Radiated Emissions (EN 55022, Class B)  
Figure 4.  
Typical Application Circuit  
V
V
OUT  
IN  
6, 7  
5
VOUT  
1
2
LMZ10503  
VIN  
EN  
C
O
FB  
C
in  
SS  
GND  
4, EP  
R
fbt  
3
C
SS  
C
R
comp  
comp  
R
fbb  
2
Submit Documentation Feedback  
Copyright © 2010–2013, Texas Instruments Incorporated  
Product Folder Links: LMZ10503  
LMZ10503  
www.ti.com  
SNVS641H –JANUARY 2010–REVISED APRIL 2013  
Connection Diagram  
VOUT  
VOUT  
FB  
7
6
5
4
3
2
1
Exposed Pad  
Connect to GND  
GND  
SS  
EN  
VIN  
Figure 5. Top View  
7-Lead PFM  
Package Number NDW0007A  
PIN DESCRIPTIONS  
Pin Number  
Name  
Description  
1
VIN  
Power supply input. A low ESR input capacitance should be located as close as possible to the VIN pin and  
exposed pad (EP).  
2
3
EN  
SS  
Active high enable input for the device.  
Soft-start control pin. An internal 2 µA current source charges an external capacitor connected between SS  
and GND pins to set the output voltage ramp rate during startup. The SS pin can also be used to configure  
the tracking feature.  
4
5
GND  
FB  
Power ground and signal ground. Provide a direct connection to the EP. Place the bottom feedback resistor  
as close as possible to GND and FB pin.  
Feedback pin. This is the inverting input of the error amplifier used for sensing the output voltage. Keep the  
copper area of this node small.  
6, 7  
EP  
VOUT  
The output terminal of the internal inductor. Connect the output filter capacitor between VOUT pin and EP.  
Exposed  
Pad  
Exposed pad is used as a thermal connection to remove heat from the device. Connect this pad to the PC  
board ground plane in order to reduce thermal resistance value. EP must also provide a direct electrical  
connection to the input and output capacitors ground terminals. Connect EP to pin 4.  
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam  
during storage or handling to prevent electrostatic damage to the MOS gates.  
Absolute Maximum Ratings(1)(2)  
VIN, VOUT, EN, FB, SS to GND  
ESD Susceptibility(3)  
-0.3V to 6.0V  
±2 kV  
Power Dissipation  
Internally Limited  
150°C  
Junction Temperature  
Storage Temperature Range  
-65°C to 150°C  
245°C  
Peak Reflow Case Temperature  
(30 sec)  
For soldering specifications, refer to the following document: www.ti.com/lit/snoa549c  
(1) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which  
operation of the device is intended to be functional. For ensured specifications and test conditions, see the Electrical Characteristics.  
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and  
specifications.  
(3) The human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor into each pin. Test method is per JESD22-AI14S.  
Operating Ratings(1)  
VIN to GND  
2.95V to 5.5V  
Junction Temperature (TJ)  
-40°C to 125°C  
(1) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which  
operation of the device is intended to be functional. For ensured specifications and test conditions, see the Electrical Characteristics.  
Copyright © 2010–2013, Texas Instruments Incorporated  
Submit Documentation Feedback  
3
Product Folder Links: LMZ10503  
LMZ10503  
SNVS641H –JANUARY 2010–REVISED APRIL 2013  
www.ti.com  
Electrical Characteristics  
Specifications with standard typeface are for TJ = 25°C only; limits in bold face type apply over the operating junction  
temperature range TJ of -40°C to 125°C. Minimum and maximum limits are ensured through test, design, or statistical  
correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes  
only. VIN = VEN = 3.3V, unless otherwise indicated in the conditions column.  
Symbol  
Parameter  
Conditions  
Min(1)  
Typ(2)  
Max(1) Units  
SYSTEM PARAMETERS  
V FB  
Total Feedback Voltage Variation  
VIN = 2.95V to 5.5V  
VOUT = 2.5V  
IOUT = 0A to 3A  
0.78  
0.8  
0.82  
V
Including Line and Load Regulation  
Feedback Voltage Variation  
Feedback Voltage Variation  
V FB  
V FB  
VIN = 3.3V, VOUT = 2.5V  
IOUT = 0A  
0.787  
0.785  
0.8  
0.812  
0.81  
2.95  
V
V
V
VIN = 3.3V, VOUT = 2.5V  
IOUT = 3A  
0.798  
VIN(UVLO)  
Input UVLO Threshold (Measured at VIN Rising  
pin)  
2.6  
2.4  
2
Falling  
1.95  
3.8  
ISS  
Soft-Start Current  
Charging Current  
µA  
mA  
µA  
A
IQ  
Non-Switching Input Current  
Shut Down Quiescent Current  
Output Current Limit (Average Current)  
Frequency Fold-back  
VFB = 1V  
1.7  
260  
5.2  
250  
3
ISD  
VIN = 5.5V, VEN = 0V  
VOUT = 2.5V  
500  
6.7  
IOCL  
fFB  
In current limit  
kHz  
PWM SECTION  
fSW  
Drange  
Switching Frequency  
750  
0
1000  
1160  
100  
kHz  
%
PWM Duty Cycle Range  
ENABLE CONTROL  
VEN-IH  
EN Pin Rising Threshold  
EN Pin Falling Threshold  
1.23  
1.06  
1.8  
V
V
VEN-IF  
0.8  
THERMAL CONTROL  
TSD  
TJ for Thermal Shutdown  
145  
10  
°C  
°C  
TSD-HYS  
Hysteresis for Thermal Shutdown  
THERMAL RESISTANCE  
(3)  
θJA  
θJC  
Junction to Ambient  
Junction to Case  
See  
20  
°C/W  
°C/W  
No air flow  
1.9  
PERFORMANCE PARAMETERS  
ΔVOUT  
Output Voltage Ripple  
Refer to Table 3  
VOUT = 2.5V  
Bandwidth Limit = 2 MHz  
7
5
mVpk-  
pk  
ΔVOUT  
Output Voltage Ripple  
Refer to Table 5  
mVpk-  
Bandwidth Limit = 20 MHz  
pk  
ΔVFB / VFB  
ΔVOUT / VOUT  
Feedback Voltage Line Regulation  
Output Voltage Line Regulation  
ΔVIN = 2.95V to 5.5V  
IOUT = 0A  
0.04  
0.04  
%
%
ΔVIN = 2.95V to 5.5V  
IOUT = 0A, VOUT = 2.5V  
ΔVFB / VFB  
Feedback Voltage Load Regulation  
Output Voltage Load Regulation  
IOUT = 0A to 3A  
0.25  
0.25  
%
%
ΔVOUT / VOUT  
IOUT = 0A to 3A  
VOUT = 2.5V  
(1) Min and Max limits are 100% production tested at an ambient temperature (TA) of 25°C. Limits over the operating temperature range are  
ensured through correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality  
Level (AOQL).  
(2) Typical numbers are at 25°C and represent the most likely parametric norm.  
(3) θ JA measured on a 2.25” x 2.25” (5.8 cm x 5.8 cm) four layer board, with one ounce copper, thirty six 10mil thermal vias, no air flow,  
and 1W power dissipation. Refer to PCB Layout Diagrams or Evaluation Board Application Note: AN-2022 (SNVA421).  
4
Submit Documentation Feedback  
Copyright © 2010–2013, Texas Instruments Incorporated  
Product Folder Links: LMZ10503  
LMZ10503  
www.ti.com  
SNVS641H –JANUARY 2010–REVISED APRIL 2013  
Electrical Characteristics (continued)  
Specifications with standard typeface are for TJ = 25°C only; limits in bold face type apply over the operating junction  
temperature range TJ of -40°C to 125°C. Minimum and maximum limits are ensured through test, design, or statistical  
correlation. Typical values represent the most likely parametric norm at TJ = 25°C, and are provided for reference purposes  
only. VIN = VEN = 3.3V, unless otherwise indicated in the conditions column.  
Symbol  
Efficiency  
Parameter  
Conditions  
Min(1)  
Typ(2)  
Max(1) Units  
η
Peak Efficiency (1A) VIN = 5V  
VOUT = 3.3V  
VOUT = 2.5V  
VOUT = 1.8V  
VOUT = 1.5V  
VOUT = 1.2V  
VOUT = 0.8V  
VOUT = 2.5V  
VOUT = 1.8V  
VOUT = 1.5V  
VOUT = 1.2V  
VOUT = 0.8V  
VOUT = 3.3V  
VOUT = 2.5V  
VOUT = 1.8V  
VOUT = 1.5V  
VOUT = 1.2V  
VOUT = 0.8V  
VOUT = 2.5V  
VOUT = 1.8V  
VOUT = 1.5V  
VOUT = 1.2V  
VOUT = 0.8V  
96.3  
94.9  
93.3  
92.2  
90.5  
86.9  
95.7  
94.0  
92.9  
91.3  
87.9  
94.8  
93  
%
η
η
Peak Efficiency (1A) VIN = 3.3V  
%
%
%
Full Load Efficiency (3A) VIN = 5V  
90.8  
89.3  
87.1  
82.3  
92.4  
89.8  
88.2  
85.9  
80.8  
η
Full Load Efficiency (3A) VIN = 3.3V  
Copyright © 2010–2013, Texas Instruments Incorporated  
Submit Documentation Feedback  
5
Product Folder Links: LMZ10503  
LMZ10503  
SNVS641H –JANUARY 2010–REVISED APRIL 2013  
www.ti.com  
Typical Performance Characteristics  
Unless otherwise specified, the following conditions apply: VIN = VEN = 5.0V, CIN is 47 µF 10V X5R ceramic capacitor; TAMBIENT  
= 25°C for efficiency curves and waveforms.  
Load Transient Response  
VIN = 3.3V, VOUT = 2.5V, IOUT = 0.3A to 2.7A to 0.3A step  
20 MHz Bandwidth Limited  
Load Transient Response  
VIN = 5.0V, VOUT = 2.5V, IOUT = 0.3A to 2.7A to 0.3A step  
20 MHz Bandwidth Limited  
Refer to Table 5 for BOM, includes optional components  
Refer to Table 5 for BOM, includes optional components  
Figure 6.  
Figure 7.  
Output Voltage Ripple  
VIN = 3.3V, VOUT = 2.5V, IOUT = 3A, 20 mV/DIV  
Refer to Table 5 for BOM  
Output Voltage Ripple  
VIN = 5.0V, VOUT = 2.5V, IOUT = 3A, 20 mV/DIV  
Refer to Table 5 for BOM  
Figure 8.  
Figure 9.  
6
Submit Documentation Feedback  
Copyright © 2010–2013, Texas Instruments Incorporated  
Product Folder Links: LMZ10503  
 
LMZ10503  
www.ti.com  
SNVS641H –JANUARY 2010–REVISED APRIL 2013  
Typical Performance Characteristics (continued)  
Unless otherwise specified, the following conditions apply: VIN = VEN = 5.0V, CIN is 47 µF 10V X5R ceramic capacitor; TAMBIENT  
= 25°C for efficiency curves and waveforms.  
Efficiency  
VOUT = 3.3V  
Efficiency  
VOUT = 2.5V  
Figure 10.  
Figure 11.  
Efficiency  
VOUT = 1.8V  
Efficiency  
VOUT = 1.5V  
Figure 12.  
Figure 13.  
Efficiency  
VOUT = 1.2V  
Efficiency  
VOUT = 0.8V  
Figure 14.  
Figure 15.  
Copyright © 2010–2013, Texas Instruments Incorporated  
Submit Documentation Feedback  
7
Product Folder Links: LMZ10503  
LMZ10503  
SNVS641H –JANUARY 2010–REVISED APRIL 2013  
www.ti.com  
Typical Performance Characteristics (continued)  
Unless otherwise specified, the following conditions apply: VIN = VEN = 5.0V, CIN is 47 µF 10V X5R ceramic capacitor; TAMBIENT  
= 25°C for efficiency curves and waveforms.  
Current Derating  
VIN = 5V, θJA = 20°C / W  
Current Derating  
VIN = 3.3V, θJA = 20°C / W  
Figure 16.  
Figure 17.  
Radiated Emissions (EN55022, Class B)  
VIN = 5V, VOUT = 2.5V, IOUT = 3A  
Evaluation board  
Startup  
VOUT = 2.5V, IOUT = 0A  
Figure 18.  
Figure 19.  
Pre-biased Startup  
VOUT = 2.5V, IOUT = 0A  
Figure 20.  
8
Submit Documentation Feedback  
Copyright © 2010–2013, Texas Instruments Incorporated  
Product Folder Links: LMZ10503  
LMZ10503  
www.ti.com  
SNVS641H –JANUARY 2010–REVISED APRIL 2013  
Block Diagram  
VIN  
1
1W  
2.2 mF  
2
3
2.2 mF  
2.2 mH  
EN  
SS  
Voltage  
Mode  
Control  
6, 7  
VOUT  
5
4, EP  
GND  
FB  
DESIGN GUIDELINE AND OPERATING DESCRIPTION  
Design Steps  
LMZ10503 is fully supported by Webench® and offers the following: component selection, performance,  
electrical, and thermal simulations as well as the Build-It board, for a reduced design time. On the other hand, all  
external components can be calculated by following the design procedure below.  
1. Determine the input voltage and output voltage. Also, make note of the ripple voltage and voltage transient  
requirements.  
2. Determine the necessary input and output capacitance.  
3. Calculate the feedback resistor divider.  
4. Select the optimized compensation component values.  
5. Estimate the power dissipation and board thermal requirements.  
6. Follow the PCB design guideline.  
7. Learn about the LMZ10503 features such as enable, input UVLO, soft-start, tracking, pre-biased startup,  
current limit, and thermal shutdown.  
Design Example  
For this example the following application parameters exist.  
•
•
•
•
•
VIN = 5V  
VOUT = 2.5V  
IOUT = 3A  
ΔVOUT = 20 mVpk-pk  
ΔVo_tran = ±20 mVpk-pk  
Input Capacitor Selection  
A 22 µF or 47 µF high quality dielectric (X5R, X7R) ceramic capacitor rated at twice the maximum input voltage  
is typically sufficient. The input capacitor must be placed as close as possible to the VIN pin and GND exposed  
pad to substantially eliminate the parasitic effects of any stray inductance or resistance on the PC board and  
supply lines.  
Copyright © 2010–2013, Texas Instruments Incorporated  
Submit Documentation Feedback  
9
Product Folder Links: LMZ10503  
LMZ10503  
SNVS641H –JANUARY 2010–REVISED APRIL 2013  
www.ti.com  
Neglecting capacitor equivalent series resistance (ESR), the resultant input capacitor AC ripple voltage is a  
triangular waveform. The minimum input capacitance for a given peak-to-peak value (ΔVIN) of VIN is specified as  
follows:  
IOUT x D x (1 - D)  
Cin  
8
fSW x DVIN  
(1)  
(2)  
where the PWM duty cycle, D, is given by:  
VOUT  
D =  
VIN  
If ΔVIN is 1% of VIN, this equals to 50 mV and fSW = 1 MHz  
3A x (2.5V  
5V ) x (1 -  
)
5V  
2.5V  
Cin  
8
8 15 µF  
1 MHz x 50 mV  
(3)  
A second criteria before finalizing the Cin bypass capacitor is the RMS current capability. The necessary RMS  
current rating of the input capacitor to a buck regulator can be estimated by  
ICin(RMS) = IOUT x D(1-D)  
(4)  
2.5V  
5V  
2.5V  
5V  
’
◊
≈
1 -  
ICin(RMS) = 3A x  
= 1.5A  
«
(5)  
With this high AC current present in the input capacitor, the RMS current rating becomes an important  
parameter. The maximum input capacitor ripple voltage and RMS current occur at 50% duty cycle. Select an  
input capacitor rated for at least the maximum calculated ICin(RMS)  
.
Additional bulk capacitance with higher ESR may be required to damp any resonance effects of the input  
capacitance and parasitic inductance.  
Output Capacitor Selection  
In general, 22 µF to 100 µF high quality dielectric (X5R, X7R) ceramic capacitor rated at twice the maximum  
output voltage is sufficient given the optimal high frequency characteristics and low ESR of ceramic dielectrics.  
Although, the output capacitor can also be of electrolytic chemistry for increased capacitance density.  
Two output capacitance equations are required to determine the minimum output capacitance. One equation  
determines the output capacitance (CO) based on PWM ripple voltage. The second equation determines CO  
based on the load transient characteristics. Select the largest capacitance value of the two.  
The minimum capacitance, given the maximum output voltage ripple (ΔVOUT) requirement, is determined by the  
following equation:  
DiL  
CO  
í
8 x fSW x [DVOUT œ (DiL x RESR)]  
(6)  
Where the peak to peak inductor current ripple (ΔiL) is equal to:  
(VIN - VOUT) x D  
DiL =  
L x fSW  
(7)  
RESR is the total output capacitor ESR, L is the inductance value of the internal power inductor, where L = 2.2  
µH, and fSW = 1 MHz. Therefore, per the design example:  
2.5V  
(5V œ 2.5V) x  
5V  
2.2 mH x 1 MHz  
= 568 mA  
DiL =  
(8)  
The minimum output capacitance requirement due to the PWM ripple voltage is:  
568 mA  
CO  
í
8 x 1 MHz x [20 mV œ (568 mA x 3 mÖ)]  
(9)  
CO í 4 mF  
(10)  
Three miliohms is a typical RESR value for ceramic capacitors.  
The following equation provides a good first pass capacitance requirement for a load transient:  
10  
Submit Documentation Feedback  
Copyright © 2010–2013, Texas Instruments Incorporated  
Product Folder Links: LMZ10503  
LMZ10503  
www.ti.com  
SNVS641H –JANUARY 2010–REVISED APRIL 2013  
Istep x VFB x L x VIN  
CO  
í
4 x VOUT x (VIN - VOUT) x DVo_tran  
(11)  
Where Istep is the peak to peak load step (for this example Istep = 10% to 90% of the maximum load), VFB = 0.8V,  
and ΔVo_tran is the maximum output voltage deviation, which is ±20 mV.  
Therefore the capacitance requirement for the given design parameters is:  
2.4A x 0.8V x 2.2 µH x 5V  
Co 8  
4 x 2.5V x (5V - 2.5V) x 20 mV  
(12)  
Co 8 42 µF  
(13)  
In this particular design the output capacitance is determined by the load transient requirements.  
Table 1 lists some examples of commercially available capacitors that can be used with the LMZ10503.  
Table 1. Recommended Output Filter Capacitors  
CO (µF)  
22  
Voltage (V), RESR (mΩ)  
6.3, < 5  
Make  
Manufacturer  
TDK  
Part Number  
C3216X5R0J226M  
C3216X5R0J476M  
C3225X5R0J476M  
C3225X5R1A476M  
C3225X5R0J107M  
TPSD157M006#0050  
6TPE100MPB2  
Case Size  
1206  
Ceramic, X5R  
Ceramic, X5R  
Ceramic, X5R  
Ceramic, X5R  
Ceramic, X5R  
Tantalum  
47  
6.3, < 5  
TDK  
1206  
47  
6.3, < 5  
TDK  
1210  
47  
10.0, < 5  
6.3, < 5  
TDK  
1210  
100  
100  
100  
150  
330  
470  
TDK  
1210  
6.3, 50  
AVX  
D, 7.5 x 4.3 x 2.9 mm  
B2, 3.5 x 2.8 x 1.9 mm  
C2, 6.0 x 3.2 x 1.8 mm  
D3L, 7.3 x 4.3 x 2.8 mm  
E, 7.3 x 4.3 x 4.1 mm  
6.3, 25  
Organic Polymer  
Organic Polymer  
Organic Polymer  
Niobium Oxide  
Sanyo  
Sanyo  
Sanyo  
AVX  
6.3, 18  
6TPE150MIC2  
6.3, 18  
6TPE330MIL  
6.3, 23  
NOME37M006#0023  
Output Voltage Setting  
A resistor divider network from VOUT to the FB pin determines the desired output voltage as follows:  
Rfbt + Rfbb  
VOUT = 0.8V x  
Rfbb  
(14)  
Rfbt is defined based on the voltage loop requirements and Rfbb is then selected for the desired output voltage.  
Resistors are normally selected as 0.5% or 1% tolerance. Higher accuracy resistors such as 0.1% are also  
available.  
The feedback voltage (at VOUT = 2.5V) is accurate to within -2.5% / +2.5% over temperature and over line and  
load regulation. Additionally, the LMZ10503 contains error nulling circuitry to substantially eliminate the feedback  
voltage variation over temperature as well as the long term aging effects of the internal amplifiers. In addition the  
zero nulling circuit dramatically reduces the 1/f noise of the bandgap amplifier and reference. The manifestation  
of this circuit action is that the duty cycle will have two slightly different but distinct operating points, each evident  
every other switching cycle.  
Loop Compensation  
The LMZ10503 preserves flexibility by integrating the control components around the internal error amplifier while  
utilizing three small external compensation components from VOUT to FB. An integrated type II (two pole, one  
zero) voltage-mode compensation network is featured. To ensure stability, an external resistor and small value  
capacitor can be added across the upper feedback resistor as a pole-zero pair to complete a type III (three pole,  
two zero) compensation network. The compensation components recommended in Table 2 provide type III  
compensation at an optimal control loop performance. The typical phase margin is 45° with a bandwidth of 80  
kHz. Calculated output capacitance values not listed in Table 2 should be verified before designing into  
production. A detailed application note is available to provide verification support, AN-2013 (SNVA417). In  
general, calculated output capacitance values below the suggested value will have reduced phase margin and  
higher control loop bandwidth. Output capacitance values above the suggested values will experience a lower  
Copyright © 2010–2013, Texas Instruments Incorporated  
Submit Documentation Feedback  
11  
Product Folder Links: LMZ10503  
 
LMZ10503  
SNVS641H –JANUARY 2010–REVISED APRIL 2013  
www.ti.com  
bandwidth and increased phase margin. Higher bandwidth is associated with faster system response to sudden  
changes such as load transients. Phase margin changes the characteristics of the response. Lower phase  
margin is associated with underdamped ringing and higher phase margin is associated with overdamped  
response. Losing all phase margin will cause the system to be unstable; an optimized area of operation is 30° to  
60° of phase margin, with a bandwidth of 100 kHz ±20 kHz.  
V
IN  
VOUT  
VIN  
EN  
C
comp  
R
fbt  
LMZ10503  
R
comp  
FB  
GND  
R
fbb  
Table 2. LMZ10503 Compensation Component Values  
VIN (V)  
CO (µF)  
ESR (mΩ)  
Rfbt (kΩ)(1)  
Ccomp (pF)(1)  
Rcomp (kΩ)(1)  
Min  
2
Max  
20  
20  
10  
5
22  
143  
100  
71.5  
56.2  
59  
39  
100  
180  
270  
270  
270  
360  
360  
56.2  
150  
270  
360  
360  
360  
470  
470  
8.06  
8.25  
4.32  
2.1  
47  
2
100  
150  
150  
150  
220  
220  
22  
1
1
5.0  
10  
26  
15  
31  
2
25  
50  
30  
60  
20  
20  
10  
5
10.8  
23.7  
14  
66.5  
53.6  
59  
30.1  
5.62  
5.49  
2.8  
100  
66.5  
45.3  
40.2  
40.2  
43.2  
40.2  
40.2  
47  
2
100  
150  
150  
150  
220  
220  
1
1
1.5  
3.3  
10  
26  
15  
31  
25  
50  
30  
60  
7.32  
15.4  
10.5  
20.5  
(1) In the special case where the output voltage is 0.8V, it is recommended to remove Rfbb and keep Rfbt, Rcomp, and Ccomp for a type III  
compensation.  
Estimate Power Dissipation And Board Thermal Requirements  
Use the current derating curves in the Typical Performance Characteristics section to obtain an estimate of  
power loss (PIC_LOSS). For the design case of VIN = 5V, VOUT = 2.5V, IOUT = 3A, TA(MAX) = 85°C , and TJ(MAX)  
125°C, the device must see a thermal resistance from case to ambient (θCA) of less than:  
TJ(MAX) - TA(MAX)  
=
- qJC  
qCA  
<
PIC_LOSS  
(15)  
(16)  
Given the typical thermal resistance from junction to case (θJC) to be 1.9°C/W (typ.). Continuously operating at a  
TJ greater than 125°C will have a shorten life span.  
To reach θCA = 69.5°C/W, the PCB is required to dissipate heat effectively. With no airflow and no external heat,  
a good estimate of the required board area covered by 1oz. copper on both the top and bottom metal layers is:  
500 °C x cm 2  
Board Area_cm2 8  
.
qCA  
W
(17)  
12  
Submit Documentation Feedback  
Copyright © 2010–2013, Texas Instruments Incorporated  
Product Folder Links: LMZ10503  
LMZ10503  
www.ti.com  
SNVS641H –JANUARY 2010–REVISED APRIL 2013  
(18)  
As a result, approximately 7.2 square cm of 1oz. copper on top and bottom layers is required for the PCB design.  
The PCB copper heat sink must be connected to the exposed pad (EP). Approximately thirty six, 10mils (254  
μm) thermal vias spaced 59mils (1.5 mm) apart must connect the top copper to the bottom copper. For an  
extended discussion and formulations of thermal rules of thumb, refer to AN-2020 (SNVA419). For an example of  
a high thermal performance PCB layout with θJA of 20°C/W, refer to the evaluation board application note AN-  
2022 (SNVA421) and for results of a study of the effects of the PCB designs, refer to AN-2026 (SNVA424).  
PC Board Layout Guidelines  
PC board layout is an important part of DC-DC converter design. Poor board layout can disrupt the performance  
of a DC-DC converter and surrounding circuitry by contributing to EMI, ground bounce and resistive voltage drop  
in the traces. These can send erroneous signals to the DC-DC converter resulting in poor regulation or instability.  
Good layout can be implemented by following a few simple design rules.  
Figure 21. High Current Loops  
1. Minimize area of switched current loops.  
From an EMI reduction standpoint, it is imperative to minimize the high di/dt current paths. The high current that  
does not overlap contains high di/dt, see Figure 21. Therefore physically place input capacitor (Cin1) as close as  
possible to the LMZ10503 VIN pin and GND exposed pad to avoid observable high frequency noise on the  
output pin. This will minimize the high di/dt area and reduce radiated EMI. Additionally, grounding for both the  
input and output capacitor should consist of a localized top side plane that connects to the GND exposed pad  
(EP).  
2. Have a single point ground.  
The ground connections for the feedback, soft-start, and enable components should be routed only to the GND  
pin of the device. This prevents any switched or load currents from flowing in the analog ground traces. If not  
properly placed, poor grounding can result in degraded load regulation or erratic output voltage ripple behavior.  
Provide the single point ground connection from pin 4 to EP.  
3. Minimize trace length to the FB pin.  
Both feedback resistors, Rfbt and Rfbb, and the compensation components, Rcomp and Ccomp, should be located  
close to the FB pin. Since the FB node is high impedance, keep the copper area as small as possible. This is  
most important as relatively high value resistors are used to set the output voltage.  
4. Make input and output bus connections as wide as possible.  
This reduces any voltage drops on the input or output of the converter and maximizes efficiency. To optimize  
voltage accuracy at the load, ensure that a separate feedback voltage sense trace is made at the load. Doing so  
will correct for voltage drops and provide optimum output accuracy.  
5. Provide adequate device heat-sinking.  
Copyright © 2010–2013, Texas Instruments Incorporated  
Submit Documentation Feedback  
13  
Product Folder Links: LMZ10503  
 
LMZ10503  
SNVS641H –JANUARY 2010–REVISED APRIL 2013  
www.ti.com  
Use an array of heat-sinking vias to connect the exposed pad to the ground plane on the bottom PCB layer. If  
the PCB has multiple copper layers, thermal vias can also be employed to make connection to inner layer heat-  
spreading ground planes. For best results use a 6 x 6 via array with minimum via diameter of 10mils (254 μm)  
thermal vias spaced 59mils (1.5 mm). Ensure enough copper area is used for heat-sinking to keep the junction  
temperature below 125°C.  
Additional Features  
Enable  
The LMZ10503 features an enable (EN) pin and associated comparator to allow the user to easily sequence the  
LMZ10503 from an external voltage rail, or to manually set the input UVLO threshold. The turn-on or rising  
threshold and hysteresis for this comparator are typically 1.23V and 0.15V respectively. The precise reference for  
the enable comparator allows the user to ensure that the LMZ10503 will be disabled when the system demands  
it to be.  
The EN pin should not be left floating. For always-on operation, connect EN to VIN.  
Enable AND UVLO  
Using a resistor divider from VIN to EN as shown in the schematic diagram below, the input voltage at which the  
part begins switching can be increased above the normal input UVLO level according to  
Rent + Renb  
VIN(UVLO) = 1.23V x  
Renb  
(19)  
For example, suppose that the required input UVLO level is 3.69V. Choosing Renb = 10 kΩ, then we calculate  
Rent = 20 kΩ.  
V
IN  
VIN  
EN  
LMZ10503  
R
ent  
Cin1  
R
enb  
GND  
Alternatively, the EN pin can be driven from another voltage source to cater to system sequencing requirements  
commonly found in FPGA and other multi-rail applications. The following schematic shows an LMZ10503 that is  
sequenced to start based on the voltage level of a master system rail (VOUT1).  
Master Power Supply  
V
OUT1  
V
IN  
V
VIN  
EN  
OUT2  
VOUT  
R
ent  
LMZ10503  
C
O1  
C
in1  
R
enb  
GND  
Soft-Start  
The LMZ10503 begins to operate when both the VIN and EN, voltages exceed the rising UVLO and enable  
thresholds, respectively. A controlled soft-start eliminates inrush currents during startup and allows the user more  
control and flexibility when sequencing the LMZ10503 with other power supplies.  
In the event of either VIN or EN decreasing below the falling UVLO or enable threshold respectively, the voltage  
on the soft-start pin is collapsed by discharging the soft-start capacitor by a 14 µA (typ.) current sink to ground.  
14  
Submit Documentation Feedback  
Copyright © 2010–2013, Texas Instruments Incorporated  
Product Folder Links: LMZ10503  
LMZ10503  
www.ti.com  
SNVS641H –JANUARY 2010–REVISED APRIL 2013  
Soft-Start Capacitor  
Determine the soft-start capacitance with the following relationship  
tSS x ISS  
VFB  
CSS  
=
(20)  
where VFB is the internal reference voltage (nominally 0.8V), ISS is the soft-start charging current (nominally 2 µA)  
and CSS is the external soft-start capacitance.  
Thus, the required soft-start capacitor per unit output voltage startup time is given by  
CSS = 2.5 nF / ms  
(21)  
For example, a 4 ms soft-start time will yield a 10 nF capacitance. The minimum soft-start capacitance is 680 pF.  
Tracking  
The LMZ10503 can track the output of a master power supply during soft-start by connecting a resistor divider to  
the SS pin. In this way, the output voltage slew rate of the LMZ10503 will be controlled by a master supply for  
loads that require precise sequencing. When the tracking function is used, a small value soft-start capacitor  
should be connected to the SS pin to alleviate output voltage overshoot when recovering from a current limit  
fault.  
Master Power  
Supply  
V
OUT1  
V
IN  
V
VIN  
OUT2  
VOUT  
R
trkt  
EN  
SS  
LMZ10503  
C
O1  
C
in1  
V
SS  
R
trkb  
GND  
Tracking - Equal Soft-Start Time  
One way to use the tracking feature is to design the tracking resistor divider so that the master supply output  
voltage, VOUT1, and the LMZ10503 output voltage, VOUT2, both rise together and reach their target values at the  
same time. This is termed ratiometric startup. For this case, the equation governing the values of tracking divider  
resistors Rtrkb and Rtrkt is given by  
Rtrkt  
Rtrkb  
=
VOUT1 -1.0V  
(22)  
The above equation includes an offset voltage, of 200 mV, to ensure that the final value of the SS pin voltage  
exceeds the reference voltage of the LMZ10503. This offset will cause the LMZ10503 output voltage to reach  
regulation slightly before the master supply. A value of 33 kΩ 1% is recommended for Rtrkt as a compromise  
between high precision and low quiescent current through the divider while minimizing the effect of the 2 µA soft-  
start current source.  
For example, if the master supply voltage VOUT1 is 3.3V and the LMZ10503 output voltage was 1.8V, then the  
value of Rtrkb needed to give the two supplies identical soft-start times would be 14.3 kΩ. A timing diagram for  
this example, the equal soft-start time case, is shown below.  
Copyright © 2010–2013, Texas Instruments Incorporated  
Submit Documentation Feedback  
15  
Product Folder Links: LMZ10503  
LMZ10503  
SNVS641H –JANUARY 2010–REVISED APRIL 2013  
www.ti.com  
RATIOMETRIC STARTUP  
VOUT1  
VOUT2  
EN  
TIME  
Tracking - Equal Slew Rates  
Alternatively, the tracking feature can be used to have similar output voltage ramp rates. This is referred to as  
simultaneous startup. In this case, the tracking resistors can be determined based on the following equation  
0.8V  
VOUT2 - 0.8V  
Rtrkb  
=
x Rtrkt  
(23)  
(24)  
and to ensure proper overdrive of the SS pin  
VOUT2 < 0.8 x V OUT1  
For the example case of VOUT1 = 5V and VOUT2 = 2.5V, with Rtrkt set to 33 kΩ as before, Rtrkb is calculated from  
the above equation to be 15.5 kΩ. A timing diagram for the case of equal slew rates is shown below.  
SIMULTANEOUS STARTUP  
VOUT1  
VOUT2  
EN  
TIME  
Pre-Bias Startup Capability  
At startup, the LMZ10503 is in a pre-biased state when the output voltage is greater than zero. This often occurs  
in many multi-rail applications such as when powering an ASIC, FPGA, or DSP. The output can be pre-biased in  
these applications through parasitic conduction paths from one supply rail to another. Even though the  
LMZ10503 is a synchronous converter, it will not pull the output low when a pre-bias condition exists. The  
LMZ10503 will not sink current during startup until the soft-start voltage exceeds the voltage on the FB pin. Since  
the device does not sink current it protects the load from damage that might otherwise occur if current is  
conducted through the parasitic paths of the load.  
Current Limit  
When a current greater than the output current limit (IOCL) is sensed, the on-time is immediately terminated and  
the low side MOSFET is activated. The low side MOSFET stays on for the entire next four switching cycles.  
During these skipped pulses, the voltage on the soft-start pin is reduced by discharging the soft-start capacitor by  
a current sink on the soft-start pin of nominally 14 µA. Subsequent over-current events will drain more and more  
charge from the soft-start capacitor, effectively decreasing the reference voltage as the output droops due to the  
pulse skipping. Reactivation of the soft-start circuitry ensures that when the over-current situation is removed, the  
part will resume normal operation smoothly.  
16  
Submit Documentation Feedback  
Copyright © 2010–2013, Texas Instruments Incorporated  
Product Folder Links: LMZ10503  
LMZ10503  
www.ti.com  
SNVS641H –JANUARY 2010–REVISED APRIL 2013  
Over-Temperature Protection  
When the LMZ10503 senses a junction temperature greater than 145°C (typ.), both switching MOSFETs are  
turned off and the part enters a standby state. Upon sensing a junction temperature below 135°C (typ.), the part  
will re-initiate the soft-start sequence and begin switching once again.  
LMZ10503 Application Circuit Schematic and BOMs  
This section provides several application solutions with an associated bill of materials. The compensation for  
each solution was optimized to work over the full input range. Many applications have a fixed input voltage rail. It  
is possible to modify the compensation to obtain a faster transient response for a given input voltage operating  
point.  
V
IN  
U1  
V
OUT  
6, 7  
5
1
2
VOUT  
FB  
VIN  
EN  
C
O1  
LMZ10503  
C
in1  
SS  
GND  
R
fbt  
3
4, EP  
C
SS  
Rcomp  
C
comp  
R
fbb  
Figure 22.  
Table 3. Bill of Materials, VIN = 3.3V to 5V, VOUT = 2.5V, IOUT (MAX) = 3A, Optimized for Electrolytic Input and  
Output Capacitance  
Designator  
U1  
Description  
Case Size  
PFM-7  
Manufacturer  
Texas Instruments  
Sanyo  
Manufacturer P/N  
LMZ10503TZ-ADJ  
6TPE150MIC2  
Quantity  
SIMPLE SWITCHER ®  
150 µF, 6.3V, 18 mΩ  
330 µF, 6.3V, 18 mΩ  
1
1
1
Cin1  
C2, 6.0 x 3.2 x 1.8 mm  
CO1  
D3L, 7.3 x 4.3 x 2.8  
mm  
Sanyo  
6TPE330MIL  
Rfbt  
Rfbb  
100 kΩ  
47.5 kΩ  
0603  
0603  
0603  
0603  
0603  
Vishay Dale  
Vishay Dale  
Vishay Dale  
TDK  
CRCW0603100KFKEA  
CRCW060347K5FKEA  
CRCW060315K0FKEA  
C1608C0G1H331J  
1
1
1
1
1
Rcomp  
Ccomp  
CSS  
15 kΩ  
330 pF, ±5%, C0G, 50V  
10 nF, ±10%, X7R, 16V  
Murata  
GRM188R71C103KA01  
Table 4. Bill of Materials, VIN = 3.3V, VOUT = 0.8V, IOUT (MAX) = 3A, Optimized for Solution Size and  
Transient Response  
Designator  
U1  
Description  
SIMPLE SWITCHER ®  
47 µF, X5R, 6.3V  
110 kΩ  
Case Size  
PFM-7  
1206  
Manufacturer  
Texas Instruments  
TDK  
Manufacturer P/N  
LMZ10503TZ-ADJ  
Quantity  
1
2
1
1
1
1
Cin1, CO1  
Rfbt  
C3216X5R0J476M  
0402  
Vishay Dale  
Vishay Dale  
Murata  
CRCW0402100KFKED  
CRCW04021K00FKED  
GRM1555C1H270JZ01  
GRM155R71C103KA01  
Rcomp  
Ccomp  
CSS  
1.0 kΩ  
0402  
27 pF, ±5%, C0G, 50V  
10 nF, ±10%, X7R, 16V  
0402  
0402  
Murata  
Copyright © 2010–2013, Texas Instruments Incorporated  
Submit Documentation Feedback  
17  
Product Folder Links: LMZ10503  
LMZ10503  
SNVS641H –JANUARY 2010–REVISED APRIL 2013  
www.ti.com  
U1  
Optional  
V
OUT  
V
IN  
6, 7  
1
2
VOUT  
FB  
VIN  
EN  
C
O1  
C
C
O3  
O2  
LMZ10503  
C
comp  
+
C
C
in1  
R
in2  
fbt  
5
SS  
GND  
R
comp  
4, EP  
3
C
SS  
Optional  
R
fbb  
Figure 23.  
Table 5. Bill of Materials, VIN = 3.3V to 5V, VOUT = 2.5V, IOUT (MAX) = 3A, Optimized for Low Input and  
Output Ripple Voltage and Fast Transient Response  
Designator  
U1  
Description  
SIMPLE SWITCHER®  
22 µF, X5R, 10V  
220 µF, 10V, AL-Elec  
4.7 µF, X5R, 10V  
22 µF, X5R, 6.3V  
100 µF, X5R, 6.3V  
75 kΩ  
Case Size  
PFM-7  
1210  
E
Manufacturer  
Texas Instruments  
AVX  
Manufacturer P/N  
LMZ10503TZ-ADJ  
1210ZD226MAT  
Quantity  
1
2
Cin1  
Cin2  
Panasonic  
AVX  
EEE1AA221AP  
1*  
1*  
1*  
1
CO1  
0805  
1206  
1812  
0402  
0402  
0402  
0402  
0402  
0805ZD475MAT  
CO2  
AVX  
12066D226MAT  
CO3  
AVX  
18126D107MAT  
Rfbt  
Vishay Dale  
Vishay Dale  
Vishay Dale  
Murata  
CRCW040275K0FKED  
CRCW040234K8FKED  
CRCW04021K00FKED  
GRM1555C1H221JA01D  
GRM155R71C103KA01  
1
Rfbb  
34.8 kΩ  
1
Rcomp  
Ccomp  
CSS  
1.0 kΩ  
1
220 pF, ±5%, C0G, 50V  
10 nF, ±10%, X7R, 16V  
1
Murata  
1
Table 6. Output Voltage Setting (Rfbt = 75 kΩ)  
VOUT  
3.3V  
Rfbb  
23.7 kΩ  
34.8 kΩ  
59 kΩ  
2.5 V  
1.8 V  
1.5 V  
1.2 V  
0.9 V  
84.5 kΩ  
150 kΩ  
590 kΩ  
U1  
V
OUT  
V
6, 7  
IN  
1
2
VOUT  
FB  
VIN  
EN  
C
O1  
C
C
O3  
O2  
LMZ10503  
R
en1  
5
+
C
C
in3  
C
C
C
in1  
in4  
in5  
in2  
SS  
GND  
R
fbt  
3
4, EP  
C
SS  
C
comp  
R
comp  
3
R
fbb  
Figure 24.  
18  
Submit Documentation Feedback  
Copyright © 2010–2013, Texas Instruments Incorporated  
Product Folder Links: LMZ10503  
LMZ10503  
www.ti.com  
SNVS641H –JANUARY 2010–REVISED APRIL 2013  
Table 7. Bill of Materials for Evaluation Board, VIN = 3.3V to 5V, VOUT = 2.5V, IOUT (MAX) = 3A  
Designator  
U1  
Description  
SIMPLE SWITCHER®  
1 µF, X7R, 16V  
4.7 µF, X5R, 6.3V  
22 µF, X5R, 16V  
47 µF, X5R, 6.3V  
220 µF, 10V, AL-Elec  
100 µF, X5R, 6.3V  
75 kΩ  
Case Size  
PFM-7  
0805  
0805  
1210  
1210  
E
Manufacturer  
Texas Instruments  
TDK  
Manufacturer P/N  
LMZ10503TZ-ADJ  
C2012X7R1C105K  
C2012X5R0J475K  
C3225X5R1C226M  
C3225X5R0J476M  
EEE1AA221AP  
Quantity  
1
1
2
2
1
1
1
1
1
1
1
1
1
Cin1  
Cin2, CO1  
Cin3, CO2  
Cin4  
TDK  
TDK  
TDK  
Cin5  
Panasonic  
TDK  
CO3  
1812  
0805  
0805  
0805  
0603  
0805  
0805  
C4532X5R0J107M  
CRCW080575K0FKEA  
CRCW080534K8FKEA  
CRCW08051K10FKEA  
C1608C0G1H181J  
CRCW0805100KFKEA  
C2012C0G1H103J  
Rfbt  
Vishay Dale  
Vishay Dale  
Vishay Dale  
TDK  
Rfbb  
34.8 kΩ  
Rcomp  
Ccomp  
Ren1  
1.1 kΩ  
180 pF, ±5%, C0G, 50V  
100 kΩ  
Vishay Dale  
TDK  
CSS  
10 nF, ±5%, C0G, 50V  
Table 8. Output Voltage Setting (Rfbt = 75 kΩ)  
VOUT  
3.3V  
Rfbb  
23.7 kΩ  
34.8 kΩ  
59 kΩ  
2.5 V  
1.8 V  
1.5 V  
1.2 V  
0.9 V  
84.5 kΩ  
150 kΩ  
590 kΩ  
Figure 25.  
Table 9. Bill of Materials, VIN = 5V, VOUT = 2.5V, IOUT (MAX) = 3A, Complies with EN55022 Class B Radiated  
Emissions  
Designator  
U1  
Description  
SIMPLE SWITCHER®  
1 µF, X7R, 16V  
4.7 µF, X5R, 6.3V  
47 µF, X5R, 6.3V  
100 µF, X5R, 6.3V  
75 kΩ  
Case Size  
PFM-7  
0805  
Manufacturer  
Texas Instruments  
TDK  
Manufacturer P/N  
LMZ10503TZ-ADJ  
C2012X7R1C105K  
C2012X5R0J475K  
C3225X5R0J476M  
C4532X5R0J107M  
CRCW080575K0FKEA  
CRCW080534K8FKEA  
CRCW08051K10FKEA  
C1608C0G1H181J  
C2012C0G1H103J  
Quantity  
1
1
1
1
1
1
1
1
1
1
Cin1  
Cin2  
0805  
TDK  
Cin3  
1210  
TDK  
CO1  
1812  
TDK  
Rfbt  
0805  
Vishay Dale  
Vishay Dale  
Vishay Dale  
TDK  
Rfbb  
34.8 kΩ  
0805  
Rcomp  
Ccomp  
CSS  
1.1 kΩ  
0805  
180 pF, ±5%, C0G, 50V  
10 nF, ±5%, C0G, 50V  
0603  
0805  
TDK  
Copyright © 2010–2013, Texas Instruments Incorporated  
Submit Documentation Feedback  
19  
Product Folder Links: LMZ10503  
LMZ10503  
SNVS641H –JANUARY 2010–REVISED APRIL 2013  
www.ti.com  
Table 10. Output Voltage Setting (Rfbt = 75 kΩ)  
VOUT  
3.3 V  
2.5 V  
1.8 V  
1.5 V  
1.2 V  
0.9 V  
Rfbb  
23.7 kΩ  
34.8 kΩ  
59 kΩ  
84.5 kΩ  
150 kΩ  
590 kΩ  
PCB Layout Diagrams  
The PCB design is available in the LMZ10503 product folder at www.ti.com.  
Figure 26. Top Copper  
Figure 27. Internal Layer 1 (Ground)  
20  
Submit Documentation Feedback  
Copyright © 2010–2013, Texas Instruments Incorporated  
Product Folder Links: LMZ10503  
LMZ10503  
www.ti.com  
SNVS641H –JANUARY 2010–REVISED APRIL 2013  
Figure 28. Internal Layer 2 (Ground and Signal Traces)  
Figure 29. Bottom Copper  
Copyright © 2010–2013, Texas Instruments Incorporated  
Submit Documentation Feedback  
21  
Product Folder Links: LMZ10503  
 
LMZ10503  
SNVS641H –JANUARY 2010–REVISED APRIL 2013  
www.ti.com  
REVISION HISTORY  
Changes from Revision G (April 2013) to Revision H  
Page  
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 21  
22  
Submit Documentation Feedback  
Copyright © 2010–2013, Texas Instruments Incorporated  
Product Folder Links: LMZ10503  
PACKAGE OPTION ADDENDUM  
www.ti.com  
31-May-2013  
PACKAGING INFORMATION  
Orderable Device  
Status Package Type Package Pins Package  
Eco Plan Lead/Ball Finish  
MSL Peak Temp  
Op Temp (°C)  
-40 to 85  
Device Marking  
Samples  
Drawing  
Qty  
(1)  
(2)  
(3)  
(4/5)  
LMZ10503TZ-ADJ/NOPB  
LMZ10503TZE-ADJ/NOPB  
LMZ10503TZX-ADJ/NOPB  
ACTIVE  
PFM  
PFM  
PFM  
NDW  
7
7
7
250  
Green (RoHS  
& no Sb/Br)  
CU SN  
CU SN  
CU SN  
Level-3-245C-168 HR  
Level-3-245C-168 HR  
Level-3-245C-168 HR  
LMZ10503  
TZ-ADJ  
ACTIVE  
ACTIVE  
NDW  
NDW  
45  
Green (RoHS  
& no Sb/Br)  
-40 to 85  
LMZ10503  
TZ-ADJ  
500  
Green (RoHS  
& no Sb/Br)  
-40 to 85  
LMZ10503  
TZ-ADJ  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability  
information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that  
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between  
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight  
in homogeneous material)  
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.  
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation  
of the previous line and the two combined represent the entire Device Marking for that device.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
31-May-2013  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
Addendum-Page 2  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
8-Apr-2013  
TAPE AND REEL INFORMATION  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
(mm) W1 (mm)  
LMZ10503TZ-ADJ/NOPB  
PFM  
PFM  
NDW  
NDW  
7
7
250  
500  
330.0  
330.0  
24.4  
24.4  
10.6 14.22  
10.6 14.22  
5.0  
5.0  
16.0  
16.0  
24.0  
24.0  
Q2  
Q2  
LMZ10503TZX-ADJ/NOP  
B
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
8-Apr-2013  
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
SPQ  
Length (mm) Width (mm) Height (mm)  
LMZ10503TZ-ADJ/NOPB  
LMZ10503TZX-ADJ/NOPB  
PFM  
PFM  
NDW  
NDW  
7
7
250  
500  
367.0  
367.0  
367.0  
367.0  
45.0  
45.0  
Pack Materials-Page 2  
MECHANICAL DATA  
NDW0007A  
BOTTOM SIDE OF PACKAGE  
TOP SIDE OF PACKAGE  
TZA07A (Rev D)  
www.ti.com  
IMPORTANT NOTICE  
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other  
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest  
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and  
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale  
supplied at the time of order acknowledgment.  
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms  
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary  
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily  
performed.  
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and  
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide  
adequate design and operating safeguards.  
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or  
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information  
published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or  
endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the  
third party, or a license from TI under the patents or other intellectual property of TI.  
Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration  
and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered  
documentation. Information of third parties may be subject to additional restrictions.  
Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service  
voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.  
TI is not responsible or liable for any such statements.  
Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements  
concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support  
that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which  
anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause  
harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use  
of any TI components in safety-critical applications.  
In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to  
help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and  
requirements. Nonetheless, such components are subject to these terms.  
No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties  
have executed a special agreement specifically governing such use.  
Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in  
military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components  
which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and  
regulatory requirements in connection with such use.  
TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of  
non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.  
Products  
Applications  
Audio  
www.ti.com/audio  
amplifier.ti.com  
dataconverter.ti.com  
www.dlp.com  
Automotive and Transportation www.ti.com/automotive  
Communications and Telecom www.ti.com/communications  
Amplifiers  
Data Converters  
DLP® Products  
DSP  
Computers and Peripherals  
Consumer Electronics  
Energy and Lighting  
Industrial  
www.ti.com/computers  
www.ti.com/consumer-apps  
www.ti.com/energy  
dsp.ti.com  
Clocks and Timers  
Interface  
www.ti.com/clocks  
interface.ti.com  
logic.ti.com  
www.ti.com/industrial  
www.ti.com/medical  
Medical  
Logic  
Security  
www.ti.com/security  
Power Mgmt  
Microcontrollers  
RFID  
power.ti.com  
Space, Avionics and Defense  
Video and Imaging  
www.ti.com/space-avionics-defense  
www.ti.com/video  
microcontroller.ti.com  
www.ti-rfid.com  
www.ti.com/omap  
OMAP Applications Processors  
Wireless Connectivity  
TI E2E Community  
e2e.ti.com  
www.ti.com/wirelessconnectivity  
Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265  
Copyright © 2013, Texas Instruments Incorporated  

LMZ10503TZX-ADJ/NOPB CAD模型

原理图符号

PCB 封装图

LMZ10503TZX-ADJ/NOPB 替代型号

型号 制造商 描述 替代类型 文档
LMZ10503TZ-ADJ/NOPB TI LMZ10503 3A SIMPLE SWITCHER® Power Module wi 类似代替
LMZ10503TZE-ADJ/NOPB TI LMZ10503 3A SIMPLE SWITCHER® Power Module wi 类似代替
LMZ10504TZ-ADJ/NOPB TI 采用引线式表面贴装 TO 封装的 5.5V、4A 电源模块 | NDW | 7 | -40 类似代替

LMZ10503TZX-ADJ/NOPB 相关器件

型号 制造商 描述 价格 文档
LMZ10503_1006 NSC 3A SIMPLE SWITCHER® Power Module with 5.5V Maximum Input Voltage 获取价格
LMZ10504 NSC 4A SIMPLE SWITCHER®Power Module with 5.5V Maximum Input Voltage 获取价格
LMZ10504 TI 采用引线式表面贴装 TO 封装的 5.5V、4A 电源模块 获取价格
LMZ10504EXT NSC 4A SIMPLE SWITCHER® Power Module with 5.5V Maximum Input Voltage for Military and Rugged Applications 获取价格
LMZ10504EXT TI 4A SIMPLE SWITCHER Power Module With 5.5-V Maximum Input Voltage for Demanding and Rugged Applications 获取价格
LMZ10504EXTTZ NSC LMZ1050xEXT Evaluation Board 获取价格
LMZ10504EXTTZ/NOPB TI 4A SIMPLE SWITCHER Power Module With 5.5-V Maximum Input Voltage for Demanding and Rugged Applications 获取价格
LMZ10504EXTTZE NSC 4A SIMPLE SWITCHER® Power Module with 5.5V Maximum Input Voltage for Military and Rugged Applications 获取价格
LMZ10504EXTTZE/NOPB TI 4A SIMPLE SWITCHER Power Module With 5.5-V Maximum Input Voltage for Demanding and Rugged Applications 获取价格
LMZ10504EXTTZX NSC 4A SIMPLE SWITCHER® Power Module with 5.5V Maximum Input Voltage for Military and Rugged Applications 获取价格

LMZ10503TZX-ADJ/NOPB 相关文章

  • 加特兰进军 UWB 芯片领域，凭何脱颖而出？
    2025-06-13
    24
  • 0.7nm 芯片路线图升级：Forksheet 架构助力芯片性能提升
    2025-06-13
    19
  • 多层 PCB 设计探究：过孔如何 “致命” 影响高频信号传输
    2025-06-13
    35
  • 英伟达携手多方势力，推进 AI 数据中心 800V HVDC 架构落地
    2025-06-13
    25

    • 热门型号

  • 1N5930
  • 1N5942B
  • 1N4001
  • MBR3050CT
  • RTA02-8D
  • 4116T
  • 5KP43A/4
  • 1N5260A
  • MC79L05
  • BZX85C30
  • 9510-G
  • W2PE-54WZ-P
  • 1N6063
  • 2SA673
  • 20IMX35
    • Hi,有什么可以帮您？ 在线客服 或 微信扫码咨询
  • 概述
  • 规格参数
  • 数据手册
  • CAD模型
  • 替代型号
    • 2025 ICPDF网 联系我们和版权申明:QQ 272164286