概述
数据手册SN74AHCT273DB 概述
OCTAL D-TYPE FLIP-FLOPS WITH CLEAR 八路D型触发器与Clear
SN74AHCT273DB 数据手册
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OCTAL D-TYPE FLIP-FLOPS
WITH CLEAR
SCLS375D – JUNE 1997 – REVISED JANUARY 2000
SN54AHCT273 . . . J OR W PACKAGE
SN74AHCT273 . . . DB, DGV, DW, N, OR PW PACKAGE
(TOP VIEW)
EPIC (Enhanced-Performance Implanted
CMOS) Process
Inputs Are TTL-Voltage Compatible
CLR
1Q
1D
2D
2Q
3Q
3D
4D
4Q
V
CC
Contain Eight Flip-Flops With Single-Rail
Outputs
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
8Q
8D
7D
7Q
6Q
6D
Direct Clear Input
Individual Data Input to Each Flip-Flop
Applications Include:
– Buffer/Storage Registers
– Shift Registers
13 5D
12 5Q
– Pattern Generators
Latch-Up Performance Exceeds 250 mA Per
JESD 17
11
GND
CLK
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
SN54AHCT273 . . . FK PACKAGE
(TOP VIEW)
– 1000-V Charged-Device Model (C101)
Package Options Include Plastic
Small-Outline (DW), Shrink Small-Outline
(DB), Thin Very Small-Outline (DGV), Thin
Shrink Small-Outline (PW), and Ceramic
Flat (W) Packages, Ceramic Chip Carriers
(FK), and Standard Plastic (N) and Ceramic
(J) DIPs
3
2
1
20 19
18
2D
2Q
3Q
3D
4D
8D
17 7D
4
5
6
7
8
16
15
14
7Q
6Q
6D
9 10 11 12 13
description
Thesedevicesarepositive-edge-triggeredD-type
flip-flops with a direct clear (CLR) input.
Information at the data (D) inputs meeting the setup time requirements is transferred to the Q outputs on the
positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a particular voltage level and is not
directly related to the transition time of the positive-going pulse. When CLK is at either the high or low level, the
D input has no effect at the output.
The SN54AHCT273 is characterized for operation over the full military temperature range of –55°C to 125°C.
The SN74AHCT273 is characterized for operation from –40°C to 85 °C.
FUNCTION TABLE
(each flip-flop)
INPUTS
OUTPUT
Q
CLK
D
X
H
L
CLR
L
X
↑
L
H
L
H
H
↑
H
L
X
Q
0
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
EPIC is a trademark of Texas Instruments Incorporated.
Copyright 2000, Texas Instruments Incorporated
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AHCT273, SN74AHCT273
OCTAL D-TYPE FLIP-FLOPS
WITH CLEAR
SCLS375D – JUNE 1997 – REVISED JANUARY 2000
†
logic symbol
1
CLR
CLK
R
11
C1
3
2
5
1D
2D
3D
4D
5D
6D
1D
1Q
2Q
3Q
4Q
5Q
6Q
4
7
6
8
9
13
14
12
15
17
18
16
19
7D
8D
7Q
8Q
†
This symbol is in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
logic diagram (positive logic)
1D
2D
3D
4D
5D
13
6D
14
7D
17
8D
18
3
4
7
8
11
CLK
1D
C1
1D
C1
1D
C1
1D
C1
1D
C1
1D
C1
1D
C1
1D
C1
R
R
R
R
R
R
R
R
1
CLR
2
5
6
9
12
5Q
15
6Q
16
7Q
19
8Q
1Q
2Q
3Q
4Q
logic diagram, each flip-flop (positive logic)
C
C
D
TG
C
TG
C
Q
C
C
TG
CLK(I)
TG
C
C
C
C
R
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AHCT273, SN74AHCT273
OCTAL D-TYPE FLIP-FLOPS
WITH CLEAR
SCLS375D – JUNE 1997 – REVISED JANUARY 2000
†
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
CC
Input voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7 V
I
Output voltage range, V (see Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to V
+ 0.5 V
O
CC
Input clamp current, I (V < 0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –20 mA
IK
I
Output clamp current, I
(V < 0 or V > V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±20 mA
OK
O O CC
Continuous output current, I (V = 0 to V ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±25 mA
Continuous current through V
Package thermal impedance, θ (see Note 2): DB package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70°C/W
O
O
CC
CC
or GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±75 mA
JA
DGV package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92°C/W
DW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58°C/W
N package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69°C/W
PW package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83°C/W
Storage temperature range, T
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C
stg
†
Stresses beyond those listed under “absolute maximum ratings” may cause permanent damage to the device. These are stress ratings only, and
functional operation of the device at these or any other conditions beyond those indicated under “recommended operating conditions” is not
implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
NOTES: 1. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
2. The package thermal impedance is calculated in accordance with JESD 51.
recommended operating conditions (see Note 3)
SN54AHCT273 SN74AHCT273
UNIT
MIN
4.5
2
MAX
MIN
4.5
2
MAX
V
V
V
V
V
Supply voltage
5.5
5.5
V
V
CC
IH
IL
High-level input voltage
Low-level input voltage
Input voltage
0.8
5.5
0.8
5.5
V
0
0
0
0
V
I
Output voltage
V
V
V
O
CC
–8
CC
–8
I
High-level output current
Low-level output current
Input transition rise or fall time
Operating free-air temperature
mA
mA
ns/V
°C
OH
OL
I
8
8
20
85
∆t/∆v
20
T
A
–55
125
–40
NOTE 3: All unused inputs of the device must be held at V
or GND to ensure proper device operation. Refer to the TI application report,
CC
Implications of Slow or Floating CMOS Inputs, literature number SCBA004.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
3
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AHCT273, SN74AHCT273
OCTAL D-TYPE FLIP-FLOPS
WITH CLEAR
SCLS375D – JUNE 1997 – REVISED JANUARY 2000
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
T
A
= 25°C
TYP
SN54AHCT273 SN74AHCT273
PARAMETER
TEST CONDITIONS
= –50
V
UNIT
CC
MIN
4.4
MAX
MIN
4.4
MAX
MIN
4.4
MAX
I
A
4.5
OH
V
4.5 V
4.5 V
V
OH
OL
3.94
3.8
3.8
I
= –8 mA
OH
OL
I
= 50
A
0.1
0.36
±0.1
4
0.1
0.44
±1*
40
0.1
0.44
±1
V
V
I
= 8 mA
OL
I
I
V = V
or GND
or GND,
0 V to 5.5 V
5.5 V
A
A
I
I
CC
CC
V = V
I = 0
O
40
CC
I
One input at 3.4 V,
Other inputs at V
‡
5.5 V
1.35
10
1.5
1.5
10
A
∆I
CC
or GND
CC
V = V or GND
CC
C
5 V
2.5
pF
i
I
* On products compliant to MIL-PRF-38535, this parameter is not production tested at V
This is the increase in supply current for each input at one of the specified TTL voltage levels rather than 0 V or V
CC
= 0 V.
CC
†
.
timing requirements over recommended operating free-air temperature range, V
(unless otherwise noted) (see Figure 1)
= 5 V ± 0.5 V
CC
T
= 25°C
SN54AHCT273 SN74AHCT273
A
UNIT
MIN
5
MAX
MIN
6
MAX
MIN
6
MAX
CLR low
t
Pulse duration
ns
w
CLK high or low
Data before CLK↑
CLR before CLK↑
5
6.5
5
6.5
5
5
t
t
ns
ns
Setup time
su
2.5
0
2.5
0
2.5
0
Hold time, data after CLK↑
h
switching characteristics over recommended operating free-air temperature range,
= 5 V ± 0.5 V (unless otherwise noted) (see Figure 1)
V
CC
T = 25°C
A
SN54AHCT273 SN74AHCT273
FROM
(INPUT)
TO
LOAD
PARAMETER
UNIT
(OUTPUT) CAPACITANCE
MIN
TYP
MAX
MIN
65**
45
MAX
MIN
65
45
1
MAX
C
C
C
= 15 pF
= 50 pF
= 15 pF
75** 120**
L
L
L
f
MHz
ns
max
50
75
7.5**
5.5**
5.8**
8.5
t
t
t
t
t
t
t
10**
7.5**
8.2**
11
1** 11.6**
11.6
8.8
10
CLR
CLK
Q
Q
Q
Q
PHL
PLH
PHL
PHL
PLH
PHL
sk(o)
1**
1**
1
8.8**
10**
12.6
9.8
1
C
C
C
C
= 15 pF
= 50 pF
= 50 pF
= 50 pF
ns
L
L
L
L
1
1
12.6
9.8
11
ns
CLR
CLK
6.5
8.5
1
1
ns
6.8
9.2
1
11
1
1***
1
ns
** On products compliant to MIL-PRF-38535, this parameter is not production tested.
*** On products compliant to MIL-PRF-38535, this parameter does not apply.
PRODUCT PREVIEW information concerns products in the formative or
design phase of development. Characteristic data and other
specifications are design goals. Texas Instruments reserves the right to
change or discontinue these products without notice.
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AHCT273, SN74AHCT273
OCTAL D-TYPE FLIP-FLOPS
WITH CLEAR
SCLS375D – JUNE 1997 – REVISED JANUARY 2000
noise characteristics, V
= 5 V, C = 50 pF, T = 25°C (see Note 4)
CC
L
A
SN74AHCT273
UNIT
PARAMETER
MIN
TYP
MAX
V
V
V
V
V
Quiet output, maximum dynamic V
0.76
V
V
V
V
V
OL(P)
OL(V)
OH(V)
IH(D)
IL(D)
OL
Quiet output, minimum dynamic V
Quiet output, minimum dynamic V
High-level dynamic input voltage
Low-level dynamic input voltage
–0.48
OL
4.4
2
OH
0.8
NOTE 4: Characteristics are for surface-mount packages only.
operating characteristics, T = 25°C
A
PARAMETER
TEST CONDITIONS
No load, f = 1 MHz
TYP
UNIT
C
Power dissipation capacitance
27
pF
pd
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
SN54AHCT273, SN74AHCT273
OCTAL D-TYPE FLIP-FLOPS
WITH CLEAR
SCLS375D – JUNE 1997 – REVISED JANUARY 2000
PARAMETER MEASUREMENT INFORMATION
V
CC
Open
GND
S1
R
= 1 kΩ
L
TEST
S1
From Output
Under Test
Test
Point
From Output
Under Test
t
t
/t
Open
PLH PHL
/t
C
C
L
t
V
CC
L
PLZ PZL
/t
(see Note A)
(see Note A)
GND
PHZ PZH
Open Drain
V
CC
LOAD CIRCUIT FOR
LOAD CIRCUIT FOR
TOTEM-POLE OUTPUTS
3-STATE AND OPEN-DRAIN OUTPUTS
3 V
1.5 V
Timing Input
0 V
t
w
t
h
3 V
t
su
3 V
0 V
1.5 V
1.5 V
Input
Input
1.5 V
1.5 V
Data Input
0 V
VOLTAGE WAVEFORMS
PULSE DURATION
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
3 V
0 V
3 V
0 V
Output
Control
1.5 V
1.5 V
1.5 V
1.5 V
t
t
t
t
t
PZL
PLZ
PLH
PHL
Output
Waveform 1
V
≈V
OH
CC
In-Phase
Output
50% V
50% V
50% V
CC
50% V
CC
CC
V
S1 at V
(see Note B)
CC
V
V
+ 0.3 V
OL
V
OL
OL
t
t
t
PHL
PLH
PZH
PHZ
Output
Waveform 2
S1 at GND
V
OH
V
OH
Out-of-Phase
Output
– 0.3 V
OH
50% V
50% V
CC
CC
CC
V
≈0 V
(see Note B)
OL
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
INVERTING AND NONINVERTING OUTPUTS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
LOW- AND HIGH-LEVEL ENABLING
NOTES: A. includes probe and jig capacitance.
C
L
B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control.
Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control.
C. All input pulses are supplied by generators having the following characteristics: PRR ≤ 1 MHz, Z = 50 Ω, t ≤ 3 ns, t ≤ 3 ns.
O
r
f
D. The outputs are measured one at a time with one input transition per measurement.
Figure 1. Load Circuit and Voltage Waveforms
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
IMPORTANT NOTICE
Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue
any product or service without notice, and advise customers to obtain the latest version of relevant information
to verify, before placing orders, that information being relied on is current and complete. All products are sold
subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those
pertaining to warranty, patent infringement, and limitation of liability.
TI warrants performance of its semiconductor products to the specifications applicable at the time of sale in
accordance with TI’s standard warranty. Testing and other quality control techniques are utilized to the extent
TI deems necessary to support this warranty. Specific testing of all parameters of each device is not necessarily
performed, except those mandated by government requirements.
CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF
DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE (“CRITICAL
APPLICATIONS”). TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, AUTHORIZED, OR
WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT DEVICES OR SYSTEMS OR OTHER
CRITICAL APPLICATIONS. INCLUSION OF TI PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO
BE FULLY AT THE CUSTOMER’S RISK.
In order to minimize risks associated with the customer’s applications, adequate design and operating
safeguards must be provided by the customer to minimize inherent or procedural hazards.
TI assumes no liability for applications assistance or customer product design. TI does not warrant or represent
that any license, either express or implied, is granted under any patent right, copyright, mask work right, or other
intellectual property right of TI covering or relating to any combination, machine, or process in which such
semiconductor products or services might be or are used. TI’s publication of information regarding any third
party’s products or services does not constitute TI’s approval, warranty or endorsement thereof.
Copyright 2000, Texas Instruments Incorporated
SN74AHCT273DB 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| SN74AHCT273DBLE | TI | AHCT/VHCT SERIES, OCTAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO20, PLASTIC, SSOP-20 | 获取价格 |
|
| SN74AHCT273DBR | TI | OCTAL D-TYPE FLIP-FLOPS WITH CLEAR | 获取价格 |
|
| SN74AHCT273DBRE4 | TI | OCTAL D-TYPE FLIP-FLOPS WITH CLEAR | 获取价格 |
|
| SN74AHCT273DBRG4 | TI | OCTAL D-TYPE FLIP-FLOPS WITH CLEAR | 获取价格 |
|
| SN74AHCT273DGV | TI | OCTAL D-TYPE FLIP-FLOPS WITH CLEAR | 获取价格 |
|
| SN74AHCT273DGVR | TI | OCTAL D-TYPE FLIP-FLOPS WITH CLEAR | 获取价格 |
|
| SN74AHCT273DGVRE4 | TI | OCTAL D-TYPE FLIP-FLOPS WITH CLEAR | 获取价格 |
|
| SN74AHCT273DGVRG4 | TI | OCTAL D-TYPE FLIP-FLOPS WITH CLEAR | 获取价格 |
|
| SN74AHCT273DW | TI | OCTAL D-TYPE FLIP-FLOPS WITH CLEAR | 获取价格 |
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| SN74AHCT273DWE4 | TI | OCTAL D-TYPE FLIP-FLOPS WITH CLEAR | 获取价格 |
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