概述
数据手册TPSM86838 概述
采用 HotRod QFN 封装的4.5V 至28V 输入、8A FCCM 模式、同步降压模块
TPSM86838 数据手册
通过下载TPSM86838数据手册来全面了解它。这个PDF文档包含了所有必要的细节，如产品概述、功能特性、引脚定义、引脚排列图等信息。
PDF下载参考文献
TPSM86837, TPSM86838
ZHCSR53B –OCTOBER 2023 –REVISED MAY 2024
TPSM8683x 4.5V 至28V 输入、8A 同步降压电源模块
1 特性
该器件具有4.5V 至28V 的宽工作输入电压范围，非常
适合由 12V、19V、24V 总线电源轨供电的系统。
TPSM8683x 支持高达 8A 的持续输出电流，相应的输
出电压介于0.6V 和5.5V 之间。
• 输入电压范围为4.5V 至28V
• 0.6V 至5.5V 输出电压范围
• 8A 持续输出电流能力
• 集成MOSFET、电感器和基本无源器件
• 在25°C 下，具有0.6V ±1% 的基准电压
• D-CAP3™ 控制模式，用于快速瞬态响应
• TPSM86838 具有FCCM，用于实现伪固定频率和
较低的输出纹波
• TPSM86837 具有Eco-mode，可实现较高的轻负
载效率
• 可调节软启动时间（通过SS 电容器调节）
• 内置输出放电功能
TPSM8683x 使用 DCAP3 控制模式来提供快速瞬态响
应、良好的线性调整率和负载调整率，无需外部补偿，
并支持低等效串联电阻 (ESR) 输出电容器（ 如
MLCC）。
TPSM86838 在轻负载期间以强制连续导通模式
(FCCM) 运行，并且在所有负载条件下均可保持较低的
输出纹波。TPSM86837 以Eco-mode 运行，可在轻负
载条件下实现高效率。
• 可选800kHz 和1200kHz 开关频率
• 电源正常状态指示器，可监测输出电压
• 支持高达98% 的负荷运行
• 非闭锁UV、OV、OT 和UVLO 保护
• –40°C 至+150°C 的工作结温范围
• 19 引脚5.0mm × 5.5mm QFN HotRod™ 封装
TPSM8683x 提供完整的非锁存OV（过压）、UV（欠
压）、OC（过流）、OT（过热）以及 UVLO（欠压锁
定）保护，并具有电源正常状态指示器和输出放电功能
特性。
TPSM8683x 可采用 19 引脚 5.0mm × 5.5mm HotRod
QFN 封装，额定结温范围为–40°C 至150°C。
2 应用
器件信息
封装和封装尺寸(1) (2)
器件型号
TPSM86838
TPSM86837
模式
FCCM
ECO
• 工业应用：医疗应用、工厂自动化和控制（IPC、
机器人）、测试和测量、专业音频视频
• 适用于12V、19V 和24V 电源总线应用的空间受限
POL
RCG（B3QFN，19），
5.0mm× 5.5mm
(1) 有关更多信息，请参阅节10。
(2) 封装尺寸（长× 宽）为标称值，并包括引脚（如适用）。
3 说明
TPSM8683x 是一款高效、高压输入、易于使用的同步
降压电源模块。该器件集成了功率 MOSFET、屏蔽式
电感器和基本无源器件，更大限度地减小了设计尺寸。
100%
80%
60%
40%
VIN
CIN
VIN
VIN
VOUT
VOUT
SW
VOUT
EN
EN
BST
TPSM8683x
SS
PG
RFBT
Css
COUT
MODE
FB
AGND
PGND
RMD
RFBB
20%
VIN=12V
VIN=19V
VIN=24V
0
0
1
2
3
4
5
6
7
8
Iout (A)
简化版原理图
TPSM86838 效率，Vout = 5V，Fsw = 800kHz
本资源的原文使用英文撰写。为方便起见，TI 提供了译文；由于翻译过程中可能使用了自动化工具，TI 不保证译文的准确性。为确认
准确性，请务必访问ti.com 参考最新的英文版本（控制文档）。
English Data Sheet: SLVSH20
TPSM86837, TPSM86838
ZHCSR53B –OCTOBER 2023 –REVISED MAY 2024
www.ti.com.cn
Table of Contents
7 Application and Implementation..................................20
7.1 Application Information............................................. 20
7.2 Typical Application.................................................... 20
7.3 Power Supply Recommendations.............................25
7.4 Layout....................................................................... 26
8 Device and Documentation Support............................28
8.1 Device Support......................................................... 28
8.2 Documentation Support............................................ 28
8.3 接收文档更新通知..................................................... 28
8.4 支持资源....................................................................28
8.5 Trademarks...............................................................28
8.6 静电放电警告............................................................ 28
8.7 术语表....................................................................... 28
9 Revision History............................................................ 28
10 Mechanical, Packaging, and Orderable
1 特性................................................................................... 1
2 应用................................................................................... 1
3 说明................................................................................... 1
4 Pin Configuration and Functions...................................3
5 Specifications.................................................................. 5
5.1 Absolute Maximum Ratings........................................ 5
5.2 ESD Ratings............................................................... 5
5.3 Recommended Operating Conditions.........................5
5.4 Thermal Information....................................................6
5.5 Electrical Characteristics.............................................6
5.6 Typical Characteristics................................................8
6 Detailed Description......................................................13
6.1 Overview...................................................................13
6.2 Functional Block Diagram.........................................14
6.3 Feature Description...................................................14
6.4 Device Functional Modes..........................................18
Information.................................................................... 29
Copyright © 2024 Texas Instruments Incorporated
2
提交文档反馈
Product Folder Links: TPSM86837 TPSM86838
English Data Sheet: SLVSH20
TPSM86837, TPSM86838
ZHCSR53B –OCTOBER 2023 –REVISED MAY 2024
www.ti.com.cn
4 Pin Configuration and Functions
1
16
VOUT
VOUT
MODE
EN
2
3
4
5
6
7
15
14
13
12
11
10
NC
17
PGND
NC
FB
NC
18
AGND
PG
PGND
BOOT
SW
SW
19
SS
PGND
9
8
VIN
VIN
图4-1. 19-Pin B3QFN RCG Package (Top View)
表4-1. Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
NO.
Output voltage. These pins are connected to the internal buck inductor. Connect these pins to the
output load and connect external output capacitors between these pins and PGND.
VOUT
1, 16
O
I
Switching frequency selection pin. Connect this pin to a resistor to AGND for different switching
frequency options shown in 表6-1.
MODE
EN
2
3
Enable input control. Driving EN high or leaving this pin floating enables the module. A resistor divider
can be used to imply an UVLO function.
I
Feedback input. Connect the midpoint of the feedback resistor divider to this pin. Connect the upper
resistor (RFBT) of the feedback divider to VOUT at the desired point of regulation. Connect the lower
resistor (RFBB) of the feedback divider to AGND. Do not leave open or connect to ground.
FB
4
I
AGND
PG
5
6
G
O
Ground of internal analog circuitry. Connect AGND to PGND plane at a single point.
Open-drain power-good monitor output that asserts low if the output voltage is out of PG threshold due
to overvoltage, undervoltage, thermal shutdown, EN shutdown, or during soft start.
Soft-start time selection pin. Connecting an external capacitor to AGND to set the soft-start time. A
minimum 22nF ceramic capacitor must be connected at this pin, which sets the minimum soft-start time
to approximately 2.2ms. Do not float.
SS
7
I
Input supply voltage. A 100nF input capacitor is internally connected from this pin to PGND within the
module. Externally, connect input capacitors between these pins and PGND in close proximity to the
device.
VIN
SW
8, 9
10, 11
12
P
O
Switching node. Do not place any external component on this pin or connect to any signal. The amount
of copper placed on this pin must be kept to a minimum to prevent issues with noise and EMI.
Bootstrap pin for the internal high-side gate driver. A 100nF bootstrap capacitor is internally connected
from this pin to SW within the module to provide the bootstrap voltage. Do not place any external
component on this pin or connect to any signal.
BOOT
I/O
13, 14,
15
NC
No connection. Tie to GND for better thermal performance.
—
Copyright © 2024 Texas Instruments Incorporated
3
提交文档反馈
Product Folder Links: TPSM86837 TPSM86838
English Data Sheet: SLVSH20
TPSM86837, TPSM86838
ZHCSR53B –OCTOBER 2023 –REVISED MAY 2024
www.ti.com.cn
表4-1. Pin Functions （续）
PIN
TYPE(1)
DESCRIPTION
NAME
NO.
17, 18,
19
Power ground. This pin is the return current path for the power stage of the device. Connect these pads
to the input supply return, the load return, and the capacitors associated with the VIN and VOUT pins.
PGND
G
(1) I = input, O = output, G = ground, P = power
Copyright © 2024 Texas Instruments Incorporated
English Data Sheet: SLVSH20
4
提交文档反馈
Product Folder Links: TPSM86837 TPSM86838
TPSM86837, TPSM86838
ZHCSR53B –OCTOBER 2023 –REVISED MAY 2024
www.ti.com.cn
5 Specifications
5.1 Absolute Maximum Ratings
Over the recommended operating junction temperature range of –40°C to +150°C (unless otherwise noted)(1)
MIN
–0.3
–0.3
–0.3
–0.3
–0.3
–2
MAX
UNIT
V
VIN
32
BOOT
SW + 6
V
Input voltage
BOOT-SW
EN, FB, MODE
PGND, AGND
SW
6
6
V
V
0.3
32
35
6
V
V
Output voltage
SW (< 10ns transient)
PG
V
–5
V
–0.3
Mechanical
vibration
MIL-STD-883D, Method 2007.2, 20Hz to 2kHz
20
G
G
MIL-STD-883D, Method 2002.3, 1ms, 1/2 sine,
mounted
Mechanical shock
500
Operating junction temperature, TJ
Storage temperature, Tstg
150
150
°C
°C
–40
–65
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions. If
used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
5.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged device model (CDM), per ANSI/ESDA/JEDEC JS-002(2)
Electrostatic
discharge
VESD
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
5.3 Recommended Operating Conditions
Over the recommended operating junction temperature range of –40°C to 150°C (unless otherwise noted).
MIN
NOM
MAX
UNIT
V
VIN
4.5
28
BOOT
SW + 5.5
5.5
V
–0.1
–0.1
–0.1
–0.1
–1
BOOT-SW
EN, FB, MODE
PGND, AGND
SW
V
Input voltage
5.5
V
0.1
V
28
V
Output voltage
PG
5.5
V
–0.1
–40
Operating junction temperature, TJ
150
°C
Copyright © 2024 Texas Instruments Incorporated
5
提交文档反馈
Product Folder Links: TPSM86837 TPSM86838
English Data Sheet: SLVSH20
TPSM86837, TPSM86838
ZHCSR53B –OCTOBER 2023 –REVISED MAY 2024
www.ti.com.cn
5.4 Thermal Information
TPSM8683x
RCG
(B3QFN)
THERMAL METRIC1
UNIT
19 PINS
Effective Junction-to-ambient thermal resistance
(TPSM8683x EVM)
Eff RθJA
24
°C/W
RθJA
ΨJT
Junction-to-ambient thermal resistance (JEDEC)
Junction-to-top characterization parameter2
Junction-to-board characterization parameter3
36
0.5
12
°C/W
°C/W
°C/W
ΨJB
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report.
(2) The junction-to-top board characterization parameter, ΨJT, estimates the junction temperature, TJ , of a device in a real system, using
a procedure described in JESD51-2A (section 6 and 7). TJ = ΨJT × PDIS + TT; where PDIS is the power dissipated in the device and TT
is the temperature of the top of the device.
(3) The junction-to-top board characterization parameter, ΨJB, estimates the junction temperature, TJ, of a device in a real system, using a
procedure described in JESD51-2A (section 6 and 7). TJ = ΨJB × PDIS + TB; where PDIS is the power dissipated in the device and TB is
the temperature of the board 1mm from the device.
5.5 Electrical Characteristics
The electrical ratings specified in this section apply to all specifications in this document unless otherwise noted. These
specifications are interpreted as conditions that do not degrade the parametric or functional specifications of the device for
the life of the product containing it. Typical values correspond to TJ = 25°C, VIN = 24V. Minimum and maximum limits are
based on TJ = –40°C to +150°C, VIN = 4.5V to 28V (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
TJ = 25°C, VEN = 5V, VFB = 0.7V
(TPSM86838)
350
µA
Quiescent current,
operating 1
IQ
TJ = 25°C, VEN = 5V, VFB = 0.65V
(TPSM86837)
45
3
µA
µA
Shutdown supply
current
ISD
TJ = 25°C, VEN = 0V
UVLO
Wake up VIN voltage
Shutdown VIN voltage
Hysteresis VIN voltage
4.0
3.5
4.2
3.65
550
4.4
3.8
V
V
VIN undervoltage
lockout
UVLO
mV
ENABLE(EN PIN)
IEN_INPUT
Input current
VEN = 1.1V
1
3
µA
µA
IEN_HYS
Hysteresis current
VEN = 1.3V
EN rising
EN falling
VEN_ON
1.18
1.07
1.26
V
V
Enable threshold
VEN_OFF
1
FEEDBACK VOLTAGE
VOUT = 5V, continuous mode operation, TJ
= 25°C
0.594
0.591
0.6
0.6
0.606
0.609
V
V
VFB
Feedback voltage
VOUT = 5V, continuous mode operation, TJ
= –40°C to 150°C
CURRENT LIMIT
Low-side MOSFET
valley current limit
ILS_OCL
8
9.6
11.1
A
Copyright © 2024 Texas Instruments Incorporated
English Data Sheet: SLVSH20
6
提交文档反馈
Product Folder Links: TPSM86837 TPSM86838
TPSM86837, TPSM86838
ZHCSR53B –OCTOBER 2023 –REVISED MAY 2024
www.ti.com.cn
5.5 Electrical Characteristics （续）
The electrical ratings specified in this section apply to all specifications in this document unless otherwise noted. These
specifications are interpreted as conditions that do not degrade the parametric or functional specifications of the device for
the life of the product containing it. Typical values correspond to TJ = 25°C, VIN = 24V. Minimum and maximum limits are
based on TJ = –40°C to +150°C, VIN = 4.5V to 28V (unless otherwise noted).
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
High-side MOSFET
peak current limit
IHS_OCL
INOC
12.75
15
17.25
A
Reverse current limit
for FCCM
3
A
DUTY CYCLE and FREQUENCY CONTROL
VIN = 24V, VOUT = 5V, continuous mode
operation,
FSW
Switching frequency
800
kHz
Mode setting to 800kHz
tON(MIN)
Minimum on time2
Minimum off time2
ns
ns
50
tOFF(MIN)
TJ = 25°C
150
SOFT START
ISS
Soft-start charging
current
6
uA
POWER GOOD
PG lower threshold -
falling
% of VFB
% of VFB
% of VFB
% of VFB
85%
90%
PG lower threshold -
rising
VPGTH
PG upper threshold -
falling
110%
115%
PG upper threshold -
rising
PG from low-to-high
PG from high-to-low
64
32
us
us
tPG_DLY
PG delay
Output OVP
threshold
VOVP
OVP detect(L->H)
TJ = 25°C
125%
32
tOVP_DEG
VUVP
OVP Prop deglitch
us
Output UVP
threshold
Hiccup detect(H->L)
65%
UV protection hiccup
wait time
tUVP_WAIT
256
us
UV protection hiccup
time before recovery
tUVP_HICCUP
10.5
*tSS
THERMAL SHUTDOWN
Temperature rising
Hysteresis
150
165
30
°C
°C
Thermal shutdown threshold3
SW DISCHARGE RESISTANCE
VOUT discharge resistance
VEN = 0, VSW = 0.5V, TJ = 25°C
200
Ω
(1) Not representative of the total input current of the system when in regulation. Specified by design and characterization test.
(2) Not production tested. Specified by design.
(3) Not production tested. Specified by design and engineering sample correlation.
Copyright © 2024 Texas Instruments Incorporated
7
提交文档反馈
Product Folder Links: TPSM86837 TPSM86838
English Data Sheet: SLVSH20
TPSM86837, TPSM86838
ZHCSR53B –OCTOBER 2023 –REVISED MAY 2024
www.ti.com.cn
5.6 Typical Characteristics
VIN = 12V (unless otherwise noted)
50
48
46
44
42
40
-40
0
40
80
120
160
Junction Temperature (C)
图5-2. TPSM86838 Quiescent Current vs Temperature
图5-1. TPSM86837 Quiescent Current vs Temperature
5.6
0.612
0.608
0.604
0.6
4.8
4
3.2
2.4
1.6
0.596
0.592
0.588
-40
0
40
80
120
160
-40
0
40
80
120
160
Junction Temperature (C)
Junction Temperature (C)
图5-4. Feedback Voltage vs Temperature
图5-3. Shutdown Current vs Temperature
4.2
1.2
1.175
1.15
4.1
4
VEN_Rise (V)
VEN_Fall (V)
VINUVLO_Rise (V)
VINUVLO_Fall (V)
1.125
1.1
3.9
3.8
3.7
3.6
1.075
1.05
-40
0
40
80
120
160
-40
0
40
80
120
160
Junction Temperature (C)
Junction Temperature (C)
图5-6. EN Threshold vs Temperature
图5-5. VIN UVLO Threshold vs Temperature
Copyright © 2024 Texas Instruments Incorporated
English Data Sheet: SLVSH20
8
提交文档反馈
Product Folder Links: TPSM86837 TPSM86838
TPSM86837, TPSM86838
ZHCSR53B –OCTOBER 2023 –REVISED MAY 2024
www.ti.com.cn
5.6 Typical Characteristics (continued)
VIN = 12V (unless otherwise noted)
图5-8. High-Side Peak Current Limit vs Temperature
图5-7. Low-Side Valley Current Limit vs Temperature
900
900
800
700
600
800
700
600
Iout=0.1A
Iout=0.1A
Iout=6A
Iout=6A
Iout=8A
Iout=8A
500
500
0
5
10
15
20
25
30
0
5
10
15
20
25 30
Vin (V)
Vin (V)
图5-9. TPSM86838 Switching Frequency vs Input Voltage, Fsw 图5-10. TPSM86838 Switching Frequency vs Input Voltage, Fsw
= 800kHz, Vo = 1.8V = 800kHz, Vo = 3.3V
900
800
700
600
500
400
1300
1200
1100
1000
900
Iout=0.1A
Iout=6A
Iout=8A
800
Iout=0.1A
Iout=6A
Iout=8A
700
0
5
10
15
Vin (V)
20
25
30
5
10
15
20
25
30
Vin (V)
图5-12. TPSM86838 Switching Frequency vs Input Voltage, Fsw
图5-11. TPSM86838 Switching Frequency vs Input Voltage, Fsw
= 1200kHz, Vo = 1.8V
= 800kHz, Vo = 5V
Copyright © 2024 Texas Instruments Incorporated
9
提交文档反馈
Product Folder Links: TPSM86837 TPSM86838
English Data Sheet: SLVSH20
TPSM86837, TPSM86838
ZHCSR53B –OCTOBER 2023 –REVISED MAY 2024
www.ti.com.cn
5.6 Typical Characteristics (continued)
VIN = 12V (unless otherwise noted)
1300
1200
1100
1000
900
1400
1200
1000
800
600
Iout=0.1A
Iout=6A
Iout=8A
Iout=0.1A
Iout=6A
Iout=8A
800
700
400
0
5
10
15
20
25
30
5
10
15
20
25
30
Vin (V)
Vin (V)
图5-13. TPSM86838 Switching Frequency vs Input Voltage, Fsw 图5-14. TPSM86838 Switching Frequency vs Input Voltage, Fsw
= 1200kHz, Vo = 3.3V
= 1200kHz, Vo = 5V
900
800
700
600
500
Vout=1.8V
Vout=3.3V
Vout=5V
0.001
0.01
0.1
1
10
Iout (A)
图5-15. TPSM86837 Switching Frequency vs Output Current,
图5-16. TPSM86838 Switching Frequency vs Output Current,
Fsw = 800kHz, Vin = 24V
Fsw = 800kHz, Vin = 24V
1600
1200
800
1500
1250
1000
750
400
Vout=1.8V
Vout=3.3V
Vout=5V
Vout=1.8V
Vout=3.3V
Vout=5V
0
0.001
500
0.001
0.01
0.1
Iout (A)
1
10
0.01
0.1
Iout (A)
1
10
图5-17. TPSM86837 Switching Frequency vs Output Current,
图5-18. TPSM86838 Switching Frequency vs Output Current,
Fsw = 1200kHz, Vin = 24V
Fsw = 1200kHz, Vin = 24V
Copyright © 2024 Texas Instruments Incorporated
10
提交文档反馈
Product Folder Links: TPSM86837 TPSM86838
English Data Sheet: SLVSH20
TPSM86837, TPSM86838
ZHCSR53B –OCTOBER 2023 –REVISED MAY 2024
www.ti.com.cn
5.6 Typical Characteristics (continued)
VIN = 12V (unless otherwise noted)
100%
80%
60%
40%
20%
0
VIN=4.5V
VIN=12V
VIN=24V
0
1
2
3
4
5
6
7
8
Iout (A)
图5-19. TPSM86837 Efficiency, VOUT = 1.8V, Fsw = 800kHz
图5-20. TPSM86838 Efficiency, VOUT = 1.8V, Fsw = 800kHz
100%
80%
60%
40%
20%
VIN=4.5V
VIN=12V
VIN=24V
0
0.001
0.01
0.1
1
10
Iout (A)
图5-21. TPSM86837 Efficiency, VOUT = 3.3V, Fsw = 800kHz
图5-22. TPSM86838 Efficiency, VOUT = 3.3V, Fsw = 800kHz
100%
100%
80%
60%
40%
80%
60%
40%
20%
20%
VIN=12V
VIN=19V
VIN=24V
VIN=12V
VIN=19V
VIN=24V
0
0.001
0
0.01
0.1
Iout (A)
1
10
0
1
2
3
4
5
6
7
8
Iout (A)
图5-23. TPSM86837 Efficiency, VOUT = 5V, Fsw = 800kHz
图5-24. TPSM86838 Efficiency, VOUT = 5V, Fsw = 800kHz
Copyright © 2024 Texas Instruments Incorporated
11
提交文档反馈
Product Folder Links: TPSM86837 TPSM86838
English Data Sheet: SLVSH20
TPSM86837, TPSM86838
ZHCSR53B –OCTOBER 2023 –REVISED MAY 2024
www.ti.com.cn
5.6 Typical Characteristics (continued)
VIN = 12V (unless otherwise noted)
100%
80%
60%
40%
20%
0
100%
80%
60%
40%
20%
0
VIN=4.5V
VIN=12V
VIN=24V
VIN=4.5V
VIN=12V
VIN=24V
0.001
0.01
0.1
Iout (A)
1
10
0
1
2
3
4
5
6
7
8
Iout (A)
图5-25. TPSM86837 Efficiency, VOUT = 1.8V, Fsw = 1200kHz
图5-26. TPSM86838 Efficiency, VOUT = 1.8V, Fsw = 1200kHz
100%
80%
60%
40%
20%
VIN=4.5V
VIN=12V
VIN=24V
0
0
1
2
3
4
5
6
7
8
Iout (A)
图5-27. TPSM86837 Efficiency, VOUT = 3.3V, Fsw = 1200kHz
图5-28. TPSM86838 Efficiency, VOUT = 3.3V, Fsw = 1200kHz
100%
100%
80%
60%
40%
80%
60%
40%
20%
20%
VIN=12V
VIN=19V
VIN=24V
VIN=12V
VIN=19V
VIN=24V
0
0.001
0
0.01
0.1
Iout (A)
1
10
0
1
2
3
4
5
6
7
8
Iout (A)
图5-29. TPSM86837 Efficiency, VOUT = 5V, Fsw = 1200kHz
图5-30. TPSM86838 Efficiency, VOUT = 5V, Fsw = 1200kHz
Copyright © 2024 Texas Instruments Incorporated
12
提交文档反馈
Product Folder Links: TPSM86837 TPSM86838
English Data Sheet: SLVSH20
TPSM86837, TPSM86838
ZHCSR53B –OCTOBER 2023 –REVISED MAY 2024
www.ti.com.cn
6 Detailed Description
6.1 Overview
The TPSM8683x is an easy-to-use, synchronous buck DC/DC power module designed for a wide variety of
applications where reliability, small design size, and low EMI signature are of paramount importance. With
integrated power MOSFETs, a shielded buck inductor, and basic passives, the TPSM8683x is a 8A synchronous
buck module operating from 4.5V to 28V input voltage (VIN), and the output voltage ranges from 0.6V to 5.5V.
The proprietary D-CAP3 control mode enables low external component count, ease of design, optimization of the
power design for power, size, and efficiency. The device employs D-CAP3 control mode that provides fast
transient response with no external compensation components and an accurate feedback voltage. TPSM86837
operates in Eco-mode to attain high efficiency at light load. TPSM86838 operates in FCCM mode which has the
quasi-fixed switching frequency at both light and heavy load. The TPSM8683x is able to adapt both low
equivalent series resistance (ESR) output capacitors such as POSCAP or SP-CAP, and ultra-low ESR ceramic
capacitors.
The TPSM8683x incorporates specific features to improve EMI performance in noise-sensitive applications:
• An optimized package and pinout design enables a shielded switch-node layout that mitigates radiated EMI.
• Parallel input and output paths with symmetrical capacitor layouts minimize parasitic inductance, switch
voltage ringing, and radiated field coupling
• Integrated power MOSFETs with enhanced gate drive control enable low-noise PWM switching.
The TPSM8683x module also includes inherent protection features for robust system requirements:
• An open-drain PGOOD indicator for power-rail sequencing and fault reporting
• Precision enable input with hysteresis, providing programmable non-latched input undervoltage lockout
(UVLO)
• Non-latched overvoltage protections
• Hiccup-mode overcurrent protection with cycle-by-cycle valley current limits
• Thermal shutdown with automatic recovery.
Leveraging a pin arrangement designed for simple layout that requires only a few external components, the
TPSM8683x is specified to maximum junction temperatures of 150°C.
Copyright © 2024 Texas Instruments Incorporated
13
English Data Sheet: SLVSH20
提交文档反馈
Product Folder Links: TPSM86837 TPSM86838
TPSM86837, TPSM86838
ZHCSR53B –OCTOBER 2023 –REVISED MAY 2024
www.ti.com.cn
6.2 Functional Block Diagram
PG rising threshold
+
PG
PG
Logic
UV threshold
OV threshold
+
+
UV
OV
+
PG falling threshold
Regulator
VREG5
VIN
+
0.6 V
UVLO
Reference
+
4.2 V
/3.65 V
GND
FB
SS
SW
HSDOC
Limit
Ripple Injection
Iss
BOOT
Control Logic
SS
ꢀꢁOn/Off time
ꢀꢁMin On/Off time
ꢀꢁEco-mode or FCCM
ꢀꢁSoft-start
One Shot
ꢀꢁPower Good
ꢀꢁLarge Duty
SW
TSD
+
165°C /
30°C
XCON
ꢀꢁOCL for HSD and LSD
ꢀꢁUVP/OVP/TSD
ꢀꢁOutput discharge
VREG5
VOUT
Ih
Ip
EN
+
+
Enable
Threshold
OCL
PGND
AGND
+
MODE
Switching Frequency
ZC
+
NOCL
Discharge Control
6.3 Feature Description
6.3.1 The Adaptive On-Time Control and PWM Operation
The main control loop of the TPSM8683x is an adaptive on-time pulse width modulation (PWM) controller that
supports a proprietary D-CAP3 control mode. The D-CAP3 control mode combines adaptive on-time control with
an internal compensation circuit for quasi-fixed frequency and low external component count configuration with
both low-ESR and ceramic output capacitors. The D-CAP3 control mode is stable even with virtually no ripple at
the output. The TPSM8683x also includes an error amplifier that makes the output voltage very accurate. No
external current sense network or loop compensation is required for D-CAP3 control mode.
Copyright © 2024 Texas Instruments Incorporated
English Data Sheet: SLVSH20
14
提交文档反馈
Product Folder Links: TPSM86837 TPSM86838
TPSM86837, TPSM86838
ZHCSR53B –OCTOBER 2023 –REVISED MAY 2024
www.ti.com.cn
At the beginning of each cycle, the high-side MOSFET is turned on. This MOSFET is turned off after internal
one-shot timer expires. This one-shot duration is set proportional to the output voltage, VOUT, and is inversely
proportional to the module input voltage, VIN, to maintain a pseudo-fixed frequency over the input voltage range,
hence called adaptive on-time control. When the feedback voltage falls below the reference voltage, the one-
shot timer is reset and the high-side MOSFET is turned on again. An internal ripple generation circuit is added to
the reference voltage for emulating the output ripple, and this action enables the use of very low-ESR output
capacitors, such as multi-layered ceramic caps (MLCC).
6.3.2 Mode Selection
TPSM8683x has a MODE pin to configure the switching frequency, as shown in 表 6-1. The device reads the
voltage on the MODE pin during start-up and latches onto one of the MODE options list in 表 6-1.The voltage on
the MODE pin can be set by connecting a resistor to AGND. A guideline for the MODE resistor in 1% resistors in
shown in 表6-1. The MODE pin setting can be reset only by a VIN or EN power cycling.
图 6-1 shows the typical start-up sequence of the device after the enable signal triggers the EN turn-on
threshold. After the voltage of internal VCC crosses the UVLO rising threshold, the MODE setting is read. After
this process, the MODE is latched and does not change until VIN or EN toggles to restart-up this device. Then
after a delay, the internal soft-start function begins to ramp up and Vout ramps up smoothly. When Vout is up to
the reference voltage, PGOOD turns to high after a delay.
表6-1. MODE Pin Settings for TPSM8683x
MODE Pin
R = 162kohm
R = 374kohm
Switching Frequency
800kHz
1200kHz
EN Threshold
1.18 V
EN
VCC UVLO
4.2 V
Internal
VCC
MODE
Detection
MODE
Internal VCC
Vss = 900 mV SS-end
Vss = 640 mV
Vss = 600 mV
40 µs
64 µs
Tss
(40-100) µs
SS
Vss = 40 mV
Vout
T = Tss
64 us
T = 0.43 × Tss
PGOOD
图6-1. Power-Up Sequence
6.3.2.1 FCCM Control and Eco-mode Control
TPSM86838 operates in forced continuous conduction mode (FCCM) in light load conditions and allows the
inductor current to become negative. In FCCM, the switching frequency is maintained at a quasi-fixed level over
the entire load range, which is designed for applications requiring tight control of the switching frequency and
output voltage ripple at the cost of lower efficiency under light load compared with that under Eco-mode. This
Copyright © 2024 Texas Instruments Incorporated
15
提交文档反馈
Product Folder Links: TPSM86837 TPSM86838
English Data Sheet: SLVSH20
TPSM86837, TPSM86838
ZHCSR53B –OCTOBER 2023 –REVISED MAY 2024
www.ti.com.cn
mode also can help to avoid switching frequency dropping into audible range that can introduce some audible
noise.
TPM86837 is set to Eco-mode to maintain high light load efficiency. As the output current decreases from heavy
load condition, the inductor current is also reduced and eventually comes to a point that the rippled valley
touches zero level, which is the boundary between continuous conduction and discontinuous conduction modes.
The rectifying MOSFET is turned off when the zero inductor current is detected. As the load current further
decreases the converter runs into discontinuous conduction mode. The on-time is kept almost the same as in the
continuous conduction mode so that longer time is needed to discharge the output capacitor with smaller load
current to the level of the reference voltage. This process makes the switching frequency lower, proportional to
the load current, and keeps the light load efficiency high. The transition point to the light load operation IOUT(LL)
current can be calculated by 方程式1.
V
− V
× V
OUT OUT
1
IN
I
=
×
(1)
OUT LL
2 × L × Fsw
V
IN
6.3.3 Soft Start and Prebiased Soft Start
The TPSM8683x has an adjustable soft-start time that can be set by connecting a capacitor between SS and
AGND. When the EN pin becomes high, the soft-start charge current (ISS) begins charging the external capacitor
(CSS) connected between SS and AGND. 方程式2 calculates the soft-start time (TSS) :
C
×V
ss REF
T
=
(2)
ss
I
SS
If the external capacitor (CSS) has pre-stored voltage at start-up, the device initially discharges the external
capacitor voltage to lower voltage then charge again to prevent inrush start-up.
If the output capacitor is prebiased at start-up, the device initiates switching and starts ramping up only after the
internal reference voltage becomes greater than the feedback voltage VFB. This scheme make sure that the
converters ramp up smoothly into regulation point.
6.3.4 Enable and Adjusting Undervoltage Lockout
The EN pin provides electrical on and off control of the device. When the EN pin voltage exceeds the threshold
voltage, the device begins operating. If the EN pin voltage is pulled below the threshold voltage, the regulator
stops switching and enters the standby operation.
The EN pin has an internal pullup current source which allows the user to float the EN pin to enable the device. If
an application requires control of the EN pin, open-drain or open-collector output logic can be used to interface
with the pin.
The TPSM8683x implements internal undervoltage lockout (UVLO) circuitry on the VIN pin. The device is
disabled when the VIN pin voltage falls below the internal VIN UVLO threshold. The internal VIN UVLO threshold
has a hysteresis of 550mV.
If an application requires a higher UVLO threshold on the VIN pin, then the EN pin can be configured as shown
in 图 6-2. When using the external UVLO function, TI recommends setting the hysteresis at a value greater than
500mV.
The EN pin has a small pullup current, Ip, which sets the default state of the pin to enable when no external
components are connected. The pullup current is also used to control the voltage hysteresis for the UVLO
function because the pullup current increases by Ih when the EN pin crosses the enable threshold. Use 方程式 3
and 方程式 4 to calculate the values of R1 and R2 for a specified UVLO threshold. After R1, R2 are settled
down, the VEN voltage can be calculated by 方程式5, which must be lower than 5.5V with maximum VIN.
Copyright © 2024 Texas Instruments Incorporated
English Data Sheet: SLVSH20
16
提交文档反馈
Product Folder Links: TPSM86837 TPSM86838
TPSM86837, TPSM86838
ZHCSR53B –OCTOBER 2023 –REVISED MAY 2024
www.ti.com.cn
VIN
Device
R1
R2
Ip
Ih
EN
图6-2. Adjustable VIN Undervoltage Lockout
V
ENfalling
V
V
×
− V
START
STOP
V
ENrising
R =
1
(3)
V
ENfalling
I
×
1 −
+ I
p
h
V
ENrising
R
× V
1
ENfalling
R =
2
(4)
(5)
− V
+ R × I + I
1 p h
STOP
ENfalling
R
× V + R × R × I + I
2
IN
1
1
2
2
p
h
V
=
EN
R
+ R
Where
• Ip = 1µA
• Ih = 3µA
• VENfalling = 1.07V
• VENrising = 1.18V
6.3.5 Output Overcurrent Limit and Undervoltage Protection
The output overcurrent protection (OCP) is implemented using a cycle-by-cycle low-side MOSFET valley current
detection and high-side MOSFET peak current detection. The switching current is monitored by measuring the
MOSFET drain to source voltage. This voltage is proportional to the switching current. To improve accuracy, the
voltage sensing is temperature compensated.
There are some important considerations for this type of overcurrent limit. When the load current is higher than
the ILS_LIMIT added by one half of the peak-to-peak inductor ripple current, or higher than IHS_LIMIT subtracted by
one half of the peak-to-peak inductor ripple current, the OCP is triggered and the current is being limited, output
voltage tends to drop because the load demand is higher than what the module can support. When the output
voltage falls below 65% of the target voltage, the UVP comparator detects this fall and shuts down the device
after a deglitch wait time of 256 us and then re-start after the hiccup time of 10.5 cycles of soft-start time. When
the overcurrent condition is removed, the output recovers.
6.3.6 Overvoltage Protection
When the output voltage becomes higher than 125% of the target voltage, the OVP is triggered. The output is
discharged after a deglitch time of 32us and both the high-side MOSFET driver and the low-side MOSFET driver
turn off. When the overvoltage condition is removed, the output voltage recovers.
Copyright © 2024 Texas Instruments Incorporated
17
English Data Sheet: SLVSH20
提交文档反馈
Product Folder Links: TPSM86837 TPSM86838
TPSM86837, TPSM86838
ZHCSR53B –OCTOBER 2023 –REVISED MAY 2024
www.ti.com.cn
6.3.7 UVLO Protection
Undervoltage Lockout protection(UVLO) monitors the internal regulator voltage. When the voltage is lower than
UVLO threshold voltage, the device is shut down. This protection is non-latched.
6.3.8 Thermal Shutdown
The junction temperature (TJ) of the device is monitored by an internal temperature sensor. If TJ exceeds 165°C
(typical), the device goes into thermal shutdown. Both the high-side and low-side power FETs are turned off and
the discharge path is turned on. When TJ decreases below the hysteresis amount, the module resumes normal
operation, beginning with soft start. To avoid unstable conditions, a hysteresis of typically 30°C is implemented
on the thermal shutdown temperature.
6.3.9 Output Voltage Discharge
The TPSM8683x has a built-in discharge function by using an integrated MOSFET with 200Ω RDS(on), which is
connected to the output terminal SW. The discharge is slow due to the lower current capability of the MOSFET.
The discharge path turns on when the device is turned off due to UV, OV, OT, and EN shutdown conditions.
6.3.10 Power Good
The TPSM8683x has a built-in power-good (PG) function to indicate whether the output voltage has reached an
appropriate level or not. The PG signal can be used for start-up sequencing of multiple rails. The PG pin is an
open-drain output that requires a pullup resistor (to any voltage below 5.5V). TI recommends a pullup resistor of
100 kΩ to pull the pin up to 5V voltage. The pin can sink 10mA of current and maintain the specified logic low
level. After the FB pin voltage is between 90% and 110% of the internal reference voltage (VREF) and after a
deglitch time of 64µs, the PG turns to high impedance status. The PG pin is pulled low after a deglitch time of
32µs when FB pin voltage is lower than 85% of the internal reference voltage or greater than 115% of the
internal reference voltage, or in events of thermal shutdown, EN shutdown, UVLO conditions. VIN must remain
present for the PG pin to stay Low. The PG pin logic are shown in 表6-2.
表6-2. Power-Good Pin Logic Table
PG Logic Status
Device State
High Impedance
Low
VFB does not trigger VPGTH
VFB triggers VPGTH
√
Enable (EN = High)
√
√
√
√
Shutdown (EN = Low)
UVLO
2V < VIN < VUVLO
TJ > TSD
Thermal shutdown
Power supply removal
VIN < 2V
√
6.3.11 Large Duty Operation
The TPSM8683x can support large duty operations by smoothly dropping down the switching frequency. The
switching frequency is allowed to smoothly drop to make TON extended to implement the large duty operation
and also improve the performance of the load transient performance. The TPSM8683x can support up to 98%
duty cycle operation.
6.4 Device Functional Modes
6.4.1 Standby Operation
The TPSM8683x can be placed in standby mode by pulling the EN pin low. The device operates with a
shutdown current of 3µA (typical) when in standby condition.
6.4.2 Light Load Operation
TPSM86837 operates in Eco-mode, which maintains high efficiency at light loading. As the output current
decreases from heavy load conditions, the inductor current is also reduced and eventually comes to a point
Copyright © 2024 Texas Instruments Incorporated
English Data Sheet: SLVSH20
18
提交文档反馈
Product Folder Links: TPSM86837 TPSM86838
TPSM86837, TPSM86838
ZHCSR53B –OCTOBER 2023 –REVISED MAY 2024
www.ti.com.cn
where the rippled valley touches zero level, which is the boundary between continuous conduction and
discontinuous conduction modes. The rectifying MOSFET is turned off when the zero inductor current is
detected. As the load current further decreases, the converter runs into discontinuous conduction mode. The on-
time is kept almost the same as the on-time was in continuous conduction mode so that discharging the output
capacitor with smaller load current to the level of the reference voltage takes longer. This fact makes the
switching frequency lower, proportional to the load current, and keeps the light load efficiency high.
TPSM86838 operates in forced CCM (FCCM) mode. The switching frequency is maintained at an almost
constant level over the entire load range which is designed for applications requiring tight control of the switching
frequency and output voltage ripple at the cost of lower efficiency under light load.
Copyright © 2024 Texas Instruments Incorporated
19
English Data Sheet: SLVSH20
提交文档反馈
Product Folder Links: TPSM86837 TPSM86838
TPSM86837, TPSM86838
ZHCSR53B –OCTOBER 2023 –REVISED MAY 2024
www.ti.com.cn
7 Application and Implementation
备注
Information in the following applications sections is not part of the TI component specification, and TI
does not warrant its accuracy or completeness. TI’s customers are responsible for determining
suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
7.1 Application Information
The schematic of 图7-1 shows a typical application for TPSM8683x. This design converts an input voltage range
of 4.5V to 28V down to 1.8V with a maximum output current of 8A.
7.2 Typical Application
The application schematic in 图 7-1 shows the TPSM8683x 4.5V to 28V Input, 1.8V output module design
meeting the requirements for 8A output. This circuit is available as the evaluation module (EVM). The sections
provide the design procedure.
TPSM8683xRCG
图7-1. TPSM8683x 1.8V, 8A Reference Design
7.2.1 Design Requirements
表7-1 shows the design parameters for this application.
表7-1. Design Parameters
PARAMETER
Input voltage range
EXAMPLE VALUE
24V nominal, 4.5V to 28V
Output voltage
1.8V
ΔVOUT = ±5%
20mV
Transient response, 8A load step
Output ripple voltage
Output current rating
Operating frequency
8A
800kHz
Copyright © 2024 Texas Instruments Incorporated
20
提交文档反馈
Product Folder Links: TPSM86837 TPSM86838
English Data Sheet: SLVSH20
TPSM86837, TPSM86838
ZHCSR53B –OCTOBER 2023 –REVISED MAY 2024
www.ti.com.cn
7.2.2 Detailed Design Procedure
7.2.2.1 Output Voltage Resistors Selection
The output voltage is set with a resistor divider from the output node to the VFB pin. TI recommends to use 1%
tolerance or better divider resistors. Start by using 方程式 6 to calculate VOUT. R6 is optional and can be used to
measure the control loop frequency response.
To improve efficiency at very light loads consider using larger value resistors. If the resistance is too high, the
device is more susceptible to noise and voltage errors from the VFB input current are more noticeable. Please
note that TI does not recommend dynamically adjusting output voltage.
R7
V
= 0.6 × 1 +
R8
(6)
OUT
7.2.2.2 Output Filter Selection
The LC filter used as the output filter has double pole at:
1
f
=
(7)
p
2π ×
L
× C
OUT
OUT
At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal
gain of the device. The low frequency phase is 180 degrees. At the output filter pole frequency, the gain rolls off
at a –40dB per decade rate and the phase drops rapidly. D-CAP3 control mode introduces a high frequency
zero that reduces the gain roll off to –20dB per decade and increases the phase to 90 degrees one decade
above the zero frequency. The inductor and capacitor for the output filter must be selected so that the double
pole of 方程式 7 is located below the high frequency zero but close enough that the phase boost provided by the
high frequency zero provides adequate phase margin for a stable circuit. To meet this requirement, use the
values recommended in 表7-2.
表7-2. Recommended Component Values
COUT (µF)(3)
C8 (pF)(4)
Switching
R7
(kΩ)(2)
R8
(kΩ)
Output Voltage
(V)(1)
Frequency (kHz)
Typical
Maximum
1.05
1.8
7.5
20
10
10
22uF × 3
22uF × 3
22uF × 10
30-100 (47
typical)
22uF × 10
22uF × 10
800
30-100 (47
typical)
3.3
45.3
10
22uF × 3
30-100 (47
typical)
5
73.2
7.5
20
10
10
10
22uF × 2
22uF × 3
22uF × 3
22uF × 10
22uF × 10
22uF × 10
1.05
1.8
30-100 (47
typical)
1200
30-100 (47
typical)
3.3
5
45.3
73.2
10
10
22uF × 3
22uF × 2
22uF × 10
22uF × 10
100-200
(150 typical)
(1) Please use the recommended COUT of the higher and closest output rail for unlisted output rails.
(2) R7 = 0Ωfor VOUT = 0.6V.
(3) COUT in this data sheet is using Murata GRM32ER71E226KE15L 25VDC capacitor. TI
recommends to use the same effective output capacitance. The effective capacitance is defined as
the actual capacitance under DC bias and temperature, not the rated or nameplate values. All high
value ceramic capacitors have a large voltage coefficient in addition to normal tolerances and
temperature effects. A careful study of bias and temperature variation of any capacitor bank must
Copyright © 2024 Texas Instruments Incorporated
21
提交文档反馈
Product Folder Links: TPSM86837 TPSM86838
English Data Sheet: SLVSH20
TPSM86837, TPSM86838
ZHCSR53B –OCTOBER 2023 –REVISED MAY 2024
www.ti.com.cn
be made to make sure that the minimum value of effective capacitance is provided. Refer to the
information of DC bias and temperature characteristics from manufacturers of ceramic capacitors.
Higher than Cout_max capacitance is allowed by careful tuning the feedforward compensation.
(4) R10 and C8 can be used to improve the load transient response or improve the loop-phase margin.
The Optimizing Transient Response of Internally Compensated DCDC Converters with Feed-
forward Capacitor application report is helpful when experimenting with a feed-forward capacitor.
The capacitor value and ESR determines the amount of output voltage ripple. The TPSM8683x is intended for
use with ceramic or other low ESR capacitors. Use 方程式8 to determine the required RMS current rating for the
output capacitor.
V
× V − V
IN
OUT
OUT
× Fsw
I
=
(8)
CO RMS
12 × V × L
IN
OUT
For this design, three MuRata GRM32ER71E226KE15L 25VDC 22µF output capacitors are used so that the
effective capacitance is 68µF at DC biased voltage of 1.8V.
7.2.2.3 Input Capacitor Selection
The TPSM8683x requires input decoupling capacitors, and a bulk capacitor is needed depending on the
application. TI recommends at least two 10µF ceramic capacitors for the decoupling capacitor. The capacitor
voltage rating must be greater than the maximum input voltage. Use 方程式 9 to calculate the input voltage
ripple.
I
× 0.25
OUTMAX
∆ V
=
(9)
IN
C
× Fsw
IN
The capacitor must also have a ripple current rating greater than the maximum input current ripple of the
application. Use 方程式10 to calculate the input ripple current:
V
− V
OUT
V
IN MIN
×
V
OUT
I
= I
×
(10)
CIN RMS
OUT
V
IN MIN
IN MIN
Copyright © 2024 Texas Instruments Incorporated
English Data Sheet: SLVSH20
22
提交文档反馈
Product Folder Links: TPSM86837 TPSM86838
TPSM86837, TPSM86838
ZHCSR53B –OCTOBER 2023 –REVISED MAY 2024
www.ti.com.cn
7.2.3 Application Curves
100%
80%
60%
40%
20%
0
VIN=4.5V
VIN=12V
VIN=24V
0
1
2
3
4
5
6
7
8
Iout (A)
图7-2. TPSM86837 Efficiency
图7-3. TPSM86838 Efficiency
1.85
1.825
1.8
1.875
1.85
1.825
1.8
1.775
1.775
1.75
VIN=4.5V
VIN=12V
VIN=24V
Iout=0.1
Iout=6
Iout=8
1.75
0.001
0.01
0.1
1
10
0
5
10
15
20
25
30
Iout (A)
VIN (V)
图7-4. TPSM86838 Load Regulation
图7-5. TPSM86838 Line Regulation
900
800
700
600
200
150
100
50
Iout=6A
Iout=8A
Iout=0.1A
25 30
500
0
0
0
5
10
15
20
25
30
5
10
15
20
Vin (V)
Vin (V)
图7-6. Switching Frequency vs Input Voltage
图7-7. TPSM86837 Switching Frequency vs Input
Voltage
Copyright © 2024 Texas Instruments Incorporated
23
提交文档反馈
Product Folder Links: TPSM86837 TPSM86838
English Data Sheet: SLVSH20
TPSM86837, TPSM86838
ZHCSR53B –OCTOBER 2023 –REVISED MAY 2024
www.ti.com.cn
900
800
700
600
500
Vin = 20 mV/div (AC)
Vout = 20 mV/div (1.8V DC o set)
SW = 20 V/div
40 us/div
Iout=0.1A
25 30
图7-9. TPSM86837 Steady State Waveform, IOUT
=
0
5
10
15
Vin (V)
20
0.01A
图7-8. TPSM86838 Switching Frequency vs Input
Voltage
Vin = 20 mV/div (AC)
Vout = 10 mV/div (1.8V DC o set)
SW = 20 V/div
Vin = 500 mV/div (AC)
Vout = 20 mV/div (1.8V DC o set)
SW = 20 V/div
1 us/div
1 us/div
图7-10. TPSM86838 Steady State Waveform, IOUT
=
图7-11. Steady State Waveform, IOUT = 8A
0.01A
EN = 5 V/div
EN = 5 V/div
Vout = 2 V/div
Vout = 1 V/div
SW = 20 V/div
PG = 2 V/div
SW = 20 V/div
PG = 2 V/div
2 ms/div
200 us/div
图7-12. Enable Relative to EN
图7-13. Disable Relative to EN
Copyright © 2024 Texas Instruments Incorporated
English Data Sheet: SLVSH20
24
提交文档反馈
Product Folder Links: TPSM86837 TPSM86838
TPSM86837, TPSM86838
ZHCSR53B –OCTOBER 2023 –REVISED MAY 2024
www.ti.com.cn
Vout = 100 mV/div
Vout = 100 mV/div
Iout = 5 A/div
Iout = 5 A/div
400 us/div
400 us/div
图7-14. TPSM86837 Transient Response 0A to 4A 图7-15. TPSM86838 Transient Response 0A to 4A
Vout = 100 mV/div
Iout = 5 A/div
Vout = 100 mV/div
Iout = 5 A/div
400 us/div
400 us/div
图7-16. TPSM86837 Transient Response 0A to 8A 图7-17. TPSM86838 Transient Response 0A to 8A
7.3 Power Supply Recommendations
The TPSM8683x is designed to operate from input supply voltage in the range of 4.5V to 28V. Buck modules
require the input voltage to be higher than the output voltage for proper operation. Input supply current must be
appropriate for the desired output current. If the input voltage supply is located far from the TPSM8683x circuit,
TI recommends some additional input bulk capacitance.
7.3.1 Application Thermal Considerations
The power module integrates the main power dissipating elements, the power switches and magnetics, all into
one package, which enables smaller design size and simplifies the development. Therefore, in addition to the IC
losses, the heat generated from the inductor direct current resistance (DCR) and core losses add to the total
power dissipated in the package. Under the same operating conditions as the discrete counterparts (which have
an external inductor), the module has the challenge of dissipating more heat through a smaller surface area.
There is a constraint on the maximum output current that modules can deliver at higher operating ambient
temperatures due to limitations in maximum temperature ratings for both the inductor and IC.
The temperature rise of module can be calculated by using efficiency and EVM effective RθJA. 方程式 11
calculates the power loss from the data sheet efficiency curves:
1
η
Power Loss = V
× I
×
OUT
− 1
(11)
OUT
Where ƞ is the application conditions efficiency. As an example, 图7-2 shows the efficiency curve at 25°C for the
24Vin, 1.8Vout, 800kHz condition. At 8A load, with nearly 81% efficiency, 方程式 11 calculates the power loss as
3.378W. Multiplying by the EVM effective RθJA 24 °C/W gives a temperature rise of 81°C.
The maximum temperature rating for TPSM8683x is 150°C. Subtracting this temperature rise from the 150°C
maximum temperature results in a maximum ambient temperature of 69°C. Consider operation within this
ambient temperature.
Copyright © 2024 Texas Instruments Incorporated
25
English Data Sheet: SLVSH20
提交文档反馈
Product Folder Links: TPSM86837 TPSM86838
TPSM86837, TPSM86838
ZHCSR53B –OCTOBER 2023 –REVISED MAY 2024
www.ti.com.cn
7.4 Layout
7.4.1 Layout Guidelines
The following list summarizes the essential guidelines for PCB layout and component placement to optimize
DC/DC module performance, including thermals and EMI signature.
1. Use a four-layer PCB with two-ounce copper thickness for good thermal performance and with maximum
ground plane.
2. Place input capacitors as close as possible to the VIN pins. Note the dual and symmetrical arrangement of
the input capacitors based on the VIN1 and VIN2 pins located on each side of the module package. The
high-frequency currents are split in two and effectively flow in opposing directions such that the related
magnetic fields contributions cancel each other, leading to improved EMI performance.
• Use low-ESR 1206 or 1210 ceramic capacitors with X7R or X7S dielectric.
• Make ground return paths for the input capacitors consist of localized top-side planes that connect to the
PGND pads under the module.
• Make VIN traces as wide as possible to reduce trace impedance. The wide areas are also of advantage
from the view point of heat dissipation. Even though the VIN pins are connected internally, use a wide
polygon plane on a bottom PCB layer to connect these pins together and to the input supply.
3. Place output capacitors as close as possible to the VOUT pins. A similar dual and symmetrical arrangement
of the output capacitors enables magnetic field cancellation and EMI mitigation.
• Make ground return paths for the output capacitors consist of localized top-side planes that connect to
the PGND pads under the module.
• Make VOUT traces as wide as possible to reduce trace impedance. The wide areas are also of
advantage from the view point of heat dissipation. Even though the VOUT pins are connected internally,
use a wide polygon plane on a bottom PCB layer to connect these pins together and to the load, thus
reducing conduction loss and thermal stress.
4. Keep the FB trace as short as possible by placing the feedback resistors close to the FB pin. Reduce noise
sensitivity of the output voltage feedback path by placing the resistor divider close to the FB pin, rather than
close to the load. FB is the input to the voltage-loop error amplifier and represents a high-impedance node
sensitive to noise. Route a trace from the upper feedback resistor to the required point of output voltage
regulation. Place the voltage feedback loop away from the high-voltage switching trace, and preferably has
ground shield.
5. Provide enough PCB area for proper heatsinking. Use sufficient copper area to achieve a low thermal
impedance commensurate with the maximum load current and ambient temperature conditions. For
operation at full rated load, the top-side ground plane is an important heat-dissipating area. Use an array of
heat-sinking vias to connect the exposed pads (PGND) of the package to the PCB ground plane. If the PCB
has multiple copper layers, connect these thermal vias to inner-layer ground planes.
Copyright © 2024 Texas Instruments Incorporated
English Data Sheet: SLVSH20
26
提交文档反馈
Product Folder Links: TPSM86837 TPSM86838
TPSM86837, TPSM86838
ZHCSR53B –OCTOBER 2023 –REVISED MAY 2024
www.ti.com.cn
7.4.2 Layout Example
图7-18. TPSM8683x Layout
VOUT
Ex Vcc
EN
SS
PG
Mode
AGND
FB
VOUT
VIN
Output Cap
Input Cap
PGND
PGND
PGND
PGND
Input Cap
Output Cap
VOUT
VIN
PGND
图7-19. TPSM8683x Top Layer Design
Copyright © 2024 Texas Instruments Incorporated
27
English Data Sheet: SLVSH20
提交文档反馈
Product Folder Links: TPSM86837 TPSM86838
TPSM86837, TPSM86838
ZHCSR53B –OCTOBER 2023 –REVISED MAY 2024
www.ti.com.cn
8 Device and Documentation Support
8.1 Device Support
8.1.1 第三方产品免责声明
TI 发布的与第三方产品或服务有关的信息，不能构成与此类产品或服务或保修的适用性有关的认可，不能构成此
类产品或服务单独或与任何TI 产品或服务一起的表示或认可。
8.2 Documentation Support
8.2.1 Related Documentation
For related documentation see the following:
• Texas Instruments, TPSM86838 Buck Module Evaluation Module EVM user's guide
• Texas Instruments, Optimizing Transient Response of Internally Compensated DCDC Converters with Feed-
forward Capacitor application report
8.3 接收文档更新通知
要接收文档更新通知，请导航至 ti.com 上的器件产品文件夹。点击通知 进行注册，即可每周接收产品信息更改摘
要。有关更改的详细信息，请查看任何已修订文档中包含的修订历史记录。
8.4 支持资源
TI E2E™ 中文支持论坛是工程师的重要参考资料，可直接从专家处获得快速、经过验证的解答和设计帮助。搜索
现有解答或提出自己的问题，获得所需的快速设计帮助。
链接的内容由各个贡献者“按原样”提供。这些内容并不构成 TI 技术规范，并且不一定反映 TI 的观点；请参阅
TI 的使用条款。
8.5 Trademarks
D-CAP3™, HotRod™, and TI E2E™ are trademarks of Texas Instruments.
所有商标均为其各自所有者的财产。
8.6 静电放电警告
静电放电(ESD) 会损坏这个集成电路。德州仪器(TI) 建议通过适当的预防措施处理所有集成电路。如果不遵守正确的处理
和安装程序，可能会损坏集成电路。
ESD 的损坏小至导致微小的性能降级，大至整个器件故障。精密的集成电路可能更容易受到损坏，这是因为非常细微的参
数更改都可能会导致器件与其发布的规格不相符。
8.7 术语表
TI 术语表
本术语表列出并解释了术语、首字母缩略词和定义。
9 Revision History
注：以前版本的页码可能与当前版本的页码不同
Changes from Revision A (December 2023) to Revision B (May 2024)
Page
• 通篇添加了 TPSM86837.....................................................................................................................................1
Changes from Revision * (October 2023) to Revision A (December 2023)
Page
• 将文档状态从“预告信息”更改为“量产数据”................................................................................................1
Copyright © 2024 Texas Instruments Incorporated
English Data Sheet: SLVSH20
28
提交文档反馈
Product Folder Links: TPSM86837 TPSM86838
TPSM86837, TPSM86838
ZHCSR53B –OCTOBER 2023 –REVISED MAY 2024
www.ti.com.cn
10 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
Copyright © 2024 Texas Instruments Incorporated
29
English Data Sheet: SLVSH20
提交文档反馈
Product Folder Links: TPSM86837 TPSM86838
PACKAGE OPTION ADDENDUM
www.ti.com
15-May-2024
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
TPSM86837RCGR
TPSM86838RCGR
ACTIVE
ACTIVE
B3QFN
B3QFN
RCG
RCG
19
19
1000 RoHS & Green
1000 RoHS & Green
NIPDAU
Level-3-245C-168 HR
Level-3-245C-168 HR
-40 to 150
-40 to 150
TPSM86837
TPSM86838
Samples
Samples
NIPDAU
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
15-May-2024
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
16-May-2024
TAPE AND REEL INFORMATION
REEL DIMENSIONS
TAPE DIMENSIONS
K0
P1
W
B0
Reel
Diameter
Cavity
A0
A0 Dimension designed to accommodate the component width
B0 Dimension designed to accommodate the component length
K0 Dimension designed to accommodate the component thickness
Overall width of the carrier tape
W
P1 Pitch between successive cavity centers
Reel Width (W1)
QUADRANT ASSIGNMENTS FOR PIN 1 ORIENTATION IN TAPE
Sprocket Holes
Q1 Q2
Q3 Q4
Q1 Q2
Q3 Q4
User Direction of Feed
Pocket Quadrants
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPSM86837RCGR
TPSM86838RCGR
B3QFN
B3QFN
RCG
RCG
19
19
1000
1000
330.0
330.0
16.4
16.4
5.28
5.28
5.78
5.78
4.28
4.28
8.0
8.0
16.0
16.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-May-2024
TAPE AND REEL BOX DIMENSIONS
Width (mm)
H
W
L
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPSM86837RCGR
TPSM86838RCGR
B3QFN
B3QFN
RCG
RCG
19
19
1000
1000
336.0
336.0
336.0
336.0
48.0
48.0
Pack Materials-Page 2
PACKAGE OUTLINE
RCG0019A
B3QFN - 4.1 mm max height
S
C
A
L
E
2
.
0
0
0
PLASTIC QUAD FLATPACK - NO LEAD
5.1
4.9
A
B
PIN 1 INDEX AREA
5.6
5.4
4.1
3.9
C
SEATING PLANE
0.08 C
0.05
0.00
3X
1.6 0.1
SYMM
(0.125) TYP
20X (0.15)
(0.2) TYP
4X 0.5
4X 0.65
9
8
19
18
17
2X 1.05
SYMM
2X 2.5
10X 0.5
3X 0.8 0.1
0.3
12X
0.2
0.1
0.05
16
1
C A B
C
0.85
0.75
PIN 1 ID
12X
0.8
0.7
4X
0.1
0.05
C A B
C
4229318/A 12/2022
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
RCG0019A
B3QFN - 4.1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
4X (1.2)
3X (1.6)
SYMM
4X (0.325)
4X (0.5)
4X (0.65)
1
16
SEE SOLDER MASK
DETAIL
10X (0.5)
17
2X (1.05)
SYMM
18
19
(R0.05) TYP
20X (0.25)
12X (1)
3X (0.8)
9
8
(4.4)
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 15X
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
METAL UNDER
SOLDER MASK
METAL EDGE
EXPOSED METAL
SOLDER MASK
OPENING
EXPOSED
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DEFINED
(PREFERRED)
SOLDER MASK DETAILS
NOT TO SCALE
4229318/A 12/2022
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
RCG0019A
B3QFN - 4.1 mm max height
PLASTIC QUAD FLATPACK - NO LEAD
4X (1.2)
4X (0.55)
3X (1.47)
4X (0.5)
4X (0.65)
16
1
10X (0.5)
17
2X (1.05)
SYMM
18
19
(R0.05) TYP
20X (0.25)
20X (1)
3X (0.76)
4X (0.75)
8
9
SYMM
(4.4)
SOLDER PASTE EXAMPLE
BASED ON 0.125 MM THICK STENCIL
SCALE: 15X
PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE
PADS 1, 8, 9 & 16: 90%
PADS 17, 18 & 19: 82%
4229318/A 12/2022
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
重要声明和免责声明
TI“按原样”提供技术和可靠性数据（包括数据表）、设计资源（包括参考设计）、应用或其他设计建议、网络工具、安全信息和其他资源，
不保证没有瑕疵且不做出任何明示或暗示的担保，包括但不限于对适销性、某特定用途方面的适用性或不侵犯任何第三方知识产权的暗示担
保。
这些资源可供使用 TI 产品进行设计的熟练开发人员使用。您将自行承担以下全部责任：(1) 针对您的应用选择合适的 TI 产品，(2) 设计、验
证并测试您的应用，(3) 确保您的应用满足相应标准以及任何其他功能安全、信息安全、监管或其他要求。
这些资源如有变更，恕不另行通知。TI 授权您仅可将这些资源用于研发本资源所述的 TI 产品的应用。严禁对这些资源进行其他复制或展示。
您无权使用任何其他 TI 知识产权或任何第三方知识产权。您应全额赔偿因在这些资源的使用中对 TI 及其代表造成的任何索赔、损害、成
本、损失和债务，TI 对此概不负责。
TI 提供的产品受 TI 的销售条款或 ti.com 上其他适用条款/TI 产品随附的其他适用条款的约束。TI 提供这些资源并不会扩展或以其他方式更改
TI 针对 TI 产品发布的适用的担保或担保免责声明。
TI 反对并拒绝您可能提出的任何其他或不同的条款。IMPORTANT NOTICE
邮寄地址：Texas Instruments, Post Office Box 655303, Dallas, Texas 75265
Copyright © 2024，德州仪器 (TI) 公司
TPSM86838 相关器件
| 型号 | 制造商 | 描述 | 价格 | 文档 |
| TPSM8A28 | TI | TPSM8A28, TPSM8A29 2.7-V to 16-V Input, 12-A, 15-A Buck Power Modules with Differential Remote Sense | 获取价格 |
|
| TPSM8A28RDGR | TI | TPSM8A28, TPSM8A29 2.7-V to 16-V Input, 12-A, 15-A Buck Power Modules with Differential Remote Sense | 获取价格 |
|
| TPSM8A29 | TI | TPSM8A28, TPSM8A29 2.7-V to 16-V Input, 12-A, 15-A Buck Power Modules with Differential Remote Sense | 获取价格 |
|
| TPSM8A29RDGR | TI | TPSM8A28, TPSM8A29 2.7-V to 16-V Input, 12-A, 15-A Buck Power Modules with Differential Remote Sense | 获取价格 |
|
| TPSM8D6B24 | TI | 4V 至 16V 输入、双路 25A/单路 50A PMBus® 电源模块 | 获取价格 |
|
| TPSM8D6B24MOWR | TI | 4V 至 16V 输入、双路 25A/单路 50A PMBus® 电源模块 | MOW | 59 | -40 to 125 | 获取价格 |
|
| TPSM8D6C24 | TI | 4V 至 16V 输入、双路 35A PMBus® 电源模块 | 获取价格 |
|
| TPSM8D6C24MOWR | TI | 4V 至 16V 输入、双路 35A PMBus® 电源模块 | MOW | 59 | -40 to 125 | 获取价格 |
|
| TPSM8S6B24MOYR | TI | 具有增强安全性的 4V 至 16V 输入、25A、4x 可堆叠 PMBus® 电源模块 | MOY | 45 | -40 至 125 | 获取价格 |
|
| TPSM8S6B24S | TI | 具有增强安全性的 4V 至 16V 输入、25A、4x 可堆叠 PMBus? 电源模块 | 获取价格 |
|
TPSM86838 相关文章
三星电子专注提升1b DRAM性能与良率，否认重新设计传闻
- 2025-01-22
- 25
特朗普宣布OpenAI、软银等联手投资5000亿美元建设人工智能基础设施
- 2025-01-22
- 29
思瑞浦新推车规级LIN SBC芯片TPT1028Q，引领汽车电子高效新纪元
- 2025-01-22
- 26
比利时氮化镓制造商BelGaN破产，中国买家积极竞购设备资产
- 2025-01-22
- 24
