TPSM8A29
更新时间：2025-01-11 23:24:17
品牌：TI
描述：TPSM8A28, TPSM8A29 2.7-V to 16-V Input, 12-A, 15-A Buck Power Modules with Differential Remote Sense
概述
数据手册TPSM8A29 概述
TPSM8A28, TPSM8A29 2.7-V to 16-V Input, 12-A, 15-A Buck Power Modules with Differential Remote Sense
TPSM8A29 数据手册
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SLVSFQ9A – AUGUST 2021 – REVISED NOVEMBER 2021
TPSM8A28, TPSM8A29 2.7-V to 16-V Input, 12-A, 15-A Buck Power Modules with
Differential Remote Sense
1 Features
3 Description
•
•
•
TPSM8A28: 3-V to 16-V input range up to 12 A
TPSM8A29: 4-V to 16-V input range up to 15 A
2.7-V to 16-V input range with external bias
ranging from 4.75 V to 5.3 V
Output voltage range: 0.6 V to 5.5 V
Integrated MOSFET, inductor, and basic passives
D-CAP3™ control mode with fast load-step
response
Supports all ceramic output capacitors
0.6-V reference voltage has ±1% tolerance from
–40°C to +125°C junction temperature
Selectable FCCM or auto-skip Eco-mode™ for high
light-load efficiency
Programmable current limit with RTRIP
Pin-selectable switching frequency: 600 kHz, 800
kHz, 1 MHz
The TPSM8A28 and TPSM8A29 buck power modules
are small and highly efficient. This module family
contains integrates inductor and basic passives, and
does not require external compensation, minimizing
solution size.
•
•
•
Features include differential remote sense, high-
performance integrated MOSFETs, and an accurate
0.6-V reference, D-CAP3™ control mode,selectable
Skip-mode and programmable soft-start.
•
•
TPSM8A28 and TPSM8A29 are lead-free, and fully
RoHS compliant without exemption.
•
Device Information
•
•
PART NUMBER
TPSM8A28
PACKAGE(1)
B3QFN-RDG
B3QFN-RDG
BODY SIZE (NOM)
6.5 mm × 7.5 mm
6.5 mm × 7.5 mm
TPSM8A29
•
•
•
•
•
•
•
•
Differential remote sense for high output accuracy
Programmable soft-start time
External reference input for tracking
Prebiased start-up capability
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Open-drain power-good output
Hiccup for OC and UV faults, latch-off for OV faults
6.5-mm × 7.5-mm × 4.0-mm, RDG package
Fully RoHS compliant without exemption
2 Applications
•
•
•
•
Data center switch
Core router
Single board computer
Optical module
VOUT
VIN
VOUT
DNC
SW
VIN
EN
VCC
Vosns+
Vosns-
TPSM8A28
TPSM8A29
FB
PGOOD
MODE
TRIP
VSNS-
SS/
REFIN
AGND
PGND
Net-tie
Efficiency Graph
Simplified Schematic
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
TPSM8A28, TPSM8A29
SLVSFQ9A – AUGUST 2021 – REVISED NOVEMBER 2021
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Table of Contents
1 Features............................................................................1
2 Applications.....................................................................1
3 Description.......................................................................1
4 Revision History.............................................................. 2
5 Pin Configuration and Functions...................................3
6 Specifications.................................................................. 5
6.1 Absolute Maximum Ratings........................................ 5
6.2 ESD Ratings............................................................... 5
6.3 Recommended Operating Conditions.........................5
6.4 Thermal Information....................................................6
6.5 Electrical Characteristics.............................................6
6.6 Typical Characteristics................................................9
7 Detailed Description......................................................10
7.1 Overview...................................................................10
7.2 Functional Block Diagram.........................................10
7.3 Feature Description...................................................11
7.4 Device Functional Modes..........................................19
8 Application and Implementation..................................23
8.1 Application Information............................................. 23
8.2 Typical Application.................................................... 23
9 Power Supply Recommendations................................34
10 Layout...........................................................................35
10.1 Layout Guidelines................................................... 35
10.2 Layout Example...................................................... 35
10.3 EMI..........................................................................36
11 Device and Documentation Support..........................38
11.1 Device Support........................................................38
11.2 Documentation Support.......................................... 38
11.3 Receiving Notification of Documentation Updates..38
11.4 Support Resources................................................. 38
11.5 Trademarks............................................................. 38
11.6 Electrostatic Discharge Caution..............................38
11.7 Glossary..................................................................38
12 Mechanical, Packaging, and Orderable
Information.................................................................... 39
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision * (August 2021) to Revision A (November 2021)
Page
•
Changed TPSM8A29 from Advance Information to Production Data and added TPSM8A28........................... 1
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5 Pin Configuration and Functions
PGND
VOUT
VOUT 10
25
11
20
19
PGND
PGND
1
21 PGND
FB
TRIP
9
8
12
13
PGOOD
SW
VCC
2
3
4
5
6
7
VSNS-
AGND
18 EN
24 PGND
22
PGND
MODE
BOOT
VIN
7
6
5
4
3
2
14 AGND
17
16
15
VIN
VIN
SS/REF IN
15
16
17
VIN
VIN
23 VIN
23 VIN
VIN
VIN
SS/REF IN
BOOT
MODE
VIN
14 AGND
PGND
22
24 PGND
VCC
SW
18 EN
AGND
TRIP
8
9
13
12
VSNS-
FB
PGOOD
19
20
21 PGND
PGND
1
PGND
VOUT 10
25
11
PGND
VOUT
Figure 5-1. 25-Pin B3QFN RDG Package (Top View) Figure 5-2. 25-Pin B3QFN RDG Package (Bottom
View)
Table 5-1. Pin Functions
PIN
TYPE(1)
DESCRIPTION
NAME
NO.
1, 20, 21,
22, 24, 25
PGND
G
O
Power ground of internal low-side MOSFET
Output switching terminal of the power converter. No external connection needed. Do not
connect.
SW
2
Internal 4.5-V LDO output. Float or connect to an external power supply between 4.75 V
and 5.3 V to save the power losses on the internal LDO. The voltage source on this pin
powers both the internal circuitry and gate driver. A 1-μF bypass capacitor is built in. No
external bypass capacitors are required.
VCC
3
I/O
Power-supply input pins for the integrated power MOSFET pair and the internal LDO.
Place the decoupling input capacitors from the VIN pins to PGND pins as close as
possible.
4, 5, 16, 17,
23
VIN
P
Supply rail for the high-side gate driver. A boot capacitor is integrated inside module. No
external connection is needed. Do not connect.
BOOT
6
I/O
The MODE pin sets Forced continuous-conduction mode (FCCM) or Skip-mode
operation. It also selects the operating frequency by connecting a resistor from the MODE
pin to AGND pin. ±1% tolerance resistor is recommended. See Table 7-1 for details.
MODE
AGND
TRIP
7
8, 14
9
I
G
Ground pin. Reference point for the internal control circuits
Current limit setting pin. Connect a resistor to AGND to set the current limit trip point.
±1% tolerance resistor is highly recommended. See Section 7.3.9 for details on the OCL
setting.
I/O
These pins are connected to the output terminal of inductor. Connect these pins to output
bypass capacitors.
VOUT
FB
10, 11
12
O
I
Output voltage feedback input. A resistor divider from the VOUT to VSNS– (tapped to FB
pin) sets the output voltage.
The return connection for a remote voltage sensing configuration. It is also used as
ground for the internal reference. Short to AGND for a single-end sense configuration.
VSNS–
13
I
Dual-function pin. Soft-start function: Connecting a capacitor to the VSNS– pin programs
the soft-start time. Minimum soft-start time (1.5 ms) is fixed internally. REFIN function: The
device always looks at the voltage on this SS/REFIN pin as the reference for the control
loop. The internal reference voltage can be overridden by an external DC voltage source
on this pin for tracking application.
SS/REFIN
EN
15
18
I/O
I
Enable pin. The enable pin turns the DC/DC switching converter on or off. Floating the EN
pin before start-up disables the converter. The recommended operating condition for EN
pin is maximum 5.5 V. Do not connect the EN pin to the VIN pin directly.
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Table 5-1. Pin Functions (continued)
PIN
TYPE(1)
DESCRIPTION
NAME
NO.
Open-drain power-good status signal. When the FB voltage moves outside the specified
limits, PGOOD goes low after a 2-µs delay.
PGOOD
19
O
(1) I = Input, O = Output, P = Supply, G = Ground
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6 Specifications
6.1 Absolute Maximum Ratings
over operating free-air temperature range (unless otherwise noted)(1)
MIN
–0.3
–0.3
–3.0
–3.0
–0.3
–0.3
–0.3
–0.3
–0.3
MAX
18
UNIT
VIN
DC
18
SW
Transient < 10 ns
Transient < 2 ns
22
Input voltage(2)
22
BOOT
24
V
VSNS–
+0.3
6
TRIP, MODE, SS/REFIN, FB, EN
PGOOD
6
Output voltage
VCC
6
Mechanical shock
Mil-STD-883H, Method 2002.5, 1 msec, 1/2 sine, mounted
500
20
G
G
Mechanical vibration Mil-STD-883H, Method 2007.3, 20 to 2000 Hz
Operating junction temperature, TJ
–40
–55
125
150
°C
°C
Storage temperature, Tstg
(1) Operation outside the Absolute Maximum Ratings may cause permanent device damage. Absolute Maximum Ratings do not imply
functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions.
If used outside the Recommended Operating Conditions but within the Absolute Maximum Ratings, the device may not be fully
functional, and this may affect device reliability, functionality, performance, and shorten the device lifetime.
(2) All voltages are with respect to network ground terminal.
6.2 ESD Ratings
VALUE
±2000
±500
UNIT
Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1)
Charged-device model (CDM), per ANSI/ESDA/JEDEC JS-002(2)
Electrostatic
discharge
V(ESD)
V
(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process. Manufacturing with
less than 500-V HBM is possible with the necessary precautions.
(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.
6.3 Recommended Operating Conditions
over operating free-air temperature range (unless otherwise noted)
MIN
2.7
MAX
16
UNIT
VIN with valid external bias on VCC
VIN with internal LDO, TPSM8A28
VIN with internal LDO, TPSM8A29
External reference to SS/REFIN
External bias range for VCC
VIN to enable the converter with internal LDO
TRIP, MODE, FB, EN
3.0
16
4.0
16
0.5
1.2
5.3
V
Input voltage
4.75
3.3
–0.1
–50
–0.1
4.5
5.5
50
VSNS– (refer to AGND)
PGOOD
mV
V
5.5
5.3
10
Output voltage
VCC
Input current
PGOOD
0
mA
°C
Junction temperature, TJ
Operating junction temperature
–40
125
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6.4 Thermal Information
TPSM8A28 TPSM8A29
THERMAL METRIC(1)
RDG (B3QFN)
25 PINS
21.6
UNIT
RθJA
Junction-to-ambient thermal resistance
Junction-to-case (top) thermal resistance
Junction-to-board thermal resistance
°C/W
°C/W
°C/W
RθJC(top)
RθJB
7.5
13.0
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics Application
Report.
6.5 Electrical Characteristics
TJ = –40°C to +125°C, VCC = Internal 4.5V LDO, both TPSM8A29 and TPSM8A28 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
SUPPLY CURRENT
VIN operating nonswitching supply
current
VEN = 2 V, VFB = 0.65 V, VIN = 12 V, no
external bias on the VCC pin
IQ_VIN
680
9.5
680
75
850
20
µA
µA
µA
µA
VEN = 0 V, VIN =12 V, no external bias on the
VCC pin
ISD_VIN
IQ_VCC
ISD_VCC
VIN shutdown supply current
VCC quiescent current
VCC shutdown current
TJ = 25°C, VEN = 2 V, VFB = 0.65 V, VIN = 5
V, 5.0 V external bias on the VCC pin
820
85
TJ = 25°C, VEN = 0 V, VIN = 0 V, 5.0 V
external bias on the VCC pin
REFERENCE VOLTAGE
VINTREF Internal REF voltage
TJ = 25°C
600
mV
mV
mV
nA
Internal REF voltage tolerance
Internal REF voltage tolerance
FB input current
TJ = 0°C to 70°C
TJ = –40°C to 125°C
VFB = VINTREF
597
594
603
606
100
IFB
50
70
OUTPUT DISCHARGE
VIN = 12 V, VCC = internal LDO, Vsw = 0.5
V, power conversion disabled
RDischg
Output discharge resistance
Ω
SWITCHING FREQUENCY
VIN = 12 V, VOUT = 1.2 V, RMODE = 0 Ω to
AGND
490
720
840
620
800
750
880
VO switching frequency, FCCM
operation
VIN = 12 V, VOUT = 1.2 V, RMODE = 30.1 kΩ
to AGND
fSW
kHz
VIN = 12 V, VOUT = 1.2 V, RMODE = 60.4 kΩ
to AGND
1000
70
1250
tON(min)
tOFF(min)
ENABLE
VENH
Minimum on time
Minimum off time
TJ = 25°C(1)
85
ns
ns
TJ = 25°C, HS FET gate falling to rising(1)
220
EN enable threshold voltage (rising)
EN disable threshold voltage (falling)
EN hysteresis voltage
1.17
0.97
1.22
1.02
0.2
1.27
1.07
V
V
VENL
VENHYST
VENLEAK
V
EN input leakage current
VEN = V
0.5
5
µA
EN pin to AGND. EN floating disables the
converter.
EN internal pulldown resistance
6500
kΩ
INTERNAL VCC LDO
VCC
Internal LDO output voltage
VIN = 12 V, ILOAD = 2 mA
VCC rising
4.32
2.80
2.62
4.5
2.87
2.7
4.68
2.94
2.77
V
V
V
VCC undervoltage-lockout (UVLO)
threshold voltage
VCCUVLO
VCC falling
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6.5 Electrical Characteristics (continued)
TJ = –40°C to +125°C, VCC = Internal 4.5V LDO, both TPSM8A29 and TPSM8A28 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
VCC undervoltage-lockout (UVLO)
threshold voltage
VCCUVLO
VCCDO
VCC hysteresis
0.17
V
LDO low-droop dropout voltage
LDO overcurrent limit
VIN = 3.0 V, IVCC_LOAD = 2 mA, TJ = 25°C
All VINs, all temperature
62
75
mV
mA
105
158
STARTUP
VO rising from 0 V to 95% of final setpoint,
CSS/REFIN = open
tSS
Soft-start time
1
1.5
ms
SS/REFIN sourcing current
SS/REFIN sinking current
VSS/REFIN = 0 V
VSS/REFIN = 1 V
36
12
µA
µA
The delay from EN goes high to the first SW
rising edge with internal LDO configuration.
CVCC = 2.2 µF. CSS/REFIN = 220 nF
EN to first switching delay, internal
LDO
0.93
2
ms
The delay from EN goes high to the
first SW rising edge with external VCC
bias configuration. VCC bias must reach
regulation before EN ramp up. CSS/REFIN
= 220 nF.
EN to first switching delay, external
VCC bias
550
900
µs
PGOOD COMPARATOR
FB rising, PGOOD low to high
FB rising, PGOOD high to low
FB falling, PGOOD high to low
FB rising, PGOOD stays high
89%
113%
77%
92.5%
116%
95%
119%
83%
VPGTH
PGOOD threshold
80%
VPGTH
IPG
OOB (out-of-bounds) threshold
PGOOD sink current
103%
105.5%
108%
VPGOOD = 0.4 V, VIN = 12 V, VCC = Internal
LDO
25
mA
mV
IPGOOD = 5.5 mA, VIN = 12 V, VCC = internal
LDO
IPG
PGOOD low-level output voltage
PGOOD delay time
400
Delay for PGOOD from low to high
Delay for PGOOD from high to low
1.0
0.5
1.4
5
ms
µs
tPG_delay
PGOOD leakage current when
pulled high
IPG_lkg
TJ = 25°C, VPGOOD = 3.3 V, VFB = VINTREF
5
850
µA
mV
mV
V
VIN = 0 V, VCC = 0 V, VEN = 0 V, PGOOD
pulled up to 3.3 V through a 100-kΩ resistor
710
850
PGOOD clamp low-level output
voltage
VIN = 0 V, VCC = 0 V, VEN = 0 V, PGOOD
pulled up to 3.3 V through a 10-kΩ resistor
1000
1.5
Minimum VCC for valid PGOOD
output
OVERCURRENT PROTECTION
RTRIP
RTRIP
TRIP pin resistance range
TRIP pin resistance range
TPSM8A28
TPSM8A29
4.02
0
14.7
14.7
kΩ
kΩ
Current limit threshold, TPSM8A29 Valley current on LS FET, 0 kΩ ≤ RTRIP ≤ 3.3
IOCL
14.8
18.4
21.7
A
only
kΩ TPSM8A29 only
IOCL
Current limit threshold
Current limit threshold
Current limit threshold
KOCL for RTRIP equation
Negative current limit threshold
Valley current on LS FET, RTRIP = 4.02 kΩ
Valley current on LS FET, RTRIP = 4.99 kΩ
Valley current on LS FET, RTRIP = 10 kΩ
12.0
9.9
14.2
12.0
16.3
14.1
8.1
A
A
IOCL
IOCL
3.9
6.0
A
KOCL
INOCL
60000
–10
A Ω
A
All VINs
–12
–8
Zero-cross detection current
threshold, open loop
IZC
VIN = 12 V, VCC = Internal LDO
400
mA
UVLO
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6.5 Electrical Characteristics (continued)
TJ = –40°C to +125°C, VCC = Internal 4.5V LDO, both TPSM8A29 and TPSM8A28 (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
2.7
UNIT
V
Rising
Falling
2.1
2.4
VINUVLO
VIN UVLO threshold voltage
1.55
1.85
2.15
V
Overvoltage-protection (OVP)
threshold voltage
VOVP
113%
116%
119%
THERMAL SHUTDOWN
Thermal shutdown threshold(1)
Thermal shutdown hysteresis(1)
Temperature rising
165
30
°C
°C
TSDN
(1) Specified by design. Not production tested.
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6.6 Typical Characteristics
100
95
90
85
80
75
70
65
60
55
100
95
90
85
80
75
70
65
60
55
50
Output Voltage
Output Voltage
0.6 V
0.8 V
1.0 V
1.2 V
1.8 V
2.5 V
3.3 V
5.0 V
0.6 V
0.8 V
1.0 V
1.2 V
1.8 V
2.5 V
3.3 V
5 V
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
IOUT (A)
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
Figure 6-2. Efficiency vs Output Current, 12 VIN, 600 KHz,
FCCM, Internal VCC LDO
IOUT (A)
Figure 6-1. Efficiency vs Output Current, 12 VIN, 600 KHz, Skip
Mode, Internal VCC LDO
115
110
105
100
95
115
110
105
100
95
90
90
85
85
80
80
400 LFM
200 LFM
100 LFM
400 LFM
200 LFM
100 LFM
75
75
70
70
Nat Conv
65
Nat Conv
65
0
3
6
Output Current (A)
9
12
15
0
3
6
Output Current (A)
9
12
15
PTPS
PTPS
Figure 6-3. SOA, 12 V 1VoutIN, 600 KHz, FCCM, Internal VCC
LDO
Figure 6-4. SOA, 12 V 3.3VoutIN, 600 KHz, FCCM, Internal VCC
LDO
115
110
105
100
95
115
110
105
100
95
90
90
85
85
80
80
400 LFM
100 LFM
200 LFM
400 LFM
200 LFM
100 LFM
75
75
70
70
Nat Conv
65
Nat Conv
65
0
2.5
5 7.5
Output Current (A)
10
12.5
0
3
6
Output Current (A)
9
12
15
PTPS
PTPS
Figure 6-5. SOA, 12 V 5.0VoutIN, 600 KHz, FCCM, Internal VCC
LDO
Figure 6-6. SOA, 5Vin 1.0VoutIN, 600 KHz, FCCM, Internal VCC
LDO
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7 Detailed Description
7.1 Overview
The TPSM8A28 and TPSM8A29 power modules feature high effcieincy and small footprint. These devices are
suitable for low voltage point-of-load applications up to 15 A. The conversion input voltage ranges from 2.7 V
to 16 V, and the external VCC input voltage ranges from 4.75 V to 5.3 V, and output voltage ranges from 0.6
V to 5.5 V. These power modules uses D-CAP3™ mode control combined with adaptive on-time architecture.
The D-CAP3™ mode uses emulated current information to control the modulation and tracks the preset switching
frequency over a wide range of input and output voltages. Advantages of this control scheme is that it does
not require a phase-compensation network outside, which makes the device easy-to-use and also allows low
external component count. Further advantage of this control scheme is that it supports stable operation with all
low-ESR output capacitors (such as ceramic capacitor and low-ESR polymer capacitor). It also adjusts switching
frequency as needed during load-step transient.
7.2 Functional Block Diagram
PGOOD
Soft-start
PG Falling
SS/REFIN
generator
Threshold
+
UV
Internal
Soft-start
VIN
EN
PGOOD Driver
LDO
+
OV
VCC
Reference
generator
VCC
PG Rising
Threshold
FB
BOOT
REG
PGOOD
+
+
+
VCCOK
Control Logic
VINOK
BOOT
VIN
VCC UVLO
VSNS-
VIN
PWM
+
VIN UVLO
ñ
ñ
ñ
ñ
ñ
ñ
ñ
ñ
tON generator
Minimum On/Off
Light Load
FCCM/Skip
Internal
Ramp
VCC UVLO
VIN UVLO
VOUT
XCON
EN
Enable
Output OVP/UVP
Thermal Shutdown
EN
+
1.22 V / 1.02 V
SW
Valley Current
Limit & ZCD
OC
Limit
TRIP
MODE
AGND
PGND
MODE
Selection
Fsw &
Mode
+
ThermalOK
165°C /
135°C
Output Soft
Discharge
GND
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7.3 Feature Description
7.3.1 Internal VCC LDO and Using External Bias on VCC Pin
The TPSM8A28 and TPSM8A29 power modules have internal 4.5-V LDO that takes input from VIN rail and
output to VCC. When the VIN voltage rises above the VINUVLO rising threshold, and the EN voltage rises above
the enable threshold (typically 1.22 V), the internal LDO is enabled and starts regulating output voltage on the
VCC pin. The VCC voltage provides the bias voltage for the internal analog circuitry and also provides the supply
voltage for the gate drives.
The VCC pin has an internal bypass capacitor integrated inside the module and does not require external
bypassing. An external bias that is above the output voltage of the internal LDO can override the internal LDO.
This enhances the efficiency of the converter because the VCC current now runs off this external bias instead of
the internal linear regulator.
The VCC UVLO circuit monitors the VCC pin voltage and disables the whole converter when VCC falls below the
VCC UVLO falling threshold. Maintaining a stable and clean VCC voltage is required for a smooth operation of
the device.
The following are considerations when using an external bias on the VCC pin:
•
When the external bias is applied on the VCC pin early enough (for example, before EN signal comes in), the
internal LDO is always forced off and the internal analog circuits has a stable power supply rail at their power
enable.
•
(Not recommended) If the external bias is applied on the VCC pin late (for example, after EN signal comes
in), any power-up and power-down sequencing can be applied as long as there is no excess current pulled
out of the VCC pin. It is important to understand that an external discharge path on the VCC pin, which can
pull a current higher than the current limit of the internal LDO from the VCC pin, can potentially turn off VCC
LDO thereby shutting down the converter output.
•
A good power-up sequence is when at least the VIN UVLO rising threshold or EN rising threshold is satisfied
later than the VCC UVLO rising threshold. For example, VIN applied first, then the external bias applied, and
then EN signal goes high.
7.3.2 Enable
When the EN pin voltage rises above the enable threshold voltage (typically 1.22 V) and VIN rises above the
VIN UVLO rising threshold, the device enters its internal power-up sequence. The EN to first switching delay is
specified in the Start-Up section in the Electrical Characteristics table.
When using the internal VCC LDO, the internal power-up sequence includes three sequential steps. During the
first period, the VCC voltage is charged up on the VCC bypass capacitor by a 11-mA current source. The length
of this VCC LDO start-up time varies with the capacitance on the VCC pin. However, if VIN voltage ramps up
very slowly, the VCC LDO output voltage is limited by theVIN voltage level, so the VCC LDO start-up time can
be extended longer. Since the VCC LDO start-up time is relatively long, the internal VINTREF build-up happens
and finishes during this period. Once the VCC voltage crosses above the VCC UVLO rising threshold (typically
2.87 V), the device moves to the second step, power-on delay. The MODE pin setting detection, SS/REFIN pin
detection, and control loop initialization are finished within this 285-μs delay. The soft-start ramp starts when the
285-μs power-on delay finishes. During the soft-start ramp power stage, switching does not happen until the
SS/REFIN pin voltage reaches 50 mV. This introduces a SS delay, which varies with the external capacitance on
the SS/REFIN pin.
Figure 7-1 shows an example where the VIN UVLO rising threshold is satisfied earlier than the EN rising
threshold. In this scenario, the VCC UVLO rising threshold becomes the gating signal to start the internal
power-up sequence, and the sequence between VIN and EN does not matter.
When using an external bias on the VCC pin, the internal power-up sequence still includes three sequential
steps. The first period is much shorter since the VCC voltage is built up already. A 100-µs period allows the
internal references start up and stabilize. This 100-µs period includes not only the 0.6-V VINTREF, but also all of
the other reference voltages for various functions. The device then moves to the second step, power-on delay.
The MODE pin setting detection, SS/REFIN pin detection, and control loop initialization are finished within this
285-μs delay. The soft-start ramp starts when the 285-μs power-on delay finishes. During the soft-start ramp
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power stage, switching does not happen until the SS/REFIN pin voltage reaches 50 mV. This introduced a SS
delay, which varies with the external capacitance on the SS/REFIN pin.
Figure 7-2 shows an example where both the VIN UVLO rising threshold and EN rising threshold are satisfied
later than the VCC UVLO rising threshold. In this scenario, the VIN UVLO rising threshold or EN rising threshold,
whichever is satisfied later, becomes the gating signal to start the internal power-up sequence.
2.4V
VIN
1.22V
EN
2.87V
VCC LDO
Power-on
delay
VCC LDO
Startup
50mV
SS/REFIN
SS delay
FB
SW pulses are omitted to
simplify the illustration
……
SW
Figure 7-1. Internal Power-up Sequence Using Internal LDO
2.87V
VCC
External
3.3V Bias
2.4V
VIN
EN
1.22V
Power-on
delay
VREF
Build-up
SS/REFIN
50mV
SS delay
FB
SW pulses are omitted to
simplify the illustration
……
SW
Figure 7-2. Internal Power-up Sequence Using External Bias
The EN pin has an internal filter to avoid unexpected ON or OFF due to small glitches. The time constant of this
RC filter is 5 µs. For example, when applying a 3.3-V voltage source on the EN pin, which jumps from 0 V to
3.3 V with ideal rising edge, the internal EN signal reaches 2.086 V after 5 µs, which is 63.2% of applied 3.3-V
voltage level.
A internal pulldown resistor is implemented between the EN pin and AGND pin. To avoid impact to the EN
rising/falling threshold, this internal pulldown resistor is set to 6.5 MΩ. With this pulldown resistor, floating the
EN pin before start-up keeps the device under disabled state. During nominal operation when the power stage
switches, this large internal pulldown resistor may not have enough noise immunity to hold the EN pin low.
The recommended operating condition for EN pin is maximum 5.5 V. Do not connect the EN pin to the VIN pin
directly.
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7.3.3 Output Voltage Setting
The output voltage is programmed by the voltage divider resistors, RFB_HS and RFB_LS. Connect RFB_HS between
the FB pin and the positive node of the load, and connect RFB_LS between the FB pin and the VSNS– pin. The
recommended RFB_LS value is 10 kΩ, ranging from 1 kΩ to 20 kΩ. Determine RFB_HS by using Equation 1.
VO - V
INTREF
RFB _HS
=
ìRFB _LS
V
INTREF
(1)
The FB accuracy is determined by two elements. The first element is the accuracy of the internal 600-mV
reference, which is applied to the SS/REFIN pin unless an external VREF is applied. Both TPSM8A28 and
TPSM8A29 offer ±0.5% VINTREF accuracy from a 0°C to 85°C temperature range, and ±1.0% VINTREF accuracy
from a -40°C to 125°C temperature range. The second element is the SS/REFIN-to-FB accuracy, which tells the
user how accurately the control loop regulates the FB node to the SS/REFIN pin. The TPSM8A29 offers ±0.6%
SS/REFIN-to-FB accuracy from a -40°C to 125°C temperature range. For example, when operating from a 0°C
to 85°C temperature range, the total FB accuracy is ±1.1%, which includes the impact from the chip junction
temperature and also the variation from part to part.
To improve the overall VOUT accuracy, using ±1% accuracy or better resistor for FB voltage divider is highly
recommended.
Regardless of remote sensing or single-end sensing connection, the FB voltage divider, RFB_HS and RFB_LS
must be always placed as close as possible to the device.
,
7.3.3.1 Remote Sense
The TPSM8A28 and TPSM8A29 modules feature remote sense function through the FB and VSNS– pins.
Remote sense function compensates a potential voltage drop on the PCB traces, helping maintain VOUT
tolerance under steady state operation and load transient event. Connecting the FB voltage divider resistors
to the remote location allows sensing of the output voltage at a remote location. The connections from the FB
voltage divider resistors to the remote location must be a pair of PCB traces with at least 12-mil trace width, and
must implement Kelvin sensing across a high bypass capacitor of 0.1 μF or higher. The ground connection of the
remote sensing signal must be connected to the VSNS– pin. The VOUT connection of the remote sensing signal
must be connected to the feedback resistor divider with the lower feedback resistor, RFB_LS, terminated at the
VSNS– pin. To maintain stable output voltage and minimize the ripple, the pair of remote sensing lines must stay
away from any noise sources such as inductor and SW nodes, or high frequency clock lines. It is recommended
to shield the pair of remote sensing lines with ground planes above and below.
Single-ended VO sensing is often used for local sensing. For this configuration, connect the higher FB resistor,
RFB_HS, to a high-frequency local bypass capacitor of 0.1 μF or higher, and short VSNS– to AGND.
The recommended VSNS– operating range (refer to AGND pin) is –50 mV to +50 mV.
7.3.4 Internal Fixed Soft Start and External Adjustable Soft Start
The TPSM8A28 and TPSM8A29 power modules allow both internal fixed soft start and external adjustable soft
start. The internal soft-start time is 1.5 ms. The soft-start time can be increased by adding a soft-start (SS)
capacitor between the SS/REFIN and VSNS– pins. The total SS capacitor value can be determined by Equation
2. The device follows the longer SS ramp among the internal SS time and the SS time determined by the
external SS capacitors.
The device does not require a capacitor from the SS/REFIN pin to AGND, so it is not recommended to place a
capacitor from the SS/REFIN pin to AGND. If both CSS/REFIN-to-VSNS– and CSS/REFIN-to-AGND capacitors exist,
place CSS/REFIN-to-VSNS– more closely to the shortest trace back to the VSNS– pin.
The SS/REFIN pin is discharged internally during the internal power-on delay to make sure the soft-start ramp
always starts from zero.
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t
SS(ms)ì36(mA )
CSS(nF)=
VINTREF( V)
(2)
7.3.5 External REFIN for Output Voltage Tracking
The TPSM8A28 and TPSM8A29 provide analog input pin (SS/REFIN) to accept an external reference (that is,
a DC voltage source). The device always looks at the voltage on this SS/REFIN pin as the reference for the
control loop. When an external voltage reference is applied between the SS/REFIN pin and VSNS– pin, it acts
as the reference voltage, so the FB voltage follows this external voltage reference exactly. The same ±0.6%
SS/REFIN-to-FB accuracy from a -40°C to 125°C temperature range applies here too.
In the middle of internal power-on delay, a detection circuit senses the voltage on the SS/REFIN pin to tell
whether an active DC voltage source is applied. Before the detection happens, the SS/REFIN pin tries to
discharge any energy on the SS/REFIN capacitors through an internal 120-Ω resistor to AGND, lasting 125
µs. Then, within a 32-µs window, the detection circuit compares the SS/REFIN pin voltage with an internal
reference equal to 89% of VINTREF. This discharge operation makes sure a SS capacitor with left-over energy is
not wrongly detected as a voltage reference. If the external voltage reference failed to supply sufficient current
and hold a voltage level higher than 89% of VINTREF, the SS/REFIN detection circuit provides a wrong detection
result.
If the detection result is that the SS/REFIN pin voltage holds higher than 89% of VINTREF, which tells an active
DC voltage source is used as external reference, the device always uses the SS/REFIN pin voltage instead
of the internal VINTREF as the reference for PGOOD threshold, VOUT OVP, and VOUT UVP threshold. On this
configuration, since the SS/REFIN pin senses a DC voltage and no soft-start ramp on this pin, the internal fixed
soft start is used for start-up. Once the internal soft-start ramp finishes, the power-good signal becomes high
after a 1.06-ms internal delay. The whole internal soft-start ramp takes 2 ms to finish because the soft-start ramp
goes beyond VINTREF
.
If the detection result is that SS/REFIN pin voltage falls below 89% of VINTREF, which tells no external reference
is connected, the device first uses the internal fixed VINTREF as the reference for PGOOD threshold, VOUT OVP,
and VOUT UVP threshold. On this configuration, given the SS/REFIN pin sees a soft-start ramp on this pin, the
slower ramp amongst the internal fixed soft start and the external soft start determines the start-up of FB. Once
both the internal and external soft-start ramp finishes, the power-good signal becomes high after a 1.06-ms
internal delay. The whole internal soft-start ramp takes 2 ms to finish. The external soft-start done signal goes
high when FB reaches a threshold equal to VINTREF – 50 mV. The device waits for the PGOOD status transition
from low to high, then starts using the SS/REFIN pin voltage instead of the internal VINTREF as the reference for
PGOOD threshold, VOUT OVP, and VOUT UVP threshold.
On this external REFIN configuration, applying a stabilized DC external reference to SS/REFIN pin before the
EN high signal is recommended. During the internal power-on delay, the external reference must be capable
of holding the SS/REFIN pin equal to or higher than 89% of VINTREF, so that the device can correctly detect
the external reference and choose the right thresholds for power good, VOUT OVP, and VOUT UVP. After the
power-good status transits from low to high, the external reference can be set in a range of 0.5 V to 1.2 V. To
overdrive the SS/REFIN pin during nominal operation, the external reference has to be able to sink more than
36-µA current if the external reference is lower than the internal VINTREF, or source more than 12-µA current
if the external reference is higher than the internal VINTREF. When driving the SS/REFIN pin by an external
reference through a resistor divider, the resistance of the divider must be low enough to provide the sinking or
sourcing current capability.
If the external voltage source must transition up and down between any two voltage levels, the slew rate must be
no more than 1 mV/μs.
7.3.6 Frequency and Operation Mode Selection
The TPSM8A29 provides forced CCM operation for tight output ripple applications and auto-skip Eco-mode for
high light-load efficiency. The TPSM8A29 allows users to select the switching frequency and operation mode by
connecting a resistor from the MODE pin to the AGND pin. Table 7-1 lists the resistor values for the switching
frequency and operation mode selection. TI recommends ±1% tolerance resistors with a typical temperature
coefficient of ±100 ppm/°C.
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The MODE state is set and latched during the internal power-on delay period. Changing the MODE pin
resistance after the power-on delay does not change the status of the device. The internal circuit sets the
MODE pin status to 600 kHz / Skip mode if the MODE pin is left open during the power-on delay period.
To make sure the internal circuit detects the desired option correctly, do not place any capacitor on the MODE
pin.
Table 7-1. MODE Pin Selection
MODE PIN
CONNECTIONS
OPERATION MODE UNDER LIGHT
LOAD
SWITCHING FREQUENCY
(fSW) (kHz)
Short to VCC
Skip-mode
Skip-mode
600
800
243-kΩ ± 10% to AGND
121-kΩ ± 10% to AGND
60.4-kΩ ±10% to AGND
30.1-kΩ ±10% to AGND
Short to AGND
Skip-mode
1000
1000
800
Forced CCM
Forced CCM
Forced CCM
600
7.3.7 D-CAP3™ Control
The TPSM8A28 and TPSM8A29 use D-CAP3™ mode control to achieve fast load transient while maintaining the
ease-of-use feature. The D-CAP3™ control architecture includes an internal ripple generation network, enabling
the use of very low ESR output capacitors such as multi-layered ceramic capacitors (MLCC) and low-ESR
polymer capacitors. No external current sensing network or voltage compensators are required with D-CAP3™
control architecture. The role of the internal ripple generation network is to emulate the ripple component of the
inductor current information and then combine it with the voltage feedback signal to regulate the loop operation.
The amplitude of the ramp is determined by VIN, VOUT, operating frequency, and the R-C time-constant of the
internal ramp circuit. At different switching frequency settings (see Table 7-1), the R-C time-constant varies
to maintain a relatively constant ramp amplitude. Also, the device uses internal circuitry to cancel the DC
offset caused by the injected ramp, and significantly reduce the DC offset caused by the output ripple voltage,
especially under light-load condition.
For any control topologies supporting no external compensation design, there is a minimum range, maximum
range, or both, of the output filter it can support. The output filter used is a low-pass L-C circuit. This L-C filter
has double pole that is described in Equation 3.
1
f
=
P
2´ p´ L
´ C
OUT
OUT
(3)
At low frequencies, the overall loop gain is set by the output set-point resistor divider network and the internal
gain. The low frequency L-C double pole has a 180-degree drop in phase. At the output filter frequency, the
gain rolls off at a –40 dB per decade rate and the phase drops rapidly. The internal ripple generation network
introduces a high-frequency zero that reduces the gain roll off from –40 dB to –20 dB per decade and increases
the phase by 90 degrees per decade above the zero frequency.
The inductor and capacitor selected for the output filter must be such that the double pole of Equation 3 is
located no higher than 1/30th of operating frequency. Choose very small output capacitance leads to relatively
high frequency L-C double pole, which allows the overall loop gain to stay high until the L-C double frequency.
Make sure the zero from the internal ripple generation network has relatively high frequency as well. The loop
with very small output capacitance can have too high of crossover frequency, which is not desired. Use Table 7-2
to help locate the internal zero based on the selected switching frequency.
Table 7-2. Locating the Zero
SWITCHING
FREQUENCIES
(fSW) (kHz)
ZERO (fZ) LOCATION (kHz)
600
800
84.5
84.5
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Table 7-2. Locating the Zero (continued)
SWITCHING
FREQUENCIES
(fSW) (kHz)
ZERO (fZ) LOCATION (kHz)
1000
106
In general, where reasonable (or smaller) output capacitance is desired, the output ripple requirement and load
transient requirement can be used to determine the necessary output capacitance for stable operation.
1
f
=
= f
Z
P
2´ p´ L
´ C
OUT
OUT
(4)
For the maximum output capacitance recommendation, select the inductor and capacitor values so that the L-C
double pole frequency is no less than 1/100th of the operating frequency. With this starting point, verify the small
signal response on the board using the following one criteria:
•
Phase margin at the loop crossover is greater than 50 degrees
The actual maximum output capacitance can go higher as long as the phase margin is greater than 50 degrees.
However, small signal measurement (bode plot) must be done to confirm the design.
If MLCC is used, consider the derating characteristics to determine the final output capacitance for the design.
For example, when using an MLCC with specifications of 10 µF, X5R, and 6.3 V, the derating by DC bias and AC
bias are 80% and 50%, respectively. The effective derating is the product of these two factors, which in this case
is 40% and 4 µF. Consult with capacitor manufacturers for specific characteristics of the capacitors to be used in
the system/applications.
For higher output voltage at or above 2 V, additional phase boost can be required in order to secure sufficient
phase margin due to phase delay/loss for higher output voltage (large on time (tON)) setting in a fixed on-time
topology based operation. A feedforward capacitor placed in parallel with RFB_HS wasfound to be very effective
to boost the phase margin at loop crossover. Refer to Optimizing Transient Response of Internally Compensated
dc-dc Converters With Feedforward Capacitor Application Report for details.
Besides boosting the phase, a feedforward capacitor feeds more VOUT node information into the FB node by the
AC coupling. This feedforward during load transient event enables the control loop a faster response to VOUT
deviation. However, this feedforward during steady state operation also feeds more VOUT ripple and noise into
FB. High ripple and noise on FB usually leads to more jitter, or even double pulse behavior. To determine the
final feedforward capacitor value, impacts to phase margin, load transient performance, and ripple and nosie on
FB must be all considered. Using Frequency Analysis equipment to measure the crossover frequency and the
phase margin is recommended.
7.3.8 Low-Side FET Zero-Crossing
A zero-crossing circuit is used to perform the zero inductor-current detection during Skip-mode operation. The
function compensates the inherent offset voltage of the Z-C comparator and delay time of the Z-C detection
circuit. The zero-crossing threshold is set to a positive value to avoid negative inductor current. As a result, the
TPSM8A28 and TPSM8A29 power modules deliver better light-load efficiency.
7.3.9 Current Sense and Positive Overcurrent Protection
For a buck converter, during the on time of the high-side FET, the switch current increases at a linear rate
determined by the following:
•
•
•
•
input voltage
output voltage
the on time
the output inductor value
During the on time of the low-side FET, this current decreases linearly. The average value of the switch current
equals to the load current.
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The output overcurrent limit (OCL) is implemented using a cycle-by-cycle valley current detect control circuit.
The inductor current is monitored during the on time of the low-side FET by measuring the low-side FET
drain-to-source current. If the measured drain-to-source current of the low-side FET is above the current limit
threshold, the low-side FET stays ON until the current level becomes lower than the current limit threshold.
This type of behavior reduces the average output current sourced by the device. During an overcurrent
condition, the current to the load exceeds the current to the output capacitors. Thus, the output voltage tends to
decrease. Eventually, when the output voltage falls below the undervoltage-protection threshold (80%), the UVP
comparator detects it and shuts down the device after a wait time of 68 µs. The device then enters a hiccup
sleep period for approximately 14 ms. After this waiting period, the device attempts to start up again/remains
latched off state (both high-side and low-side FETs are latched off) until a reset of VIN or a re-toggling on the EN
pin. Figure 7-3 shows the cycle-by-cycle valley current limit behavior as well as the wait time before the device
shuts down.
If an OCL condition happens during start-up, the device still has cycle-by-cycle current limit based on low-side
valley current. After soft start is finished, the UV event, which is caused by the OC event, shuts down the device
and enters Hiccup mode with a wait time of 68 µs.
The resistor, RTRIP, connected from the TRIP pin to AGND sets current limit threshold. ±1% tolerance resistor is
highly recommended because a worse tolerance resistor provides less accurate OCL threshold.
To protect the device from unexpected connection on the TRIP pin, an internal fixed OCL clamp is implemented.
This internal OCL clamp limits the maximum valley current on LS FET when TRIP pin has too small resistance to
AGND, or is accidently shorted to ground.
6ì104
KOCL
RTRIP
=
=
V -V ì V
V -V ì V
(
)
(
)
1
2
1
1
2
1
IN
O
O
IN
O
O
IOCLIM
-
ì
ì
IOCLIM
-
ì
ì
V
Lì fSW
V
L ì fSW
IN
IN
(5)
where
•
•
•
•
•
•
IOCLIM is overcurrent limit threshold for load current in A
RTRIP is TRIP resistor value in Ω
VIN is input voltage value in V
VO is output voltage value in V
L is output inductor value in µH
fSW is switching frequency in MHz
Figure 7-3. Overcurrent Protection
7.3.10 Low-Side FET Negative Current Limit
The device has a fixed, cycle-by-cycle negative current limit. Similar with the positive overcurrent limit, the
inductor current is monitored during the on time of the low-side FET. To prevent too large negative current
flowing through low-side FET, when the low-side FET detects –10-A current (typical threshold), the device
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turns off low-side FET and then turns on high-side FET for a proper on time (determined by VIN/VO/fSW). After
high-side FET on time expires, the low-side FET turns on again.
The device must not trigger the –10-A negative current limit threshold during nominal operation, unless a
too small inductor value is chosen or the inductor becomes saturated. This negative current limit is used to
discharge output capacitors during an output OVP or an OOB event. See Section 7.3.12 and Section 7.3.13 for
details.
7.3.11 Power Good
TPSM8A28 and TPSM8A29 have gower-good output that output high when the converter output voltage is within
specification. The power-good output is an open-drain output and must be pulled up to VCC pin or an external
voltage source (< 5.5 V) through a pullup resistor (typically 30.1 kΩ). The recommended power-good pullup
resistor value is 1 kΩ to 100 kΩ.
Once both the internal and external soft-start ramp finishes, the power-good signal becomes high after a
1.06-ms internal delay. The whole internal soft-start ramp takes 2 ms to finish. The external soft-start done signal
goes high when FB reaches a threshold equal to VINTREF – 50 mV. If the FB voltage drops to 80% of the VINTREF
voltage or exceeds 116% of the VINTREF voltage, the power-good signal latches low after a 2-µs internal delay.
The power-good signal can only be pulled high again after re-toggling EN or a reset of VIN.
If the input supply fails to power up the device, for example VIN and VCC both stays at zero volts, the
power-good pin clamps low by itself when this pin is pulled up through an external resistor.
Once the VCC voltage level rises above the minimum VCC threshold for valid PGOOD output (maximum 1.5 V),
internal power-good circuit is enabled to hold the PGOOD pin to the default status. By default, PGOOD is pulled
low and this low-level output voltage is no more than 400 mV with 5.5-mA sinking current. The power-good
function is fully activated after the soft-start operation is completed.
7.3.12 Overvoltage and Undervoltage Protection
The TPSM8A28 and TPSM8A29 devices monitor a resistor-divided feedback voltage to detect overvoltage
and undervoltage events. When the FB voltage becomes lower than 80% of the VINTREF voltage, the UVP
comparator detects and an internal UVP delay counter begins counting. After the 68-µs UVP delay time, the
device enters Hiccup mode and re-starts with a sleep time of 14 ms. The UVP function enables after the
soft-start period is complete.
When the FB voltage becomes higher than 116% of the VINTREF voltage, the OVP comparator detects and the
circuit latches OFF the high-side MOSFET driver and turns on the low-side MOSFET until reaching a negative
current limit INOCL. Upon reaching the negative current limit, the low-side FET is turned off, and the high-side
FET is turned on again for a proper on time (determined by VIN/VO/fSW). The device operates in this cycle until
the output voltage is pulled lower than the UVP threshold voltage for 68 µs. After the 68-µs UVP delay time, both
the high-side FET and the low-side FET are latched OFF. The fault is cleared with a reset of VIN or by retoggling
the EN pin.
During the 68-μs UVP delay time, if output voltage becomes higher than the UV threshold, thus it is not qualified
for the UV event, the timer is reset to zero. When the output voltage triggers the UV threshold again, the timer of
the 68 μs re-starts.
7.3.13 Out-Of-Bounds (OOB) Operation
TPSM8A28 and TPSM8A29 devices have out-of-bounds (OOB) overvoltage protection that protects the output
load at a much lower overvoltage threshold of 5% above the VINTREF voltage. OOB protection does not trigger an
overvoltage fault, so the device is on non-latch mode after an OOB event. OOB protection operates as an early
no-fault overvoltage-protection mechanism. During the OOB operation, the controller operates in forced CCM
mode. Turning on the low-side FET beyond the zero inductor current quickly discharges the output capacitor
thus helps the output voltage to fall quickly towards the setpoint. During the operation, the cycle-by-cycle
negative current limit is also activated for the safe operation of the internal FETs.
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7.3.14 Output Voltage Discharge
When the device is disabled through EN, it enables the output voltage discharge mode. This mode forces both
high-side and low-side FETs to latch off, but turns on the discharge FET, which is connected from SW to PGND,
to discharge the output voltage. Once the FB voltage drops below 100 mV, the discharge FET is turned off.
The output voltage discharge mode is activated by any of below fault events:
•
•
•
•
EN pin goes low to disable the converter.
Thermal shutdown (OTP) is triggered.
VCC UVLO (falling) is triggered.
VIN UVLO (falling) is triggered.
7.3.15 UVLO Protection
The device monitors the voltage on both the VIN and the VCC pins. If the VCC pin voltage is lower than the
VCCUVLO falling threshold voltage, the device shuts off. If the VCC voltage increases beyond the VCCUVLO rising
threshold voltage, the device turns back on. VCC UVLO is a non-latch protection.
When the VIN pin voltage is lower than the VINUVLO falling threshold voltage but the VCC pin voltage is still
higher than the VCCUVLO rising threshold voltage, the device stops switching and discharges SS/REFIN pin.
Once the VIN voltage increases beyond the VINUVLO rising threshold voltage, the device re-initiates the soft start
and switches again. VIN UVLO is a non-latch protection.
7.3.16 Thermal Shutdown
The device monitors internal junction temperature. If the temperature exceeds the threshold value (typically
165°C), the device stops switching and discharges the SS/REFIN pin. When the temperature falls approximately
30°C below the threshold value, the device turns back on with a re-initiated soft start. Thermal shutdown is a
non-latch protection.
7.4 Device Functional Modes
7.4.1 Auto-Skip Eco-Mode Light Load Operation
While the MODE pin is pulled to VCC directly or connected to AGND pin through a resistor larger than 121 kΩ,
the device automatically reduces the switching frequency at light-load conditions to maintain high efficiency. This
section describes the operation in detail.
As the output current decreases from heavy load condition, the inductor current also decreases until the rippled
valley of the inductor current touches zero level. Zero level is the boundary between the continuous-conduction
and discontinuous-conduction modes. The synchronous MOSFET turns off when this zero inductor current is
detected. As the load current decreases further, the converter runs into discontinuous-conduction mode (DCM).
The on time is maintained to a level approximately the same as during continuous-conduction mode operation
so that discharging the output capacitor with a smaller load current to the level of the reference voltage requires
more time. The transition point to the light-load operation IO(LL) (for example: the threshold between continuous-
and discontinuous-conduction mode) is calculated as shown in Equation 6.
V
- V
´ V
(
)
OUT OUT
V
IN
1
IN
I
=
´
OUT LL
( )
2´L ´ f
SW
(6)
where
fSW is the switching frequency
•
Using only ceramic capacitors is recommended for Skip mode.
7.4.2 Forced Continuous-Conduction Mode
When the MODE pin is tied to the AGND pin through a resistor less than 60.4 kΩ, the controller operates
in continuous conduction mode (CCM) during light-load conditions. During CCM, the switching frequency
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maintained to an almost constant level over the entire load range, which is suitable for applications requiring
tight control of the switching frequency.
7.4.3 Powering the Device From a 12-V Bus
Both TPSM8A28 and TPSM8A29 can be powered by a single 12-V bus. In this configuration, the internal LDO is
powered by a 12-V bus and generates a 4.5-V output to bias the internal analog circuitry and also powers up the
gate drives. The VIN range under this configuration for TPSM8A29 is 4 V to 16 V for up to 15-A load current. VIN
range for TPSM8A28 is 3 V to 16 V for up to 12 A. Figure 7-4 shows an example for this single VIN configuration.
VIN and EN are the two signals to enable the part. For a start-up sequence, any sequence between the VIN and
EN signals can power the device up correctly.
VIN: 4V – 16V
10
11
VOUT
VOUT
4
VIN
VIN
VIN
VIN
VOUT
5
CIN
16
17
23
EN
18
19
EN
CFF, Optional
PGOOD
PGOOD
Vosns+
COUT
RPG_pullup
12
FB
3
7
9
8
VCC
RFB_HS
RFB_LS
RMODE
MODE
TRIP
Vosns-
RTRIP
13
15
VSNS-
CSS
SS/
REFIN
AGND
PGND
Figure 7-4. Single VIN Configuration With 12-V Bus
7.4.4 Powering the Device From a 5.0-V Bus
The TPSM8A29 can deliver up to a 15-A load current when powering from a 5-V bus, 12 A for TPSM8A28.
To make sure the internal analog circuitry and the gate drives are powered up properly, the VCC pin must be
shorted to the VIN pins with a low impedance trace. A trace with at least 24-mil width is recommended. Due
to the maximum rating limit on the VCC pin, the VIN input range under this configuration is 4.75 V to 5.3 V.
The input voltage must stay higher than both VIN UVLO and VCC UVLO, otherwise the device shuts down
immediately. Figure 7-5 shows an example for this single VIN configuration.
VIN and EN are the two signals to enable the part. For start-up sequence, any sequence between the VIN and
EN signals can power the device up correctly.
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VIN: 4.75V-5.3V
10
11
VOUT
VOUT
4
VIN
VIN
VIN
VIN
VOUT
5
CIN
16
17
23
EN
18
19
EN
CFF, Optional
PGOOD
PGOOD
Vosns+
COUT
RPG_pullup
12
FB
3
7
9
8
VCC
RFB_HS
RFB_LS
RMODE
MODE
TRIP
Vosns-
RTRIP
13
15
VSNS-
CSS
SS/
REFIN
AGND
PGND
Figure 7-5. Single VIN Configuration With 5.0-V Bus
7.4.5 Powering the Device From a Split-Rail Configuration
The TPSM8A28 and TPSM8A29 devices can be configured to split-rail by using an independent power supply
that applies a valid bias on to VCC pin. Connecting a valid VCC bias to the VCC pin overrides the internal LDO,
thus saves power loss on that linear regulator and helps to improve overall system level efficiency. 5.0-V rail is
the common choice as VCC bias. With a stable VCC bias, the VIN input range under this configuration can be as
low as 2.7 V and up to 16 V for both TPSM8A28 and TPSM8A29.
Figure 7-6 shows an example for this split rail configuration.
The VCC external bias current during nominal operation varies with the bias voltage level and also the operating
frequency. For example, by setting the device to Skip mode, the VCC pins decreases current draw from the
external bias when the frequency decreases under light-load condition. The typical VCC external bias current
under FCCM operation is listed in the Electrical Characteristics table to help the user prepare the capacity of the
external bias.
Under split rail configuration, VIN, VCC bias, and EN are the signals to enable the part. For start-up sequence,
it is recommended that at least one of VIN UVLO rising threshold and EN rising threshold is satisfied later than
VCC UVLO rising threshold. A practical start-up sequence example is: VIN applied first, then the external bias
applied, and then EN signal goes high.
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VIN: 2.75-16V
10
11
VOUT
VOUT
4
VIN
VIN
VIN
VIN
VOUT
5
CIN
16
17
23
EN
18
19
EN
CFF, Optional
PGOOD
PGOOD
Vosns+
COUT
RPG_pullup
VCC: 4.75V to 5.3V
12
FB
3
7
9
8
VCC
RFB_HS
RFB_LS
RMODE
MODE
TRIP
Vosns-
RTRIP
13
15
VSNS-
CSS
SS/
REFIN
AGND
PGND
Figure 7-6. Split Rail Configuration With External VCC Bias
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8 Application and Implementation
Note
Information in the following applications sections is not part of the TI component specification,
and TI does not warrant its accuracy or completeness. TI’s customers are responsible for
determining suitability of components for their purposes, as well as validating and testing their design
implementation to confirm system functionality.
8.1 Application Information
The TPSM8A28 and TPSM8A29 power modules feature an integrated power inductor and some basic passives.
The devices are small and highly efficient, suitable for low output voltage point-of-load applications up to 15
A. These devices features proprietary D-CAP3™ mode control combined with adaptive on-time architecture.
This combination builds modern low-duty-ratio and ultra-fast load-step-response DC/DC converters in an ideal
fashion. The output voltage ranges from 0.6 V to 5.5 V. The conversion input voltage ranges from 2.7 V to 16
V, and the VCC input voltage ranges from 4.75 V to 5.3 V. The D-CAP3™ control mode uses emulated current
information to control the modulation. An advantage of this control scheme is that it does not require an external
phase-compensation network, which makes the device easy to use and also allows for a low external component
count. Another advantage of this control scheme is that it supports stable operation with all low-ESR output
capacitors (such as ceramic capacitor and low-ESR polymer capacitor). Adaptive on-time control tracks the
preset switching frequency over a wide range of input and output voltages while increasing switching frequency
as needed during a load-step transient.
8.2 Typical Application
The schematic shows a typical application for the TPSM8A29. This example describes the design procedure of
converting an input voltage range of 9.6 V to 14.4 V to a 1-V output, up to 15-A load current.
VOUT: 1 V, 15
A
VIN: 4 to 16V
VIN
2
1
1
2
4
5
16
17
23
10
11
VOUT
VIN
VIN
VIN
VIN
VIN
VOUT
VOUT
COUT
8x47uF
CIN
2x22uF
REN_T
20k
6
3
BOOT
VCC
BOOT
VCC
PGND
RPGOOD
30.1k
13 VSNS-
VSNS
PGND
R1
REN_B
10k
19 PGOOD
15 SS/REF
12 FB
Cff
6.65k
PGOOD
SS/REF_IN
FB
PGND
EN 18
EN
PGND
R2
10.0k
Mode
7
9
2
8
14
AGND
MODE
TRIP
SW
AGND
AGND
TRIP
SW
1
20
21-22
24-25
PGND
PGND
PGND
PGND
0
RTRIP
4.02k
AGND
PGND
PGND
NT1
TPSM8A29RDGR
AGND
AGND
PGND
Figure 8-1. Application Circuit Diagram
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8.2.1 Design Requirements
This design uses the parameters listed in Table 8-1. A switching frequency of 600 kHz was chosen to maximize
efficiency. See Table 7-1 for all switching frequency and operating mode configurations.
Table 8-1. Design Example Specifications
DESIGN PARAMETER
Voltage range
CONDITION
MIN
TYP
12
MAX
UNIT
V
VIN
9.6
14.4
VOUT
ILOAD
Output voltage
1.0
V
Output load current
15
A
VRIPPLE Output voltage ripple
VIN = 12 V, IOUT = 15 A
10
mVPP
V TRANS Output voltage undershoot and IOUT = 50% to 100% step, 5 A/µs slew rate
overshoot after load step
±50
mV
IOVER
tSS
Output overcurrent
Soft-start time
15
1.5
A
ms
kHz
fSW
Switching frequency
600
Operating mode
FCCM
25
TA
Operating temperature
°C
8.2.2 Detailed Design Procedure
The external component selection is a simple process using D-CAP3™ mode. Select the external components
using the following steps.
8.2.2.1 Output Voltage Setting Point
The output voltage is programmed by the voltage-divider resistors, R1 and R2, shown in Equation 7. Connect
R1 between the FB pin and the output, and connect R2 between the FB pin and VSNS–. The recommended R2
value is 10 kΩ, but it can also be set to another value between the range of 1 kΩ to 20 kΩ. Determine R1 by
using Equation 7. For 1.0 VOUT, a value of 6.65 kΩ is chosen.
V
− V
INTREF
OUT
1 V − 0.6 V
R1 =
× R2 =
× 10 kΩ = 6.65 kΩ
(7)
V
0.6 V
INTREF
8.2.2.2 Choose the Inductor
An optimized 0.6-μH inductor is integrated inside the module.
8.2.2.3 Set the Current Limit (TRIP)
The RTRIP resistor sets the valley current limit. Equation 8 calculates the recommended current limit target.
Equation 9 calculates the RTRIP resistor to set the current limit. The typical valley current limit target is 15.0 A,
and the closest standard value for RTRIP is 4.02 kΩ.
V
− V
× V
OUT OUT
IN MIN
0.6 μH × V
9.6 V − 1 V × 1 V
1
2
1
2
I
= I
−
OUT
×
= 15 A −
×
= 13.756 A
0.6 μH × 9.6 V × 600 kHz
(8)
(9)
LIMVALLEY
× fsw
IN MIN
60000
LIMVALLEY
60000
= 4.0 kΩ
15 A
R
=
=
TRIP
I
With the current limit set, Equation 10 calculates the typical maximum output current at current limit. Equation 11
calculates the typical peak current at current limit. For worst case calculations, the tolerance of the inductance
(20%) and the current limit must be included.
V
− V
× V
OUT OUT
IN MIN
0.6 μH × V
9.6 V − 1 V × 1 V
1
2
1
2
I
= I
−
×
= 15 A −
×
= 16.24 A
0.6 μH × 9.6 V × 600 kHz
(10)
OUTLIM
LIMVALLEY
× fsw
IN MIN
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V
− V
× V
OUT OUT
IN MAX
0.6 μH × V
14.4 V − 1 V × 1 V
1
2
1
2
I
= I
−
×
= 15 A −
×
= 16.29 A
0.6 μH × 14.4 V × 600 kHz
(11)
L PEAK
LIMVALLEY
× fsw
IN MAX
8.2.2.4 Choose the Output Capacitor
There are three considerations for selecting the value of the output capacitor.
1. Stability
2. Steady state output voltage ripple
3. Regulator transient response to a change load current
First, the minimum output capacitance must be calculated based on these three requirements. Equation 12
calculates the minimum capacitance to keep the LC double pole below 1/30th the fSW to meet stability
requirements. This requirement helps to keep the LC double pole close to the internal zero.
2
2
30
2π × fsw
1
30
1
C
>
×
=
×
= 105.5 μF
(12)
OUT_STABILITY
0.6 μH
0.6 μH
2π × 600 kHz
V
− Vout
IN MAX
V
Vout
0.6 μH × fsw
14.4 V − 1V
1V
0.6 μH × 600kHz
×
×
IN MAX
14.4 V
C
>
=
= 53.8 μF
(13)
OUT_RIPPLE
8 × V
× fsw
8 × 10 mV × 600kHz
ripple
Equation 13 calculates the minimum capacitance to meet the steady state output voltage ripple requirement
of 10 mV. This calculation is for FCCM operation and does not include the portion of the output voltage ripple
caused by the ESR or ESL of the output capacitors. Equation 14 and Equation 15 calculate the minimum
capacitance to meet the transient response requirement of ±50 mV for a 7.5-A step. These equations calculate
the necessary output capacitance to hold the output voltage steady while the inductor current ramps up or ramps
down after a load step.
Vout
2
2
1V
0.6 μH × I
STEP
×
+ toff
0.6 μH × 7.5
×
+ 220ns
V
× fsw
IN MIN
9.6 V × 600kHz
9.6 V − 1 V
9.6 V × 600kHz
C
>
=
(14)
OUT_UNDERSHOOT
V
− V
IN MIN
OUT
2 × 50mV × 1V ×
− 220ns
2 × V
× V
×
OUT
− toff
TRANS
V
× fsw
IN MIN
= 104.4 μF
2
2
0.6 μH × I
0.6 μH × 7.5
STEP
× V
C
>
=
= 337.5 μF
2 × 50mV × 1V
(15)
OUT_OVERSHOOT
2 × V
TRANS
OUT
The output capacitance needed to meet the overshoot requirement is the highest value, so this sets the
required minimum output capacitance for this example. Stability requirements can also limit the maximum output
capacitance. Equation 16 calculates the recommended maximum output capacitance. This calculation keeps
the LC double pole above 1/100th the fSW. It can be possible to use more output capacitance but the stability
must be checked through a bode plot or transient response measurement. The selected output capacitance
is 8 × 47-μF ceramic capacitors. When using ceramic capacitors, the capacitance must be derated due to
DC and AC bias effects. The selected capacitors derate to approximately 95% of their nominal value giving
an effective total capacitance of approximately 357 μF. This effective capacitance meets the minimum and
maximum requirements.
2
2
50
π × fsw
1
50
1
C
<
×
=
×
= 1172.7 μF
(16)
OUT_STABILITY
0.6 μH
0.6 μH
π × 600 kHz
This application uses all ceramic capacitors so the effects of ESR on the ripple and transient were ignored. If
using non-ceramic capacitors, as a starting point, the ESR must be below the values calculated in Equation 17 to
meet the ripple requirement and Equation 18 to meet the transient requirement. For more accurate calculations
or if using mixed output capacitors, the impedance of the output capacitors must be used to determine if the
ripple and transient requirements can be met.
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V
RIPPLE
10 mV
×
R
<
<
=
= 3.86 mΩ
(17)
ESR_RIPPLE
ESR_TRANS
V
− Vout
14.4 V − 1 V
1 V
IN MAX
V
Vout
0.6 μH × fsw
×
14.4 V
0.6 μH × 600 kHz
IN MAX
V
TRANS
50 mV
7.5 A
R
=
= 6.67 mΩ
(18)
I
STEP
8.2.2.5 Choose the Input Capacitors (CIN)
The device requires input bypass capacitors between the VIN and PGND pins to bypass the power stage.
The bypass capacitors must be placed as close as possible to the pins of the IC as the layout will allow. At
least 10-µF of ceramic capacitance is required. Two 0.1-μF and one 1-nF capacitors are integrated inside to
the module package, eliminating the need for typical high frequency bypass capacitors. However, they can be
used if desired. The high frequency bypass capacitors minimizes high frequency voltage overshoot across the
power-stage. The ceramic capacitors must be high-quality dielectric of X6S or better for their high capacitance-
to-volume ratio and stable characteristics across temperature. In addition to this, more bulk capacitance can be
needed on the input depending on the application to minimize variations on the input voltage during transient
conditions.
The input capacitance required to meet a specific input ripple target can be calculated with Equation 19.
A recommended target input voltage ripple is 5% the minimum input voltage, 480 mV in this example. The
calculated input capacitance is 4.86 μF, and the minimum input capacitance of 10 µF exceeds this. This example
meets these two requirements with 2 × 22-µF ceramic capacitors. An input capacitor must be used on both sides
of the module during layout, close to pins 5 and 16.
Vout
1 V
9.6 V
Vout × Iout × 1 −
1 V × 15 A × 1 −
V
IN MIN
C
>
=
= 4.86 μF
600 kHz × 9.6 V × 480 mV
(19)
IN
fsw × V
× V
IN MIN
IN_RIPPLE
The capacitor must also have an RMS current rating greater than the maximum input RMS current in the
application. The input RMS current the input capacitors must support is calculated by Equation 20 and is 4.588 A
in this example. The ceramic input capacitors have a current rating greater than this.
2
V
− Vout
IN MIN
V
Vout
0.6 μH × fsw
×
V
− Vout
IN MIN
V
IN MIN
Vout
2
I
=
=
×
× I
+
=
(20)
(21)
CIN RMS
OUT
V
12
IN MIN
IN MIN
2
9.6 V − 1 V
1 V
×
9.6 V
0.6 μH × 600 kHz
1 V
9.6 V
9.6 V − 1 V
2
I
×
× 15 A +
= 4.588 A
CIN RMS
9.6 V
12
For applications requiring bulk capacitance on the input, such as ones with low input voltage and high current,
the selection process in this article is recommended.
8.2.2.6 Soft-Start Capacitor (SS/REFIN Pin)
The capacitor placed on the SS/REFIN pin can be used to extend the soft-start time past the internal 1.5-ms
soft start. The required external capacitance can be calculated with Equation 2. The module incorporates a 1-nF
capacitor between the SS/REFIN pin and VSNS-. This example uses a minimum default soft-start time of 1.5
ms.
8.2.2.7 EN Pin Resistor Divider
A resistor divider on the EN pin can be used to increase the input voltage the converter begins its startup
sequence. To set the start voltage, first select the bottom resistor (REN_B). The recommended value is between
1 kΩ and 100 kΩ. There is an internal pulldown resistance with a nominal value of 6 MΩ. This must be included
for the most accurate calculations. This is especially important when the bottom resistor is a higher value, near
100 kΩ. This example uses a 10-kΩ resistor and this combined with the internal resistance in parallel results in
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an equivalent bottom resistance of 9.98 kΩ. The top resistor value for the target start voltage is calculated with
Equation 22. In this example, the nearest standard value of 20 kΩ is selected for REN_T. When selecting a start
voltage in a wide input range application, be cautious that the EN pin absolute maximum voltage of 6 V is not
exceeded.
R
× V
start
EN_B
V
10 kΩ × 3.7 V
− 10 kΩ = 20 kΩ
1.22 V
R
=
− R
=
(22)
EN_T
EN_B
ENH
The start and stop voltages with the selected EN resistor divider can be calculated with Equation 23 and
Equation 24, respectively.
R
+ R
EN_B
EN_T
R
20 kΩ + 10 kΩ
10 kΩ
V
= V
×
ENH
= 1.22 V ×
= 3.66 V
(23)
start
EN_B
R
+ R
EN_T
EN_B
20 kΩ + 10 kΩ
10 kΩ
V
= V
×
= 1 . 02 V ×
= 3.06 V
(24)
stop
ENL
R
EN_B
8.2.2.8 VCC Bypass Capacitor
A 1.0-μF bypass capacitor is integrated inside the module. No external bypass is required.
8.2.2.9 BOOT Capacitor
A 0.1-μF boot capacitor is integrated inside the module, no additional boot capacitor is necessary.
8.2.2.10 PGOOD Pullup Resistor
The PGOOD pin is open-drain so a pullup resistor is required when using this pin. The recommended value is
between 1 kΩ and 100 kΩ.
8.2.3 Application Curves
100
95
90
85
80
75
70
65
60
55
50
100
95
90
85
80
75
70
65
60
55
50
5 Vin
12 Vin
16 Vin
5 VIN
12 VIN
16 VIN
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
IOUT (A)
IOUT (A)
VOUT = 0.6 V fsw = 600 kHz Internal bias
FCCM
VOUT = 0.8 V fsw = 600 kHz Internal bias
FCCM
Figure 8-2. Efficiency
Figure 8-3. Efficiency
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100
95
90
85
80
75
70
65
60
55
50
100
95
90
85
80
75
70
65
60
55
50
5 Vin
12 Vin
16 Vin
5 Vin
12 Vin
16 Vin
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
IOUT (A)
IOUT (A)
VOUT = 1.0 V fsw = 600 kHz Internal bias
FCCM
VOUT = 1.2 V fsw = 600 kHz Internal bias
FCCM
Figure 8-4. Efficiency
Figure 8-5. Efficiency
100
95
90
85
80
75
70
65
60
55
50
100
95
90
85
80
75
70
65
60
55
50
5 Vin
12 Vin
16 Vin
5 Vin
12 Vin
16 Vin
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
IOUT (A)
IOUT (A)
VOUT = 1.8 V fsw = 600 kHz Internal bias
FCCM
VOUT = 2.5 V fsw = 600 kHz Internal bias
FCCM
Figure 8-6. Efficiency
Figure 8-7. Efficiency
100
95
90
85
80
75
70
65
60
55
50
100
95
90
85
80
75
70
65
60
55
50
8 Vin
12 Vin
16 Vin
8 Vin
12 Vin
16 Vin
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
IOUT (A)
IOUT (A)
VOUT = 3.3 V fsw = 600 kHz Internal bias
FCCM
VOUT = 5 V
fsw = 600 kHz Internal bias
FCCM
Figure 8-8. Efficiency
Figure 8-9. Efficiency
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95
92.5
90
0.601
0.6008
0.6006
0.6004
0.6002
0.6
0.5998
0.5996
0.5994
0.5992
0.599
87.5
85
82.5
80
77.5
75
0.5988
0.5986
0.5984
0.5982
0.598
Input Voltage
5 V
Switching Frequency
600 kHz
12 V
16 V
800 kHz
1000 kHz
72.5
70
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
IOUT (A)
IOUT (A)
VOUT = 0.6 V fSW = 600 kHz Internal bias
FCCM
VIN = 12 V
VOUT = 1 V
Internal bias
FCCM
Figure 8-11. Load Regulation
Figure 8-10. Efficiency
0.801
0.80075
0.8005
0.80025
0.8
1.003
1.0025
1.002
0.79975
0.7995
0.79925
0.799
1.0015
1.001
0.79875
0.7985
0.79825
0.798
0.79775
0.7975
0.79725
0.797
1.0005
Input Voltage
5 V
1
0.9995
0.999
Input Voltage
5 V
12 V
16 V
12 V
16 V
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
IOUT (A)
IOUT (A)
VOUT = 0.8 V fSW = 600 kHz Internal bias
FCCM
VOUT = 1.0 V fSW = 600 kHz Internal bias
Figure 8-13. Load Regulation
1.805
FCCM
Figure 8-12. Load Regulation
1.202
1.2015
1.201
1.2005
1.2
1.804
1.803
1.802
1.801
1.8
Input Voltage
5 V
Input Voltage
5 V
1.1995
1.199
1.799
1.798
12 V
16 V
12 V
16 V
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
IOUT (A)
IOUT (A)
VOUT = 1.2 V fSW = 600 kHz Internal bias
FCCM
VOUT = 1.8 V fSW = 600 kHz Internal bias
FCCM
Figure 8-14. Load Regulation
Figure 8-15. Load Regulation
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2.505
2.504
2.503
2.502
2.501
2.5
3.34
3.335
3.33
3.325
3.32
2.499
2.498
2.497
2.496
2.495
3.315
3.31
Input Voltage
5 V
Input Voltage
8 V
12 V
16 V
12 V
16 V
3.305
3.3
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
IOUT (A)
IOUT (A)
VOUT = 2.5 V fSW = 600 kHz Internal bias
FCCM
VOUT = 3.3 V fSW = 600 kHz Internal bias
FCCM
Figure 8-16. Load Regulation
Figure 8-17. Load Regulation
5.02
5.015
5.01
5.005
5
1.005
1.004
1.003
1.002
1.001
1
0.999
0.998
0.997
0.996
0.995
4.995
4.99
4.985
4.98
Input Voltage
5 V
12 V
16 V
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
4
5
6
7
8
9
10 11 12 13 14 15 16
VIN (V)
IOUT (A)
VOUT = 5 V fSW = 600 kHz Internal bias
FCCM
VOUT = 1.0
V
Internal
bias
fSW = 600
kHz
IOUT = 5 A
FCCM
Figure 8-18. Load Regulation
Figure 8-19. Line Regulation
1,000
650
625
600
575
550
525
500
475
450
950
900
850
800
750
700
650
600
550
500
450
400
350
Switching Frequency
600 kHz
Output Voltage
800 kHz
1000 kHz
0.6 V
1.0 V
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14 15
4
5
6
7
8
9
10 11 12 13 14 15 16
VIN (V)
IOUT (A)
VIN = 12 V
VOUT = 1.0 V Internal bias
FCCM
IOUT = 5 A
fSW = 600 kHz Internal bias
FCCM
Figure 8-20. Switching Frequency
Figure 8-21. Switching Frequency
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700
1,200
1,100
1,000
900
650
600
550
500
450
800
700
Output Voltage
Output Voltage
600
0.6 V
0.8 V
1.0 V
1.2 V
1.8 V
2.5 V
3.3 V
5.0 V
0.6 V
0.8 V
1.0 V
1.2 V
1.8 V
2.5 V
3.3 V
5.0 V
500
400
400
0
0
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
1
2
3
4
5
6
7
8
9 10 11 12 13 14 15
IOUT (A)
IOUT (A)
fSW = 1000
kHz
VIN = 12 A
fSW = 600 kHz Internal bias
FCCM
VIN = 12 V
Internal bias
FCCM
Figure 8-22. Switching Frequency
Figure 8-23. Switching Frequency
700
675
650
625
600
575
550
525
500
1,200
1,150
1,100
1,050
1,000
950
900
850
800
750
Load Current
Load Current
1 mA
1 A
10 A
15 A
1 mA
1 A
10 A
15 A
700
650
5 A
5 A
600
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
VOUT (V)
VOUT (V)
VIN = 12 V
fSW = 600 kHz Internal bias
FCCM
fSW = 1000
kHz
VIN = 12 V
Internal bias
FCCM
Figure 8-24. Switching Frequency
Figure 8-25. Switching Frequency
In the following images, all measurements taken with VIN = 12 V, VOUT = 1 V, fSW = 600 kHz, internal bias, TAMB
= 25°C
IOUT = 15 A
FCCM
IOUT = 0 A
FCCM
Figure 8-27. Output Voltage Ripple, VRIPPLE = 7.6
mV
Figure 8-26. Output Voltage Ripple, VRIPPLE = 6.4
mV
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IOUT = 0 A
DCM
IOUT = 0.5 A
DCM
Figure 8-28. Output Voltage Ripple, VRIPPLE = 20.3
mV
Figure 8-29. Output Voltage Ripple, VRIPPLE = 10.4
mV
IOUT = 0 A
DCM
IOUT = 1 A
DCM
Figure 8-31. Startup Through VIN (Enable Floating)
Figure 8-30. Output Voltage Ripple, VRIPPLE = 8.8
mV
IOUT = 0 A
DCM
IOUT = 15 A
FCCM
Figure 8-33. Startup Through Enable
Figure 8-32. Startup Through VIN (Enable Floating)
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IOUT = 15 A
FCCM
IOUT = 0 A
FCCM
Figure 8-34. Startup Through Enable
Figure 8-35. Startup Through Enable into
Prebiased Load
ISTEP = 7.5 A - 15 A - 7.5 A
5 A/μs
IOUT = 15 A
FCCM
Figure 8-37. Transient Response, VPP = 74 mV
Figure 8-36. Shutdown Through Enable
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9 Power Supply Recommendations
The devices are designed to operate from a wide input voltage supply range between 2.7 V and 16 V when
the VCC pin is powered by an external bias ranging from 4.75 V to 5.3 V. Both input supplies (VIN and VCC
bias) must be well regulated. Proper bypassing of input supplies (VIN and VCC bias) is also critical for noise
performance, as are PCB layout and grounding scheme. See the recommendations in Section 10.
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10 Layout
10.1 Layout Guidelines
Before beginning a design using one of the devices, consider the following:
•
•
•
Place the input and output capacitors on the top side of the PCB. In order to shield and isolate the small
signal traces from noisy power lines, insert at least one solid ground inner plane.
At least thirteen PGND vias are required to be placed as close as possible to the PGND pins (pins 1, 20, 21,
22, 24, and 25). This minimizes parasitic impedance and also lowers thermal resistance.
Always place the feedback resistors near the device to minimize the FB trace distance, no matter single-end
sensing or remote sensing.
– For remote sensing, the connections from the FB voltage divider resistors to the remote location should
be a pair of PCB traces with at least 12-mil trace width, and should implement Kelvin sensing across a
high bypass capacitor of 0.1 μF or higher. The ground connection of the remote sensing signal must be
connected to the VSNS– pin. The VOUT connection of the remote sensing signal must be connected to the
feedback resistor divider with the lower feedback resistor terminated at the VSNS– pin. To maintain stable
output voltage and minimize the ripple, the pair of remote sensing lines should stay away from any noise
sources such as inductor and SW nodes, or high frequency clock lines. And it is recommended to shield
the pair of remote sensing lines with ground planes above and below.
– For single-end sensing, connect the higher FB resistor to a high-frequency local bypass capacitor of
0.1-μF or higher, and short VSNS– to AGND with shortest trace.
•
•
Pin 8 (AGND pin) must be connected to a solid PGND plane at a single point. Use the common AGND via to
connect the TRIP and MODE resistors to the inner ground plane if applicable. Pin 14 is also an AGND pin,
and is connected internally to pin 8. No external connection between pins 8 and 14 is required, however, pin
8 must be used as the AGND connection.
See Figure 10-1 for the layout recommendation.
10.2 Layout Example
Figure 10-2. Recommended Layout Bottom Side
Figure 10-1. Recommended Layout Top Side
10.2.1 Thermal Performance on the TI EVM
Test conditions: fSW = 600 kHz, VIN = 12 V, VOUT = 1 V, IOUT = 15 A, COUT = 8 × 47 µF (1206/6.3V/X7R), IC:
82.5°C
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Figure 10-3. Thermal Image at 25°C Ambient, 12 Vin, 1 Vout, 15 A, 600 kHz
Test conditions:
fSW = 600 kHz, VIN = 12 V, VOUT = 5 V, IOUT = 12 A, COUT = 8 × 47 µF (1206/6.3V/X7R)
IC: 88.7°C
Figure 10-4. Thermal Image at 25°C Ambient, 12 Vin,5 Vout, 12 A, 600 kHz
10.3 EMI
The TPSM8A28 and TPSM8A29 are compliant with EN55011 Class-A radiated emissions. Figure 11-1 and
Figure 11-2 show examples of radiated emissions plots. The graphs include the plots of the antenna in the
horizontal and vertical positions.
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The EMI plots were measured using the standard TPSM8A29EVM with Ferrite 61 type beads on the input wire.
Figure 10-5. Radiated Emissions 12-V Input, 1.0-V Outputs, 15-A/Output Load
Figure 10-6. Radiated Emissions 5-V Input, 1-V Output, 15-A/Output Load
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Third-Party Products Disclaimer
TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT
CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES
OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER
ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.
11.2 Documentation Support
11.2.1 Related Documentation
Optimizing Transient Response of Internally Compensated dc-dc Converters With Feedforward Capacitor
Application Report
11.3 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. Click on
Subscribe to updates to register and receive a weekly digest of any product information that has changed. For
change details, review the revision history included in any revised document.
11.4 Support Resources
TI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straight
from the experts. Search existing answers or ask your own question to get the quick design help you need.
Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and do
not necessarily reflect TI's views; see TI's Terms of Use.
11.5 Trademarks
D-CAP3™ and Eco-mode™, are trademarks of TI.
TI E2E™ is a trademark of Texas Instruments.
All trademarks are the property of their respective owners.
11.6 Electrostatic Discharge Caution
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may
be more susceptible to damage because very small parametric changes could cause the device not to meet its published
specifications.
11.7 Glossary
TI Glossary
This glossary lists and explains terms, acronyms, and definitions.
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com
15-Dec-2021
PACKAGING INFORMATION
Orderable Device
Status Package Type Package Pins Package
Eco Plan
Lead finish/
Ball material
MSL Peak Temp
Op Temp (°C)
Device Marking
Samples
Drawing
Qty
(1)
(2)
(3)
(4/5)
(6)
PTPSM8A29RDGR
TPSM8A28RDGR
ACTIVE
ACTIVE
B3QFN
B3QFN
RDG
RDG
25
25
1000
1000
TBD
Call TI
Call TI
-40 to 125
-40 to 125
RoHS (In
Work) & Green
(In Work)
NIPDAU
Level-3-250C-168 HR
TPSM8A28
TPSM8A29RDGR
ACTIVE
B3QFN
RDG
25
1000
RoHS (In
Work) & Green
(In Work)
NIPDAU
Level-3-250C-168 HR
-40 to 125
TPSM8A29
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
Addendum-Page 1
PACKAGE OPTION ADDENDUM
www.ti.com
15-Dec-2021
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Dec-2021
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
Package Package Pins
Type Drawing
SPQ
Reel
Reel
A0
B0
K0
P1
W
Pin1
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant
(mm) W1 (mm)
TPSM8A28RDGR
TPSM8A29RDGR
B3QFN
B3QFN
RDG
RDG
25
25
1000
1000
330.0
330.0
16.4
16.4
6.9
6.9
7.9
7.9
4.3
4.3
12.0
12.0
16.0
16.0
Q1
Q1
Pack Materials-Page 1
PACKAGE MATERIALS INFORMATION
www.ti.com
16-Dec-2021
*All dimensions are nominal
Device
Package Type Package Drawing Pins
SPQ
Length (mm) Width (mm) Height (mm)
TPSM8A28RDGR
TPSM8A29RDGR
B3QFN
B3QFN
RDG
RDG
25
25
1000
1000
336.0
336.0
336.0
336.0
48.0
48.0
Pack Materials-Page 2
PACKAGE OUTLINE
B3QFN - 4.1 mm max height
PLASTIC QUAD FLAT PACK- NO LEAD
RDG0025A
6.6
6.4
B
A
7.6
7.4
PIN 1 INDEX AREA
4.1
3.9
C
SEATING PLANE
0.08
0.01
0.00
C
2.45
2.35
4X
1.85
1.75
(0.2) TYP
0.55
0.45
4X
4X 0.8
11
10
25
1.21
1.11
4X
24
0.56
0.46
2X 6.15
2X 4.55
23
2X 1.23
22
21
2X 2.59
1
20
0.4
0.3
16X
14X 0.65
0.7
0.6
0.1
16X
1.25
1.15
PIN 1 ID
4X
C A B
0.1
C
A B
0.05
C
0.05
C
4226094/A 08/2020
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. The package thermal pad must be soldered to the printed circuit board for optimal thermal and mechanical performance.
www.ti.com
EXAMPLE BOARD LAYOUT
B3QFN - 4.1 mm max height
PLASTIC QUAD FLAT PACK- NO LEAD
RDG0025A
(6.05)
(5.5)
2X (2.4)
(1.8)
(0.05) MIN
ALL AROUND
TYP
(R 0.05) TYP
20
1
16X 0.35
2X 2.52
23
2X (6.15)
2X (4.55)
0.000 PKG ℄
(0.51)
(0.91)
3X (1.92)
(2.92)
14X (0.65)
10
11
4X (0.5)
16X (0.85)
4X (1.4)
(Ø0.2) TYP
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE: 12X
SOLDER MASK
OPENING
0.05 MIN
ALL AROUND
0.05 MAX
ALL AROUND
METAL
EXPOSED METAL
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
EXPOSED METAL
SOLDER MASK
DEFINED
NON- SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
4226094/A 08/2020
NOTES: (continued)
4. This package is designed to be soldered to a thermal pad on the board. For more information, see Texas Instruments literature
number SLUA271 (www.ti.com/lit/slua271).
5. Vias are optional depending on application, refer to device data sheet. If any vias are implemented, refer to their locations shown
on this view. It is recommended that vias under paste be filled, plugged or tented.
www.ti.com
EXAMPLE STENCIL DESIGN
B3QFN - 4.1 mm max height
PLASTIC QUAD FLAT PACK- NO LEAD
RDG0025A
(6.05)
(5.5)
(R 0.05) TYP
8X (0.9)
20
1
16X 0.35
22
8X 0.96
2X (0.6)
23
2X (6.15)
2X (4.55)
0.000 PKG ℄
2X 0.51
2X (1.28)
24
2X (2.55)
(2.92)
14X (0.65)
10
11
4X (0.5)
16X (0.85)
4X (1.4)
(Ø0.2) TYP
SOLDER PASTE EXAMPLE
BASED ON 0.1 mm THICK STENCIL
SOLDER COVERAGE:
PIN 21 & 22 : 57%
PIN 23 : 67%
PIN 24 & 25 : 57%
SCALE: 15X
4226094/A 08/2020
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
www.ti.com
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DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”
AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANY
IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRD
PARTY INTELLECTUAL PROPERTY RIGHTS.
These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriate
TI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicable
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These resources are subject to change without notice. TI grants you permission to use these resources only for development of an
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TI objects to and rejects any additional or different terms you may have proposed. IMPORTANT NOTICE
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Copyright © 2021, Texas Instruments Incorporated
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