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UCC27525DGNR

更新时间：2025-01-22 12:16:32
品牌：TI
描述：Dual 5-A High-Speed Low-Side Gate Driver

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UCC27525DGNR 概述

Dual 5-A High-Speed Low-Side Gate Driver 双5 -A高速低侧栅极驱动器 FET驱动器 MOSFET 驱动器

UCC27525DGNR 规格参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active零件包装代码：MSOP
包装说明：HTSSOP, TSSOP8,.19针数：8
Reach Compliance Code：compliantECCN代码：EAR99
HTS代码：8542.39.00.01风险等级：1.64
Is Samacsys：N高边驱动器：NO
接口集成电路类型：BUFFER OR INVERTER BASED MOSFET DRIVERJESD-30 代码：S-PDSO-G8
JESD-609代码：e4长度：3 mm
湿度敏感等级：1功能数量：2
端子数量：8最高工作温度：140 °C
最低工作温度：-40 °C最大输出电流：5 A
标称输出峰值电流：5 A输出极性：TRUE AND INVERTED
封装主体材料：PLASTIC/EPOXY封装代码：HTSSOP
封装等效代码：TSSOP8,.19封装形状：SQUARE
封装形式：SMALL OUTLINE, HEAT SINK/SLUG, THIN PROFILE, SHRINK PITCH峰值回流温度（摄氏度）：260
电源：4.5/18 V认证状态：Not Qualified
座面最大高度：1.1 mm子类别：MOSFET Drivers
最大供电电压：18 V最小供电电压：4.5 V
标称供电电压：12 V表面贴装：YES
技术：BICMOS温度等级：AUTOMOTIVE
端子面层：Nickel/Palladium/Gold/Silver (Ni/Pd/Au/Ag)端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED断开时间：0.023 µs
接通时间：0.023 µs宽度：3 mm
Base Number Matches：1

UCC27525DGNR 数据手册

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UCC27523, UCC27524, UCC27525, UCC27526  
www.ti.com  
SLUSAQ3F –NOVEMBER 2011–REVISED MAY 2013  
Dual 5-A High-Speed Low-Side Gate Driver  
Check for Samples: UCC27523, UCC27524, UCC27525, UCC27526  
1
FEATURES  
APPLICATIONS  
2
•
•
•
•
•
Industry-Standard Pin Out  
•
•
•
•
Switch-Mode Power Supplies  
Two Independent Gate-Drive Channels  
5-A Peak Source and Sink-Drive Current  
Independent-Enable Function for Each Output  
DC-to-DC Converters  
Motor Control, Solar Power  
Gate Drive for Emerging Wide Band-Gap  
Power Devices such as GaN  
TTL and CMOS Compatible Logic Threshold  
Independent of Supply Voltage  
DESCRIPTION  
•
•
Hysteretic-Logic Thresholds for High Noise  
Immunity  
The UCC2752x family of devices are dual-channel  
high-speed low-side gate-driver devices capable of  
effectively driving MOSFET and IGBT power  
switches. Using a design that inherently minimizes  
shoot-through current, UCC2752x is capable of  
delivering high-peak current pulses of up to 5-A  
source and 5-A sink into capacitive loads along with  
rail-to-rail drive capability and extremely small  
propagation delay typically 13 ns. In addition, the  
drivers feature matched internal propagation delays  
between the two channels which are very well suited  
for applications requiring dual-gate drives with critical  
timing, such as synchronous rectifiers. This also  
enables connecting two channels in parallel to  
effectively increase current-drive capability or driving  
two switches in parallel with a single input signal. The  
input pin thresholds are based on TTL and CMOS  
compatible low-voltage logic, which is fixed and  
independent of the VDD supply voltage. Wide  
hysteresis between the high and low thresholds offers  
excellent noise immunity.  
Inputs and Enable Pin-Voltage Levels Not  
Restricted by VDD Pin Bias Supply Voltage  
•
•
4.5 to 18-V Single-Supply Range  
Outputs Held Low During VDD-UVLO, (ensures  
glitch-free operation at power-up and power-  
down)  
•
•
Fast Propagation Delays (13-ns typical)  
Fast Rise and Fall Times (7-ns and 6-ns  
typical)  
•
•
1-ns Typical Delay Matching Between 2-  
Channels  
Two Outputs are Paralleled for Higher Drive  
Current  
•
•
Outputs Held in LOW When Inputs Floating  
PDIP-8, SOIC-8, MSOP-8 PowerPAD™ and 3-  
mm × 3-mm WSON-8 Package Options  
•
Operating Temperature Range of –40°C to  
+140°C  
PRODUCT MATRIX  
One Inverting and One  
Non-Inverting Input  
Dual Input Configuration  
UCC27526  
Dual Inverting Inputs  
UCC27523  
Dual Non-Inverting Inputs  
UCC27524  
UCC27525  
INA-  
1
8
INA+  
ENA  
1
8
7
6
5
ENB  
ENA  
INA  
1
2
3
4
8
7
6
5
ENB  
ENA  
INA  
1
2
3
4
8
7
6
5
ENB  
INA  
GND  
INB  
2
3
4
OUTA  
VDD  
OUTA  
VDD  
OUTA  
VDD  
INB-  
GND  
2
3
4
7
6
5
INB+  
OUTA  
VDD  
GND  
INB  
GND  
INB  
OUTB  
OUTB  
OUTB  
OUTB  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
PowerPAD is a trademark of Texas Instruments.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2011–2013, Texas Instruments Incorporated  
 
UCC27523, UCC27524, UCC27525, UCC27526  
SLUSAQ3F –NOVEMBER 2011–REVISED MAY 2013  
www.ti.com  
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with  
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.  
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more  
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.  
DESCRIPTION (CONTINUED)  
The UCC2752x family provide the combination of three standard logic options — dual-inverting, dual-non  
inverting, one inverting and one non-inverting driver. UCC27526 features a dual input design which offers  
flexibility of both inverting (IN- pin) and non-inverting (IN+ pin) configuration for each channel. Either IN+ or IN-  
pin controls the state of the driver output. The unused input pin is used for enable and disable functions. For  
safety purpose, internal pullup and pulldown resistors on the input pins of all the devices in UCC2752x family  
ensure that outputs are held LOW when input pins are in floating condition. UCC27323, UCC27324 and  
UCC27325 feature Enable pins (ENA and ENB) to have better control of the operation of the driver applications.  
The pins are internally pulled up to VDD for active-high logic and are left open for standard operation.  
UCC2752x family of devices are available in SOIC-8 (D), MSOP-8 with exposed pad (DGN) and 3-mm × 3-mm  
WSON-8 with exposed pad (DSD) packages. UCC27524 is also offered in PDIP-8 (P) package. UCC27526 is  
only offered in 3-mm × 3-mm WSON (DSD) package.  
ORDERING INFORMATION(1)(2)  
PART NUMBER  
PACKAGE  
OPERATING TEMPERATURE RANGE, TA  
SOIC 8-Pin (D), MSOP 8-pin (DGN),  
WSON 8-pin (DSD)  
UCC27523  
SOIC 8-Pin (D), MSOP 8-pin (DGN),  
WSON 8-pin (DSD), PDIP 8-pin (P)  
UCC27524  
-40°C to 140°C  
SOIC 8-Pin (D), MSOP 8-pin (DGN),  
WSON 8-pin (DSD)  
UCC27525  
UCC27526  
WSON 8-pin (DSD)  
(1) For the most current package and ordering information, see Package Option Addendum at the end of this document.  
(2) All packages use Pb-Free lead finish of Pd-Ni-Au which is compatible with MSL level 1 at 255°C to 260°C peak reflow temperature to be  
compatible with either lead free or Sn/Pb soldering operations. DSD package is rated MSL level 2.  
TOPSIDE MARKING INFORMATION  
PART NUMBER WITH PACKAGE DESIGNATOR  
TOP MARKINGS  
27524  
UCC27524D  
UCC27524DGN  
27524  
UCC27524DSD  
SBA  
UCC27524P  
27524  
UCC27523D  
27523  
UCC27523DGN  
27523  
UCC27523DSD  
27523  
UCC27525D  
27525  
UCC27525DGN  
27525  
UCC27525DSD  
27525  
UCC27526DSD  
SCB  
2
Submit Documentation Feedback  
Copyright © 2011–2013, Texas Instruments Incorporated  
Product Folder Links: UCC27523, UCC27524, UCC27525, UCC27526  
 
UCC27523, UCC27524, UCC27525, UCC27526  
www.ti.com  
SLUSAQ3F –NOVEMBER 2011–REVISED MAY 2013  
ABSOLUTE MAXIMUM RATINGS(1)(2)  
over operating free-air temperature range (unless otherwise noted)  
MIN  
-0.3 to  
MAX  
20.0  
UNIT  
Supply voltage range  
OUTA, OUTB voltage  
VDD  
DC  
-0.3 to VDD + 0.3  
-2.0 to VDD + 0.3  
V
Repetitive pulse < 200 ns(3)  
Output continuous source/sink  
current  
IOUT_DC  
0.3  
5
A
V
Output pulsed source/sink current  
(0.5 µs)  
IOUT_pulsed  
INA, INB, INA+, INA-, INB+, INB-, ENA, ENB voltage(4)  
Human body model, HBM  
Charge device model, CDM  
-0.3  
20  
4000  
1000  
150  
ESD(5)  
Operating virtual junction temperature, TJ range  
Storage temperature range, Tstg  
-40  
-65  
150  
°C  
Soldering, 10 sec.  
Reflow  
300  
Lead temperature  
260  
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings  
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating  
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.  
(2) All voltages are with respect to GND unless otherwise noted. Currents are positive into, negative out of the specified terminal. See  
Packaging Section of the datasheet for thermal limitations and considerations of packages.  
(3) Values are verified by characterization on bench.  
(4) The maximum voltage on the Input and Enable pins is not restricted by the voltage on the VDD pin.  
(5) These devices are sensitive to electrostatic discharge; follow proper device handling procedures.  
RECOMMENDED OPERATING CONDITIONS  
over operating free-air temperature range (unless otherwise noted)  
MIN  
4.5  
-40  
0
TYP  
MAX  
18  
UNIT  
V
Supply voltage range, VDD  
12  
Operating junction temperature range  
Input voltage, INA, INB, INA+, INA-, INB+, INB-  
Enable voltage, ENA and ENB  
140  
18  
°C  
V
0
18  
Copyright © 2011–2013, Texas Instruments Incorporated  
Submit Documentation Feedback  
3
Product Folder Links: UCC27523, UCC27524, UCC27525, UCC27526  
 
 
UCC27523, UCC27524, UCC27525, UCC27526  
SLUSAQ3F –NOVEMBER 2011–REVISED MAY 2013  
www.ti.com  
THERMAL INFORMATION  
UCC27523,  
UCC27524,  
UCC27525  
UCC27523,  
UCC27524,  
UCC27525  
MSOP (DGN)(1)  
THERMAL METRIC  
UNITS  
SOIC (D)  
8 PINS  
130.9  
80.0  
8 PINS  
71.8  
65.6  
7.4  
θJA  
Junction-to-ambient thermal resistance(2)  
Junction-to-case (top) thermal resistance(3)  
Junction-to-board thermal resistance(4)  
Junction-to-top characterization parameter(5)  
Junction-to-board characterization parameter(6)  
Junction-to-case (bottom) thermal resistance(7)  
θJCtop  
θJB  
71.4  
°C/W  
ψJT  
21.9  
7.4  
ψJB  
70.9  
31.5  
19.6  
θJCbot  
n/a  
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.  
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as  
specified in JESD51-7, in an environment described in JESD51-2a.  
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-  
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.  
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB  
temperature, as described in JESD51-8.  
(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted  
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).  
(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted  
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).  
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific  
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.  
Spacer  
THERMAL INFORMATION  
UCC27524  
UCC27523,  
UCC27524,  
UCC27525,  
UCC27526  
THERMAL METRIC  
UNITS  
PDIP (P)  
8 PINS  
62.1  
WSON (DSD)(1)  
8 PINS  
46.7  
46.7  
22.4  
0.7  
θJA  
Junction-to-ambient thermal resistance(2)  
Junction-to-case (top) thermal resistance(3)  
Junction-to-board thermal resistance(4)  
Junction-to-top characterization parameter(5)  
Junction-to-board characterization parameter(6)  
Junction-to-case (bottom) thermal resistance(7)  
θJCtop  
θJB  
52.7  
39.1  
°C/W  
ψJT  
31.0  
ψJB  
39.1  
22.6  
9.5  
θJCbot  
n/a  
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.  
(2) The junction-to-ambient thermal resistance under natural convection is obtained in a simulation on a JEDEC-standard, high-K board, as  
specified in JESD51-7, in an environment described in JESD51-2a.  
(3) The junction-to-case (top) thermal resistance is obtained by simulating a cold plate test on the package top. No specific JEDEC-  
standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.  
(4) The junction-to-board thermal resistance is obtained by simulating in an environment with a ring cold plate fixture to control the PCB  
temperature, as described in JESD51-8.  
(5) The junction-to-top characterization parameter, ψJT, estimates the junction temperature of a device in a real system and is extracted  
from the simulation data for obtaining θJA, using a procedure described in JESD51-2a (sections 6 and 7).  
(6) The junction-to-board characterization parameter, ψJB, estimates the junction temperature of a device in a real system and is extracted  
from the simulation data for obtaining θJA , using a procedure described in JESD51-2a (sections 6 and 7).  
(7) The junction-to-case (bottom) thermal resistance is obtained by simulating a cold plate test on the exposed (power) pad. No specific  
JEDEC standard test exists, but a close description can be found in the ANSI SEMI standard G30-88.  
Spacer  
4
Submit Documentation Feedback  
Copyright © 2011–2013, Texas Instruments Incorporated  
Product Folder Links: UCC27523, UCC27524, UCC27525, UCC27526  
UCC27523, UCC27524, UCC27525, UCC27526  
www.ti.com  
SLUSAQ3F –NOVEMBER 2011–REVISED MAY 2013  
ELECTRICAL CHARACTERISTICS  
VDD = 12 V, TA = TJ = -40°C to 140°C, 1-µF capacitor from VDD to GND. Currents are positive into, negative out of the  
specified terminal (unless otherwise noted,)  
PARAMETER  
Bias Currents  
TEST CONDITION  
MIN  
TYP  
MAX  
UNITS  
VDD = 3.4 V,  
INA=VDD,  
INB=VDD  
55  
25  
110  
175  
Startup current,  
(based on UCC27524 Input  
configuration)  
IDD(off)  
μA  
VDD = 3.4 V,  
INA=GND,  
INB=GND  
75  
145  
Under Voltage LockOut (UVLO)  
TJ = 25°C  
3.91  
3.70  
4.20  
4.20  
4.50  
4.65  
VON  
Supply start threshold  
TJ = -40°C to 140°C  
V
Minimum operating voltage  
after supply start  
VOFF  
3.40  
0.20  
3.90  
0.30  
4.40  
0.50  
VDD_H  
Supply voltage hysteresis  
Inputs (INA, INB, INA+, INA-, INB+, INB-), UCC2752X (D, DGN, DSD)  
Output high for non-inverting input pins  
Output low for inverting input pins  
VIN_H  
Input signal high threshold  
1.9  
2.1  
2.3  
Output low for non-inverting input pins  
Output high for inverting input pins  
V
V
VIN_L  
Input signal low threshold  
Input hysteresis  
1.0  
1.2  
1.4  
VIN_HYS  
0.70  
0.90  
1.10  
INPUTS (INA, INB, INA+, INA-, INB+, INB-) UCC27524P ONLY  
Output high for non-inverting input pins  
Output low for inverting input pins  
VIN_H  
Input signal high threshold  
2.3  
Output low for non-inverting input pins  
Output high for inverting input pins  
VIN_L  
Input signal low threshold  
Input hysteresis  
1.0  
VIN_HYS  
0.9  
Enable (ENA, ENB) UCC2752X (D, DGN, DSD)  
VEN_H  
VEN_L  
Enable signal high threshold  
Enable signal low threshold  
Output enabled  
Output disabled  
1.9  
0.95  
0.70  
2.1  
1.15  
0.95  
2.3  
1.35  
1.10  
V
V
VEN_HYS Enable hysteresis  
ENABLE (ENA, ENB) UCC27524P ONLY  
VEN_H  
VEN_L  
Enable signal high threshold  
Enable signal low threshold  
Output enabled  
Output disabled  
2.3  
0.95  
VEN_HYS Enable hysteresis  
0.95  
±5  
Outputs (OUTA, OUTB)  
ISNK/SRC Sink/source peak current(1)  
VDD-VOH High output voltage  
CLOAD = 0.22 µF, FSW = 1 kHz  
IOUT = -10 mA  
A
V
0.075  
0.01  
7.5  
VOL  
ROH  
ROL  
Low output voltage  
Output pullup resistance(2)  
IOUT = 10 mA  
IOUT = -10 mA  
2.5  
5
Ω
Ω
Output pulldown resistance  
IOUT = 10 mA  
0.15  
0.5  
1
Switching Time  
(1) Ensured by design.  
(2) ROH represents on-resistance of only the P-Channel MOSFET device in pullup structure of UCC2752X output stage.  
Submit Documentation Feedback  
Product Folder Links: UCC27523, UCC27524, UCC27525, UCC27526  
Copyright © 2011–2013, Texas Instruments Incorporated  
5
 
 
 
 
 
 
 
 
 
 
UCC27523, UCC27524, UCC27525, UCC27526  
SLUSAQ3F –NOVEMBER 2011–REVISED MAY 2013  
www.ti.com  
ELECTRICAL CHARACTERISTICS (continued)  
VDD = 12 V, TA = TJ = -40°C to 140°C, 1-µF capacitor from VDD to GND. Currents are positive into, negative out of the  
specified terminal (unless otherwise noted,)  
PARAMETER  
TEST CONDITION  
MIN  
TYP  
MAX  
18  
UNITS  
(3)  
tR  
tF  
Rise time  
CLOAD = 1.8 nF  
CLOAD = 1.8 nF  
7
6
Fall time(3)  
10  
Delay matching between 2  
channels  
INA = INB, OUTA and OUTB at 50% transition  
point  
tM  
1
15  
13  
13  
4
Minimum input pulse width  
that changes the output state  
ns  
tPW  
25  
23  
23  
Input to output propagation  
tD1, tD2  
tD3, tD4  
CLOAD = 1.8 nF, 5-V input pulse  
CLOAD = 1.8 nF, 5-V enable pulse  
6
6
(3)  
delay  
EN to output propagation  
(3)  
delay  
(3) See timing diagrams in Figure 1, Figure 2, Figure 3 and Figure 4  
Timing Diagrams  
High  
Input  
Low  
High  
Input  
Low  
High  
High  
Enable  
Enable  
Low  
Low  
90%  
Output  
10%  
90%  
Output  
10%  
tD3  
tD4  
tD3  
tD4  
UDG-11218  
UDG-11217  
Figure 1. Enable Function  
(For Non-Inverting Input Driver Operation)  
Figure 2. Enable Function  
(For Inverting Input Driver Operation)  
High  
Input  
Low  
High  
Input  
Low  
High  
High  
Enable  
Enable  
Low  
Low  
90%  
Output  
10%  
90%  
Output  
10%  
UDG-11220  
tD1  
tD2  
tD1  
tD2  
UDG-11219  
Figure 3. Non-Inverting Input Driver Operation  
Figure 4. Inverting Input Driver Operation  
6
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Copyright © 2011–2013, Texas Instruments Incorporated  
Product Folder Links: UCC27523, UCC27524, UCC27525, UCC27526  
 
 
UCC27523, UCC27524, UCC27525, UCC27526  
www.ti.com  
SLUSAQ3F –NOVEMBER 2011–REVISED MAY 2013  
DEVICE INFORMATION  
UCC27523,4,5(D,DGN) &  
UCC27524P  
(TOP VIEW)  
UCC2752(3,4,5)DSD  
(TOP VIEW)  
UCC27526 DSD  
(TOP VIEW)  
1
2
8
7
1
2
8
7
ENA  
INA  
ENB  
ENA  
INA  
ENB  
1
2
8
7
INA-  
INB-  
INA+  
INB+  
OUTA  
OUTA  
3
4
6
5
3
4
6
5
GND  
INB  
VDD  
3
4
6
5
GND  
INB  
VDD  
GND  
OUTA  
VDD  
OUTB  
OUTB  
OUTB  
Figure 5.  
TERMINAL FUNCTIONS (UCC27523 / UCC27524 / UCC27525)  
TERMINAL  
I/O  
FUNCTION  
NUMBER  
NAME  
1
ENA  
I
Enable input for Channel A: ENA biased LOW Disables Channel A output  
regardless of INA state, ENA biased HIGH or floating Enables Channel A output,  
ENA allowed to float hence the pin-to-pin compatibility with UCC2732X N/C pin.  
2
INA  
I
Input to Channel A: Inverting Input in UCC27523, Non-Inverting Input in UCC27524,  
Inverting Input in UCC27525, OUTA held LOW if INA is unbiased or floating.  
3
4
GND  
INB  
-
I
Ground: All signals referenced to this pin.  
Input to Channel B: Inverting Input in UCC27523, Non-Inverting Input in UCC27524,  
Non-Inverting Input in UCC27525, OUTB held LOW if INB is unbiased or floating.  
5
6
7
8
OUTB  
VDD  
O
I
Output of Channel B  
Bias supply input  
OUTA  
ENB  
O
I
Output of Channel A  
Enable input for Channel B: ENB biased LOW Disables Channel B output  
regardless of INB state, ENB biased HIGH or floating Enables Channel B output,  
ENB allowed to float hence the pin-to-pin compatibility with UCC2732X N/C pin.  
TERMINAL FUNCTIONS (UCC27526)  
TERMINAL  
I/O  
FUNCTION  
NUMBER  
NAME  
1
INA-  
I
Inverting Input to Channel A: When Channel A is used in Non-Inverting  
configuration, connect INA- to GND in order to Enable Channel A output, OUTA held  
LOW if INA- is unbiased or floating.  
2
INB-  
I
Inverting Input to Channel B: When Channel B is used in Non-Inverting  
configuration, connect INB- to GND in order to Enable Channel B output, OUTB held  
LOW if INB- is unbiased or floating.  
3
4
5
6
7
GND  
OUTB  
VDD  
-
I
Ground: All signals referenced to this pin.  
Output of Channel B  
O
I
Bias Supply Input  
OUTA  
INB+  
Output of Channel A  
O
Non-Inverting Input to Channel B: When Channel B is used in Inverting  
configuration, connect INB+ to VDD in order to Enable Channel B output, OUTB held  
LOW if INB+ is unbiased or floating.  
8
INA+  
I
Non-Inverting Input to Channel A: When Channel A is used in Inverting  
configuration, connect INA+ to VDD in order to Enable Channel A output, OUTA held  
LOW if INA+ is unbiased or floating.  
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Table 1. Device Logic Table (UCC27523/UCC27524/UCC27525)  
UCC27523  
UCC27524  
UCC27525  
ENA  
H
ENB  
H
INA  
L
INB  
L
OUTA  
OUTB  
OUTA  
OUTB  
OUTA  
OUTB  
H
H
L
H
L
L
L
L
H
L
H
H
L
L
H
L
H
H
L
H
H
H
H
L
H
L
H
H
L
H
H
H
H
L
H
L
L
H
L
L
L
Any  
x(1)  
L
Any  
x(1)  
L
L
L
L
Any  
x(1)  
x(1)  
x(1)  
x(1)  
Any  
x(1)  
x(1)  
x(1)  
x(1)  
L
L
L
L
L
L
H
H
L
H
L
L
L
H
H
L
L
L
H
L
H
L
H
L
H
L
H
L
H
H
H
H
L
H
L
H
(1) Floating condition.  
Table 2. Device Logic Table (UCC27526)  
INx+ (x = A or B)  
INx- (x = A or B)  
OUTx (x = A or B)  
L
L
L
H
L
L
H
L
L
L
H
L
H
x(1)  
H
Any  
x(1)  
Any  
(1) x = Floating condition.  
8
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Functional Block Diagrams  
VDD  
VDD  
200 kW  
200 kW  
ENA  
1
8
ENB  
VDD  
VDD  
200 kW  
INA  
2
3
7
OUTA  
VDD  
GND  
VDD  
VDD  
UVLO  
6
5
VDD  
VDD  
200 kW  
INB  
4
OUTB  
UDG-11221  
Figure 6. UCC27523 Block Diagram  
VDD  
VDD  
200 kW  
200 kW  
ENA  
1
8
ENB  
VDD  
INA  
OUTA  
2
7
VDD  
400 kW  
VDD  
VDD  
UVLO  
6
5
GND  
INB  
3
4
VDD  
OUTB  
400 kW  
Figure 7. UCC27524 Block Diagram  
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VDD  
VDD  
200 kW  
200 kW  
ENA  
1
8
ENB  
VDD  
VDD  
200 kW  
INA  
2
7
OUTA  
VDD  
VDD  
UVLO  
GND  
INB  
3
4
6
5
VDD  
VDD  
OUTB  
400 kW  
UDG-11223  
Figure 8. UCC27525 Block Diagram  
INA+  
8
VDD  
400 kW  
5
VDD  
VDD  
VDD  
200 kW  
INA-  
GND  
1
3
6
OUTA  
VDD  
UVLO  
VDD  
INB+  
7
4
OUTB  
VDD  
400 kW  
200 kW  
INB-  
2
UDG-11222  
Figure 9. UCC27526 Block Diagram  
10  
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TYPICAL CHARACTERISTICS  
START-UP CURRENT  
vs  
OPERATING SUPPLY CURRENT  
vs  
TEMPERATURE (Outputs switching)  
TEMPERATURE  
4
3.5  
3
Input=VDD  
Input=GND  
0.14  
0.12  
0.1  
VDD = 12 V  
0.08  
0.06  
fSW = 500 kHz  
CL = 500 pF  
VDD=3.4V  
150  
2.5  
−50  
−50  
0
50  
100  
0
50  
100  
150  
Temperature (°C)  
Temperature (°C)  
G001  
G002  
Figure 10.  
Figure 11.  
SUPPLY CURRENT  
vs  
TEMPERATURE (Outputs in DC on/off condition)  
UVLO THRESHOLD  
vs  
TEMPERATURE  
0.6  
0.5  
0.4  
0.3  
0.2  
5
4.5  
4
Input=GND  
Input=VDD  
UVLO Rising  
UVLO Falling  
3.5  
3
Enable=12 V  
VDD = 12 V  
−50  
0
50  
100  
150  
−50  
0
50  
100  
150  
Temperature (°C)  
Temperature (°C)  
Figure 12.  
G012  
G003  
Figure 13.  
INPUT THRESHOLD  
vs  
TEMPERATURE  
ENABLE THRESHOLD  
vs  
TEMPERATURE  
2.5  
2
2.5  
2
VDD = 12 V  
VDD = 12 V  
1.5  
1
1.5  
1
Input High Threshold  
Input Low Threshold  
Enable High Threshold  
Enable Low Threshold  
0.5  
−50  
0.5  
−50  
0
50  
100  
150  
0
50  
100  
150  
Temperature (°C)  
Temperature (°C)  
G004  
G005  
Figure 14.  
Figure 15.  
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TYPICAL CHARACTERISTICS (continued)  
OUTPUT PULLUP RESISTANCE  
OUTPUT PULLDOWN RESISTANCE  
vs  
vs  
TEMPERATURE  
TEMPERATURE  
7
6
5
4
3
1
0.8  
0.6  
0.4  
0.2  
VDD = 12 V  
IOUT = −10 mA  
VDD = 12 V  
IOUT = 10 mA  
−50  
0
50  
100  
150  
−50  
0
50  
100  
150  
Temperature (°C)  
Temperature (°C)  
G006  
G007  
Figure 16.  
Figure 17.  
RISE TIME  
vs  
TEMPERATURE  
FALL TIME  
vs  
TEMPERATURE  
10  
9
9
8
7
6
5
VDD = 12 V  
CLOAD = 1.8 nF  
VDD = 12 V  
CLOAD = 1.8 nF  
8
7
6
5
−50  
0
50  
100  
150  
−50  
0
50  
100  
150  
Temperature (°C)  
Temperature (°C)  
G008  
G009  
Figure 18.  
Figure 19.  
INPUT TO OUTPUT PROPAGATION DELAY  
EN TO OUTPUT PROPAGATION DELAY  
vs  
vs  
TEMPERATURE  
TEMPERATURE  
18  
16  
14  
12  
10  
8
18  
16  
14  
12  
10  
8
Turn−on  
Turn−off  
EN to Output High  
EN to Output Low  
VDD = 12 V  
CLOAD = 1.8 nF  
VDD = 12 V  
CLOAD = 1.8 nF  
−50  
0
50  
100 150  
−50  
0
50  
100 150  
Temperature (°C)  
Temperature (°C)  
G010  
G011  
Figure 20.  
Figure 21.  
12  
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TYPICAL CHARACTERISTICS (continued)  
OPERATING SUPPLY CURRENT  
PROPAGATION DELAYS  
vs  
vs  
FREQUENCY  
SUPPLY VOLTAGE  
60  
50  
40  
30  
20  
10  
0
22  
18  
14  
10  
6
VDD = 4.5 V  
VDD = 12 V  
VDD = 15 V  
Input to Output On delay  
Input to Ouptut Off Delay  
EN to Output On Delay  
EN to Output Off Delay  
CLOAD = 1.8 nF  
Both channels switching  
CLOAD = 1.8 nF  
0
100 200 300 400 500 600 700 800 900 1000  
4
8
12  
16  
20  
Frequency (kHz)  
Supply Voltage (V)  
Figure 23.  
G013  
G014  
Figure 22.  
RISE TIME  
vs  
SUPPLY VOLTAGE  
FALL TIME  
vs  
SUPPLY VOLTAGE  
18  
14  
10  
6
10  
8
CLOAD = 1.8 nF  
CLOAD = 1.8 nF  
6
4
4
8
12  
16  
20  
4
8
12  
16  
20  
Supply Voltage (V)  
Figure 24.  
Supply Voltage (V)  
Figure 25.  
G015  
G016  
ENABLE THRESHOLD  
vs  
TEMPERATURE  
2.5  
2
VDD = 4.5 V  
Enable High Threshold  
Enable Low Threshold  
1.5  
1
0.5  
−50  
0
50  
100  
150  
Temperature (°C)  
G017  
Figure 26.  
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APPLICATION INFORMATION  
High-current gate-driver devices are required in switching power applications for a variety of reasons. In order to  
effect fast switching of power devices and reduce associated switching-power losses, a powerful gate-driver  
device employs between the PWM output of control devices and the gates of the power semiconductor devices.  
Further, gate-driver devices are indispensable when having the PWM controller device directly drive the gates of  
the switching devices is sometimes not feasible. With advent of digital power, this situation is often encountered  
because the PWM signal from the digital controller is often a 3.3-V logic signal which is not capable of effectively  
turning on a power switch. A level-shifting circuitry is needed to boost the 3.3-V signal to the gate-drive voltage  
(such as 12 V) in order to fully turn on the power device and minimize conduction losses. Traditional buffer-drive  
circuits based on NPN/PNP bipolar transistors in totem-pole arrangement, being emitter-follower configurations,  
prove inadequate with digital power because they lack level-shifting capability. Gate-driver devices effectively  
combine both the level-shifting and buffer-drive functions. Gate-driver devices also find other needs such as  
minimizing the effect of high-frequency switching noise by locating the high-current driver physically close to the  
power switch, driving gate-drive transformers and controlling floating power-device gates, reducing power  
dissipationx and thermal stress in controller devices by moving gate-charge power losses into the controller.  
Finally, emerging wide band-gap power-device technologies such as GaN based switches, which are capable of  
supporting very high switching frequency operation, are driving special requirements in terms of gate-drive  
capability. These requirements include operation at low VDD voltages (5 V or lower), low propagation delays,  
tight delay matching and availability in compact, low-inductance packages with good thermal capability. In  
summary gate-driver devices are an extremely important component in switching power combining benefits of  
high-performance, low-cost, component-count, board-space reduction and simplified system design.  
ENB  
UCC2752x  
ENA  
1
2
3
4
ENA  
ENB  
OUTA  
VDD  
8
7
6
5
INA  
INA  
V+  
GND  
INB  
GND  
INB  
OUTB  
GND  
GND  
UDG-11225  
Figure 27. UCC2752x Typical Application Diagram (x = 3, 4 Or 5)  
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UCC27526  
INA-  
INA-  
1
2
3
4
INA+  
INB+  
OUTA  
VDD  
8
7
6
5
INB+  
INB-  
GND  
OUTB  
V+  
GND  
GND  
GND  
UDG-11226  
Figure 28. UCC27526 Channel A in Inverting And Channel B In Non-Inverting Configuration,  
(Enable Function Not Used)  
OUTA is  
ENABLED when  
UCC27526  
ENA is HIGH  
INA-  
ENB  
ENA  
1
2
3
4
INA-  
INA+  
8
7
6
5
INB+  
INB-  
INB+  
OUTB is  
ENABLED when  
ENB is LOW  
GND OUTA  
V+  
GND  
OUTB  
VDD  
GND  
GND  
UDG-11227  
Figure 29. UCC27526 Channel A in Inverting And Channel B In Non-Inverting Configuration,  
(Enable Function Implemented)  
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Introduction  
The UCC2752x family of products represent Texas Instruments’ latest generation of dual-channel low-side high-  
speed gate-driver devices featuring 5-A source/sink current capability, industry best-in-class switching  
characteristics and a host of other features listed in Table 3 all of which combine to ensure efficient, robust and  
reliable operation in high-frequency switching power circuits.  
Table 3. UCC2752x Family of Features and Benefits  
FEATURE  
Best-in-class 13-ns (typ) propagation delay  
1-ns (typ) delay matching between channels  
BENEFIT  
Extremely low-pulse transmission distortion  
Ease of paralleling outputs for higher (2 times) current capability,  
ease of driving parallel-power switches  
Expanded VDD Operating range of 4.5 to 18 V  
Flexibility in system design  
Expanded operating temperature range of –40°C to +140°C  
(See ELECTRICAL CHARACTERISTICS table)  
VDD UVLO Protection  
Outputs are held Low in UVLO condition, which ensures predictable,  
glitch-free operation at power-up and power-down  
Outputs held Low when input pins (INx) in floating condition  
Outputs enable when enable pins (ENx) in floating condition  
Safety feature, especially useful in passing abnormal condition tests  
during safety certification  
Pin-to-pin compatibility with UCC2732X family of products from TI, in  
designs where pin #1, 8 are in floating condition  
CMOS/TTL compatible input and enable threshold with wide  
hysteresis  
Enhanced noise immunity, while retaining compatibility with  
microcontroller logic level input signals (3.3V, 5V) optimized for  
digital power  
Ability of input and enable pins to handle voltage levels not restricted System simplification, especially related to auxiliary bias supply  
by VDD pin bias voltage architecture  
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VDD and Under Voltage Lockout  
The UCC2752x devices have internal undervoltage-lockout (UVLO) protection feature on the VDD pin supply  
circuit blocks. When VDD is rising and the level is still below UVLO threshold, this circuit holds the output LOW,  
regardless of the status of the inputs. The UVLO is typically 4.25 V with 350-mV typical hysteresis. This  
hysteresis prevents chatter when low VDD supply voltages have noise from the power supply and also when  
there are droops in the VDD bias voltage when the system commences switching and there is a sudden increase  
in IDD. The capability to operate at low voltage levels such as below 5 V, along with best in class switching  
characteristics, is especially suited for driving emerging GaN power semiconductor devices.  
For example, at power up, the UCC2752x driver-device output remains LOW until the VDD voltage reaches the  
UVLO threshold if Enable pin is active or floating. The magnitude of the OUT signal rises with VDD until steady-  
state VDD is reached. The non-inverting operation in Figure 30 shows that the output remains LOW until the  
UVLO threshold is reached, and then the output is in-phase with the input. The inverting operation in Figure 31  
shows that the output remains LOW until the UVLO threshold is reached, and then the output is out-phase with  
the input. With UCC27526 the output turns to high-state only if INX+ is high and INX– is low after the UVLO  
threshold is reached.  
Because the device draws current from the VDD pin to bias all internal circuits, for the best high-speed circuit  
performance, two VDD bypass capacitors are recommended to prevent noise problems. The use of surface  
mount components is highly recommended. A 0.1-μF ceramic capacitor must be located as close as possible to  
the VDD to GND pins of the gate-driver device. In addition, a larger capacitor (such as 1-μF) with relatively low  
ESR must be connected in parallel and close proximity, in order to help deliver the high-current peaks required  
by the load. The parallel combination of capacitors presents a low impedance characteristic for the expected  
current levels and switching frequencies in the application.  
VDD Threshold  
VDD Threshold  
VDD  
EN  
VDD  
EN  
IN  
IN  
OUT  
OUT  
UDG-11229  
UDG-11228  
Figure 30. Power-Up Non-Inverting Driver  
Operating Supply Current  
Figure 31. Power-Up Inverting Driver  
The UCC2752x products feature very low quiescent IDD currents. The typical operating-supply current in UVLO  
state and fully-on state (under static and switching conditions) are summarized in Figure 10, Figure 11 and  
Figure 12. The IDD current when the device is fully on and outputs are in a static state (DC high or DC low, refer  
Figure 11) represents lowest quiescent IDD current when all the internal logic circuits of the device are fully  
operational. The total supply current is the sum of the quiescent IDD current, the average IOUT current due to  
switching and finally any current related to pullup resistors on the enable pins and inverting input pins. For  
example when the inverting Input pins are pulled low additional current is drawn from VDD supply through the  
pullup resistors (refer to Figure 6 though Figure 9). Knowing the operating frequency (fSW) and the MOSFET gate  
(QG) charge at the drive voltage being used, the average IOUT current can be calculated as product of QG and  
fSW  
.
A complete characterization of the IDD current as a function of switching frequency at different VDD bias voltages  
under 1.8-nF switching load in both channels is provided in Figure 22. The strikingly linear variation and close  
correlation with theoretical value of average IOUT indicates negligible shoot-through inside the gate-driver device  
attesting to its high-speed characteristics.  
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Input Stage  
The input pins of UCC2752x gate-driver devices are based on a TTL and CMOS compatible input-threshold logic  
that is independent of the VDD supply voltage. With typically high threshold = 2.1 V and typically low threshold =  
1.2 V, the logic level thresholds are conveniently driven with PWM control signals derived from 3.3-V and 5-V  
digital power-controller devices. Wider hysteresis (typ 0.9 V) offers enhanced noise immunity compared to  
traditional TTL logic implementations, where the hysteresis is typically less than 0.5 V. UCC2752x devices also  
feature tight control of the input pin threshold voltage levels which eases system design considerations and  
ensures stable operation across temperature (refer to Figure 14). The very low input capacitance on these pins  
reduces loading and increases switching speed.  
The UCC2752x devices feature an important safety feature wherein, whenever any of the input pins is in a  
floating condition, the output of the respective channel is held in the low state. This is achieved using VDD pullup  
resistors on all the Inverting inputs (INA, INB in UCC27523, INA in UCC27525 and INA-, INB- in UCC27526) or  
GND pulldown resistors on all the non-inverting input pins (INA, INB in UCC27524, INB in UCC27525 and INA+,  
INB+ in UCC27526), as shown in the device block diagrams.  
While UCC27523/4/5 devices feature one input pin per channel, the UCC27526 features a dual input  
configuration with two input pins available to control the output state of each channel. With the UCC27526 device  
the user has the flexibility to drive each channel using either a non-inverting input pin (INx+) or an inverting input  
pin (INx-). The state of the output pin is dependent on the bias on both the INx+ and INx- pins (where x = A, B).  
Once an Input pin is chosen to drive a channel, the other input pin of that channel (the unused input pin) must be  
properly biased in order to enable the output of the channel. The unused input pin cannot remain in a floating  
condition because, as mentioned earlier, whenever any input pin is left in a floating condition, the output of that  
channel is disabled using the internal pullup or pulldown resistors for safety purposes. Alternatively, the unused  
input pin is used effectively to implement an enable/disable function, as explained below.  
•
•
•
In order to drive the channel x (x = A or B) in a non-inverting configuration, apply the PWM control input  
signal to INx+ pin. In this case, the unused input pin, INx-, must be biased low (eg. tied to GND) in order to  
enable the output of this channel.  
–
Alternately, the INx- pin can be used to implement the enable/disable function using an external logic  
signal. OUTx is disabled when INx- is biased High and OUTx is enabled when INX- is biased low.  
In order to drive the channel x (x = A or B) in an Inverting configuration, apply the PWM control input signal to  
INX- pin. In this case, the unused input pin, INX+, must be biased high (eg. tied to VDD) in order to enable  
the output of the channel.  
–
Alternately, the INX+ pin can be used to implement the enable/disable function using an external logic  
signal. OUTX is disabled when INX+ is biased low and OUTX is enabled when INX+ is biased high.  
Finally, it is worth noting that the UCC27526 output pin can be driven into high state only when INx+ pin is  
biased high and INx- input is biased low.  
Refer to the input/output logic truth table and typical application diagram, (Figure 28 and Figure 29), for additional  
clarification.  
The input stage of each driver is driven by a signal with a short rise or fall time. This condition is satisfied in  
typical power supply applications, where the input signals are provided by a PWM controller or logic gates with  
fast transition times (<200 ns) with a slow changing input voltage, the output of the driver may switch repeatedly  
at a high frequency. While the wide hysteresis offered in UCC2752x definitely alleviates this concern over most  
other TTL input threshold devices, extra care is necessary in these implementations. If limiting the rise or fall  
times to the power device is the primary goal, then an external resistance is highly recommended between the  
output of the driver and the power device. This external resistor has the additional benefit of reducing part of the  
gate-charge related power dissipation in the gate driver device package and transferring it into the external  
resistor itself.  
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SLUSAQ3F –NOVEMBER 2011–REVISED MAY 2013  
Enable Function  
The enable function is an extremely beneficial feature in gate-driver devices especially for certain applications  
such as synchronous rectification where the driver outputs disable in light-load conditions to prevent negative  
current circulation and to improve light-load efficiency.  
UCC27523/4/5 devices are provided with independent enable pins ENx for exclusive control of each driver-  
channel operation. The enable pins are based on a non-inverting configuration (active-high operation). Thus  
when ENx pins are driven high the drivers are enabled and when ENx pins are driven low the drivers are  
disabled. Like the input pins, the enable pins are also based on a TTL and CMOS compatible input-threshold  
logic that is independent of the supply voltage and are effectively controlled using logic signals from 3.3-V and 5-  
V microcontrollers. The UCC2752X devices also feature tight control of the Enable-function threshold-voltage  
levels which eases system design considerations and ensures stable operation across temperature (refer to  
Figure 15). The ENx pins are internally pulled up to VDD using pullup resistors as a result of which the outputs of  
the device are enabled in the default state. Hence the ENx pins are left floating or Not Connected (N/C) for  
standard operation, where the enable feature is not needed. Essentially, this floating allows the UCC27523/4/5  
devices to be pin-to-pin compatible with TI’s previous generation drivers UCC27323/4/5 respectively, where pins  
#1, 8 are N/C pins. If the channel A and Channel B inputs and outputs are connected in parallel to increase the  
driver current capacity, ENA and ENB are connected and driven together.  
The UCC27526 device does not feature dedicated enable pins. However, as mentioned earlier, an  
enable/disable function is easily implemented in UCC27526 using the unused input pin. When INx+ is pulled-  
down to GND or INx- is pulled-down to VDD, the output is disabled. Thus INx+ pin is used like an enable pin that  
is based on active high logic, while INx- is used like an enable pin that is based on active low logic.Note that  
while the ENA, ENB pins in UCC27523/4/5 are allowed to be in floating condition during standard operation and  
the outputs will be enabled, the INx+, INx- pins in UCC27526 are not allowed to be floating because this will  
disable the outputs.  
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Output Stage  
The UCC2752x device output stage features a unique architecture on the pullup structure which delivers the  
highest peak-source current when it is most needed during the Miller plateau region of the power-switch turnon  
transition (when the power switch drain or collector voltage experiences dV/dt). The output stage pullup structure  
features a P-Channel MOSFET and an additional N-Channel MOSFET in parallel. The function of the N-Channel  
MOSFET is to provide a brief boost in the peak sourcing current enabling fast turnon. This is accomplished by  
briefly turning-on the N-Channel MOSFET during a narrow instant when the output is changing state from Low to  
High.  
VCC  
ROH  
RNMOS, Pull Up  
Gate  
Voltage  
Boost  
OUT  
Anti Shoot-  
Through  
Circuitry  
Input Signal  
Narrow Pulse at  
each Turn On  
ROL  
Figure 32. UCC2752X Gate Driver Output Structure  
The ROH parameter (see ELECTRICAL CHARACTERISTICS) is a DC measurement and it is representative of  
the on-resistance of the P-Channel device only. This is because the N-Channel device is held in the off state in  
DC condition and is turned-on only for a narrow instant when output changes state from low to high. Note that  
effective resistance of UCC2752x pullup stage during the turnon instant is much lower than what is represented  
by ROH parameter.  
The pulldown structure in UCC2752x is simply composed of a N-Channel MOSFET. The ROL parameter (see  
ELECTRICAL CHARACTERISTICS), which is also a DC measurement, is representative of the impedance of the  
pulldown stage in the device. In UCC2752x, the effective resistance of the hybrid pullup structure during turnon is  
estimated to be approximately 1.5 × ROL, estimated based on design considerations.  
Each output stage in UCC2752x is capable of supplying 5-A peak source and 5-A peak sink current pulses. The  
output voltage swings between VDD and GND providing rail-to-rail operation, thanks to the MOS-output stage  
which delivers very low drop-out. The presence of the MOSFET-body diodes also offers low impedance to  
switching overshoots and undershoots which means that in many cases, external Schottky-diode clamps may be  
eliminated. The outputs of these drivers are designed to withstand 500-mA reverse current without either  
damage to the device or logic malfunction.  
The UCC2752x devices are particularly suited for dual-polarity, symmetrical drive-gate transformer applications  
where the primary winding of transformer driven by OUTA and OUTB, with inputs INA and INB being driven  
complementary to each other. This situation is due to the extremely low drop-out offered by the MOS output  
stage of these devices, both during high (VOH) and low (VOL) states along with the low impedance of the driver  
output stage, all of which allow alleviate concerns regarding transformer demagnetization and flux imbalance.  
The low propagation delays also ensure accurate reset for high-frequency applications.  
For applications that have zero voltage switching during power MOSFET turnon or turnoff interval, the driver  
supplies high-peak current for fast switching even though the miller plateau is not present. This situation often  
occurs in synchronous rectifier applications because the body diode is generally conducting before power  
MOSFET is switched on.  
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SLUSAQ3F –NOVEMBER 2011–REVISED MAY 2013  
Low Propagation Delays and Tightly Matched Outputs  
The UCC2752x driver devices feature a best in class, 13-ns (typical) propagation delay between input and output  
which goes to offer the lowest level of pulse-transmission distortion available in the industry for high frequency  
switching applications. For example in synchronous rectifier applications, the SR MOSFETs are driven with very  
low distortion when a single driver device is used to drive both the SR MOSFETs. Further, the driver devices also  
feature an extremely accurate, 1-ns (typ) matched internal-propagation delays between the two channels which  
is beneficial for applications requiring dual gate drives with critical timing. For example in a PFC application, a  
pair of paralleled MOSFETs may be driven independently using each output channel, which the inputs of both  
channels are driven by a common control signal from the PFC controller device. In this case the 1ns delay  
matching ensures that the paralleled MOSFETs are driven in a simultaneous fashion with the minimum of turnon  
delay difference. Yet another benefit of the tight matching between the two channels is that the two channels are  
connected together to effectively increase current drive capability, for example A and B channels may be  
combined into a single driver by connecting the INA and INB inputs together and the OUTA and OUTB outputs  
together. Then, a single signal controls the paralleled combination.  
Caution must be exercised when directly connecting OUTA and OUTB pins together because there is the  
possibility that any delay between the two channels during turnon or turnoff may result in shoot-through current  
conduction as shown in Figure 33. While the two channels are inherently very well matched (4-ns Max  
propagation delay), note that there may be differences in the input threshold voltage level between the two  
channels which causes the delay between the two outputs especially when slow dV/dt input signals are  
employed. The following guidelines are recommended whenever the two driver channels are paralleled using  
direct connections between OUTA and OUTB along with INA and INB:  
•
Use very fast dV/dt input signals (20 V/µs or greater) on INA and INB pins to minimize impact of differences  
in input thresholds causing delays between the channels.  
•
INA and INB connections must be made as close to the device pins as possible.  
Wherever possible, a safe practice would be to add an option in the design to have gate resistors in series with  
OUTA and OUTB. This allows the option to use 0-Ω resistors for paralleling outputs directly or to add appropriate  
series resistances to limit shoot-through current, should it become necessary.  
VDD  
VDD  
200 kW  
200 kW  
ENA  
INA  
1
2
8
7
ENB  
ISHOOT-THROUGH  
OUTA  
VDD  
Slow Input Signal  
VIN_H  
(Channel B)  
VDD  
400 kW  
VIN_H  
(Channel A)  
VDD  
VDD  
UVLO  
6
5
GND  
INB  
3
4
VDD  
OUTB  
400 kW  
Figure 33. Slow Input Signal May Cause Shoot-Through Between Channels During Paralleling  
(Recommended dV/dt Is 20 V/µs Or Higher)  
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Figure 34. Turnon Propagation Delay  
(CL = 1.8 nF, VDD = 12 V)  
Figure 35. Turnon Rise Time  
(CL = 1.8 nF, VDD = 12 V)  
Figure 36. . TurnOff Propagation Delay  
(CL = 1.8 nF, VDD = 12 V)  
Figure 37. TurnOff Fall Time  
(CL = 1.8 nF, VDD = 12 V)  
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SLUSAQ3F –NOVEMBER 2011–REVISED MAY 2013  
Drive Current and Power Dissipation  
The UCC27523/4/5/6 family of drivers are capable of delivering 5-A of current to a MOSFET gate for a period of  
several-hundred nanoseconds at VDD = 12 V. High peak current is required to turn the device ON quickly. Then,  
to turn the device OFF, the driver is required to sink a similar amount of current to ground which repeats at the  
operating frequency of the power device. The power dissipated in the gate driver device package depends on the  
following factors:  
•
Gate charge required of the power MOSFET (usually a function of the drive voltage VGS, which is very close  
to input bias supply voltage VDD due to low VOH drop-out)  
•
•
Switching frequency  
Use of external gate resistors  
Because UCC2752x features very low quiescent currents and internal logic to eliminate any shoot-through in the  
output driver stage, their effect on the power dissipation within the gate driver can be safely assumed to be  
negligible.  
When a driver device is tested with a discrete, capacitive load calculating the power that is required from the bias  
supply is fairly simple. The energy that must be transferred from the bias supply to charge the capacitor is given  
by Equation 1.  
1
2
EG  
=
CLOADVDD  
2
(1)  
where is load capacitor and is bias voltage feeding the driver.  
There is an equal amount of energy dissipated when the capacitor is charged. This leads to a total power loss  
given by Equation 2.  
2
LOAD DD SW  
P
= C  
V
f
G
where  
•
fSW is the switching frequency  
(2)  
(3)  
With VDD = 12 V, CLOAD = 10 nF and ƒSW = 300 kHz the power loss is calculated as (see Equation 3):  
2
= 10nF´12V ´300kHz = 0.432W  
P
G
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The switching load presented by a power MOSFET is converted to an equivalent capacitance by examining the  
gate charge required to switch the device. This gate charge includes the effects of the input capacitance plus the  
added charge needed to swing the drain voltage of the power device as it switches between the ON and OFF  
states. Most manufacturers provide specifications that provide the typical and maximum gate charge, in nC, to  
switch the device under specified conditions. Using the gate charge Qg, the power that must be dissipated when  
charging a capacitor is determined which by using the equivalence Qg = CLOADVDD to provide Equation 4 for  
power:  
2
LOAD DD SW  
P
= C  
V
f
= Q V f  
g DD SW  
G
(4)  
Assuming that UCC2752x is driving power MOSFET with 60 nC of gate charge (Qg = 60 nC at VDD = 12 V) on  
each output, the gate charge related power loss is calculated as (see Equation 5):  
P
= 2x60nC´12V ´300kHz = 0.432W  
G
(5)  
This power PG is dissipated in the resistive elements of the circuit when the MOSFET turns on or turns off. Half  
of the total power is dissipated when the load capacitor is charged during turnon, and the other half is dissipated  
when the load capacitor is discharged during turnoff. When no external gate resistor is employed between the  
driver and MOSFET/IGBT, this power is completely dissipated inside the driver package. With the use of external  
gate drive resistors, the power dissipation is shared between the internal resistance of driver and external gate  
resistor in accordance to the ratio of the resistances (more power dissipated in the higher resistance component).  
Based on this simplified analysis, the driver power dissipation during switching is calculated as follows (see  
Equation 6):  
æ
ç
è
ö
÷
ø
R
R
ON  
OFF  
P
= 0.5´Q ´ VDD´ f ´  
SW  
+
SW  
G
R
+ R  
R
+ R  
ON GATE  
OFF  
GATE  
where  
•
•
ROFF = ROL  
RON (effective resistance of pullup structure) = 1.5 x ROL  
(6)  
In addition to the above gate-charge related power dissipation, additional dissipation in the driver is related to the  
power associated with the quiescent bias current consumed by the device to bias all internal circuits such as  
input stage (with pullup and pulldown resistors), enable, and UVLO sections. As shown in Figure 11, the  
quiescent current is less than 0.6 mA even in the highest case. The quiescent power dissipation is calculated  
easily with Equation 7.  
P
= I  
V
Q
DD DD  
(7)  
Assuming , IDD = 6 mA, the power loss is:  
= 0.6 mA ´12V = 7.2mW  
P
Q
(8)  
Clearly, this power loss is insignificant compared to gate charge related power dissipation calculated earlier.  
With a 12-V supply, the bias current is estimated as follows, with an additional 0.6-mA overhead for the  
quiescent consumption:  
P
0.432 W  
G
I
~
=
= 0.036 A  
DD  
V
12 V  
DD  
(9)  
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SLUSAQ3F –NOVEMBER 2011–REVISED MAY 2013  
Thermal Information  
The useful range of a driver is greatly affected by the drive power requirements of the load and the thermal  
characteristics of the device package. In order for a gate driver device to be useful over a particular temperature  
range the package must allow for the efficient removal of the heat produced while keeping the junction  
temperature within rated limits. The UCC27523/4/5/6 family of drivers is available in four different packages to  
cover a range of application requirements. The thermal metrics for each of these packages are summarized in  
the Thermal Information section of the datasheet. For detailed information regarding the thermal information  
table, please refer to Application Note from Texas Instruments entitled, IC Package Thermal Metrics (SPRA953).  
Among the different package options available in the UCC2752x family, of particular mention are the DSD &  
DGN packages when it comes to power dissipation capability. The MSOP PowerPAD-8 (DGN) package and 3-  
mm × 3-mm WSON (DSD) package offer a means of removing the heat from the semiconductor junction through  
the bottom of the package. Both these packages offer an exposed thermal pad at the base of the package. This  
pad is soldered to the copper on the printed circuit board directly underneath the device package, reducing the  
thermal resistance to a very low value. This allows a significant improvement in heat-sinking over that available in  
the D or P packages. The printed circuit board must be designed with thermal lands and thermal vias to complete  
the heat removal subsystem. Note that the exposed pads in the MSOP-8 (PowerPAD) and WSON-8 packages  
are not directly connected to any leads of the package, however, it is electrically and thermally connected to the  
substrate of the device which is the ground of the device. TI recommends to externally connect the exposed  
pads to GND in PCB layout for better EMI immunity.  
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PCB Layout  
Proper PCB layout is extremely important in a high-current fast-switching circuit to provide appropriate device  
operation and design robustness. The UCC27523/4/5/6 family of gate drivers incorporates short propagation  
delays and powerful output stages capable of delivering large current peaks with very fast rise and fall times at  
the gate of power MOSFET to facilitate voltage transitions very quickly. At higher VDD voltages, the peak current  
capability is even higher (5-A peak current is at VDD = 12 V). Very high di/dt causes unacceptable ringing if the  
trace lengths and impedances are not well controlled. The following circuit layout guidelines are strongly  
recommended when designing with these high-speed drivers.  
•
Locate the driver device as close as possible to power device in order to minimize the length of high-current  
traces between the Output pins and the Gate of the power device.  
•
Locate the VDD bypass capacitors between VDD and GND as close as possible to the driver with minimal  
trace length to improve the noise filtering. These capacitors support high peak current being drawn from VDD  
during turnon of power MOSFET. The use of low inductance SMD components such as chip resistors and  
chip capacitors is highly recommended.  
•
The turnon and turnoff current loop paths (driver device, power MOSFET and VDD bypass capacitor) should  
be minimized as much as possible in order to keep the stray inductance to a minimum. High dI/dt is  
established in these loops at 2 instances during turnon and turnoff transients, which will induce significant  
voltage transients on the output pin of the driver device and Gate of the power MOSFET.  
•
•
•
Wherever possible, parallel the source and return traces, taking advantage of flux cancellation  
Separate power traces and signal traces, such as output and input signals.  
Star-point grounding is a good way to minimize noise coupling from one current loop to another. The GND of  
the driver is connected to the other circuit nodes such as source of power MOSFET and ground of PWM  
controller at one, single point. The connected paths must be as short as possible to reduce inductance and  
be as wide as possible to reduce resistance.  
•
Use a ground plane to provide noise shielding. Fast rise and fall times at OUT may corrupt the input signals  
during transition. The ground plane must not be a conduction path for any current loop. Instead the ground  
plane must be connected to the star-point with one single trace to establish the ground potential. In addition  
to noise shielding, the ground plane can help in power dissipation as well  
•
•
In noisy environments, tiying inputs of an unused channel of UCC27526 to VDD (in case of INx+) or GND (in  
case of INX-) using short traces in order to ensure that the output is enabled and to prevent noise from  
causing malfunction in the output may be necessary.  
Exercise caution when replacing the UCC2732x/UCC2742x devices with the UCC2752x:  
–
–
UCC2752x is a much stronger gate driver (5-A peak current versus 4-A peak current).  
UCC2752x is a much faster gate driver (13-ns/13-ns rise/fall propagation delay versus 25-ns/35-ns rise/fall  
propagation delay).  
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SLUSAQ3F –NOVEMBER 2011–REVISED MAY 2013  
REVISION HISTORY  
Changes from Original (November 2011) to Revision A  
Page  
•
Changed datasheet status to Production Data. .................................................................................................................... 1  
Changes from Revision A (November 2011) to Revision B  
Page  
•
•
•
Added note to packaging section, "DSD package is rated MSL level 2". ............................................................................. 2  
Changed Supply start threshold row to include two temperature ranges. ............................................................................ 5  
Changed Minimum operating voltage after supply start min and max values from 3.6 V to 4.2 V to 3.40 V and 4.40  
V. ........................................................................................................................................................................................... 5  
•
•
•
Changed Supply voltage hysteresis typ value from 0.35 to 0.30. ........................................................................................ 5  
Changed UCC27526 Block Diagram drawing. ................................................................................................................... 10  
Changed UCC27526 Channel A in Inverting and Channel B in Non-Inverting Configuration drawing. ............................. 15  
Changes from Revision B ( December 2011) to Revision C  
Page  
•
•
•
•
•
•
•
Added ROH note in the Outputs (OUTA, OUTB) section. ...................................................................................................... 5  
Added an updated Output Stage section. ........................................................................................................................... 20  
Added UCC2752X Gate Driver Output Structure image .................................................................................................... 20  
Added an updated Low Propagation Delays and Tightly Matched Outputs section. ......................................................... 21  
Added Slow Input Signal Combined with Differences in Input Threshold Voltage image. ................................................. 21  
Added updated Drive Current and Power Dissipation section. ........................................................................................... 23  
Added a PSW... equation. .................................................................................................................................................. 24  
Changes from Revision C (March 2012) to Revision D  
Page  
•
•
•
•
Changed Inputs (INA, INB, INA+, INA-, INB+, INB-) section to include UCC2752X (D, DGN, DSD) information. .............. 5  
Added Inputs (INA, INB, INA+, INA-, INB+, INB-) UCC27524P ONLY section. ................................................................... 5  
Changed Enable (ENA, ENB) section to include UCC2752X (D, DGN, DSD) information. ................................................. 5  
Added ENABLE (ENA, ENB) UCC27524P ONLY section. .................................................................................................. 5  
Changes from Revision D (April 2012) to Revision E  
Page  
•
•
Added OUTA, OUTB voltage field and values. ..................................................................................................................... 3  
Changed table note from "Values are verified by characterization and are not production tested." to "Values are  
verified by characterization on bench." ................................................................................................................................. 3  
•
•
•
•
Added note, "Values are verified by characterization and are not production tested." ........................................................ 3  
Changed Switching Time tPW values from 10 ns and 25 ns to 15 ns and 25 ns ns. ............................................................ 5  
Changed Functional Block Diagrams images. ...................................................................................................................... 9  
Changed Slow Input Signal Figure 33. ............................................................................................................................... 21  
Changes from Revision E (June 2012) to Revision F  
Page  
•
Added 0.5 to PSW equation in Drive Current and Power Dissipation section ..................................................................... 24  
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PACKAGE OPTION ADDENDUM  
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29-May-2013  
PACKAGING INFORMATION  
Orderable Device  
UCC27523D  
Status Package Type Package Pins Package  
Eco Plan Lead/Ball Finish  
MSL Peak Temp  
Op Temp (°C)  
-40 to 140  
-40 to 140  
-40 to 140  
-40 to 140  
-40 to 140  
-40 to 140  
-40 to 140  
-40 to 140  
-40 to 140  
-40 to 140  
-40 to 140  
-40 to 140  
-40 to 140  
-40 to 140  
-40 to 140  
-40 to 140  
-40 to 140  
Device Marking  
Samples  
Drawing  
Qty  
(1)  
(2)  
(3)  
(4/5)  
ACTIVE  
SOIC  
D
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
8
75  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU  
Level-1-260C-UNLIM  
27523  
27523  
27523  
27523  
27523  
27523  
27524  
27524  
27524  
27524  
SBA  
UCC27523DGN  
UCC27523DGNR  
UCC27523DR  
UCC27523DSDR  
UCC27523DSDT  
UCC27524D  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
MSOP-  
PowerPAD  
DGN  
DGN  
D
80  
2500  
2500  
3000  
250  
75  
Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM  
& no Sb/Br)  
MSOP-  
PowerPAD  
Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM  
& no Sb/Br)  
SOIC  
SON  
SON  
SOIC  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
Level-1-260C-UNLIM  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
Level-1-260C-UNLIM  
DSD  
DSD  
D
Green (RoHS  
& no Sb/Br)  
Green (RoHS  
& no Sb/Br)  
Green (RoHS  
& no Sb/Br)  
UCC27524DGN  
UCC27524DGNR  
UCC27524DR  
UCC27524DSDR  
UCC27524DSDT  
UCC27524P  
MSOP-  
PowerPAD  
DGN  
DGN  
D
80  
Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM  
& no Sb/Br)  
MSOP-  
PowerPAD  
2500  
2500  
3000  
250  
50  
Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM  
& no Sb/Br)  
SOIC  
SON  
SON  
PDIP  
SOIC  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
Level-1-260C-UNLIM  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
N / A for Pkg Type  
DSD  
DSD  
P
Green (RoHS  
& no Sb/Br)  
Green (RoHS  
& no Sb/Br)  
SBA  
Green (RoHS  
& no Sb/Br)  
27524  
27525  
27525  
27525  
27525  
UCC27525D  
D
75  
Green (RoHS  
& no Sb/Br)  
Level-1-260C-UNLIM  
UCC27525DGN  
UCC27525DGNR  
UCC27525DR  
MSOP-  
PowerPAD  
DGN  
DGN  
D
80  
Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM  
& no Sb/Br)  
MSOP-  
PowerPAD  
2500  
2500  
Green (RoHS CU NIPDAUAG Level-1-260C-UNLIM  
& no Sb/Br)  
SOIC  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU  
Level-1-260C-UNLIM  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
29-May-2013  
Orderable Device  
Status Package Type Package Pins Package  
Eco Plan Lead/Ball Finish  
MSL Peak Temp  
Op Temp (°C)  
-40 to 140  
-40 to 140  
-40 to 140  
-40 to 140  
Device Marking  
Samples  
Drawing  
Qty  
(1)  
(2)  
(3)  
(4/5)  
UCC27525DSDR  
UCC27525DSDT  
UCC27526DSDR  
UCC27526DSDT  
ACTIVE  
SON  
SON  
SON  
SON  
DSD  
8
8
8
8
3000  
Green (RoHS  
& no Sb/Br)  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
CU NIPDAU  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
Level-2-260C-1 YEAR  
27525  
27525  
SCB  
ACTIVE  
ACTIVE  
ACTIVE  
DSD  
DSD  
DSD  
250  
3000  
250  
Green (RoHS  
& no Sb/Br)  
Green (RoHS  
& no Sb/Br)  
Green (RoHS  
& no Sb/Br)  
SCB  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability  
information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that  
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between  
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight  
in homogeneous material)  
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.  
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation  
of the previous line and the two combined represent the entire Device Marking for that device.  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
Addendum-Page 2  
PACKAGE OPTION ADDENDUM  
www.ti.com  
29-May-2013  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
Addendum-Page 3  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
29-May-2013  
TAPE AND REEL INFORMATION  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
(mm) W1 (mm)  
UCC27523DGNR  
MSOP-  
Power  
PAD  
DGN  
8
2500  
330.0  
12.4  
5.3  
3.4  
1.4  
8.0  
12.0  
Q1  
UCC27523DR  
UCC27523DSDR  
UCC27523DSDT  
UCC27524DGNR  
SOIC  
SON  
SON  
D
8
8
8
8
2500  
3000  
250  
330.0  
330.0  
180.0  
330.0  
12.4  
12.4  
12.4  
12.4  
6.4  
3.3  
3.3  
5.3  
5.2  
3.3  
3.3  
3.4  
2.1  
1.1  
1.1  
1.4  
8.0  
8.0  
8.0  
8.0  
12.0  
12.0  
12.0  
12.0  
Q1  
Q2  
Q2  
Q1  
DSD  
DSD  
DGN  
MSOP-  
Power  
PAD  
2500  
UCC27524DR  
UCC27524DSDR  
UCC27524DSDT  
UCC27525DGNR  
SOIC  
SON  
SON  
D
8
8
8
8
2500  
3000  
250  
330.0  
330.0  
180.0  
330.0  
12.4  
12.4  
12.4  
12.4  
6.4  
3.3  
3.3  
5.3  
5.2  
3.3  
3.3  
3.4  
2.1  
1.1  
1.1  
1.4  
8.0  
8.0  
8.0  
8.0  
12.0  
12.0  
12.0  
12.0  
Q1  
Q2  
Q2  
Q1  
DSD  
DSD  
DGN  
MSOP-  
Power  
PAD  
2500  
UCC27525DR  
UCC27525DSDR  
UCC27525DSDT  
UCC27526DSDR  
UCC27526DSDT  
SOIC  
SON  
SON  
SON  
SON  
D
8
8
8
8
8
2500  
3000  
250  
330.0  
330.0  
180.0  
330.0  
180.0  
12.4  
12.4  
12.4  
12.4  
12.4  
6.4  
3.3  
3.3  
3.3  
3.3  
5.2  
3.3  
3.3  
3.3  
3.3  
2.1  
1.1  
1.1  
1.1  
1.1  
8.0  
8.0  
8.0  
8.0  
8.0  
12.0  
12.0  
12.0  
12.0  
12.0  
Q1  
Q2  
Q2  
Q2  
Q2  
DSD  
DSD  
DSD  
DSD  
3000  
250  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
29-May-2013  
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
SPQ  
Length (mm) Width (mm) Height (mm)  
UCC27523DGNR  
UCC27523DR  
MSOP-PowerPAD  
DGN  
D
8
8
8
8
8
8
8
8
8
8
8
8
8
8
2500  
2500  
3000  
250  
364.0  
367.0  
367.0  
210.0  
364.0  
367.0  
367.0  
210.0  
364.0  
367.0  
367.0  
210.0  
367.0  
210.0  
364.0  
367.0  
367.0  
185.0  
364.0  
367.0  
367.0  
185.0  
364.0  
367.0  
367.0  
185.0  
367.0  
185.0  
27.0  
35.0  
35.0  
35.0  
27.0  
35.0  
35.0  
35.0  
27.0  
35.0  
35.0  
35.0  
35.0  
35.0  
SOIC  
UCC27523DSDR  
UCC27523DSDT  
UCC27524DGNR  
UCC27524DR  
SON  
DSD  
DSD  
DGN  
D
SON  
MSOP-PowerPAD  
SOIC  
2500  
2500  
3000  
250  
UCC27524DSDR  
UCC27524DSDT  
UCC27525DGNR  
UCC27525DR  
SON  
DSD  
DSD  
DGN  
D
SON  
MSOP-PowerPAD  
SOIC  
2500  
2500  
3000  
250  
UCC27525DSDR  
UCC27525DSDT  
UCC27526DSDR  
UCC27526DSDT  
SON  
DSD  
DSD  
DSD  
DSD  
SON  
SON  
3000  
250  
SON  
Pack Materials-Page 2  
IMPORTANT NOTICE  
Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other  
changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest  
issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and  
complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale  
supplied at the time of order acknowledgment.  
TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms  
and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary  
to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily  
performed.  
TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and  
applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide  
adequate design and operating safeguards.  
TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or  
other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information  
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Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration  
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Copyright © 2013, Texas Instruments Incorporated  

UCC27525DGNR CAD模型

  • 引脚图

  • 封装焊盘图

    • UCC27525DGNR 替代型号

    型号 制造商 描述 替代类型 文档
    UCC27525DGN TI Dual 5-A High-Speed Low-Side Gate Driver 类似代替

    UCC27525DGNR 相关器件

    型号 制造商 描述 价格 文档
    UCC27525DR TI Dual 5-A High-Speed Low-Side Gate Driver 获取价格
    UCC27525DSD TI Dual 5-A High-Speed Low-Side Gate Driver 获取价格
    UCC27525DSDR TI Dual 5-A High-Speed Low-Side Gate Driver 获取价格
    UCC27525DSDT TI Dual 5-A High-Speed Low-Side Gate Driver 获取价格
    UCC27525DW TI 暂无描述 获取价格
    UCC27526 TI Dual 5-A High-Speed Low-Side Gate Driver 获取价格
    UCC27526DSD TI Dual 5-A High-Speed Low-Side Gate Driver 获取价格
    UCC27526DSDR TI Dual 5-A High-Speed Low-Side Gate Driver 获取价格
    UCC27526DSDT TI Dual 5-A High-Speed Low-Side Gate Driver 获取价格
    UCC27527 TI Dual 5-A High-Speed Low-Side Gate Driver Based on CMOS Input Threshold Logic 获取价格

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