ACPL-021L-000E--Datasheet/数据表在线中文翻译

ACPL-M21L, ACPL-021L and ACPL-024L

Low Power, 5 MBd Digital CMOS Optocoupler

Data Sheet

Lead (Pb) Free

RoHS 6 fully

compliant

RoHS 6 fully compliant options available;

-xxxE denotes a lead-free product

Description

Features

ACPL-M21L (single channel SO-5 package), ACPL-021L

(single channel SO-8 package) and ACPL-024L (dual

channel SO-8 package) are optically-coupled logic gates.

The detector IC has CMOS output stage and optical

•ꢀ CMOS output

•ꢀ Wide supply voltage: 2.7 V – 5.5 V

•ꢀ Low power supply current I : 1.1 mA/channel max.

DD

receiver input stage with built-in Schmitt trigger to •ꢀ Low forward current I : 1.6 mA min

F

provide logic-compatible waveforms, eliminating the

need for additional waveshaping.

•ꢀ Speed: 5 MBd typ

•ꢀ Pulse width distortion (PWD): 200 ns max

An internal shield on the ACPL-M21L/021L/024L guar-

•ꢀ Propagation delay skew (tpsk): 220 ns max

antees common mode transient immunity of 25 kV/µs

•ꢀ Propagation delay (tp): 250 ns max

at a common mode voltage of 1000 V. The ACPL-x2xL

optocouplers' series operates from a 2.7 V to 5.5 V

supply with guaranteed AC and DC performance from an

extended temperature range of -40 °C to 105 °C. Glitches

free output upon power-up and power-down of optocou-

pler.

•ꢀ Common mode rejection: 25 kV/μs min at V = 1000 V

CM

•ꢀ Hysteresis: 0.2 mA typ

•ꢀ Temperature range: -40 °C to 105 °C

•ꢀ Safety and regulatory approvals

– UL 1577 recognized – 3750 Vrms for 1 minute for

ACPL-M21L/021L/024L

Functional Diagram

TRUTH TABLE

6

1

– CSA Approval

VDD

VO

Anode

(POSITIVE LOGIC)

– IEC/EN 60747-5-5, Approval for Reinforced Insulation

5

4

LED

ON

VO

HIGH

Applications

3

GND

Cathode

Shield

OFF

LOW

•ꢀ Low isolation of high speed logic systems

•ꢀ Computer peripheral interface

•ꢀ Microprocessor system interface

•ꢀ Ground loop elimination

ACPL-M21L

1

2

3

4

8

7

6

Anode1

V_DD

V₀₁

1

8

NC

VDD

VO

2

7

6

Cathode1

Anode

NC

Cathode2

Anode2

V₀₂

3

4

Cathode

NC

•ꢀ Pulse transformer replacement

•ꢀ High speed line receiver

5

GND

Shield

ACPL-021L

ACPL-024L

•ꢀ Power control systems

A 0.1 μF bypass capacitor must be connected between pins Vdd and GND

Ordering Information

ACPL-M21L, ACPL-024L and ACPL-021L are UL Recognized with 3750 V for 1 minute per UL1577.

rms

Option

UL1577

5000 V /

rms

Surface

Mount

Tape &

Reel

Part number

RoHS Compliant Package

1 Minute Rating IEC/EN 60747-5-5 Quantity

ACPL-M21L

-000E

-060E

-500E

-560E

-000E

-060E

-500E

-560E

-000E

-060E

-500E

-560E

SO-5

SO-8

X

100 per tube

X

100 per tube

1500 per reel

100 per tube

1500 per reel

100 per tube

1500 per reel

X

ACPL-024L

ACPL-021L

X

To order, choose a part number from the part number column and combine with the desired option from the option

column to form an order entry.

Example 1:

ACPL-M21L-500E to order product of SO-5 package in Tape and Reel packaging with RoHS compliant.

Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.

2

Package Outline Drawings

ACPL-M21L SO-5 Package

LAND PATTERN RECOMMENDATION

0.3

0.5

(0.0ꢀ8

(0.0ꢂ8

ꢂ.3

(0.058

MXXX

XXX

7.0 0.ꢀ

ꢃ.ꢃ 0.ꢂ

ꢃ.ꢃ

(0.ꢂ78

(0.ꢀ76 0.00ꢁ8

ꢁ.ꢀ7

(0.3ꢀ58

(0.ꢂ73 0.00ꢃ8

ꢂ.ꢁ

(0.07ꢀ8

0.ꢃ 0.05

(0.0ꢂ6 0.00ꢀ8

ꢀ.5

(0.ꢂ08

3.6 0.ꢂ1

(0.ꢂꢃꢀ 0.00ꢃ8

0.ꢂ0ꢀ 0.ꢂ0ꢀ

0.ꢂ5 0.0ꢀ5

(0.006 0.00ꢂ8

ꢀ.5 0.ꢂ

(0.00ꢃ 0.00ꢃ8

(0.09ꢁ 0.00ꢃ8

7° MAX.

0.7ꢂ

ꢂ.ꢀ7

BSC

MIN

(0.0ꢀꢁ8

(0.0508

MAX. LEAD COPLANARITY

= 0.ꢂ0ꢀ (0.00ꢃ8

Dimensions in millimeters (inches8.

Note: Foating Lead Protrusion is 0.ꢂ5 mm (6 mils8 max.

1 Maximum Mold ꢄash on each side is 0.ꢂ5 mm (0.0068.

3

ACPL-024L/021L SO-8 Package

LAND PATTERN RECOMMENDATION

1.9

(ꢀ.ꢀ75ꢁ

ꢀ.64

(ꢀ.ꢀ25ꢁ

8

1

7

2

6

5

4

5.994 ꢀ.2ꢀ3

(ꢀ.236 ꢀ.ꢀꢀ8ꢁ

XXXV

YWW

3.937 ꢀ.127

3.95

(ꢀ.156ꢁ

7.49

(ꢀ.295ꢁ

TYPE NUMBER

(LAST 3 DIGITSꢁ

DATE CODE

(ꢀ.155 ꢀ.ꢀꢀ5ꢁ

3

PIN ONE

ꢀ.4ꢀ6 ꢀ.ꢀ76

(ꢀ.ꢀ16 ꢀ.ꢀꢀ3ꢁ

1.27ꢀ

(ꢀ.ꢀ5ꢀꢁ

1.3

(ꢀ.5ꢁ

BSC

ꢀ.432

(ꢀ.ꢀ17ꢁ

7°

* 5.ꢀ8ꢀ ꢀ.127

(ꢀ.2ꢀꢀ ꢀ.ꢀꢀ5ꢁ

45° X

3.175 ꢀ.127

(ꢀ.125 ꢀ.ꢀꢀ5ꢁ

ꢀ ~ 7°

ꢀ.228 ꢀ.ꢀ25

(ꢀ.ꢀꢀ9 ꢀ.ꢀꢀ1ꢁ

1.524

(ꢀ.ꢀ6ꢀꢁ

ꢀ.2ꢀ3 ꢀ.1ꢀ2

(ꢀ.ꢀꢀ8 ꢀ.ꢀꢀ4ꢁ

*

Total package length (inclusive of mold ꢂashꢁ

5.2ꢀ7 ꢀ.254 (ꢀ.2ꢀ5 ꢀ.ꢀ1ꢀꢁ

ꢀ.3ꢀ5

(ꢀ.ꢀ12ꢁ

MIN.

Dimensions in Millimeters (Inchesꢁ.

Note: Floating lead protrusion is ꢀ.15 mm (6 milsꢁ max.

Lead coplanarity = ꢀ.1ꢀ mm (ꢀ.ꢀꢀ4 inchesꢁ max.

Option number 5ꢀꢀ not marked.

Solder Reﬂow Proﬁle

Recommended reﬂow condition as per JEDEC Standard, J-STD-020 (latest revision). Non-Halide Flux should be used.

Regulatory Information

The ACPL-M21L/024L/021L is approved by the following organizations:

UL

Approval under UL 1577, component recognition program up to V = 3750 V

for ACPL-M21L/024L/021L

ISO

RMS

CSA

Approval under CSA Component Acceptance Notice #5.

IEC/EN 60747-5-5 (Option 060 only)

4

Insulation and Safety Related Speciﬁcations

ACPL-024L

Parameter

Symbol

ACPL-M21L ACPL-021L Units Conditions

Minimum External Air Gap

(Clearance)

L(101)

5

4.9

mm

Measured from input terminals to output

terminals, shortest distance through air.

Minimum External

Tracking (Creepage)

L(102)

CTI

5

4.8

Measured from input terminals to output

terminals, shortest distance path along body.

Minimum Internal Plastic Gap

(Internal Clearance)

0.08

Through insulation distance conductor to

conductor, usually the straight line distance

thickness between the emitter and detector.

Tracking Resistance

(Comparative Tracking Index)

175

IIIa

175

IIIa

Volts DIN IEC 112/VDE 0303 Part 1

Isolation Group

Material Group (DIN VDE 0110, 1/89, Table 1)

IEC/EN 60747-5-5 Insulation Characteristics* (Option 060)

Characteristic

ACPL-M21L/

024L/021L

Description

Symbol

Unit

Installation classiﬁcation per DIN VDE 0110/39, Table 1

for rated mains voltage ≤ 150 V_rms

for rated mains voltage ≤ 300 V_rms

I – IV

I – III

I – II

for rated mains voltage ≤ 600 V_rms

for rated mains voltage ≤ 1000 V_rms

Climatic Classiﬁcation

55/105/21

Pollution Degree (DIN VDE 0110/39)

Maximum Working Insulation Voltage

2

V_IORM

V_PR

567

V_peak

Input to Output Test Voltage, Method b*

V_IORMx 1.875 = V_PR, 100% Production Test

with t_m= 1 sec, Partial discharge < 5 pC

1063

Input to Output Test Voltage, Method a*

V_IORMx 1.6 = V_PR, Type and Sample Test,

t_m= 10 sec, Partial discharge < 5 pC

V_PR

896

V_peak

Highest Allowable Overvoltage

(Transient Overvoltage t_ini= 60 sec)

V_IOTM

6000

V_peak

Safety-limiting values – maximum values allowed in

the event of a failure.

Case Temperature

T_S

150

°C

Input Current**

I_{S, INPUT}

P_{S, OUTPUT}

R_S

mA

mW

W

Output Power**

600

>10⁹

Insulation Resistance at TS, V_IO= 500 V

*

Refer to the optocoupler section of the Isolation and Control Components Designer’s Catalog, under Product Safety Regulations section,

(IEC/EN 60747-5-5) for a detailed description of Method a and Method b partial discharge test proﬁles.

** Refer to the following ﬁgure for dependence of P and I on ambient temperature.

S

5

Absolute Maximum Ratings

Parameter

Symbol

T_S

Min

-55

-40

Max

125

105

5

Units

°C

V

Condition

Storage Temperature

Operating Temperature

Reverse Input Voltage

Supply Voltage

T_A

V_R

V_DD

I_F

6.5

8

V

Average Forward Input Current

Peak Forward Input Current

mA

A

I_F(TRAN)

1

≤ 1 μs Pulse Width,

< 300 pulses per second

Output Current

I_O

10

mA

V

At max V_DD

Output Voltage

V_O

T_LS

-0.5

V_DD+0.5

Lead Solder Temperature

Solder Reﬂow Temperature Proﬁle

260 °C for 10 sec., 1.6 mm below seating plane

See Package Outline Drawings section

Recommended Operating Conditions

Parameter

Symbol

Min

-40

0

Max

105

250

6

Units

°C

Operating Temperature

Input Current, Low Level

Input Current, High Level

Power Supply Voltage

Forward Input Voltage

T_A

I_FL

μA

mA

V

I_FH

1.6*

2.7

V_DD

V_{F (OFF)}

5.5

0.8

V

*

The initial switching threshold is 1.6 mA or less. It is recommended that 2.2 mA be used to permit at least a 20% LED degradation guardband.

Electrical Speciﬁcations (DC)

Over recommended temperature (T = -40 °C to 105 °C) and supply voltage (2.7 V ≤ V ≤ 5.5 V). All typical speciﬁcations

A

DD

are at V = 2.7 V, T = 25 °C, unless otherwise speciﬁed.

DD

A

Parameter

Symbol

V_F

Channel

Min

Typ

1.5

11

Max

Units

Test Conditions

Input Forward Voltage

2.0

V

I_F= 2.2 mA (Figure 1 & 2)

I_R= 10 μA

Input Reverse

Breakdown Voltage

BV_R

8

Logic High Output Voltage

Logic Low Output Voltage

Input Threshold Current

V_OH

V_DD- 0.1

V_DD- 1.0

V

I_F= 2.2 mA, I_O= -20 μA

I_F= 2.2 mA, I_O= -3.2 mA

(Figure 3)

V_OL

0.001

0.15

0.1

0.4

V

I_F= 0 mA, I_O= 20 μA

I_F= 0 mA, I_O= 3.2 mA

(Figure 4)

I_TH

0.5

0.6

1.2

0.5

1.0

77

1.4

1.1

2.2

1.1

2.2

mA

Figure 5

Logic Low Output Supply

Current

I_DDL

Single

Dual

V_F= 0 V, V_DD= 5.5 V,

I_O= Open (Figure 6)

Logic High Output Supply

Current

I_DDH

Single

Dual

mA

I_F= 2.2 mA, V_DD= 5.5 V,

I_O= Open (Figure 7)

Input Capacitance

C_IN

pF

f = 1 MHz, V_F= 0 V

I_F= 2.2 mA

Input Diode Temperature

Coeﬃcient

ΔV_F/ΔT_A

-1.9

mV/°C

6

Switching Speciﬁcations (AC)

Over recommended temperature (T = -40° C to +105° C), supply voltage (2.7 V ≤ V ≤ 5.5 V). All typical speciﬁcations

A

DD

are at V = 2.7 V, T = 25° C

DD

A

Parameter

Symbol

Min

Typ

Max

Units

Test Conditions

Propagation Delay Time

to Logic Low Output ^[1]

t_PHL

130

250

ns

I_F=2.2mA, C_L=15pF (Figure 8, 12)

CMOS Signal Levels

Propagation Delay Time

to Logic High Output ^[1]

t_PLH

115

250

ns

I_F=2.2mA, C_L=15pF (Figure 9, 12)

CMOS Signal Levels

Pulse Width Distortion ^[2]

Propagation Delay Skew ^[3]

PWD

t_PSK

t_R

200

220

ns

CMOS Signal Levels

Output Rise Time

(10% – 90%)

11

40

I_F= 2.2 mA, C_L= 15 pF,

CMOS Signal Levels.

Output Fall Time

(90% – 10%)

t_F

ns

I_F= 2.2 mA, C_L= 15 pF,

CMOS Signal Levels.

Static Common Mode

Transient Immunity at

Logic High Output ^[4]

|CM_H|

25

kV/μs

V_CM= 1000 V, T_A= 25° C,

I_F= 2.2 mA, C_L= 15 pF, V_I= 5 V

(R_T= 1.6 kW) or V_I= 3.3 V

(R_T= 840 W)

CMOS Signal Levels

Figure 13

Static Common Mode

Transient Immunity at

Logic Low Output ^[5]

|CM_L|

40

kV/μs

V_CM= 1000 V, T_A= 25° C,

I_F= 0 mA, C_L= 15 pF, V_I= 0 V

(R_T= 1.6 kW) or (R_T= 840 W)

CMOS Signal Levels

Figure 13

propagation delay is measured from the 50% (V or I ) on the falling edge of the input pulse to the 50% V of the falling edge of the V signal.

in F DD O

propagation delay is measured from the 50% (V or I ) on the rising edge of the input pulse to the 50% level of the rising edge of the V signal

in

F

O

2. PWD is deﬁned as |t

- t

|

PHL PLH

3.

t

PSK

is equal to the magnitude of the worst case diﬀerence in t

and/or t that will be seen between units at any given temperature within the

PHL PLH

recommended operating conditions.

4. CM is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a high logic state.

H

5. CM is the maximum tolerable rate of rise of the common mode voltage to assure that the output will remain in a low logic state.

L

6. Use of a 0.1 μF bypass capacitor connected between Vdd and ground is recommended.

Package Characteristics

All typical at T = 25° C

A

Parameter

Symbol

Part Number

Min

Typ

Max

Units

Test Conditions

Input-Output Insulation

V_ISO

ACPL-M21L/

024L/021L

3750

V_rms

RH < 50% for 1 min. T_A= 25°

C

Input-Output Resistance

Input-Output Capacitance

R_I-O

C_I-O

10¹²

0.6

W

V_I-O= 500 V

pF

f = 1 MHz, T_A= 25° C

7

1.8

1.7

1.6

1.5

1.4

1.3

1.2

100

10

1

0.1

0.01

-40

-20

0

20

40

60

80

100

1.3

1.4

1.5

1.6

1.7

1.8

T_A- TEMPERATURE - °C

V_F- FORWARD VOLTAGE - V

Figure 1. Forward Voltage vs. Temperature

Figure 2. Forward Current vs Forward Voltage

0.25

0.2

0.15

0.1

0.05

0

7

I_O= -3.2 mA

6

5

4

3

2

1

0

V_DD= 3.3 V

V_F= 0 V

I_O= 3.2 mA

0

1

2

3

4

5

6

7

-40

-20

0

20

40

60

80

100

V_DD- SUPPLY VOLTAGE - V

T_A- TEMPERATURE - °C

Figure 3. Logic High Output voltage vs Supply Voltage

Figure 4. Logic Low Output Voltage vs. Temperature

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

0.9

0.8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

I_TH_3.3 V

I_TH_5.0 V

I_DDL@ 3.3 V

I_DDL@ 5.0 V

-40

-20

0

20

40

60

80

100

-40

-20

0

20

40

60

80

100

T_A- TEMPERATURE - °C

Figure 5. Input Threshold Current vs. Temperature

Figure 6. Logic Low Output Supply Current vs. Temperature

8

0.7

0.6

0.5

0.4

0.3

0.2

0.1

0

150

140

130

120

110

100

90

80

70

60

I_F= 1.6, 2.2 and 6 mA

I_{DDH_}3.3 V

I_{DDH_}5.0 V

V_DD= 2.7 V

50

-40

-20

0

20

40

60

80

100

-40

-20

0

20

40

60

80

100

T_A- TEMPERATURE - °C

Figure 7. Logic High Output Supply Current vs. Temperature

Figure 8. Propagation Delay, t_PHLvs. Temperature

150

140

130

I_F= 1.6 mA

I_F= 2.2 mA

120

110

100

90

80

I_F= 6.0 mA

70

60

V_DD= 2.7 V

-20

50

-40

0

20

40

60

80

100

T_A- TEMPERATURE - °C

Figure 9. Propagation Delay, t_PLHvs. Temperature

4

3.5

3

6

5

4

3

2

1

0

2.5

2

1.5

1

0.5

0

V_DD= 3.3 V

V_DD= 5.0 V

0

0.0001 0.0002 0.0003 0.0004 0.0005 0.0006 0.0007 0.0008

I_F- INPUT CURRENT - A

0

0.0001 0.0002 0.0003 0.0004 0.0005 0.0006 0.0007 0.0008

I_F- INPUT CURRENT - A

Figure 10. Output Voltage vs Input Current @ Vdd = 3.3 V

Figure 11. Output Voltage vs Input Current @ Vdd = 5 V

9

PULSE GEN

t_r= t_f= 11 ns

f = 1.0 MHz

50% DUTY

CYCLE

OUTPUT V_O

MONITORING

NODE

Vdd

ACPL-M21L

I_F(ON)

50% I_F(ON)

0 mA

I_F

6

5

4

1

3

INPUT I_F

*

t_PLH

t_PHL

C_L= 15 pF

INPUT

MONITORING

NODE

V_OH

Shield

50%

OUTPUT V_O

V_OL

Rm

* 0.1 μF BYPASS — SEE NOTE 6 above. ^[6]

PULSE GEN

t_r= t_f= 11 ns

f = 1.0 MHz

50% DUTY

OUTPUT V_O

MONITORING

NODE

OUTPUT V_O

PULSE GEN

MONITORING

NODE

t_r= t_f= 11 ns

f = 1.0 MHz

50% DUTY

CYCLE

Vdd

CYCLE

ACPL-024L

ACPL-021L

I_F

1

2

3

4

8

7

6

5

8

7

6

1

*

I_F

2

INPUT

MONITORING

NODE

INPUT

MONITORING

NODE

C_L= 15 pF

3

4

5

Rm

Shield

Figure 12. Circuit for t_PLH, t_PHL, t_r, t_f

10

ACPL-M21L, ACPL-021L, ACPL-024L:

V = 3.3 V: R = 510 W 1%, R = 330 W 1%

I

1

2

V = 5.0 V: R = 1 kW 1%, R = 600 W 1%

I

1

2

R = R + R R /R ≈ 1.5

T

1

2

1

2

R₁

I_F

V_I

V_DD

1

3

6

5

4

C

V_o

C = 0.1µF

R₂

GND₂

GND₁

ACPL-M21L

R₁

R₂

I_F

V_DD

V_o1

V_o2

1

2

3

4

8

7

6

5

1

2

3

4

8

7

6

5

V_I

GND₁

GND₂

V_I

R₁

R₂

I_F

V_I

V_o1

V_o2

C

R₂

R₁

GND₂

I_F

GND₂

ACPL-021L

ACPL-024L

Figure 13. Recommended printed circuit board layout and input current limiting resistor selection

For product information and a complete list of distributors, please go to our web site: www.avagotech.com

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AV02-3462EN - April 15, 2013