33186_11--Datasheet/数据表在线中文翻译

Document Number: MC33186

Rev. 7.0, 10/2011

Freescale Semiconductor

Technical Data

H-Bridge Driver

The 33186 is a monolithic H-Bridge ideal for fractional horsepower

DC-motor and bi-directional thrust solenoid control. The IC

33186

incorporates internal control logic, charge pump, gate drive, and low

R_DS(ON)MOSFET output circuitry. The 33186 is able to control

continuous inductive DC load currents up to 5.0 A. Output loads can

be pulse width modulated (PWM-ed) at frequencies up to 10 kHz.

H-BRIDGE MOTOR DRIVER

The 33186 is parametrically specified over a temperature range of

-40°C ≤ T_A≤ 125°C, 5.0 V ≤ V+ ≤ 28 V. The IC can also be operated

up to 40 V with de-rating of the specifications. The IC is available in a

surface mount power package with exposed pad for heat sinking.

Features

• Overtemperature, Short-Circuit Protection, and Overvoltage

Protection against Transients up to 40 V at VBAT Typical

• RDSon = 150 mΩ for each output Transistor at 25°C

• Continuous DC Load Current 5 A (TC < 100°C)

• Output Current Limitation at typ 6,5 A +/- 20%

• Short-Circuit Shutdown for Output Currents over 8 A

• Logic Inputs TTL/CMOS Compatible

• Operating Frequency up to 20 kHz

• Undervoltage Disable Function

• Diagnostic Output, 2 Disable Input

DH SUFFIX

VW SUFFIX (PB-FREE)

PLASTIC PACKAGE

98ASH70702A

20-PIN HSOP

ORDERING INFORMATION

Temperature

Device

Package

Range (T )

A

• Coding Input for Alternative Functions

• Stable Operation with an External Capacitance of Maximum 47 μF

at VBAT

MC33186DH1/R2

MC33186VW1/R2

-40°C to 125°C

20 HSOP

• Pb-Free Packaging Designated by Suffix Code VW

V

33186

PWR

5.0 V

CP

SF

VBAT

OUT1

MOTOR

MCU

or

IN1

IN2

DI1

DI2

DSP

OUT2

PGND

Figure 1. 33186 Simplified Block Diagram

*This document contains certain information on a product under development. Fre-

escale reserves the right to change or discontinue this product without notice

INTERNAL BLOCK DIAGRAM

CP

VBAT

VBAT VBAT

Internal 5V

Undervoltage

Charge-Pump

SF

Overcurrent

High-Side

Gate Control: 1-2

IN1

IN2

OUT1

OUT2

Logic

Gate Control: 3-4

DI1

DI2

Overcurrent

Current Limit

Low-Side

Overtemperature

Current limitation

COD

PGND

Figure 2. 33186 Simplified Internal Block Diagram

33186

Analog Integrated Circuit Device Data

Freescale Semiconductor

2

PIN CONNECTIONS

AGND

SF

1

2

NC

IN2

20

19

18

17

16

IN1

3

DI1

VBAT

OUT1

CP

4

VBAT

5

6

5

1

OUT2

7

14 OUT2

3

1

COD

PGND

8

DI2

9

12

11

PGND

10

Metal slug is connected to power ground

(Top View)

Figure 3. 33186 Pin Locations

Table 1. 33186 Pin Description

Name

Description

Power Ground. All the ground are connected together, they should be connected as short as

possible on the PCB.

9, 10, 11, 12

Metal slug

PGND

Analog ground. All the ground are connected together, they should be connected as short as

possible on the PCB.

1

AGND

Open drain output, active low. Is set according to the truth table. When a fault appears, SF changes

typically in less than 100 ms.

2

Output

Status flag (SF)

Voltage controlled inputs with hysteresis

3,13

Inputs IN1, IN2,

DI1, DI2, COD

18, 19

When not connected or connected to GND, a stored failure will be reset by change of the voltage-

level on DI1 or DI2.

8

COD

When connected to VCC, the disable Pin DI1 and DI2 are inactive. A stored failure will be reset by

change of the voltage-level on IN1 or IN2.

H-Bridge outputs with integrated free-wheeling diodes.

6, 7, 14, 15

OUT1, OUT2

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3

PIN CONNECTIONS

Table 1. 33186 Pin Description(continued)

Name

Description

The Pins 4 and 5 are internally connected. These Pins supply the left high side and the analog/logic

part of the device.

4, 5, 16

VBAT

The Pin 16 supplies the right high side and the charge pump.

The Pins 4, 5 and 16 should be connected together on the printed circuit board with connections as

short as possible.

Supervision and protection functions

a) Supply voltage supervision

The supply voltage is supervised. If it is below its specific threshold, the power stages are switched

in tristate and the status flag is switched low.

If the supply voltage is over the specific threshold again, the power stage switches independently

into normal operation, according to the input Pins and the status flag is reset.

b) Thermal supervision

In case of overtemperature, the power stages are switched in tristate independent of the inputs

signals and the status flag is switched low.

If the level changes from high to low on DI1 (IN1) or low to high on DI2 (IN2), the output stage

switches on again if the temperature is below the specified limit.The status-flag is reset to high level

(Pin names in brackets refer to coding Pin = VCC).

c) Supervision of overcurrent on high sides and low sides

In case of over-current detection, the power stages are switched in tristate independent of the inputs

signals and the status flag is set.

If the level changes from high to low on DI1 (IN1) or low to high on DI2 (IN2) the output stage

switches on again and the status flag is reset to high level (Pin names in brackets refer to coding Pin

= VCC).

The output stage switches into the mode defined by the inputs Pins provided, and/if the temperature

is below the specified limits.

d) Current limiting on low sides

The maximum current which can flow under normal operating conditions is limited to Imax = 6,5 A

+/- 20%. When the maximum current value is reached, the output stages are switched tristate for a

fixed time. According to the time constant the current decreases until the next switch on occurs. See

page 8 for schematics.

Charge Pump output Pin

17

CP

A filtering capacitor (up to 33 nF) can be connected between Pin 17 and Gnd. Device can operate

without external capacitor, although Pin 17 decoupling capacitor help in noise reduction and allows

the device to perform a maximum speed, timing and PWM frequency.

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4

ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS

ELECTRICAL CHARACTERISTICS

MAXIMUM RATINGS

Table 2. MAXIMUM RATINGS

All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or

permanent damage to the device.

Ratings

ELECTRICAL RATINGS

Symbol

Min

Typ

Max

Unit

Supply Voltage

V

Static Destruction Proof

Dynamic Destruction Proof t < 0,5 s

V_BAT

V_Bat

- 1.0

- 2.0

–

28

40

Logic Inputs (IN1, IN2, DI1, DI2, CODE)

Output Status - Flag SF

THERMAL RATINGS

U

- 0.5

–

7.0

V

U_SF

Junction Temperature

T_J

T_S

T_A

- 40

- 55

- 40

–

+150

+125

°C

Storage Temperature

Ambient Temperature

Thermal Resistance (with power applied on 2

power MOS)

–

Rth_JC

+1.5

K/W

Thermal Resistance (with power applied on 2

power MOS)

–

Rth_JC

T_PPRT

K/W

°C

Peak Package Reflow Temperature During

Note 2.

(2)

Reflow ⁽¹⁾

,

Notes

1. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits

may cause malfunction or permanent damage to the device.

2. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow

Temperature and Moisture Sensitivity Levels (MSL),

Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes and enter the core ID to view all orderable parts. (i.e.

MC33xxxD enter 33xxx), and review parametrics.

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ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 3. STATIC ELECTRICAL CHARACTERISTICS

Characteristic noted under conditions -40°C to +125 °C, VBAT from 5 V to 28 V, unless otherwise note. Typical values reflect

approximate mean at 25°C, nominal VCC, at time of device characterization.

Characteristics

Symbol

Min

Typ

Max

Unit

POWER SUPPLY

Operating Range:

Static

–

V_BAT

5.0

–

28

40

V

Dynamic (t < 500 ms)

Stand-by current

–

f = 0 to 10 KHz; IOUT = 0 A

I V_BAT

–

35

mA

VBAT-undervoltage switch-off (without load)

Switch-off Voltage

4.15

4.5

4.4

4.75

–

4.65

5.0

–

V

Switch-on Voltage

Hysteresis

150

mV

CHARGE-PUMP SUPPLY

VBAT = 4.15 V

VBAT < 40 V

V_CP- V_BAT

3.35

–

V

20

LOGIC INPUTS

Input High

VINH

3.4

–

1.4

–

V

Input Low

VINL

Input Hysteresis

U

I

0.7

- 200

1.0

- 80

V

Input Pull Up Current (IN1, IN2, DI1)

UIN = 0.0 V

–

μA

Input Pull Down Current (DI2,COD)⁽³⁾

UDI2 = 5.0 V

I_DI2

–

25

100

μA

POWER OUTPUTS: OUT1, OUT2

Switch on resistance:

R_{OUT - VBAT}; R_{OUT - GND}

VBAT = 5 to 28 V; CCP = 0 to 33 nF

–

300

7.8

mΩ

Switch-off Current during Current Limitation

on Low Sides

(I_OUT) MAX

5.2

6.5

A

Switch-off Time during Current Limitation on

Low Sides

t_A

15

12

20.5

16.5

26

21

μs

Blanking Time during Current Limitation on

Low Sides

t_B

Notes

3. In case of negative voltage at OUT2 (respectively OUT1) this maximum pull down current at DI2 (respectively COD) Pin can be

exceeded. This happens during recirculation when the current is flowing in the low side. See curve 22.

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ELECTRICAL CHARACTERISTICS

STATIC ELECTRICAL CHARACTERISTICS

Table 3. STATIC ELECTRICAL CHARACTERISTICS(continued)

Characteristic noted under conditions -40°C to +125 °C, VBAT from 5 V to 28 V, unless otherwise note. Typical values reflect

approximate mean at 25°C, nominal VCC, at time of device characterization.

Characteristics

Symbol

Min

Typ

Max

Unit

High Side Overcurrent Detection⁽⁴⁾

Low Side Overcurrent Detection

I_OCHS

I_OCLS

11

–

A

8.0

Leakage Current

Output Stage Switched off

–

100

2.0

5.0

μA

V

Free-Wheeling Diode Forward Voltage

IOU = 3.0 A

U_D

Free-Wheeling Diode Reverse

Recovery Time

t_RR

2.0

μs

IFM =1.0 A, di/dt = 4.0 A/µs

Switch-off Temperature

Hysteresis

160

20

–

190

30

°C

OUTPUT STATUS FLAG (OPEN DRAIN OUTPUT)

Output High (SF not set)

USF = 5.0 V

–

I_SF

–

10

μA

Output Low (SF set)

ISF = 300 µA

VSF

1.0

V

TIMING

PWM frequency

CCP = 33 nF

f

–

10

KHz

Maximum Switching Frequency During

Current Limitation

VBAT = 6....28 V.....C_CP= 33 nF

f

–

20

15

KHz

Output ON Delay

IN1....._>OUT1 or IN2....._>OUT2

t_DON

μs

Output OFF Delay

IN1....._>OUT1 or IN2....._>OUT2

t_DOFF

–

15

μs

Output Switching Time

CCP = 0 to 33 nF

OUTiH.....OUTiL, OUTiL.....OUTiH,

IOUT = 3.0 A

t_r, t_f

2.0

5.0

Disable Delay Time

DIi.....OUTi

t_DDIS

–

8.0

μs

Turn off in Case of Overcurrent or

Overtemperature

4.0

Power On Delay Time (CCP = 33 nF)⁽⁵⁾

–

1.0

5.0

ms

Notes

4. In case of overcurrent, the time when the current is greater than 7.8 A is lower than 30 μs, with a maximum frequency of 1 kHz.

5. This parameter corresponds to the time for CCP to reach its nominal value when VBAT is applied.

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ELECTRICAL CHARACTERISTICS

TRUTH TABLE

Table 4. TRUTH TABLE

Device State

Input Conditions

Status

SF⁽⁹⁾SF⁽¹⁰⁾

H

Outputs

DI1 ⁽⁸⁾

DI2 ⁽⁸⁾

H

IN1

H

L

IN2

L

OU1

H

L

OU2

L

1-Forward

L

H

L

2-Reverse

H

L

H

L

3-Free Wheeling Low

4-Free Wheeling High

5-Disable 1

L

H

L

H

L

H

X

Z

H

X

Z

H

Z

H

Z

H

X

L

X

H

6-Disable 2

L

H

Z

7-IN1 Disconnected

8-IN2 Disconnected

9-DI1 Disconnected

10-DI2 Disconnected

11-Current Limit.active

12-Undervoltage⁽⁶⁾

13-Overtemperature⁽⁷⁾

14-Overcurrent⁽⁷⁾

Notes

H

L

H

X

Z

X

H

Z

L

H

X

H

Z

X

L

X

H

Z

L

H

Z

H

L

H

Z

X

L

Z

X

L

Z

X

L

Z

6. In case of undervoltage, tristate and status-flag are reset automatically.

7. Whenever overcurrent or overtemperature is detected, the fault is stored (i.e.status-flag remains low). The tristate conditions and the

status-flag are reset via DI1 (IN1) or DI2 (IN2). Pin names in brackets refer to coding Pin (COD = VCC).

8. If COD = VCC then DI1 and DI2 are not active.

9. COD = nc or GND

10. COD = VCC

L = Low

H = High

X = High or Low

Z = High impedance (all output stage transistors are switched off).

33186

Analog Integrated Circuit Device Data

8

Freescale Semiconductor

ELECTRICAL CHARACTERISTICS

10k

47µF

Ccp=33nF

VCC

VBAT

Voltage

Regulator

Power Ground

VBAT

SF

CP

IN1

IN2

OUT1

M

DI1

DI2

OUT2

COD

GND

Power Ground

Figure 4. Typical Application

INn

50%

t_DON

t_DOFF

90%

OUn

10%

Figure 5. Output Delay Time

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9

ELECTRICAL CHARACTERISTICS

DIn

50%

t_DDIS

OUn

Z

10%

Figure 6. Disable Delay Time

90%

OUn

10%

tf

tr

Figure 7. Output Switching Time

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ELECTRICAL CHARACTERISTICS

Load-

current

Overturned

> 8A

TYP 6.5A

A

Control

signal

Status

Flag

Overcurrent detection

DetailA

t_A

t_B

6.5A

t_A= switch-off time in current limitation

t_B= current limitation blanking time

Figure 8. Current Limitation on Low Side

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ELECTRICAL CHARACTERISTICS

2,83

2,82

13,5

13

12,5

12

2,81

2,80

11,5

11

2,79

2,78

10,5

10

VBAT=12V

2,77

2,76

2,75

9,5

9

-50

-25

0

25

50

75

C)

100 125

-25

0

25

50

75

C)

100 125

T, TEMPERATURE (

°

T, TEMPERATURE (

°

Figure 9. Stand-by Current vs. Temperature

Figure 12. High Threshold Input Voltage vs.

Temperature

5,00

45

4,90

Tambient=25°C

without Ccp

40

4,80

4,70

Switch on Voltage

Switch off Voltage

35

30

25

20

15

10

4,60

4,50

4,40

4,30

4,20

5

0

-50

-25

0

25

50

75

C)

100 125

T, TEMPERATURE (

°

5

10

15

20

25

30

35

0

Figure 10. VBAT Undervoltage vs. Temperature

BATTERY VOLTAGE (V)

Figure 13. Vcp vs. Battery Voltage

1,89

1,88

200

VBAT=5V without Ccp

1,87

1,86

190

180

170

160

150

140

1,85

1,84

1,83

1,82

1,81

130

120

-50

-25

0

25

50

75

C)

100

125

T, TEMPERATURE (

°

110

-50

-25

0

25

50

75

C)

100 125

T, TEMPERATURE (

°

Figure 11. Low Threshold Input Voltage vs. Temperature

Figure 14. RDSON vs. Temperature

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ELECTRICAL CHARACTERISTICS

ta=20.5µs

7,20

7,10

7,00

6,90

6,80

6,70

6,60

Imotor (1A/div)

Out1 (5V/div)

6,50

6,40

6,30

Out2 (5V/div)

-50

-25

0

25

50

75

C)

100 125

T, TEMPERATURE (

°

Figure 18. Switch off Time

Figure 15. Switch off Current vs. Temperature

17,50

17,00

16,50

16,00

15,50

15,00

14,50

High side switch

Out1 (5V/div)

14,00

13,50

13,00

tr=3.7µs

-50

-25

0

25

50

75

C)

100 125

T, TEMPERATURE (

°

Figure 19. Output Switching Time: Tr

Figure 16. Overcurrent Detection vs. Temperature

I(out) max= 7A

Out1 (5V/div)

Imotor (1A/div)

tf=2.6µs

Figure 20. Output Switching Time: Tf

Figure 17. Current Limitation

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13

ELECTRICAL CHARACTERISTICS

in1 (1V/div)

I(5A/div)

Out1 (2V/div)

Iochs= 16A

tdoff=12.5µs

Figure 24. High Side Overcurrent High Side Detection

Figure 21. Output OFF Delay

3.2

3

2.8

2.6

tdon=5.8µs

2.4

2.2

2

1.8

1.6

1.4

1.2

1

Out1 (2V/div)

in1 (1V/div)

0.8

0.6

0.4

0.2

0

1

2

3

4

5

6

7

8

9

10 11 12 13 14 15 16 17 18 19 20

I OUT2 (A)

Figure 22. Output ON Delay

di2 (1V/div)

Note: Current through internal recirculation diode, @125°C in case of

negative voltage at OUT2

Figure 25. Maximum Di2 Input Current vs. Iout2, current

Out1 (2V/div)

tdiss=0.9µs

Figure 23. Disable Delay Time

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14

PACKAGING

SOLDERING

PACKAGING

SOLDERING

The 20 HSOP package is designed for enhanced thermal

performance. The particularity of this package is its copper

base plate on which the power die is soldered. The base plate

is soldered on a PCB to provide heat flow to the ambient and

also to provide a large thermal capacitance.

100

Of course, the more copper area on the PCB, the better

the power dissipation and transient behavior.

10

We characterized the 20 HSOP on a double side PCB.

The bottom side area of the copper is 7.8 cm². The top

surface is 2.7 cm², see Figure 26.

Rth (°C/W)

1

0,1

0,001

0,01

0,1

1

10

t, Time (s)

100

1000

10000

Figure 27. PHSOP20 Thermal Response

Figure 27 shows the thermal response with the device

soldered on to the test PCB described on Figure 26.

Top Side

Bottom Side

Figure 26. PCB Test Layout

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15

PACKAGING

PACKAGE DIMENSIONS

Important: Package dimensions are provided in package drawings. To find the most current package outline drawing, go to

www.freescale.com and perform a keyword search for the drawing’s document number.

Table 5. Package Drawing Information

Package

Suffix

Package Outline Drawing Number

20-PIN HSOP

DH/VW

98ASH70702A

Dimensions shown are provided for reference ONLY (For Layout and Design, refer to the Package Outline Drawing listed in

the following figures).

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PACKAGING

PACKAGE DIMENSIONS

VW (Pb-FREE) SUFFIX

20-PIN HSOP

98ASH70702A

ISSUE C

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PACKAGING

PACKAGE DIMENSIONS

VW (Pb-FREE) SUFFIX

20-PIN HSOP

98ASH70702A

ISSUE C

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Analog Integrated Circuit Device Data

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18

PACKAGING

PACKAGE DIMENSIONS

VW (Pb-FREE) SUFFIX

20-PIN HSOP

98ASH70702A

ISSUE C

33186

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19

ADDITIONAL DOCUMENTATION

THERMAL ADDENDUM (REV 2.0)

ADDITIONAL DOCUMENTATION

33186DH

33186VW

THERMAL ADDENDUM (REV 2.0)

Introduction

This thermal addendum is provided as a supplement to the MC33186 technical

datasheet. The addendum provides thermal performance information that may be

critical in the design and development of system applications. All electrical,

application, and packaging information is provided in the datasheet.

20-PIN

HSOP-EP

Package and Thermal Considerations

The MC33186 is offered in a 20 pin HSOP exposed pad, single die package.

There is a single heat source (P), a single junction temperature (T_J), and thermal

resistance (R_θJA).

T_J

.

=

R_θJA

P

DH SUFFIX

VW SUFFIX (Pb-FREE)

98ASH70273A

The stated values are solely for a thermal performance comparison of one

package to another in a standardized environment. This methodology is not

meant to and will not predict the performance of a package in an application-

specific environment. Stated values were obtained by measurement and

simulation according to the standards listed below.

20-PIN HSOP-EP

Note For package dimensions, refer to

the 33186 data sheet.

Standards

Table 6. Thermal Performance Comparison

1.0

Thermal Resistance

[°C/W]

29

0.2

1.0

(1), (2)

R_θJA

(2), (3)

R_θJB

9.0

69

0.2

(1), (4)

R_θJA

* All measurements

are in millimeters

(5)

R_θJC

2.0

Soldermast

openings

Notes:

1. Per JEDEC JESD51-2 at natural convection, still air condition.

2. 2s2p thermal test board per JEDEC JESD51-5 and

JESD51-7.

Thermal vias

connected to top

buried plane

20 Pin HSOP-EP

1.6 mm Pitch

16.0 mm x 11.0 mm Body

12.3 mm x 7.1 mm Exposed Pad

3. Per JEDEC JESD51-8, with the board temperature on the

center trace near the center lead.

4. Single layer thermal test board per JEDEC JESD51-3 and

JESD51-5.

Figure 28. Thermal Land Pattern for Direct Thermal

Attachment According to JESD51-5

5. Thermal resistance between the die junction and the exposed

pad surface; cold plate attached to the package bottom side,

remaining surfaces insulated.

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20

ADDITIONAL DOCUMENTATION

THERMAL ADDENDUM (REV 2.0)

A

AGND

SF

NC

1

20

19

18

17

16

15

14

13

12

11

IN2

2

IN1

DI1

3

VBAT

OUT1

COD

PGND

4

CP

5

VBAT

OUT2

DI2

6

7

8

9

PGND

10

33186DH1 Pin Connections

20-Pin HSOP-EP

1.6 mm Pitch

16.0 mm x 11.0 mm Body

12.3 x 7.1 mm exposed pad

Figure 29. Thermal Test Board

Device on Thermal Test Board

Table 7. Thermal Resistance Performance

A [mm²]

R_θJA[°C/W]

Material:

Single layer printed circuit board

FR4, 1.6 mm thickness

0

70

49

47

Cu traces, 0.07 mm thickness

300

Outline:

Area A:

80 mm x 100 mm board area,

including edge connector for

thermal testing

600

R_θJAis the thermal resistance between die junction and

ambient air.

Cu heat-spreading areas on board

surface

Ambient Conditions: Natural convection, still air

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21

ADDITIONAL DOCUMENTATION

THERMAL ADDENDUM (REV 2.0)

80

7⁷0⁰

60

50

40

3³0⁰

20

R

[°C/W]

JA

x

θ

1¹0⁰

0

300

600

0

300

600

2

Heat spreading area

^{Heat Spreading Area A [m}[^mm^]m²]

A

Figure 30. Device on Thermal Test Board R_θJA

100

10

R

x

θ

JA [°C/W]

1

0.1

1.00E-03 1.00E-02 1.00E-01 1.00E+00 1.00E+01 1.00E+02 1.00E+03 1.00E+04

Time [s]

Time[s]

Figure 31. Transient Thermal Resistance R_θJA

1 W Step Response, Device on Thermal Test Board Area A = 600 (mm²)

33186

Analog Integrated Circuit Device Data

Freescale Semiconductor

22

REVISION HISTORY

REVISION

DATE

DESCRIPTION OF CHANGES

•

Implemented Revision History page

Added Lead Free (Pb-Free) Part Number MC33186VW1

5.0

5/2006

•

Updated data sheet formal

6.0

7.0

10/2006

10/2011

Removed Peak Package Reflow Temperature During Reflow (solder reflow) parameter from

MAXIMUM RATINGS on page 5. Added note with instructions to obtain this information from

www.freescale.com.

•

Updated Package Dimensions according to the latest Freescale package specification

98ASH70702A_C

Updated to the current Freescale form and style.

33186

Analog Integrated Circuit Device Data

Freescale Semiconductor

23

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MC33186

Rev. 7.0

10/2011