07XSC200--Datasheet/数据表在线中文翻译

Document Number: MC07XSC200

Rev. 2.0, 9/2013

Freescale Semiconductor

Advance Information

Dual High Side Switch

(7.0 mOhm)

07XSC200

The 07XSC200 is one in a family of devices designed for low-voltage

lighting or factory automation applications. Its two low R_DS(ON)

MOSFETs (dual 7.0 m) can control two separate 55 W / 28 W bulbs,

and/or Xenon modules, and/or LEDs, and/or DC low voltage motors.

HIGH SIDE SWITCH

Programming, control and diagnostics are accomplished using a 16-bit

SPI interface. Its output with selectable slew rate improves

electromagnetic compatibility (EMC) behavior. Additionally, each

output has its own parallel input or SPI control for pulse-width

modulation (PWM) control if desired. The 07XSC200 allows the user to

program via the SPI, the fault current trip levels and duration of

acceptable inrush. The device has Fail-safe mode to provide fail-safe

functionality of the outputs in case of MCU damaged.

The 07XSC200 is packaged in a Pb-free power-enhanced 32 pins

SOIC package with exposed tab.

This device is powered by SMARTMOS technology.

EK SUFFIX PB-FREE

98ASA00368D

Features

32-PIN EXPOSED PAD SOIC

• Dual 7.0 m max high side switch (at 25 °C)

• Operating voltage range of 6.0 to 20 V with sleep current < 5.0 µA,

extended mode from 4.0 to 28 V

• 8.0 MHz 16-bit 3.3 V and 5.0 V SPI control and status reporting with

daisy chain capability

• PWM module using external clock or calibratable internal oscillator

with programmable outputs delay management

• Smart overcurrent shutdown compliant to huge inrush current,

severe short-circuit, overtemperature protections with time limited

auto-retry, and Fail-safe mode, in case of MCU damage

• Output OFF or ON OpenLoad detection compliant to bulbs or LEDs

and short to battery detection. Analog current feedback with

selectable ratio and board temperature feedback.

ORDERING INFORMATION

Temperature

Device

Package

Range (T )

A

MC07XSC200EK

-40 to 125 °C

32 SOIC

V_DD

V_PWR

V_DD

07XSC200

VPWR

VDD

I/O

FSB

WAKE

SI

GND

SO

HS1

HS0

SCLK

CSB

SI

SCLK

CSB

SO

MCU

LOAD

I/O

RSTB

CLOCK

IN0

I/O

LOAD

IN1

CSNS

FSI

A/D

GND

Figure 1. 07XSC200 Simplified Application Diagram

* This document contains certain information on a new product.

Specifications and information herein are subject to change without notice.

1

Internal Block Diagram

VDD

VPWR

Voltage Clamp

Internal

Regulator

Over/Undervoltage

Protections

V_DDFailure

Detection

Charge

Pump

POR

I

UP

V_REG

CSB

SCLK

Selectable Slew Rate

Gate Driver

I

DWN

Selectable Overcurrent

Detection

HS0

SO

SI

RSTB

WAKE

FSB

Severe Short-circuit

Detection

Logic

Short to VPWR

Detection

IN0

Overtemperature

Detection

IN1

CLOCK

OpenLoad

Detections

HS0

R

I

DWN

HS1

PWM

Module

Overtemperature

Prewarning

Calibratable

Oscillator

V_REG

Temperature

Feedback

Selectable Output

Current Recopy

Programmable

Watchdog

FSI

Analog MUX

V_DD

GND

CSNS

Figure 2. 07XSC200 Simplified Internal Block Diagram

07XSC200

Analog Integrated Circuit Device Data

2

Freescale Semiconductor

2

Pin Connections

2.1

Pinout Diagram

Transparent top View

1

32

31

30

29

28

27

26

25

24

23

22

21

20

19

18

17

WAKE

FSB

IN1

RSTB

CSB

SCLK

SI

2

3

4

IN0

5

CLOCK

CSNS

FSI

VDD

SO

6

7

GND

VPWR

HS1

33

VPWR

8

GND

HS0

9

10

11

12

13

14

15

16

Figure 3. 07XSC200 Pin Connection

2.2

Pin Definitions

A functional description of each pin can be found in the Functional Pin Description section beginning on page 22.

Table 1. 07XSC200 Pin Definitions

Number

Function

Pin Name

Formal Name

Definition

This input pin is used to initialize the device configuration and fault registers, as

well as place the device in a low current Sleep mode.

1

RSTB

Input

Reset (Active Low)

This input pin is connected to a chip select output of a master microcontroller

(MCU).

2

CSB

SCLK

SI

Chip Select (Active

Low)

This input pin is connected to the MCU providing the required bit shift clock for

SPI communication.

3

4

Input

Serial Clock

This is a command data input pin connected to the SPI Serial Data Output of

the MCU or to the SO pin of the previous device of a daisy chain of devices.

Input

Serial Input

This is an external voltage input pin used to supply power to the SPI circuit.

5

VDD

SO

Input

Digital Drain Voltage

(Power)

This output pin is connected to the SPI serial data input pin of the MCU or to the

SI pin of the next device of a daisy chain of devices.

6

Output

Ground

Serial Output

Those pins are the ground for the logic and analog circuitry of the device. These

pins must be shorted to board level.

7, 25

GND

Ground

07XSC200

Analog Integrated Circuit Device Data

Freescale Semiconductor

3

Table 1. 07XSC200 Pin Definitions (continued)

Number

Function

Pin Name

Formal Name

Definition

Pin 8 is a positive supply for quiet and accurate control. Pin 33 is a power supply

for the high current switch. These pins must be shorted at board level.

Connecting a heatsink to pin 33 guarantees optimal heat-evacuation

properties.

8, 33

VPWR

Power

Positive Power Supply

Protected 7.0 m high side power output pin to the load. Those pins must be

shorted at board level.

9 to 16

26

HS1

FSI

Output

Input

High Side Output

Fail-safe Input

The value of the resistance connected between this pin and ground determines

the state of the outputs after a watchdog time-out occurs.

This pin is used to output a current proportional to the designated HS0-1 output.

27

CSNS

CLOCK

Output

Input

Output Current

Monitoring

This pin is used to apply a reference clock used to control the outputs in PWM

mode through embedded PWM module.

28

Reference Clock

This input pin is used to directly control the output HS0.

This input pin is used to directly control the output HS1.

29

30

31

IN0

IN1

Input

Direct Input 0

Direct Input 1

This is an open drain configured output requiring an external pull-up resistor to

VDD for fault reporting.

FSB

Output

Fault Status (Active

Low)

This pin is used to input a Logic [1] signal so as to enable the watchdog timer

function.

32

WAKE

Input

Wake

07XSC200

Analog Integrated Circuit Device Data

4

Freescale Semiconductor

3

Electrical Characteristics

3.1

Maximum Ratings

Table 2. Maximum Ratings

All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent

damage to the device.

Ratings

Symbol

Value

Unit

ELECTRICAL RATINGS

V_PWRSupply Voltage Range

• Load Dump at 25 °C (400 ms)

• Maximum Operating Voltage

• Reverse Battery

V_PWR(SS)

V

41

28

-18

V

_DDSupply Voltage Range

V_DD

-0.3 to 5.5

V

(4)

Input/Output Voltage

-0.3 to V_DD+0.3

WAKE Input Clamp Current

CSNS Input Clamp Current

I_CL(WAKE)

I_CL(CSNS)

V_HS[0:1]

2.5

mA

V

HS [0:1] Voltage

• Positive

41

• Negative

-24

Output Current per Channel

I_HS[0:1]

A

• Nominal Continuous Current⁽¹⁾

• Short-circuit Transient Current

26

116

-26

• Reverse Continuous Current⁽¹⁾

High Side Breakdown Voltage

V

_PWR- V_HS

E_CL[0:1]

47

V

mJ

V

HS[0,1] Output Clamp Energy using single pulse method⁽²⁾

100

ESD Voltage⁽³⁾

• Human Body Model (HBM) for HS[0:1], VPWR and GND

• Human Body Model (HBM) for other pins

• Charge Device Model (CDM)

Corner Pins (1, 27, 28, 57)

V_ESD1

V_ESD2

±8000

±2000

V_ESD3

V_ESD4

±750

±500

All Other Pins

Notes

1. Continuous high side output current rating so long as maximum junction temperature is not exceeded. Calculation of maximum output

current using board thermal resistance is required.

2. Active clamp energy using single-pulse method (L = 2.0 mH, R_L= 0 , V_PWR= 14 V, T_J= 150 C initial).

3. ESD testing is performed in accordance with the Human Body Model (HBM) (C_ZAP= 100 pF, R_ZAP= 1500 ), the Machine Model (MM)

(C_ZAP= 200 pF, R_ZAP= 0 ), and the Charge Device Model (CDM), Robotic (C_ZAP= 4.0 pF).

4. Input / Output pins are: IN[0:1], CLOCK, RSTB, FSI, CSNS, SI, SCLK, CSB, SO, FSB

07XSC200

Analog Integrated Circuit Device Data

Freescale Semiconductor

5

Table 2. Maximum Ratings (continued)

All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent

damage to the device.

Ratings

Symbol

Value

Unit

THERMAL RATINGS

Operating Temperature

• Ambient

C

T_A

T_J

-40 to 125

-40 to 150

• Junction ⁽⁵⁾

Storage Temperature

THERMAL RESISTANCE

T_STG

-55 to 150

C

Thermal Resistance

• Junction to Case

C/W

R_JC

R_JA

4.0

35

• Junction to Ambient⁽⁶⁾

Peak Pin Reflow Temperature During Solder Mounting⁽⁷⁾

T_SOLDER

260

C

Notes

5. To achieve high reliability over 10 years of continuous operation, the device's continuous operating junction temperature should not

exceed 125C.

6. Device mounted on a 2s2p test board per JEDEC JESD51-2. 20 °C/W of R_θJAcan be reached in a real application case (4 layers board).

7. Pin soldering temperature limit is for 40 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may

cause malfunction or permanent damage to the device.

07XSC200

Analog Integrated Circuit Device Data

6

Freescale Semiconductor

3.2

Static Electrical Characteristics

Table 3. Static Electrical Characteristics

Characteristics noted under conditions 6.0 V V_PWR 20 V, 3.0 V  V_DD 5.5 V, -40 C  T_A 125 C, GND = 0 V, unless

otherwise noted. Typical values noted reflect the approximate parameter means at T_A= 25 °C under nominal conditions, unless

otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

POWER INPUTS

Battery Supply Voltage Range

• Fully Operational

V

PWR

6.0

4.0

–

20

28

• Extended mode⁽⁸⁾

Battery Clamp Voltage⁽⁹⁾

V

41

47

53

V

PWR(CLAMP)

V

Operating Supply Current

I

mA

PWR

PWR(ON)

• Outputs commanded ON, HS[0:1] open, IN[0:1] > V

–

6.5

20

IH

V_PWRSupply Current

I

mA

PWR(SBY)

• Outputs commanded OFF, OFF Open-load Detection Disabled, HS[0:1]

shorted to the ground with V_DD= 5.5 V

–

6.5

7.5

WAKE > V_IHor RSTB > V_IHand IN[0:1] < V_IL

Sleep State Supply Current

I

A

PWR(SLEEP)

V

_PWR= 12 V, RSTB = WAKE = CLOCK = IN[0:1] < V_IL, HS[0:1] shorted to

ground

• T_A= 25 °C

–

1.0

–

5.0

30

• T_A= 85 °C

V

Supply Voltage

V

3.0

–

5.5

V

DD

DD(ON)

Supply Current at V = 5.5 V

I

mA

DD

DD(ON)

• No SPI Communication

–

1.6

5.0

2.2

–

• 8.0 MHz SPI Communication⁽¹⁰⁾

V

Sleep State Current at V = 5.5 V

I

–

5.0

36

A

V

DD

DD(SLEEP)

Overvoltage Shutdown Threshold

Overvoltage Shutdown Hysteresis

Undervoltage Shutdown Threshold⁽¹¹⁾

V

28

32

0.8

3.9

–

PWR(OV)

V

0.2

3.3

0.5

3.4

2.2

1.5

4.3

0.9

4.5

2.8

V

PWR(OVHYS)

V

PWR(UV)

V

and V_DDPower on Reset Threshold

V

PWR

SUPPLY(POR)

PWR(UV)

V

Recovery Undervoltage Threshold

Supply Failure Threshold (for V

V

4.1

2.5

PWR(UV)_UP

V

> V

)

V

DD

PWR

PWR(UV)

DD(FAIL)

Notes

8. In extended mode, the functionality is guaranteed but not the electrical parameters. From 4.0 to 6.0 V voltage range, the device is only

protected with the thermal shutdown detection.

9. Measured with the outputs open.

10. Typical value guaranteed per design.

11. Output will automatically recover with time limited auto-retry to instructed state when V

voltage is restored to normal as long as the

PWR

V

degradation level did not go below the undervoltage power-ON reset threshold. This applies to all internal device logic that is

PWR

supplied by V

and assumes that the external V

supply is within specification.

DD

PWR

07XSC200

Analog Integrated Circuit Device Data

Freescale Semiconductor

7

Table 3. Static Electrical Characteristics (continued)

Characteristics noted under conditions 6.0 V V_PWR 20 V, 3.0 V  V_DD 5.5 V, -40 C  T_A 125 C, GND = 0 V, unless

otherwise noted. Typical values noted reflect the approximate parameter means at T_A= 25 °C under nominal conditions, unless

otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

OUTPUTS HS0 TO HS1

HS[0,1] Output Drain-to-Source ON Resistance (I = 5.0 A, T = 25 C)

R

m

HS

A

DS_01(ON)

• V

= 4.5 V

= 6.0 V

= 10 V

= 13 V

–

25.2

11.2

7.0

PWR

7.0

HS[0,1] Output Drain-to-Source ON Resistance (I = 5.0 A, T = 150 C)

R

m

HS

A

DS_01(ON)

• V

= 4.5 V

= 6.0 V

= 10 V

= 13 V

–

42.8

19.1

11.9

PWR

HS[0,1] Output Source-to-Drain ON Resistance (I = -5.0 A, V

HS

-18 V)⁽¹²⁾

R

PWR=

SD_01(ON)

• T = 25 C

–

10.5

14

A

• T = 150 C

A

HS[0,1] Maximum Severe Short-circuit Impedance Detection⁽¹³⁾

21

47

75

m

SHORT_01

HS[0,1] Output Overcurrent Detection Levels (6.0 V < V

• 28W bit = 0

< 20 V)

A

HS[0:1]

OCHI1_0

OCHI2_0

OC1_0

89.9

67

114.8

83.7

61.2

53.2

44.6

36.4

26.6

18.4

14.2

9.3

139.8

100.4

74.4

64.4

54

48

OC2_0

42

OC3_0

35.2

28.8

21

OC4_0

44

OCLO4_0

OCLO3_0

OCLO2_0

OCLO1_0

32.1

23.5

17.1

11.2

13.3

11.3

7.4

• 28W bit = 1

OCHI1_1

OCHI2_1

OC1_1

44.9

33.5

24

57.4

41.9

30.6

26.5

22.3

18.2

7.6

69.9

50.2

37.2

32.1

27

OC2_1

20.8

17.6

14.4

6.1

OC3_1

OC4_1

22

OCLO4_1

OCLO3_1

OCLO2_1

OCLO1_1

9.0

6.1

7.6

9.0

6.1

7.6

9.0

2.7

4.9

7.0

Notes

12. Source-Drain ON Resistance (Reverse Drain-to-Source ON Resistance) with negative polarity V

13. Short-circuit impedance calculated from HS[0:1] to GND pins. Value guaranteed per design.

.

PWR

07XSC200

Analog Integrated Circuit Device Data

8

Freescale Semiconductor

Table 3. Static Electrical Characteristics (continued)

Characteristics noted under conditions 6.0 V V_PWR 20 V, 3.0 V  V_DD 5.5 V, -40 C  T_A 125 C, GND = 0 V, unless

otherwise noted. Typical values noted reflect the approximate parameter means at T_A= 25 °C under nominal conditions, unless

otherwise noted.

Characteristic

OUTPUTS HS0 TO HS1 (CONTINUED)

Symbol

Min

Typ

Max

Unit

HS[0,1] Current Sense Ratio (6.0 V <

• 28W bit = 0

< 20 V, CSNS < 5.0 V)⁽¹⁴⁾

–

VHS[0:1]

• CSNS_ratio bit = 0

• CSNS_ratio bit = 1

• 28W bit = 1

C

–

1/10700

1/63600

–

SR0_0

SR1_0

• CSNS_ratio bit = 0

• CSNS_ratio bit = 1

C

–

1/5350

–

SR0_1

1/31800

SR1_1

HS[0,1] Current Sense Ratio (C

) Accuracy 

C

%

SR0

SR0_0_ACC

(6.0 V < V

< 20 V) with 28W bit = 0

HS[0:1]

25 and 125 C

• I_HS[0:1]= 12.5 A

-15

-22

-27

-30

–

15

22

27

30

• I_HS[0:1]= 5.0 A

• I_HS[0:1]= 3.0 A

• I_HS[0:1]= 1.5 A

-40 C

-20

-27

-30

-40

–

20

27

30

40

• I_HS[0:1]= 12.5 A

• I_HS[0:1]= 5.0 A

• I_HS[0:1]= 3.0 A

• I_HS[0:1]= 1.5 A

HS[0,1] Current Recopy Accuracy with one calibration point 

C

%

SR0_0_ACC

(CAL)

(6.0 V < V

< 20 V) with 28W bit = 0⁽¹⁵⁾

HS[0:1]

• I_HS[0:1]= 5.0 A

-5.0

–

5.0

HS[0,1] Current Sense Ratio (C

) Accuracy 

SR0

SR0_1_ACC

(6.0 V < V

< 20 V) with 28W bit = 1

HS[0:1]

25 and 125 C

• I_HS[0:1]= 3.0 A

• I_HS[0:1]= 1.5 A

-40 C

-25

-30

–

25

30

-30

-40

–

30

40

• I_HS[0:1]= 3.0 A

• I_HS[0:1]= 1.5 A

HS[0,1] Current Recopy Accuracy with one calibration point 

C

%

SR0_1_ACC

(CAL)

(6.0 V < V

< 20 V) with 28W bit = 1⁽¹⁵⁾

HS[0:1]

• I_HS[0:1]= 3.0 A

-5.0

–

5.0

HS[0,1] C

(6.0 V < V

Current Recopy Temperature Drift 

(C

)/(T)

%/C

SR0

SR0_0

< 20 V) with 28W bit = 0⁽¹⁶⁾

HS[0:1]

• I_HS[0:1]= 5.0 A

0.04

Notes

14. Current sense ratio = I_CSNS/ I_HS[0:1]

15. Based on statistical analysis. It is not production tested.

16. Based on statistical data: delta(C

production tested.

)/delta(T)={(measured I_CSNSat T₁- measured I_CSNSat T₂) / measured I_CSNSat room} / {T₁-T₂}. No

SR0

07XSC200

Analog Integrated Circuit Device Data

Freescale Semiconductor

9

Table 3. Static Electrical Characteristics (continued)

Characteristics noted under conditions 6.0 V V_PWR 20 V, 3.0 V  V_DD 5.5 V, -40 C  T_A 125 C, GND = 0 V, unless

otherwise noted. Typical values noted reflect the approximate parameter means at T_A= 25 °C under nominal conditions, unless

otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

OUTPUTS HS0 TO HS1 (CONTINUED)

HS[0,1] Current Sense Ratio (C ) Accuracy 

C

%

SR1

SR1_0_ACC

(6.0 V < V

< 20 V) with 28W bit = 0

HS[0:1]

25 and 125 C

• I_HS[0:1]= 12.5 A

• I_HS[0:1]= 75 A

-40 C

-20

-17

–

20

17

-28

-25

–

28

25

• I_HS[0:1]= 12.5 A

• I_HS[0:1]= 75 A

HS[0,1] Current Recopy Accuracy with one calibration point 

C

%

SR1_0_ACC

(CAL)

(6.0 V < V

< 20 V) with 28W bit = 0⁽¹⁷⁾

HS[0:1]

• I_HS[0:1]= 12.5 A

-5.0

–

5.0

HS[0,1] Current Sense Ratio (C

) Accuracy 

SR1

SR1_1_ACC

(6.0V < V

< 20V) with 28W bit = 1

HS[0:1]

25 and 125 C

• I_HS[0:1]= 12.5 A

• I_HS[0:1]= 37.5 A

-40 C

-20

-17

–

20

17

-28

-25

–

28

25

• I_HS[0:1]= 12.5 A

• I_HS[0:1]= 75 A

HS[0,1] Current Recopy Accuracy with one calibration point 

C

%

V

SR1_1_ACC

(CAL)

(6.0 V < V

< 20 V) with 28W bit = 1⁽¹⁷⁾

HS[0:1]

• I_HS[0:1]= 12.5 A

-5.0

–

5.0

Current Sense Clamp Voltage

V

CL(CSNS)

• CSNS Open; I

5.0 A with C

ratio

V_DD+0.25

V_DD+1.0

HS[0:1] =

SR0

OFF OpenLoad Detection Source Current⁽¹⁸⁾

I

30

2.0

80

–

100

4.0

A

V

OLD(OFF)

OFF OpenLoad Fault Detection Voltage Threshold

ON OpenLoad Fault Detection Current Threshold

ON OpenLoad Fault Detection Current Threshold with LED

V

3.0

330

OLD(THRES)

I

660

mA

OLD(ON)

OLD(ON_LED)

I

• V

= V

- 0.75 V

2.5

5.0

10

HS[0:1]

PWR

Output Short to V

Detection Voltage Threshold

V

PWR

OSD(THRES)

V_CL

• Output programmed OFF

V

-1.2 V

-0.8 V

-0.4

PWR

Output Negative Clamp Voltage

• 0.5 A < I

< 5.0 A, Output programmed OFF

-22

155

–

-16

HS[0:1]

Output Overtemperature Shutdown for 4.5 V < V_PWR< 28 V

T

175

195

C

SD

Notes

17. Based on statistical analysis. It is not production tested.

18. Output OFF OpenLoad Detection Current is the current required to flow through the load for the purpose of detecting the existence of an

open-load condition when the specific output is commanded OFF. Pull-up current is measured for V_HS= V_OLD(THRES)

07XSC200

Analog Integrated Circuit Device Data

10

Freescale Semiconductor

Table 3. Static Electrical Characteristics (continued)

Characteristics noted under conditions 6.0 V V_PWR 20 V, 3.0 V  V_DD 5.5 V, -40 C  T_A 125 C, GND = 0 V, unless

otherwise noted. Typical values noted reflect the approximate parameter means at T_A= 25 °C under nominal conditions, unless

otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

CONTROL INTERFACE

Input Logic High Voltage⁽¹⁹⁾

Input Logic Low Voltage⁽¹⁹⁾

V

2.0

-0.3

5.0

–

V_DD+0.3

0.8

V

IH

V

IL

Input Logic Pull-down Current (SCLK, SI)⁽²²⁾

Input Logic Pull-up Current (CSB) ⁽²³⁾

SO, FSB Tri-state Capacitance⁽²⁰⁾

I

–

20

A

pF

k

pF

V

DWN

I

–

20

UP

C

–

20

SO

Input Logic Pull-down Resistor (RSTB, WAKE, CLOCk and IN[0:1])

Input Capacitance⁽²⁰⁾

R

125

–

250

4.0

500

12

DWN

CIN

Wake Input Clamp Voltage⁽²¹⁾

V

CL(WAKE)

• I

< 2.5 mA

18

25

–

32

-0.3

–

CL(WAKE)

Wake Input Forward Voltage

• I = -2.5 mA

V

F(WAKE)

-2.0

CL(WAKE)

SO High-state Output Voltage

• I = 1.0 mA

V

SOH

V

-0.4

–

OH

DD

SO and FSB Low-state Output Voltage

V

SOL

• I = -1.0 mA

OL

–

0.4

2.0

SO, CSNS and FSB Tri-state Leakage Current

I

A

k

SO(LEAK)

RFS

• CSB = V_IHand 0 V < V_SO< V_DD, or FSB = 5.5 V, or CSNS = 0.0 V

-2.0

0.0

FSI External Pull-down Resistance⁽²⁴⁾

• Watchdog Disabled

–

0.0

1.0

–

• Watchdog Enabled

10

Infinite

Notes

19. Upper and lower logic threshold voltage range applies to SI, CSB, SCLK, FSB, IN[0:1], CLOCK and WAKE input signals. The WAKE and

RSTB signals may be supplied by a derived voltage referenced to V

.

PWR

20. Input capacitance of SI, CSB, SCLK, RSTB, IN[0:1], CLOCK and WAKE. This parameter is guaranteed by process monitoring but is not

production tested.

21. The current must be limited by a series resistance when using voltages > 7.0 V.

22. Pull-down current is with V_SI> 1.0 V and V_SCLK> 1.0 V.

23. Pull-up current is with V_CSB< 2.0 V. CSB has an active internal pull-up to V

.

DD

24. In Fail-safe HS[0:1] depends respectively on IN[0:1]. FSI has an active internal pull-up to V

~ 3.0 V.

REG

07XSC200

Analog Integrated Circuit Device Data

Freescale Semiconductor

11

3.3

Dynamic Electrical Characteristics

Table 4. Dynamic Electrical Characteristics

Characteristics noted under conditions 6.0 V V_PWR 20 V, 3.0 V  V_DD 5.5 V, -40 C  T_A 125 C, GND = 0 V unless

otherwise noted. Typical values noted reflect the approximate parameter means at T_A= 25 °C under nominal conditions unless

otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

POWER OUTPUT TIMING HS0 TO HS1

Output Rising Medium Slew Rate (medium speed slew rate / SR[1:0] = 00)⁽²⁵⁾

• V = 14 V

SR

V/s

s

R_00

0.15

0.07

0.3

0.15

0.6

0.3

1.2

0.6

0.3

1.2

PWR

Output Rising Slow Slew Rate (low speed slew rate / SR[1:0] = 01)⁽²⁵⁾

• V = 14 V

R_01

PWR

Output Falling Fast Slew Rate (high speed slew rate / SR[1:0] = 10)⁽²⁵⁾

• V = 14 V

R_10

PWR

Output Falling Medium Slew Rate (medium speed slew rate / SR[1:0] = 00)⁽²⁵⁾

• V = 14 V

F_00

0.15

0.07

0.3

PWR

Output Falling Slow Slew Rate (low speed slew rate / SR[1:0] = 01)⁽²⁵⁾

• V = 14 V

F_01

0.15

0.6

PWR

Output Rising Fast Slew Rate (high speed slew rate / SR[1:0] = 10)⁽²⁵⁾

• V = 14 V

F_10

PWR

HS[0:1] Outputs Turn-ON and OFF Delay Times^(26)(27)

= 14 V for medium speed slew rate (SR[1:0] = 00)

t

DLY_12

V

PWR

• t_DLY(ON)

• t_DLY(OFF)

80

40

130

90

180

140

Driver Output Matching Slew Rate (SR /SR )

SR

R

F

• V

= 14 V @ 25 °C and for medium speed slew rate (SR[1:0] = 00)

0.8

0

1.0

50

1.2

PWR

HS[0:1] Driver Output Matching Time (t

- t

)

t

s

DLY(ON) DLY(OFF)

RF_01

• V

= 14 V, f

= 240 Hz, PWM duty cycle = 50%, @ 25 °C for

PWM

100

PWR

medium speed slew rate (SR[1:0] = 00)

Notes

25. Rise and Fall Slew Rates measured across a 5.0 resistive load at high side output = 30% to 70% (see Figure 4, page 19).

26. Turn-ON delay time measured from rising edge of any signal (IN[0:1] and CSB) that would turn the output ON to V = V

/ 2

PWR

HS[0:1]

with R = 5.0  resistive load.

L

27. Turn-OFF delay time measured from falling edge of any signal (IN[0:1] and CSB) that would turn the output OFF to V

= V

/ 2

PWR

HS[0:1]

with R = 5.0  resistive load.

L

07XSC200

Analog Integrated Circuit Device Data

12

Freescale Semiconductor

Table 4. Dynamic Electrical Characteristics (continued)

Characteristics noted under conditions 6.0 V V_PWR 20 V, 3.0 V  V_DD 5.5 V, -40 C  T_A 125 C, GND = 0 V unless

otherwise noted. Typical values noted reflect the approximate parameter means at T_A= 25 °C under nominal conditions unless

otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

POWER OUTPUT TIMING HS0 TO HS1 (continued)

Fault Detection Blanking Time⁽²⁸⁾

Output Shutdown Delay Time⁽²⁹⁾

CSNS Valid Time⁽³⁰⁾

t_FAULT

t_DETECT

t_CNSVAL

t_WDTO

1.0

–

5.0

7.0

70

20

30

s

–

100

400

195

s

Watchdog Time-out⁽³¹⁾

217

105

310

150

ms

ON OpenLoad Fault Cyclic Detection Time with LED

T

OLD(LED)

Notes

28. Time necessary to report the fault to FSB pin.

29. Time necessary to switch-off the output in case of OT or OC or SC or UV fault detection (from negative edge of FSB pin to HS voltage =

50% of V_PWR

30. Time necessary for CSNS to be within ±5% of the targeted value (from HS voltage = 50% of V_PWRto ±5% of the targeted CSNS value).

31. For FSI open, the Watchdog time-out delay measured from the rising edge of RSTB, to HS[0,1] output state depend on the corresponding

input command.

07XSC200

Analog Integrated Circuit Device Data

Freescale Semiconductor

13

Table 4. Dynamic Electrical Characteristics (continued)

Characteristics noted under conditions 6.0 V V_PWR 20 V, 3.0 V  V_DD 5.5 V, -40 C  T_A 125 C, GND = 0 V unless

otherwise noted. Typical values noted reflect the approximate parameter means at T_A= 25 °C under nominal conditions unless

otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

POWER OUTPUT TIMING HS0 TO HS1 (continued)

HS[0,1] Output Overcurrent Time Step for 28W bit = 0

OC[1:0] = 00 (slow by default)

ms

t_{OC1_00}

t_{OC2_00}

t_{OC3_00}

t_{OC4_00}

t_{OC5_00}

t_{OC6_00}

t_{OC7_00}

4.40

1.62

2.10

2.88

4.58

10.16

73.2

6.30

2.32

8.02

3.00

3.90

4.12

5.36

6.56

8.54

14.52

104.6

18.88

134.0

OC[1:0]=01 (fast)

t_{OC1_01}

t_{OC2_01}

t_{OC3_01}

t_{OC4_01}

t_{OC5_01}

t_{OC6_01}

t_{OC7_01}

1.10

0.40

0.52

0.72

1.14

2.54

18.2

1.57

0.58

0.75

1.03

1.64

3.63

26.1

2.00

0.75

0.98

1.34

2.13

4.72

34.0

OC[1:0]=10 (medium)

t_{OC1_10}

t_{OC2_10}

t_{OC3_10}

t_{OC4_10}

t_{OC5_10}

t_{OC6_10}

t_{OC7_10}

2.20

0.81

1.05

1.44

2.29

5.08

36.6

3.15

1.16

1.50

2.06

3.28

7.26

52.3

4.01

1.50

1.95

2.68

4.27

9.44

68.0

OC[1:0]=11 (very slow)

t_{OC1_11}

t_{OC2_11}

t_{OC3_11}

t_{OC4_11}

t_{OC5_11}

t_{OC6_11}

t_{OC7_11}

8.8

3.2

12.6

4.6

16.4

21.4

7.8

4.2

6.0

5.7

8.2

10.7

17.0

37.7

272.0

9.1

13.1

29.0

209.2

20.3

146.4

07XSC200

Analog Integrated Circuit Device Data

14

Freescale Semiconductor

Table 4. Dynamic Electrical Characteristics (continued)

Characteristics noted under conditions 6.0 V V_PWR 20 V, 3.0 V  V_DD 5.5 V, -40 C  T_A 125 C, GND = 0 V unless

otherwise noted. Typical values noted reflect the approximate parameter means at T_A= 25 °C under nominal conditions unless

otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

POWER OUTPUT TIMING HS0 TO HS1 (continued)

HS[0,1] Output Overcurrent Time Step for 28W bit = 1

OC[1:0] = 00 (slow by default)

ms

t_{OC1_00}

t_{OC2_00}

t_{OC3_00}

t_{OC4_00}

t_{OC5_00}

t_{OC6_00}

t_{OC7_00}

3.4

1.1

1.4

2.0

3.4

8.5

62.4

4.9

1.6

6.4

2.1

2.8

2.9

3.8

4.9

6.4

12.2

89.2

15.9

116.0

OC[1:0] = 01 (fast)

t_{OC1_01}

t_{OC2_01}

t_{OC3_01}

t_{OC4_01}

t_{OC5_01}

t_{OC6_01}

t_{OC7_01}

0.86

0.28

0.36

0.51

0.78

2.14

20.2

1.24

0.40

0.52

0.74

1.12

3.06

22.2

1.61

0.52

0.68

0.96

1.46

3.98

28.9

OC[1:0] = 10 (medium)

t_{OC1_10}

t_{OC2_10}

t_{OC3_10}

t_{OC4_10}

t_{OC5_10}

t_{OC6_10}

t_{OC7_10}

1.7

0.5

0.7

1.0

1.7

4.2

31.2

2.5

0.8

1.0

1.5

2.5

6.1

44.6

3.3

1.0

1.3

2.0

3.3

6.0

58.0

OC[1:0] = 11 (very slow)

t_{OC1_11}

t_{OC2_11}

t_{OC3_11}

t_{OC4_11}

t_{OC5_11}

t_{OC6_11}

t_{OC7_11}

6.8

2.2

9.8

3.2

12.8

16.7

5.5

2.9

4.2

4.0

5.8

7.6

6.8

9.8

12.8

31.8

232.0

17.0

124.8

24.4

178.4

07XSC200

Analog Integrated Circuit Device Data

Freescale Semiconductor

15

Table 4. Dynamic Electrical Characteristics (continued)

Characteristics noted under conditions 6.0 V V_PWR 20 V, 3.0 V  V_DD 5.5 V, -40 C  T_A 125 C, GND = 0 V unless

otherwise noted. Typical values noted reflect the approximate parameter means at T_A= 25 °C under nominal conditions unless

otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

POWER OUTPUT TIMING HS0 TO HS1 (continued)

HS[0,1] Bulb Cooling Time Step for 28W bit = 0

CB[1:0] = 00 or 11 (medium)

ms

t_{BC1_00}

t_{BC2_00}

t_{BC3_00}

t_{BC4_00}

t_{BC5_00}

t_{BC6_00}

242

126

140

158

181

211

347

181

200

226

259

302

452

236

260

294

337

393

CB[1:0] = 01 (fast)

t_{BC1_01}

t_{BC2_01}

t_{BC3_01}

t_{BC4_01}

t_{BC5_01}

t_{BC6_01}

121

63

173

90

226

118

130

147

169

197

70

100

113

129

151

79

90

105

CB[1:0] = 10 (slow)

t_{BC1_10}

t_{BC2_10}

t_{BC3_10}

t_{BC4_10}

t_{BC5_10}

t_{BC6_10}

484

252

280

316

362

422

694

362

400

452

518

604

1904

472

520

588

674

786

HS[0,1] for 28W bit = 1

CB[1:0] = 00 or 11 (medium)

t_{BC1_00}

t_{BC2_00}

t_{BC3_00}

t_{BC4_00}

t_{BC5_00}

t_{BC6_00}

291

156

178

208

251

314

417

224

255

298

359

449

542

292

332

388

467

584

CB[1:0] = 01 (fast)

t_{BC1_01}

t_{BC2_01}

t_{BC3_01}

t_{BC4_01}

t_{BC5_01}

t_{BC6_01}

146

78

209

112

127

145

180

324

272

146

166

189

234

422

88

101

126

226

CB[1:0] = 10 (slow)

t_{BC1_10}

t_{BC2_10}

t_{BC3_10}

t_{BC4_10}

t_{BC5_10}

t_{BC6_10}

583

312

357

417

501

628

834

448

510

596

717

898

1085

582

665

775

933

1170

07XSC200

Analog Integrated Circuit Device Data

16

Freescale Semiconductor

Table 4. Dynamic Electrical Characteristics (continued)

Characteristics noted under conditions 6.0 V V_PWR 20 V, 3.0 V  V_DD 5.5 V, -40 C  T_A 125 C, GND = 0 V unless

otherwise noted. Typical values noted reflect the approximate parameter means at T_A= 25 °C under nominal conditions unless

otherwise noted.

Characteristic

Symbol

Min

Typ

Max

Unit

PWM MODULE TIMING

Input PWM Clock Range on CLOCK

f

7.68

1.0

–

2.0

–

30.72

4.0

400

781

+10

156

26

kHz

Hz

%

CLOCK

Input PWM Clock Low Frequency Detection Range on CLOCK⁽³³⁾

Input PWM Clock High Frequency Detection Range on CLOCK⁽³³⁾

Output PWM Frequency Range using external clock on CLOCK⁽³²⁾

Output PWM Frequency Accuracy using Calibrated Oscillator⁽³²⁾

Default Output PWM Frequency using Internal Oscillator

CSB Calibration Low Minimum Time Detection Range

CSB Calibration Low Maximum Tine Detection Range

Output PWM Duty Cycle Range for f_PWM= 1.0 kHz for high speed slew rate⁽³³⁾

Output PWM Duty Cycle Range for f_PWM= 400 Hz⁽³³⁾

Output PWM Duty Cycle Range for f_PWM= 200 Hz⁽³³⁾

INPUT TIMING

f

CLOCK(LOW)

f

100

31.25

-10

84

CLOCK(HIGH)

f

–

PWM

A

–

FPWM(CAL)

f

120

20

200

–

Hz

s

PWM(0)

t_CSB(MIN)

14

t_CSB(MAX)

R_PWM_1k

R_PWM_400

R_PWM_200

140

10

260

94

s

%

6.0

–

98

%

5.0

–

98

%

Direct Input Toggle Time-out

t

175

105

250

150

325

195

ms

IN

AUTO-RETRY TIMING

Auto-retry Period

t

AUTO

TEMPERATURE ON THE GND FLAG

Thermal Prewarning Detection⁽³⁴⁾

T

110

1.15

-3.5

125

1.20

-3.7

140

1.25

-3.9

°C

V

OTWAR

Analog Temperature Feedback at T_A= 25 °C with R_CSNS= 2.5 k

Analog Temperature Feedback Derating with R_CSNS= 2.5 k⁽³⁵⁾

Notes

T_FEED

DT_FEED

mV/°C

32. Clock Fail detector available for PWM_en bit is set to logic [1] and CLOCK_sel is set to logic [0].

33. The PWM ratio is measured at V_HS= 50% of V_PWRand for the default SR value. It is possible to put the device fully-on (PWM duty cycle

100%) and fully-off (duty cycle 0%). For values outside this range, a calibration is needed between the PWM duty cycle programming

and the PWM on the output with R = 5.0  resistive load.

L

34. Typical value guaranteed per design.

35. Value guaranteed per statistical analysis.

07XSC200

Analog Integrated Circuit Device Data

Freescale Semiconductor

17

Table 4. Dynamic Electrical Characteristics (continued)

Characteristics noted under conditions 6.0 V V_PWR 20 V, 3.0 V  V_DD 5.5 V, -40 C  T_A 125 C, GND = 0 V unless

otherwise noted. Typical values noted reflect the approximate parameter means at T_A= 25 °C under nominal conditions unless

otherwise noted.

Characteristic

SPI INTERFACE CHARACTERISTICS⁽³⁶⁾

Symbol

Min

Typ

Max

Unit

Maximum Frequency of SPI Operation

f

–

10

–

8.0

–

MHz

s

ns

SPI

Required Low State Duration for RSTB⁽³⁷⁾

t

WRSTB

t_CSB

Rising Edge of CSB to Falling Edge of CSB (Required Setup Time)⁽³⁸⁾

Rising Edge of RSTB to Falling Edge of CSB (Required Setup Time)⁽³⁸⁾

Falling Edge of CSB to Rising Edge of SCLK (Required Setup Time)⁽³⁸⁾

Required High State Duration of SCLK (Required Setup Time)⁽³⁸⁾

Required Low State Duration of SCLK (Required Setup Time)⁽³⁸⁾

Falling Edge of SCLK to Rising Edge of CSB (Required Setup Time)⁽³⁸⁾

SI to Falling Edge of SCLK (Required Setup Time)⁽³⁹⁾

Falling Edge of SCLK to SI (Required Setup Time)⁽³⁹⁾

SO Rise Time

1.0

5.0

500

50

60

37

49

t_ENBL

–

t

–

LEAD

t

–

WSCLKh

t

–

WSCLKl

t

–

LAG

t

–

SI(SU)

t

–

SI(HOLD)

t

RSO

• C = 80 pF

L

–

13

SO Fall Time

t

ns

FSO

• C = 80 pF

L

–

13

SI, CSB, SCLK, Incoming Signal Rise Time⁽³⁹⁾

t

–

13

60

ns

RSI

FSI

SI, CSB, SCLK, Incoming Signal Fall Time⁽³⁹⁾

t

Time from Falling Edge of CSB to SO Low-impedance⁽⁴⁰⁾

Time from Rising Edge of CSB to SO High-impedance⁽⁴¹⁾

t

SO(EN)

t

SO(DIS)

Notes

36. Parameters guaranteed by design.

37. RSTB low duration measured with outputs enabled and going to OFF or disabled condition.

38. Maximum setup time required for the 07XSC200 is the minimum guaranteed time needed from the microcontroller.

39. Rise and Fall time of incoming SI, CSB, and SCLK signals suggested for design consideration to prevent the occurrence of double

pulsing.

40. Time required for output status data to be available for use at SO. 1.0 kon pull-up on CSB.

41. Time required for output status data to be terminated at SO. 1.0 kon pull-up on CSB.

07XSC200

Analog Integrated Circuit Device Data

18

Freescale Semiconductor

3.4

Timing Diagrams

IN[0:1]

High logic level

Low logic level

Time

or

CSB

High logic level

Low logic level

V_HS[0:1]

V

PWR

R

PWM

50%V

PWR

t_DLY(OFF)

t_DLY(ON)

V_HS[0:1]

70% V

30% V

PWR

SR_F

SR_R

PWR

Time

Figure 4. Output Slew Rate and Time Delays

I

OCH1

I

OCH2

OC1

OC2

Load

Current

I

OC3

OC4

I

OCLO4

OCLO3

OCLO2

I

OCLO1

Time

t

OC3

OC1

t

OC5

t

OC6

OC7

t

OC4

OC2

Figure 5. Overcurrent Shutdown Protection

07XSC200

Analog Integrated Circuit Device Data

Freescale Semiconductor

19

I

OCH1

OCH2

I

OC1

OC2

I

OC3

OC4

OCLO4

OCLO3

I

OCLO2

OCLO1

Previous OFF duration

(t_OFF

)

t

B

C5

B

C3

C1

t

B

C6

t

B

C4

t

B

C2

Figure 6. Bulb Cooling Management

VIH

RSTB

10% V_DD

0.2 VDD

VIL

^Tt^wRSTB

TCSB

t

ENBL

CSB

t

WRSTB

TENBL

VIH

90% V

0.7VDD

DD

VIH

CSB

0.7VDD

10% V_DD

VIL

t

RSI

TrSI

TtwSCLKh

WSCLKH

Tlead

t

LEAD

t

Tlag

LAG

VIH

90% V_DD

0.7VDD

SCLK

10% V_DD

0.2VDD

VIL

t

TSIsu

SI(SU)

_Tt_wSCLKl

WSCLKl

TfSI

t

FSI

t

TSI(hold)

SI(HOLD)

VIH

900.7%VVDD

DD

Don’t Care

Valid

Don’t Care

Valid

SI

0.2VDD

10% V_DD

VIH

VIL

Figure 7. Input Timing Switching Characteristics

07XSC200

Analog Integrated Circuit Device Data

20

Freescale Semiconductor

t

FSI

RSI

TrSI

TfSI

VOH

90% V

3.5V_DD

50%

SCLK

1.0V

10% V_DD

VOL

t_SO(EN)

TdlyLH

0.210V%DDV_DD

VOH

90% V

0.7 VD_DD_D

SO

VOL

Low-to-High

Low to High

TrSO

t_RSO

T

t_V^V_A^A_L^LI_I^D_D

TfSO

t_FSO

SO

VOH

90% V

0.7 VDD_DD

High to Low

High-to-Low

0.2VDD

10% V_DD

VOL

TdlyHL

t_SO(DIS)

Figure 8. SCLK Waveform and Valid SO Data Delay Time

07XSC200

Analog Integrated Circuit Device Data

Freescale Semiconductor

21

4

Functional Description

4.1

Introduction

The 07XSC200 is one in a family of devices designed for low-voltage lighting applications. Its two low R_DS(ON)MOSFETs (dual

7.0 m) can control two separate 55 W / 28 W bulbs and/or Xenon modules.

Programming, control and diagnostics are accomplished using a 16-bit SPI interface. Its output with selectable slew rate

improves electromagnetic compatibility (EMC) behavior. Additionally, each output has its own parallel input or SPI control for

pulse-width modulation (PWM) control if desired. The 07XSC200 allows the user to program via the SPI, the fault current trip

levels and duration of acceptable lamp inrush. The device has fail-safe mode to provide fail-safe functionality of the outputs in

case of MCU damaged.

4.2

Functional Pin Description

4.2.1 Output Current Monitoring (CSNS)

The Current Sense pin provides a current proportional to the designated HS0:HS1 output or a voltage proportional to the

temperature on the GND flag. That current is fed into a ground-referenced resistor (2.5 k typical) and its voltage is monitored

by an MCU's A/D. The output type is selected via the SPI. This pin can be tri-stated through the SPI.

4.2.2 Direct Inputs (IN0, IN1)

Each IN input wakes the device. The IN0:IN1 high side input pins are also used to directly control HS0:HS1 high side output

pins. If the outputs are controlled by PWM module, the external PWM clock is applied to IN0 pin. These pins are to be driven with

CMOS levels, and they have a passive internal pull-down, R_DWN

.

4.2.3 Fault Status (FSB)

This pin is an open drain configured output requiring an external pull-up resistor to V_DDfor fault reporting. If a device fault

condition is detected, this pin is active LOW. Specific device diagnostics and faults are reported via the SPI SO pin.

4.2.4 WAKE (WAKE)

The WAKE input wakes the device. An internal clamp protects this pin from high damaging voltages with a series resistor (10 k

typ). This input has a passive internal pull-down, R_DWN

.

4.2.5 PWM Clock (CLOCK)

The clock input wakes the device. The PWM frequency and timing are generated from clock input by the PWM module. The clock

input frequency is the selectable factor 2⁷= 128. This input has a passive internal pull-down, R_DWN

.

4.2.6 RESET (RSTB)

The RESET input wakes the device. This is used to initialize the device configuration and fault registers, as well as place the

device in a low-current sleep mode. The pin also starts the watchdog timer when transitioning from logic [0] to logic [1]. This pin

has a passive internal pull-down, R_DWN

.

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4.2.7 Chip Select (CSB)

The CSB pin enables communication with the master microcontroller (MCU). When this pin is in a logic [0] state, the device is

capable of transferring information to, and receiving information from, the MCU. The 07XSC200 latches in data from the Input

Shift registers to the addressed registers on the rising edge of CSB. The device transfers status information from the power output

to the Shift register on the falling edge of CSB. The SO output driver is enabled when CSB is logic [0]. CSB should transition from

a logic [1] to a logic [0] state only when SCLK is a logic [0]. CSB has an active internal pull-up from V_DD, I_UP

.

4.2.8 Serial Clock (SCLK)

The SCLK pin clocks the internal shift registers of the 07XSC200 device. The serial input (SI) pin accepts data into the input shift

register on the falling edge of the SCLK signal while the serial output (SO) pin shifts data information out of the SO line driver on

the rising edge of the SCLK signal. It is important the SCLK pin be in a logic low state whenever CSB makes any transition. For

this reason, it is recommended the SCLK pin be in a logic [0] whenever the device is not accessed (CSB logic [1] state). SCLK

has an active internal pull-down. When CSB is logic [1], signals at the SCLK and SI pins are ignored and SO is tri-stated (high-

impedance) (see Figure 10, page 26). SCLK input has an active internal pull-down, I_DWN

.

4.2.9 Serial Input (SI)

This is a serial interface (SI) command data input pin. Each SI bit is read on the falling edge of SCLK. A 16-bit stream of serial

data is required on the SI pin, starting with D15 (MSB) to D0 (LSB). The internal registers of the 07XSC200 are configured and

controlled using a 5-bit addressing scheme described in Table 9, page 36. Register addressing and configuration are described

in Tables 10, page 36. SI input has an active internal pull-down, I_DWN

.

4.2.10 Digital Drain Voltage (VDD)

This pin is an external voltage input pin used to supply power to the SPI circuit. In the event V_DDis lost (V_DDFailure), the device

goes to Fail-safe mode.

4.2.11 Ground (GND)

These pins are the ground for the device.

4.2.12 Positive Power Supply (VPWR)

This pin connects to the positive power supply and is the source of operational power for the device. The VPWR contact is the

backside surface mount tab of the package.

4.2.13 Serial Output (SO)

The SO data pin is a tri-stateable output from the shift register. The SO pin remains in a high impedance state until the CSB pin

is put into a logic [0] state. The SO data is capable of reporting the status of the output, the device configuration, the state of the

key inputs, etc. The SO pin changes state on the rising edge of SCLK and reads out on the falling edge of SCLK. SO reporting

descriptions are provided in Table 22, page 42.

4.2.14 High Side Outputs (HS0, HS1)

Protected 7.0 m high side power outputs to the load.

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4.2.15 Fail-safe Input (FSI)

This pin incorporates an active internal pull-up current source from internal supply (V_REG). This enables the watchdog time-out

feature.

When the FSI pin is opened, the watchdog circuit is enabled. After a watchdog time-out occurs, the output states depends on

IN[0:1].

When the FSI pin is connected to GND, the watchdog circuit is disabled. The output states depends on IN[0:1] in case of V_DD

Failure condition, in case V_DDfailure detection is activated (VDD_FAIL_en bit sets to logic [1]).

4.3

Functional Internal Block Description

07XSC200 - Functional Block Diagram

Power Supply

MCU Interface & Output Control

SPI Interface

Self-protected

High Side

Switches

HS0 - HS1

Parallel Control Inputs

MCU

Interface

PWM Controller

Supply

MCU Interface & Output Control

Self-protected High Side Switches

Figure 9. Functional Block Diagram

4.3.1 Power Supply

The 07XSC200 is designed to operate from 4.0 to 28 V on the VPWR pin. Characteristics are provided from 6.0 to 20 V for the

device. The VPWR pin supplies power to internal regulator, analog, and logic circuit blocks. The V_DDsupply is used for Serial

Peripheral Interface (SPI) communication to configure and diagnose the device. This IC architecture provides a low quiescent

current sleep mode. Applying V_PWRand V_DDto the device will place the device in the Normal mode. The device will transit to

Fail-safe mode in case of failures on the SPI or/and on V_DDvoltage.

4.3.2 High Side Switches: HS0–HS1

These pins are the high side outputs controlling lamps located for the front of vehicle, such as 65 W/55 W bulbs and Xenon-HID

modules. N-channel MOSFETs with 7.0 m R_DS(ON)are self-protected and present extended diagnostics to detect bulb outage

and a short-circuit fault condition. The HS output is actively clamped during turn off of inductive loads and inductive battery line.

When driving DC motor or solenoid loads demand multiple switching, an external recirculation device must be used to maintain

the device in its Safe Operating Area.

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4.3.3 MCU Interface and Output Control

In Normal mode, each bulb is controlled directly from the MCU through the SPI. A pulse width modulation control module allows

improvement of lamp lifetime with bulb power regulation (PWM frequency range from 100 to 400 Hz) and addressing the dimming

application (day running light). An analog feedback output provides a current proportional to the load current or the temperature

of the board. The SPI is used to configure and to read the diagnostic status (faults) of high side outputs. The reported fault

conditions are: OpenLoad, short-circuit to battery, short-circuit to ground (overcurrent and severe short-circuit), thermal

shutdown, and under/overvoltage.

In Fail-safe mode, each lamp is controlled with dedicated parallel input pins. The device is configured in default mode.

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5

Functional Device Operation

5.1

SPI Protocol Description

The SPI interface has a full duplex, three-wire synchronous data transfer with four I/O lines associated with it: Serial Input (SI),

Serial Output (SO), Serial Clock (SCLK), and Chip Select (CSB).

The SI/SO pins of the 07XSC200 follow a first-in first-out (D15 to D0) protocol, with both input and output words transferring the

most significant bit (MSB) first. All inputs are compatible with 5.0 or 3.3 V CMOS logic levels.

CS

CSB

SCLK

SI

D15

D14

D13

D12 D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

SO

OD15 OD14 OD13 OD12 OD11 OD10 OD9 OD8 OD7 OD6 OD5 OD4 OD3 OD2 OD1 OD0

Notes 1. RSTB is a logic [1] state during the above operation.

2. D15 D0 relate to the most recent ordered entry of data into the device.

:

NOTES: 1. RSTB is in a logic H state during the above operation.

3. OD15:OD0 relate to the first 16 bits of ordered fault and status data out of the device.

device.

2. DO, D1, D2, ... , and D15 relate to the most recent ordered entry of program data into the LUX IC

Figure 10. Single 16-Bit Word SPI Communication

5.2

Operational Modes

The 07XSC200 has four operating modes: Sleep, Normal, Fail-safe and Fault. Table 5 and Figure 12 summarize details

contained in succeeding paragraphs.

The Figure 11 describes an internal signal called IN_ON[x] depending on IN[x] input.

t_IN

IN[x]

IN_ON[x]

Figure 11. IN_ON[x] internal signal

The 07XSC200 transits to operating modes according to the following signals:

• wake-up = RSTB or WAKE or IN_ON[0] or IN_ON[1] or CLOCK_ON,

• fail = (V_DDFailure and VDD_FAIL_en) or (Watchdog time-out and FSI input not shorted to ground),

• fault = OC[0:1] or OT[0:1] or SC[0:1] or UV or (OV and OV_dis).

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Table 5. 07XSC200 Operating Modes

Mode wake-up fail fault

Comments

Device is in Sleep mode. All outputs are OFF.

Sleep

0

1

x

Device is currently in Normal mode. Watchdog

is active if enabled.

Normal

0

Device is currently in Fail-safe mode due to

watchdog time-out or V_DDFailure conditions.

The output states are defined with the RFS

resistor connected to FSI.

Fail-safe

Fault

1

0

1

Device is currently in fault mode. The faulted

output(s) is (are) OFF. The safe auto-retry

circuitry is active to turn-on again the output(s).

1

X

x = Don’t care.

(fail=0) and (wake-up=1) and (fault=0)

Sleep

(wake-up=0)

(wake-up=1) and

(fail=1)

and (fault=0)

(wake-up=0)

(wake-up=1)

and (fault=1)

(wake-up=0)

(fail=1) and

(wake-up=1)

and (fault=1)

(fail=0) and

(wake-up=1)

and (fault=1)

Fault

Normal

(fail=0) and

(wake-up=1)

and (fault=0)

(fail=1) and

(wake-up=1)

and (fault=0)

Fail-safe

(fail=0) and (wake-up=1) and (fault=0)

(fail=1) and (wake-up=1) and (fault=0)

Figure 12. Operating Modes

5.2.1 Sleep Mode

The 07XSC200 is in Sleep mode when:

• V_PWRand V_DDare within the normal voltage range,

• wake-up = 0,

• fail = X,

• fault = X.

This is the Default mode of the device after first applying battery voltage (V_PWR) prior to any I/O transitions. This is also the state

of the device when the WAKE and RSTB, CLOCK_ON and IN_ON[0:1] are logic [0]. In the Sleep mode, the output and all unused

internal circuitry, such as the internal regulator, are off to minimize draw current. In addition, all SPI-configurable features of the

device are as if set to logic [0].

In the event of an external V_PWRsupply disconnect, an unexpected current consumption may sink on the VDD supply pin (In

Sleep state). This current leakage is about 70 mA instead of 5.0 µA and it may impact the device reliability. The device recovers

its normal operational mode once V_PWRis reconnected.

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To avoid this unexpected current leakage on the VDD supply pin, maintain the device in Normal mode with RSTB pin set to

logic[1]. This will allow diagnosis of the battery disconnection event through UV fault reporting in SPI. Then, apply 0 V on the VDD

supply pin to switch the device to Sleep state.

5.2.2 Normal Mode

The 07XSC200 is in Normal mode when:

• V_PWRand V_DDare within the normal voltage range,

• wake-up = 1,

• fail = 0,

• fault = 0.

In this mode, the NM bit is set to lfault_contrologic [1] and the outputs HS[0:1] are under control, as defined by the hson signal:

hson[x] = (((IN[x] and DIR_dis[x]) or On bit[x]) and PWM_en) or (On bit [x] and Duty_cycle[x] and PWM_en).

In this mode and also in Fail-safe, the fault condition reset depends on fault_control signal, as defined below:

fault_control[x] = ((IN_ON[x] and DIR_dis[x]) and PWM_en) or (On bit [x]).

5.2.2.1

Programmable PWM Module

The outputs HS[0:1] are controlled by the programmable PWM module if PWM_en and On bits are set to logic [1].

The clock frequency from CLOCK input pin or from the internal clock is the factor 2⁷(128) of the output PWM frequency

(CLOCK_sel bit). The outputs HS[0:1] can be controlled in the range of 5.0 to 98% with a resolution of 7 bits of duty cycle

(Table 6). The state of other IN pin is ignored.

Table 6. Output PWM Resolution

On bit

Duty cycle

X

Output state

OFF

0

1

0000000

PWM (1/128 duty cycle)

1

0000001

0000010

n

PWM (2/128 duty cycle)

PWM (3/128 duty cycle)

PWM ((n+1)/128 duty cycle)

fully ON

1111111

The timing includes seven programmable PWM switching delay (number of PWM clock rising edges) to improve overall EMC

behavior of the light module (Table 7).

Table 7. Output PWM Switching Delay

Delay bits

Output delay

000

001

010

011

100

101

110

111

no delay

16 PWM clock periods

32 PWM clock periods

48 PWM clock periods

64 PWM clock periods

80 PWM clock periods

96 PWM clock periods

112 PWM clock periods

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The clock frequency from CLOCK is permanently monitored in order to report a clock failure in case the frequency is out a

specified frequency range (from f_CLOCK(LOW)to f_CLOCK(HIGH)). In case of clock failure, no PWM feature is provided, the On bit

defines the outputs state and the CLOCK_fail bit reports [1].

5.2.2.2

Calibratable Internal Clock

The internal clock can vary as much as 30 percent corresponding to typical f_PWM(0)output switching period.

Using the existing SPI inputs and the precision timing reference already available to the MCU, the 07XSC200 allows clock period

setting within 10 percent of accuracy. Calibrating the internal clock is initiated by defined word to CALR register. The calibration

pulse is provided by the MCU. The pulse is sent on the CSB pin after the SPI word is launched. At the moment, the CSB pin

transitions from logic [1] to [0] until from logic [0] to [1] determines the period of internal clock with a multiplicative factor of 128.

CS

SI

SI command

ignored

CALR

Internal

clock duration

In case a negative CSB pulse is outside a predefined time range (from t_CSB(MIN)to t_CSB(MAX)), the calibration event will be ignored

and the internal clock will be unaltered or reset to the default value (f_PWM(0)), if this was not calibrated before.

The calibratable clock is used, instead of the clock from CLOCK input, when CLOCK_sel is set to [1].

5.2.3 Fail-safe Mode

The 07XSC200 is in Fail-safe mode when:

• V_PWRis within the normal voltage range,

• wake-up = 1,

• fail = 1,

• fault = 0.

5.2.3.1

Watchdog

If the FSI input is not grounded, the watchdog time-out detection is active when either the WAKE or IN_ON[0:1] or RSTB input

pin transitions from logic [0] to logic [1]. The WAKE input is capable of being pulled up to V_PWRwith a series of limiting resistance

limiting the internal clamp current according to the specification.

The watchdog time-out is a multiple of an internal oscillator. As long as the WD bit (D15) of an incoming SPI message is toggled

within the minimum watchdog time-out period (WDTO), the device will operate normally.

5.2.3.2

Fail-safe Conditions

If an internal watchdog time-out occurs before the WD bit for FSI open (Table 8) or in case of V_DDfailure condition (V_DD

<

V_DD(FAIL))) for VDD_FAIL_en bit is set to logic [1], the device will revert to a Fail-safe mode until the WD bit is written to logic [1]

(see fail-safe to normal mode transition paragraph) and V_DDis within the normal voltage range.

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Table 8. SPI Watchdog Activation

Typical RFSI ()

Watchdog

0 (shorted to ground)

(open)

Disabled

Enable

During the Fail-safe mode, the outputs will depend on the corresponding input. The SPI register content is reset to their default

value (except POR bit) and fault protections are fully operational.

The Fail-safe mode can be detected by monitoring the NM bit is set to [0].

5.2.4 Normal & Fail-safe Mode Transitions

Transition Fail-safe to Normal mode

To leave the Fail-safe mode, V_DDmust be in nominal voltage and the microcontroller has to send a SPI command with WDIN bit

set to logic [1]; the other bits are not considered. The previous latched faults are reset by the transition into Normal mode (auto-

retry included).

Moreover, the device can be brought out of the Fail-safe mode due to watchdog time-out issue by forcing the FSI pin to logic [0].

Transition Normal to Fail-safe mode

To leave the Normal mode, a fail-safe condition must occurred (fail=1). The previous latched faults are reset by the transition into

Fail-safe mode (auto-retry included).

5.2.5 Fault Mode

The 07XSC200 is in Fault mode when:

• V_PWRand V_DDare within the normal voltage range,

• wake-up = 1,

• fail = X,

• fault=1.

This device indicates the faults below as they occur by driving the FSB pin to logic [0] for RSTB input is pulled up:

• Overtemperature fault,

• Overcurrent fault,

• Severe short-circuit fault,

• Output(s) shorted to V_PWRfault in OFF state,

• OpenLoad fault in OFF state,

• Overvoltage fault (enabled by default),

• Undervoltage fault.

The FSB pin will automatically return to logic [1] when the fault condition is removed, except for overcurrent, severe short-circuit,

overtemperature and undervoltage which will be reset by a new turn-on command (each fault_control signal to be toggled).

Fault information is retained in the SPI fault register and is available (and reset) via the SO pin during the first valid SPI

communication.

The OpenLoad fault in ON state is only reported through SPI register without effect on the corresponding output state (HS[x])

and the FS pin.

5.2.6 Start-up Sequence

The 07XSC200 enters in Normal mode after start-up if following sequence is provided:

• VPWR and VDD power supplies must be above their undervoltage thresholds,

• generate wake-up event (wake-up=1) from 0 to 1 on RSTB. The device switches to normal mode with SPI register content is

reset (as defined in Table 10 and Table 22). All features of the 07XSC200 will be available after 50 s typical, and all SPI

registers are set to default values (set to logic [0]).

• toggle WD bit from 0 to 1.

And, in case the PWM module is used (PWM_en bit is set to logic [1]) with an external reference clock:

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• apply PWM clock on CLOCK input pin after maximum 200s (min. 50s).

If the correct start-up sequence is not provided, the PWM function is not guaranteed.

5.3

Protection and Diagnostic Features

5.3.1 Protections

Over-temperature Fault

The 07XSC200 incorporates over-temperature detection and shutdown circuitry for each output structure.

Two cases need to be considered when the output temperature is higher than T_SD

:

• If the output command is ON: the corresponding output is latched OFF. FSB will be also latched to logic [0]. To delatch the

fault and be able to turn ON again the outputs, the failure condition must disappear and the auto-retry circuitry must be active,

or the corresponding output must be commanded OFF and then ON (toggling fault_control signal of corresponding output) or

the V_SUPPLY(POR)condition, if V_DD= 0.

• If the output command is OFF: FSB will go to logic [0] till the corresponding output temperature are below T_SD

.

For both cases, the fault register OT[0:1] bit into the status register will be set to [1]. The fault bits will be cleared in the status

register after a SPI read command.

5.3.1.1

Overcurrent Fault

The 07XSC200 incorporates output shutdown in order to protect each output structure against resistive short-circuit condition.

This protection is composed by eight predefined current levels (time dependent) to fit Xenon-HID manners by default or, 55 W

or 28 W bulb profiles, selectable separately by Xenon bit and 28W bits (as illustrated Figure 14, page 39).

In the first turn-on, the lamp filament is cold and the current will be huge. fault_control signal transition from logic [0] to [1] or an

auto-retry define this event. In this case, the overcurrent protection will be fitted to inrush current, as shown in Figure 5. This

overcurrent protection is programmable: OC[1:0] bits select overcurrent slope speed and OCHI1 current step can be removed in

case the OCHI bit is set to [1].

Over-current thresholds

fault_control

hson signal

hson

PWM

In Steady state, the wire harness will be protected by OCLO2 current level by default. Three other DC overcurrent levels are

available: OCLO1 or OCLO3 or OCLO4 based on the state of the OCLO[1,0] bits.

If the load current level ever reaches the overcurrent detection level, the corresponding output will latch the output OFF and FSB

will be also latched to logic [0]. To delatch the fault and be able to turn ON again the corresponding output, the failure condition

must disappear and the auto-retry circuitry must be active or the corresponding output must be commanded OFF and then ON

(toggling fault_control signal of corresponding output) or V_SUPPLY(POR)condition if V_DD= 0.

The SPI fault report (OC[0:1] bits) is removed after a read operation.

In Normal mode using internal PWM module, the 07XSC200 incorporates also a cooling bulb filament management if OC_mode

and Xenon are set to logic [1]. In this case, the first^tstep of multi-step overcurrent protection will depend to the previous OFF

duration, as illustrated in Figure 6. The following figure illustrates the current level will be used in function to the duration of

previous OFF state (toff). The slope of cooling bulb emulator is configurable with OCOFFCB[1:0] bits.

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Depending on toff

depending to toff

Over-current thresholds

Cooling

toff

fault_control

hson signal

hson

PWM

5.3.1.2

Severe Short-circuit Fault

The 07XSC200 provides output shutdown to protect each output in case of a severe short-circuit during of the output switching.

If the short-circuit impedance is below R_SHORT,the device will latch the output OFF, FSB will go to logic [0] and the fault register

SC[0:1] bit will be set to [1]. To delatch the fault and be able to turn ON again the outputs, the failure condition must disappear

and the corresponding output must be commanded OFF and then ON (toggling fault_control signal of corresponding output) or

V_SUPPLY(POR)condition if V_DD= 0.

The SPI fault report (SC[0:1] bits) is removed after a read operation.

5.3.1.3

Overvoltage Fault (Enabled by Default)

By default, the overvoltage protection is enabled. The 07XSC200 shuts down all outputs and FSB will go to logic [0] during an

overvoltage fault condition on the VPWR pin (V_PWR> V_PWR(OV)). The outputs remain in the OFF state until the overvoltage

condition is removed (V_PWR< V_PWR(OV)- V_PWR(OVHYS)). When experiencing this fault, the OVF fault bit is set to logic [1] and

cleared after either a valid SPI read.

The overvoltage protection can be disabled through the SPI (OV_dis bit is disabled set to logic [1]). The fault register reflects any

overvoltage condition (V_PWR> V_PWR(OV)). This overvoltage diagnosis, as a warning, is removed after a read operation, if the fault

condition disappears. The HS[0:1] outputs are not commanded in R_DS(ON)above the OV threshold.

5.3.1.4

Undervoltage Fault

The output(s) will latch off at some battery voltage below VPWR_(UV). As long as the V_DDlevel stays within the normal specified

range, the internal logic states within the device will remain (configuration and reporting).

In the case where battery voltage drops below the undervoltage threshold (V_PWR< V_PWR(UV)), the outputs will turn off, FSB will

go to logic [0], and the fault register UV bit will be set to [1].

Two cases need to be considered when the battery level recovers (V_PWR> V_{PWR(UV)_UP}):

• If outputs command are low, FSB will go to logic [1] but the UV bit will remain set to 1 until the next read operation (warning

report).

• If the output command is ON, FSB will remain at logic [0]. To delatch the fault and be able to turn ON again the outputs, the

failure condition must disappear and the auto-retry circuitry must be active or the corresponding output must be commanded

OFF and then ON (toggling fault_control signal of corresponding output) or V_SUPPLY(POR)condition if V_DD= 0.

In extended mode, the output is protected by overtemperature shutdown circuitry. All previous latched faults, occurred when

V_PWRwas within the normal voltage range, are guaranteed if V_DDis within the operational voltage range or until V_SUPPLY(POR)if

VDD = 0. Any new OT fault is detected (VDD failure included) and reported through SPI above VPWR_(UV). The output state is

not changed as long as the V_PWRvoltage does not drop any lower than 3.5 V typical.

All latched faults (overtemperature, overcurrent, severe short-circuit, over and undervoltage) are reset if:

• V_DD< V_DD(FAIL)with V_PWRin nominal voltage range,

• V_DDand V_PWRsupplies is below V_SUPPLY(POR)voltage value.

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(fault_control=0)

(OpenloadON=1)

(OpenloadOFF=1

or ShortVpwr=1

or OV=1)

(OpenloadOFF=1

or ShortVpwr=1

or OV=1)

(fault_control=1 and OV=0)

(fault_control=0 or OV=1)

(fault_control=0)

OFF

if hson=0

(SC=1)

ON

if hson=1

Latched

OFF

(count=16)

(Retry=1)

(SC=1)

(OpenloadON=1)

(after Retry Period and OV=0)

(OV=1)

Auto-retry

OFF

Auto-retry

ON

if hson=1

(Retry=1)

=> count=count+1

(OpenloadOFF=1

or ShortVpwr=1

or OV=1)

(fault_control=0)

Figure 13. Auto-retry State Machine

5.3.2 Auto-retry

The auto-retry circuitry is used to reactivate the output(s) automatically in case of overcurrent or overtemperature or undervoltage

failure conditions to provide a high availability of the load.

Auto-retry feature is available in Fault mode. It is activated in case of internal retry signal is set to logic [1]:

retry[x] = OC[x] or OT[x] or UV.

The feature retries to switch-on the output(s) after one auto-retry period (t_AUTO) with a limitation in term of number of occurrence

(16 for each output). The counter of retry occurrences is reset in case of Fail-safe to Normal or Normal to Fail-safe mode

transitions. At each auto-retry, the overcurrent detection will be set to default values in order to sustain the inrush current.

The Figure 13 describes the auto-retry state machine.

5.3.3 Diagnostic

Output Shorted to V_PWRFault

The 07XSC200 incorporates output shorted to V_PWRdetection circuitry in OFF state. Output shorted to V_PWRfault is detected if

output voltage is higher than V

and reported as a fault condition when the output is disabled (OFF). The output shorted

OSD(THRES)

to V_PWRfault is latched into the status register after the internal gate voltage is pulled low enough to turn OFF the output. The

OS[0:1] and OL_OFF[0:1] fault bits are set in the status register and FSB pin reports in real time the fault. If the output shorted

to V_PWRfault is removed, the status register will be cleared after reading the register.

The open output shorted to V_PWRprotection can be disabled through SPI (OS_DIS[0:1] bit).

OpenLoad Faults

The 07XSC200 incorporates three dedicated OpenLoad detection circuitries on the output to detect in OFF and in ON state.

07XSC200

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33

5.3.3.1

OpenLoad Detection in Off State

The OFF output OpenLoad fault is detected when the output voltage is higher than V_OLD(THRES)pulled up with internal current

source (I_OLD(OFF)) and reported as a fault condition when the output is disabled (OFF). The OFF Output OpenLoad fault is latched

into the status register or when the internal gate voltage is pulled low enough to turn OFF the output. The OL_OFF[0:1] fault bit

is set in the status register. If the OpenLoad fault is removed (FSB output pin goes to high), the status register will be cleared

after reading the register.

The OFF output OpenLoad protection can be disabled through SPI (OLOFF_DIS[0:1] bit).

5.3.3.2

OpenLoad Detection in On State

The ON output OpenLoad current thresholds can be chosen by the SPI to detect a standard bulbs or LEDs (OLLED[0:1] bit set

to logic [1]). In the case where load current drops below the defined current threshold OLON bit is set to logic [1], the output stays

ON and FSB is not disturbed.

5.3.3.3

OpenLoad Detection in On State For Led

OpenLoad for LEDs only (OLLED[0:1] set to logic [1]) is detected periodically each t_OLLED(fully-on, D[6:0]=7F)_.To detect OLLED

in fully-on state, the output must be ON at least t_OLLED.

To delatch the diagnosis, the condition should be removed and the SPI read operation is needed (OL_ON[0:1] bit). The ON output

open-load protection can be disabled through the SPI (OLON_DIS[0:1] bit).

5.3.3.4

Analog Current Recopy and Temperature Feedbacks

The CSNS pin is an analog output reporting a current proportional to the designed output current or a voltage proportional to the

temperature of the GND flag (pin #14). The routing is SPI programmable (TEMP_en, CSNS_en, CSNS_s[1,0] and CSNS_ratio_s

bits).

In case the current recopy is active, the CSNS output delivers current only during ON time of the output switch without overshoot.

The maximum current is 2.0 mA, typical. The typical value of external CSNS resistor connected to the ground is 2.5 k.

The current recopy is not active in Fail-safe mode.

5.3.3.5

Temperature Prewarning Detection

In Normal mode, the 07XSC200 provides a temperature prewarning reported via the SPI, in case the temperature of the GND

flag is higher than T_OTWAR. This diagnosis (OTW bit set to [1]) is latched in the SPI DIAGR0 register. To delatch, a read SPI

command is needed.

5.3.4 Active Clamp ON VPWR

The device provides an active gate clamp circuit in order to limit the maximum transient V_PWRvoltage at V_PWR(CLAMP). In case

of an overload on an output, the corresponding output is turned off, which leads to high voltage at VPWR with an inductive V_PWR

line. When the V_PWRvoltage exceeds V_PWR(CLAMP)threshold, the turn-off on the corresponding output is deactivated and all

HS[0:1] outputs are switched ON automatically to demagnetize the inductive battery line.

5.3.5 Reverse Battery on VPWR

The output survives the application of reverse voltage as low as -18 V. Under these conditions, the ON resistance of the output

is two times higher than a typical ohmic value in forward mode. No additional passive components are required except on the

V_DDcurrent path.

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5.3.6 Ground Disconnect Protection

In the event the 07XSC200 ground is disconnected from load ground, the device protects itself and safely turns OFF the output,

regardless of the state of the output at the time of disconnection (maximum V_PWR= 16 V). A 10 k resistor needs to be added

between the MCU and each digital input pin to ensure the device turns off, during a ground disconnect and to prevent this pin

from exceeding maximum ratings.

5.3.7 Loss of Supply Lines

5.3.7.1

Loss of V

DD

If the external V_DDsupply is disconnected (or not within specification: V_DD< V_DD(FAIL), with the VDD_FAIL_en bit set to logic [1]),

all SPI register content is reset.

The outputs can still be driven by the direct inputs IN[0:1] if V_PWRis within specified voltage range. The 07XSC200 uses the

battery input to power the output MOSFET-related current sense circuitry and any other internal logic providing Fail-safe device

operation with no V_DDsupplied. In this state, the overtemperature, overcurrent, severe short-circuit, short to VPWR and OFF

OpenLoad circuitry are fully operational, with default values corresponding to all SPI bits are set to logic [0]. No current is

conducted from V_PWRto V_DD

.

5.3.7.2

Loss of V

PWR

If the external V_PWRsupply is disconnected (or not within specification), the SPI configuration, reporting, and daisy chain features

are provided for RSTB to set to logic [1] under V_DDin nominal conditions. This fault condition can be diagnosed with UV fault in

SPI STATR_s registers. The SPI pull-up and pull-down current sources are not operational. The previous device configuration

is maintained. No current is conducted from V_DDto V_PWR

.

5.3.7.3

Loss of V

and V

PWR DD

If the external V_PWRand V_DDsupplies are disconnected (or not within specification: (V_DDand V_PWR) < V_SUPPLY(POR)), all SPI

register contents are reset, with default values corresponding to all SPI bits set to logic [0] and all latched faults reset.

5.3.8 EMC Performances

All following tests are performed on the Freescale evaluation board in accordance with the typical application schematic.

The device is protected in the event of positive and negative transients on the V_PWRline (per ISO 7637-2).

The 07XSC200 successfully meets the Class 5 of the CISPR25 emission standard and 200 V/m or BCI 200 mA injection level

for immunity tests.

5.4

Logic Commands and Registers

5.4.1 Serial Input Communication

SPI communication is accomplished using 16-bit messages. A message is transmitted by the MCU starting with the MSB D15

and ending with the LSB, D0 (Table 9). Each incoming command message on the SI pin can be interpreted using the following

bit assignments: the MSB, D15, is the watchdog bit (WDIN). In some cases, output selection is done with bit D13. The next four

bits, D14-D12:D10, are used to select the command register. The remaining nine bits, D8:D0, are used to configure and control

the outputs and their protection features.

Multiple messages can be transmitted in succession to accommodate those applications where daisy-chaining is desirable, or to

confirm transmitted data, as long as the messages are all multiples of 16 bits. Any attempt made to latch in a message that is

not 16 bits will be ignored.

The 07XSC200 has defined registers, which are used to configure the device and to control the state of the outputs. Table 10

summarizes the SI registers.

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

Table 9. SI Message Bit Assignment

Bit Sig

SI Msg Bit

Message Bit Description

Watchdog in: toggled to satisfy watchdog requirements.

Register address bit used in some cases for output selection (Table 11).

Register address bits.

MSB

D15

D13

D14, D12:D10

D9

Not used (set to logic [0]).

Used to configure the inputs, outputs, and the device protection features and SO status content.

LSB

D8:D0

Table 10. Serial Input Address and Configuration Bit Map

SI Data

SI

D1 D1 D1 D1 D1

Register

D15

D9 D8

D7

D6

D5

D4

D3

D2

D1

D0

4

3

2

1

0

STATR_ WDI

X

0

SOA4

SOA3

SOA2

SOA1

SOA0

s

N

PWMR_ WDI

1

A

0

1

0

1

28W_s ON_s

PWM6_s PWM5_s PWM4_s PWM3_s PWM2_s PWM1_s PWM0_s

s

N

CONFR WDI

0_s

0

DIR_dis_ SR1_s

s

SR0_s

DELAY2_s DELAY1_ DELAY0_

N

s

CONFR WDI

1_s

Retry_

Retry_dis OS_dis_s OLON_dis OLOFF_di OLLED_e CSNS_rati

N

_s

s_s

n_s

o_s

unlimited_

s

OCR_s WDI

N

1

0

A

0

1

0

1

0

Xenon BC1_s

_s

BC0_s

OC1_s

OC0_s

OCHI_s

CSNS1

OLCO1_s OLCO0_ OC_mode

s

_s

GCR WDI

N

VDD_ PWM_en CLOCK_s TEMP_en CSNS_e

FAIL_

en

CSNS0

X

OV_dis

el

n

1

0

CALR WDI

N

0

1

0

1

0

1

0

1

0

1

0

1

0

Register

state

0

X

0

after

RST=0

or

V_DD(FAIL)

or

V_SUPPLY

(POR)

condition

x=Don’t care.

s=Output selection with the bit A as defined in Table 11.

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5.4.2 Device Register Addressing

The following section describes the possible register addresses (D[14:10]) and their impact on device operation.

5.4.2.1

Address XX000—Status Register (STATR_s)

The STATR register is used to read the device status and the various configuration register contents without disrupting the device

operation or the register contents. The register bits D[4:0] determine the content of the first sixteen bits of SO data. In addition to

the device status, this feature provides the ability to read the content of the PWMR_s, CONFR0_s, CONFR1_s, OCR_s, GCR

and CALR registers (Refer to Serial Output Communication (Device Status Return Data).

5.4.2.2

Address A A 001—Output PWM Control Register (PWMR_s)

1 0

The PWMR_s register allows the MCU to control the state of corresponding output through the SPI. Each output “s” is

independently selected for configuration based on the state of the D13 bit (Table 11).

Table 11. Output Selection

A (D13)

HS Selection

0

1

HS0 (default)

HS1

A logic [1] on bit D8 (28W_s) selects the 28 W overcurrent protection profile: the overcurrent thresholds are divided by 2, and the

inrush and cooling responses are dedicated to 28 W lamps for HS[0,1] outputs.

Bit D7 sets the output state. A logic [1] enables the corresponding output switch and a logic [0] turns it OFF (if IN input is also

pulled down). Bits D6:D0 set the output PWM duty cycle to one of 128 levels for PWM_en is set to logic [1], as shown Table 6.

5.4.2.3

Address A A 010—Output Configuration Register (CONFR0_S)

1 0

The CONFR0_s register allows the MCU to configure corresponding output switching through the SPI. Each output “s” is

independently selected for configuration based on the state of the D14:D13 bits (Table 11).

For the selected output, a logic [0] on bit D5 (DIR_DIS_s) will enable the output for direct control. A logic [1] on bit D5 will disable

the output from direct control (in this case, the output is only controlled by the On bit).

D4:D3 bits (SR1_s and SR0_s) are used to select the high or medium or low speed slew rate for the selected output, the default

value [00] corresponds to the medium speed slew rate (Table 12).

Table 12. Slew Rate Speed Selection

SR1_s (D4)

SR0_s (D3)

Slew Rate Speed

0

1

0

1

0

1

medium (default)

low

high

Not used

Incoming message bits D2:D0 reflect the desired output that will be delayed of predefined PWM clock rising edges number, as

shown Table 7, (only available for PWM_en bit is set to logic [1]).

5.4.2.4

Address A A 011—Output Configuration Register (CONFR1_s)

1 0

The CONFR1_s register allows the MCU to configure corresponding output fault management through the SPI. Each output “s”

is independently selected for configuration based on the state of the D14:D13 bits (Table 11).

A logic [1] on bit D6 (RETRY_unlimited_s) disables the auto-retry counter for the selected output, the default value [0]

corresponds to enable auto-retry feature with time limitation.

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A logic [1] on bit D5 (RETRY_dis_s) disables the auto-retry for the selected output, the default value [0] corresponds to enable

this feature.

A logic [1] on bit D4 (OS_dis_s) disables the output hard shorted to V_PWRprotection for the selected output, the default value [0]

corresponds to enable this feature.

A logic [1] on bit D3 (OLON_dis_s) disables the ON output OpenLoad detection for the selected output, the default value [0]

corresponds to enable this feature (Table 13).

A logic [1] on bit D2 (OLOFF_dis_s) disables the OFF output OpenLoad detection for the selected output, the default value [0]

corresponds to enable this feature.

A logic [1] on bit D1 (OLLED_en_s) enables the ON output OpenLoad detection for LEDs for the selected output, the default value

[0] corresponds to ON output OpenLoad detection is set for bulbs (Table 13).

Table 13. ON OpenLoad Selection

OLLED_en_s

OLON_dis_s (D3)

ONOpenLoaddetection

(D1)

0

enable with bulb

threshold (default)

0

1

enable with LED

threshold

X

disable

A logic [1] on bit D0 (CSNS_ratio_s) selects the high ratio on the CSNS pin for the corresponding output. The default value [0] is

the low ratio (Table 14).

Table 14. Current Sense Ratio Selection

CSNS_high_s (D0)

Current Sense Ratio

0

1

CRS0 (default)

CRS1

5.4.2.5

Address A A 100—Output Overcurrent Register (OCR)

1 0

The OCR_s register allows the MCU to configure corresponding output overcurrent protection through the SPI. Each output “s”

is independently selected for configuration based on the state of the D14:D13 bits (Table 11).

A logic [1] on bit D8 (Xenon_s) disables enables the Xenon 55 W or 28 W bulb overcurrent profile, as described Figure 14.

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Xenon bit set to logic [0]:

I

OCH1

I

OCH2

I

OC1

OC2

I

OCLO4

OCLO3

OCLO2

OCLO1

Time

t

OC7

OC1

OC3 OC4 OC5

OC2

OC6

t

Xenon bit set to logic [1]:

I

OCH1

OCH2

I

OC1

OC2

OC3

OC4

I

OCL4

OCL3

I

OCL2

OCL1

Time

t

OC7

OC1

t

OC3 OC4 OC5

OC6

OC2

Figure 14. Overcurrent Profile Depending on Xenon bit

D[7:6] bits allow to MCU to programmable bulb cooling curve and D[5:4] bits inrush curve for selected output, as shown Table 15

and Table 16.

Table 15. Cooling Curve Selection

BC1_s (D7)

BC0_s (D6)

Profile Curves Speed

0

1

0

1

0

1

medium (default)

slow

fast

medium

Table 16. Inrush Curve Selection

OC1_s (D5)

OC0_s (D4)

Profile Curves Speed

slow (default)

fast

0

1

0

1

0

1

medium

very slow

A logic [1] on bit D3 (OCHI_s bit) the OCHI1 level is replaced by OCHI2 during t_OC1, as shown Figure 15.

07XSC200

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39

I

OCH1

OCH2

I

OC1

I

OC2

I

OC3

OC4

I

OCL4

OCL3

I

OCL2

OCL1

Time

t

OC7

OC1

t

OC3 OC4 OC5

OC6

OC2

Figure 15. Overcurrent Profile with OCHI bit set to ‘1’

The wire harness is protected by one of four possible current levels in steady state, as defined in Table 17.

Table 17. Output Steady State Selection

OCLO1 (D2) OCLO0 (D1)

Steady State Current

0

1

0

1

0

1

OCLO2 (default)

OCLO3

OCLO4

OCLO1

Bit D0 (OC_mode_sel) allows to select the overcurrent mode, as described Table 18.

Table 18. Overcurrent Mode Selection

OC_mode_s (D0)

Overcurrent Mode

0

1

only inrush current management (default)

inrush current and bulb cooling

management

Address 00101—GLObal configuration regIster (GCR)

The GCR register allows the MCU to configure the device through the SPI.

Bit D8 allows the MCU to enable or disable the V_DDfailure detector. A logic [1] on VDD_FAIL_en bit allows switch of the outputs

HS[0:1] with PWMR register device in Fail-safe mode in case of V_DD< V_DD(FAIL).

Bit D7 allows the MCU to enable or disable the PWM module. A logic [1] on PWM_en bit allows control of the outputs HS[0:1]

with PWMR register (the direct input states are ignored).

Bit D6 (CLOCK_sel) allows to select the clock used as reference by PWM module, as described in the following Table 19.

Table 19. PWM Module Selection

PWM_en (D7) CLOCK_sel (D6)

PWM module

0

1

X

0

PWM module disabled (default)

PWM module enabled with external

clock from CLOCK

1

PWM module enabled with

internal calibrated clock

Bits D5:D4 allow the MCU to select one of two analog feedback on CSNS output pin, as shown in Table 20.

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Table 20. CSNS Reporting Selection

TEMP_en (D5) CSNS_en (D4)

CSNS reporting

0

1

CSNS tri-stated (default)

X

current recopy of selected output (D3:2]

bits)

1

0

temperature on GND flag

Table 21. Output Current Recopy Selection

CSNS1 (D3)

CSNS0 (D2)

CSNS reporting

1

0

1

HS0

HS1

The GCR register disables the overvoltage protection (D0). When this bits is [0], the overvoltage is enabled (default value).

5.4.2.6

Address 00111—Calibration Register (CALR)

The CALR register allows the MCU to calibrate internal clock, as explained in Figure 13.

5.4.3 Serial Output Communication (Device Status Return Data)

When the CSB pin is pulled low, the output register is loaded. Meanwhile, the data is clocked out MSB- (OD15-) first as the new

message data is clocked into the SI pin. The first sixteen bits of data clocking out of the SO, and following a CSB transition, is

dependent upon the previously written SPI word.

Any bits clocked out of the Serial Output (SO) pin after the first 16 bits will be representative of the initial message bits clocked

into the SI pin since the CSB pin first transitioned to a logic [0]. This feature is useful for daisy-chaining devices as well as

message verification.

A valid message length is determined following a CSB transition of [0] to [1]. If there is a valid message length, the data is latched

into the appropriate registers. A valid message length is a multiple of 16 bits. At this time, the SO pin is tri-stated and the fault

status register is now able to accept new fault status information.

SO data will represent information ranging from fault status to register contents, user selected by writing to the STATR bits OD4,

OD3, OD2, OD1, and OD0. The value of the previous bit SOA3 will determine which output the SO information applies to for the

registers which are output specific; viz., Fault, PWMR, CONFR0, CONFR1, and OCR registers.

Note that the SO data will continue to reflect the information for each output that was selected during the most recent STATR

write until changed with an updated STATR write.

The output status register correctly reflects the status of the STATR-selected register data at the time that the CSB is pulled to a

logic [0] during SPI communication, and/or for the period of time since the last valid SPI communication, with the following

exception:

• The previous SPI communication was determined to be invalid. In this case, the status will be reported as though the invalid

SPI communication never occurred

• The V_PWRvoltage is below 4.0 V, the status must be ignored by the MCU

5.4.4 Serial Output Bit Assignment

The 16 bits of serial output data depend on the previous serial input message, as explained in the following paragraphs. Table 22,

summarizes SO returned data for bits OD15:OD0.

• Bit OD15 is the MSB; it reflects the state of the watchdog bit from the previously clocked-in message

• Bits OD14:OD10 reflect the state of the bits SOA4:SOA0 from the previously clocked in message

• Bit OD9 is set to logic [1] in Normal mode (NM)

• The contents of bits OD8:OD0 depend on bits D4:D0 from the most recent STATR command SOA4:SOA0 as explained

in the paragraphs following Table 22

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41

Table 22. Serial Output Bit Map Description

SO Returned Data

S

O

A

4

S

O

A

3

S

O

A

2

S

O

A

1

S

O

A

0

OD OD OD OD OD OD

15 14 13 12 11 10 D9

O

OD8 OD7 OD6 OD5 OD4

OD3

OD2

OD1

OD0

STATR

_s

WDI SO SOA SOA SO SO

N

M

OLON OLOF

1

A

0

1

0

1

0

POR UV

OV

OS_s

OT_s

SC_s

OC_s

N

A4

3

2

A1 A0

_s

F_s

PWMR

_s

WDI SO SOA SOA SO SO

A4 A1 A0

N

M

28W

_s

ON_ PWM PWM PWM PWM3_s

PWM2_s PWM1_s PWM0_s

N

3

2

s

6_s

5_s

4_s

CONF

R0_s

WDI SO SOA SOA SO SO

A4 A1 A0

N

M

DIR_d SR1_

SR0_s

DELAY2_s DELAY1 DELAY0

X

N

3

2

is_s

s

_s

Retry_ Retry_ OS_di OLON_dis OLOFF_dis OLLED_ CSNS_r

CONF

R1_s

WDI SO SOA SOA SO SO

N

M

dis_s s_s

_s

en_s

atio_s

1

A

0

1

0

1

0

X

unlimit

ed_s

N

A4

3

2

A1 A0

WDI SO SOA SOA SO SO

A4 A1 A0

N

M

Xeno BC1

n_s _s

BC0_ OC1_ OC0_ OCHI_s

OCLO1_s OCLO0_ OC_mod

OCR_s

GCR

N

3

2

s

e_s

VDD PW CLOC TEMP CSNS CSNS1

CSNS0

X

OV_dis

WDI SO SOA SOA SO SO

N

M

_FAI M_e K_sel _en

_en

0

1

0

1

N

A4

3

2

A1 A0

L_e

n

DIAGR

0

WDI SO SOA SOA SO SO

N

M

X

IN0

X

CLOCK_fail

0

1

0

1

0

1

X

IN1

X

CAL_fail

OTW

WD_en

0

N

A4

3

2

A1 A0

DIAGR

1

WDI SO SOA SOA SO SO

A4 A1 A0

N

M

X

0

X

1

N

3

2

DIAGR

2

WDI SO SOA SOA SO SO

N A4 3 2 A1 A0

N

M

Regist

er

0

state

after

RST=

0 or

V_DD(F

_AIL)or

V_SUPP

N/ N/ N/ N/ N/

0

X

0

A

LY(POR

)

conditi

on

s=Output selection with the bit A as defined in Table 11

5.4.4.1

Previous Address SOA4:SOA0=1A000 (STATR_s)

The returned data OD8 reports logic [1] in case of previous Power ON Reset condition (V_SUPPLY(POR)). This bit is only reset by

a read operation.

Bits OD7:OD0 reflect the current state of the Fault register (FLTR) corresponding to the output previously selected with the bits

SOA3 = A (Table 22).

• OC_s: overcurrent fault detection for a selected output,

• SC_s: severe short-circuit fault detection for a selected output,

• OS_s: output shorted to VPWR fault detection for a selected output,

• OLOFF_s: OpenLoad in OFF state fault detection for a selected output,

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Freescale Semiconductor

• OLON_s: OpenLoad in ON state fault detection (depending on current level threshold: bulb or LED) for a selected output,

• OV: overvoltage fault detection,

• UV: undervoltage fault detection

• POR: power on reset detection.

The FSB pin reports all faults. For latched faults, this pin is reset by a new Switch OFF command (toggling fault_control signal).

5.4.4.2

Previous Address SOA4:SOA0=1A001 (Pwmr_s)

The returned data contains the programmed values in the PWMR register for the output selected with A.

5.4.4.3

Previous Address SOA4:SOA0=1A010 (confr0_s)

The returned data contains the programmed values in the CONFR0 register for the output selected with A.

5.4.4.4

Previous Address SOA4:SOA0=1A011 (confr1_s)

The returned data contains the programmed values in the CONFR1 register for the output selected with A.

5.4.4.5

Previous Address SOA4:SOA0=1A100 (ocr_s)

The returned data contains the programmed values in the OCR register for the output selected with A.

5.4.4.6

Previous Address SOA4:SOA0=00101 (gcr)

The returned data contains the programmed values in the GCR register.

5.4.4.7

Previous Address SOA4:SOA0=00111 (diagr0)

The returned data OD2 reports logic [1] in case of PWM clock on CLOCK pin is out of specified frequency range.

The returned data OD1 reports logic [1] in case of calibration failure.

The returned data OD0 reports logic [1] in case of overtemperature prewarning (temperature of GND flag is above T_OTWAR).

5.4.4.8

Previous Address SOA4:SOA0=01111 (diagr1)

The returned data OD4: OD3 report in real time the state of the direct input IN[1:0].

The OD0 indicates if the watchdog is enabled (set to logic [1]) or not (set to logic [0]). OD4:OD1 report the output state in case

of Fail-safe state due to watchdog time-out as explained in the following Table 23.

Table 23. Watchdog activation report

WD_en (OD0)

SPI Watchdog

0

1

disabled

enabled

5.4.4.9

Previous Address SOA4:SOA0=10111 (diagr2)

The returned data is the product ID. Bits OD2:OD0 are set to 010 for Protected Dual 7.0 m high side Switches.

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5.4.4.10 Default Device Configuration

The default device configuration is explained by the following:

• HS output is commanded by the corresponding IN input or On bit through the SPI. The medium slew-rate is used,

• HS output is fully protected by the Xenon overcurrent profile by default, the severe short-circuit protection, the undervoltage

and the overtemperature protection. The auto-retry feature is enabled,

• OpenLoad in ON and OFF state and HS shorted to V_PWRdetections are available,

• No current recopy and no analog temperature feedback active,

• Overvoltage protection is enabled,

• SO reporting fault status must be ignored,

• V_DDfailure detection is disabled.

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6

Typical Applications

The following figure shows a typical lighting application (only one vehicle corner) using an external PWM clock from the main

MCU. A redundancy circuitry has been implemented to substitute light control (from MCU to watchdog) in case of a Fail-safe

condition.

It is recommended to locate a 22 nF decoupling capacitor to the module connector.

V_PWR

V_DD

Voltage regulator

10 µF

100 nF

10 µF

100 nF

V_PWR

V_DD

V_PWR

ignition

switch

V_DD

VPWR

HS0

VDD

100 nF

10 k

100 nF

V_DD

WAKE

I/O

FSB

10 k

22 nF

CLOCK

LOAD 0

IN0

IN1

MCU

SPDL07 SOIC

10 k

SCLK

CSB

I/O

SCLK

CSB

RSTB

SI

HS1

22 nF

LOAD 1

SO

SI

SO

A/D

CSNS

FSI

10 k

GND

22 nF

2.5 k

VPWR

Watchdog

direct light commands (pedal, comodo,...)

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7

Packaging

7.1

Soldering Information

The 07XSC200 is packaged in a surface mount power package intended to be soldered directly on the printed circuit board.

The 07XSC200 was qualified in accordance with JEDEC standards J-STD-020C Pb-Free reflow profile. The maximum peak

temperature during the soldering process should not exceed 260 °C for 40 seconds maximum duration.

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7.2

Package Dimensions

Package dimensions are provided in package drawings. To find the most current package outline drawing, go to

www.freescale.com and perform a keyword search for the drawing’s document number.

Package

Suffix

Package Outline Drawing Number

32-Pin SOICW

EK

98ASA00368D

EK SUFFIX

32-PIN SOICW

98ASA00368D

REV. 0

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EK SUFFIX

32-PIN SOICW

98ASA00368D

REV. 0

07XSC200

Analog Integrated Circuit Device Data

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Freescale Semiconductor

EK SUFFIX

32-PIN SOICW

98ASA00368D

REV. 0

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8

Revision History

Revision

1.0

Date

Description of Changes

8/2013

9/2013

•

Initial release based on MC07XS3200 data sheet.

Added the note “To achieve high reliability over 10 years of continuous operation, the device's

2.0

continuous operating junction temperature should not exceed 125C.” to Operating Temperature

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Information in this document is provided solely to enable system and software implementers to use Freescale products.

There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based

on the information in this document.

How to Reach Us:

Home Page:

freescale.com

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Freescale reserves the right to make changes without further notice to any products herein. Freescale makes no

warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does

Freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any

and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be

provided in Freescale data sheets and/or specifications can and do vary in different applications, and actual performance

may vary over time. All operating parameters, including “typicals,” must be validated for each customer application by

customer’s technical experts. Freescale does not convey any license under its patent rights nor the rights of others.

Freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address:

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SMARTMOS is a trademark of Freescale Semiconductor, Inc. All other product or service names are the property of their

respective owners.

Document Number: MC07XSC200

Rev. 2.0

9/2013