07XSF517--Datasheet/数据表在线中文翻译

Document order number: MC07XSF517

Rev. 2.0, 9/2013

Freescale Semiconductor

Advance Information

Triple 7.0 mOhm and Dual

17 mOhm High Side Switch

07XSF517

The 07XSF517 is the latest achievement in DC motors and lighting

drivers. It belongs to an expanding family to control and diagnose

various types of loads, such as incandescent lamps or light-emitting

diodes (LEDs) with enhanced precision. It combines flexibility through

daisy chainable SPI 5.0 MHz, extended digital and analog feedbacks,

safety, and robustness.

ENHANCED PENTA HIGH SIDE SWITCH

Output edge shaping helps to improve electromagnetic performance.

To avoid shutting off the device upon inrush current, while still being

able to closely track the load current, a dynamic overcurrent threshold

profile is featured. Current of each channel can be sensed with a

programmable sensing ratio. Whenever communication with the

external microcontroller is lost, the device enters a Fail operation mode,

but remains operational, controllable, and protected.

EK SUFFIX (PB-FREE)

98ASA00367D

54-PIN SOICEP

This new generation of high side switch products family facilitates ECU

design due to compatible MCU software and PCB foot prints for each

device variant.

Applications

• Low voltage exterior lighting

• Low voltage industrial lighting

• Low voltage automation systems

• Halogen lamps

• Incandescent bulbs

• Light-emitting diodes (LEDs)

• HID Xenon ballasts

This family is packaged in a Pb-free power-enhanced SOIC package

with an exposed pad, which is End of Life Vehicles directive compliant.

This device is powered by SMARTMOS technology.

Features

• Triple 7.0 m and dual 17 m high side switches with high transient

current capability

• 16-bit 5.0 MHz SPI control of overcurrent profiles, channel control

including PWM duty-cycles, output-ON and -OFF OpenLoad

detections, thermal shut-down and prewarning, and fault reporting

• Output current monitoring with programmable synchronization signal

and supply voltage feedback

• DC motors

• Limp Home mode

• External smart power switch control

• Operating voltage is 7.0 to 18 V with sleep current < 5.0 µA,

extended mode from 6.0 to 28 V

• -16 V reverse polarity and ground disconnect protections

• Compatible PCB foot print and SPI software driver among the family

V

PWR

V

PWR

VCC

VPWR

07XSF517

5.0 V

Regulator

VPWR

VCC

SI

VCC

CP

SO

CSB

SCLK

SI

GND

CSB

SCLK

SO

RSTB

CLK

CSNS

SYNCB

LIMP

IN1

OUT1

Solenoid

OUT2

OUT3

OUT4

OUT5

LED Module

RSTB

CLK

M

DC Motor

Resistive load

Bulb

Main

MCU

A/D1

TRG1

PORT

A/D2

IN2

IN3

IN4

OUT

VPWR

IN

OUT6

GND

Smart Power

Spare

CSNS

GND

Figure 1. Triple 7.0 mOhm and Dual 17 mOhm Simplified Application Diagram

* This document contains certain information on a new product.

Specifications and information herein are subject to change without notice.

1

Orderable Parts

This section describes the part numbers available to be purchased along with their differences.

Table 1. Orderable Part Variations

Temperature

OUT1

Rds(on)

OUT2

Rds(on)

OUT3

OUT4

OUT5

Part Number

Notes

Package

OUT6

(T )

Rds(on) Rds(on) Rds(on)

A

SOIC 54 pins

exposed pad

(1)

MC07XSF517EK

Notes

-40 to 125 °C

17 m

7.0 m

7.0 m 7.0 m

Yes

1. To Order parts in Tape & Reel, add the R2 suffix to the part number.

Valid orderable part numbers are provided on the web. To determine the orderable part numbers for this device, go to http://

www.freescale.com and perform a part number search for the following device numbers: 07XSF517.

MC07XSF517

Analog Integrated Circuit Device Data

2

Freescale Semiconductor

Table of Contents

2

3

Internal Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

Pin Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3.1 Pinout Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3.2 Pin Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

General Product Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4.1 Relationship Between Ratings and Operating Requirements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

4.2 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

4.4 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11

4.5 Supply Currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12

General IC Functional Description and Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13

5.3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.3.1 Self-protected High Side Switches . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.3.2 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.3.3 MCU Interface and Device Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.4 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.5 Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.5.1 Power Off Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.5.2 Sleep Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.5.3 Normal Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.5.4 Fail Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5.5.5 Mode Transitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16

5.6 SPI Interface and Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5.6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5.6.2 SPI Input Register and Bit Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

5.6.3 SPI Output Register and Bit Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

5.6.4 Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20

5.6.5 Electrical Characterization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

Functional Block Requirements and Behaviors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6.1 Self-protected High Side Switches Description and Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6.1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6.1.2 Output Pulse Shaping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22

6.1.3 Output Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

6.1.4 Output Clamps . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

6.1.5 Digital Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

6.1.6 Analog Diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

6.2 Power Supply Functional Block Description and Application Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

6.2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

6.2.2 Wake State Reporting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

6.2.3 Supply Voltages Disconnection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

6.3 Communication Interface and Device Control Functional Block Description and Application Information . . . . . . . . . 57

6.3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

6.3.2 Fail Mode Input (LIMP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57

6.3.3 MCU Communication Interface Protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

6.3.4 External Smart Power Control (OUT6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60

4

5

6

MC07XSF517

Analog Integrated Circuit Device Data

Freescale Semiconductor

3

7

Typical Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

7.1.1 Application Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

7.1.2 Application Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

7.1.3 Bill of Material . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62

7.2 EMC and EMI Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

7.2.1 EMC/EMI Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

7.2.2 Fast Transient Pulse Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63

7.3 Robustness Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

7.4 PCB Layout Recommendations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

7.5 Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

7.5.1 Thermal Transient . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

7.5.2 R/C Thermal Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

8.1 Marking Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

8.2 Package Mechanical Dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71

8

9

MC07XSF517

Analog Integrated Circuit Device Data

4

Freescale Semiconductor

2

Internal Block Diagram

V_PWR

V_CC

100 nF

CP

VCC

VPWR

Power

Supply

V_S

Reverse

Battery

Protection

VPWR_PROTECTED

UVF Under-voltage

Detection

Battery

Clamp

Power-on

Reset

OVF

Charge

CPF

Pump

OTW1

OTW2

SO

Thermal

Prewarning

OTS1

Temperature

Shut-down

CSB

SPI

Selectable

Slope Control

SCLK

SI

SPIF

Selectable Over-

OC1

current Protection

RSTB

OLON1

OLOFF1

Fault

Management

Selectable Open-

load Detection

Selectable

Current Sensing

LIMP

IN1

IN2

IN3

IN4

Output Voltage

Monitoring

OUT1

OUT2

OUT1 Channel

OUT2 Channel

OUT3 Channel

PWM Module

OUT3

OUT4

Logic

V_CC

WAKEB OR

RSTB

OUT4 Channel

Clock Failure

Detection

CLK

OUT5

OUT6

V_CC

OUT5 Channel

5k

V_CC

CSNS

SYNCB

VPWR_PROTECTED

Selectable

Delay

Selectable

Analog

VPWR_PROTECTED

CSNS

Feedback

5k

Control die

Temperature

Monitoring

Power

Voltage

Monitoring

GND

Figure 2. Simplified Internal Block Diagram (Penta version)

MC07XSF517

Analog Integrated Circuit Device Data

Freescale Semiconductor

5

3

Pin Connections

3.1

Pinout Diagram

Transparent top view

NC

CLK

LIMP

IN4

IN3

IN2

IN1

CSNS SYNCB

CSNS

GND

OUT1

OUT3

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

NC

CP

RSTB

CSB

SCLK

SI

VCC

SO

OUT6

GND

OUT2

OUT4

54

53

52

51

50

49

48

47

46

45

44

43

42

41

40

39

55

VPWR

18

19

20

21

22

23

24

25

26

27

37

36

35

34

33

32

31

30

29

28

OUT5

NC

Figure 3. Pinout Diagram

3.2

Pin Definitions

Table 2. 07XSF517 Pin Definitions

Pin Number Pin Name Pin Function

Formal Name

Definition

This pin is the connection for an external capacitor for charge pump use only.

3

4

CP

Internal

supply

Charge-pump

This input pin is used to initialize the device configuration and fault registers,

as well as place the device in a low-current sleep mode. This pin has a

passive internal pull-down.

RSTB

SPI

Reset

This input pin is connected to a chip select output of a master microcontroller

(MCU). When this digital signal is high, SPI signals are ignored. Asserting

this pin low starts an SPI transaction. The transaction is indicated as

completed when this signal returns to high level. This pin has a passive

internal pull-up to V_CCthrough a diode.

5

CSB

SPI

Chip select

This input pin is connected to the MCU providing the required bit shift clock

for SPI communication. This pin has an passive internal pull-down.

6

7

SCLK

SI

SPI

Serial clock

Serial input

This pin is the data input of the SPI communication interface. The data at the

input are sampled on the positive edge of the SCLK. This pin has a passive

internal pull-down.

MC07XSF517

Analog Integrated Circuit Device Data

6

Freescale Semiconductor

Table 2. 07XSF517 Pin Definitions (continued)

Pin Number Pin Name Pin Function

Formal Name

Definition

This pin is a power supply pin for internal logic, the SPI I/Os and the OUT6

driver.

8

9

VCC

SO

Power supply MCU power supply

This output pin is connected to the SPI Serial Data Input pin of the MCU or

to the SI pin of the next device of a daisychain of devices. The SPI changes

on the negative edge of SCLK. When CSB is high, this pin is high-

impedance.

SPI

Serial Output

This output pin controls an external Smart Power Switch by logic level. This

pin has a passive internal pull-down.

10

OUT6

GND

Output

External Solid State

Ground

These pins are the ground for the logic and analog circuitries of the device.

For ESD and electrical parameter accuracy purpose, the ground pins must

be shorted on the board.

11, 44

Ground

Protected high side power output pins to the load.

These pins are not connected.

12, 13

OUT2

OUT4

NC

Output

N/A

Channel #2

Channel #4

14, 15, 16

1, 2, 18… 27,

53, 54

Not connected

Protected high side power output pins to the load.

28… 37

39, 40, 41

42, 43

OUT5

OUT3

OUT1

CSNS

Output

Channel #5

Channel #3

Channel #1

Current sense

Output

This pin reports an analog value proportional to the designated OUT[1:5]

output current or the temperature of the exposed pad or the supply voltage.

It is used externally to generate a ground-referenced voltage for the

microcontroller (MCU). Current recopy and analog voltage feedbacks are

SPI programmable.

45

Feedback

This open drain output pin allows synchronizing the MCU A/D conversion.

This pin requires an external pull-up resistor to VCC.

46

47

CSNS

SYNCB

Feedback

Input

Current sense

synchronization

This input wakes up the device. This input pin is used to directly control

corresponding channel in Fail mode. During Normal mode the control of the

outputs by the control inputs is SPI programmable.This pin has a passive

internal pull-down.

IN1

Direct input #1

Direct input #2

Direct input #3

Direct input #4

Limp Home

This input wakes up the device. This input pin is used to directly control

corresponding channel in Fail mode. During Normal mode the control of the

outputs by the control inputs is SPI programmable.This pin has a passive

internal pull-down

48

49

50

51

IN2

Input

This input wakes up the device. This input pin is used to directly control

corresponding channel in Fail mode. During Normal mode the control of the

outputs by the control inputs is SPI programmable.This pin has a passive

internal pull-down

IN3

This input wakes up the device. This input pin is used to directly control

corresponding channel in Fail mode. During Normal mode the control of the

outputs by the control inputs is SPI programmable.This pin has a passive

internal pull-down

IN4

The Fail mode can be activated by this digital input. This pin has a passive

internal pull-down.

LIMP

MC07XSF517

Analog Integrated Circuit Device Data

Freescale Semiconductor

7

Table 2. 07XSF517 Pin Definitions (continued)

Pin Number Pin Name Pin Function

Formal Name

Definition

This pin is an input/output pin. It is used to report the device sleep-state

information. It is also used to apply reference PWM clock which will be

divided by 2⁸in Normal operating mode. This pin has a passive internal pull-

down.

52

CLK

Input/Output

Device mode

feedback

Reference PWM

clock

This exposed pad connects to the positive power supply and is the source of

operational power for the device.

55

VPWR

Power

Supply

Supply power

supply

Pins 17 and 38 are omitted.

MC07XSF517

Analog Integrated Circuit Device Data

8

Freescale Semiconductor

4

General Product Characteristics

4.1

Relationship Between Ratings and Operating Requirements

The analog portion of device is supplied by the voltage applied to the VPWR exposed pad. Thereby the supply of internal circuitry

(logic in case of a V_CCdisconnect, charge pump, gate drive,...) is derived from the VPWR pin.

In case of a reverse supply:

•

the internal supply rail is protected (max. -16 V)

the output drivers (OUT1… OUT5) are switched on, to reduce the power consumption in the drivers when using

incandescent bulbs

Fatal Range

Reverse

protection

Degraded Operating

Range

Normal

Operating Range

Degraded Operating

Range

Potential Failure

Fatal Range

Probable

permanent

failure

- Reduced performance

- Probable failure in

case of short-circuit

Probable

permanent

failure

- Reduced performance Full performance - Reduced performance

- Full protection but

accuracy not

- Full protection but

accuracy not

guaranteed

- no PMW feature for

UV to 6.0 V

Operating Range

V

6

V

0

4

1

-

Fatal Range

Accepted Industry

Standard Practices

Fatal Range

Probable

permanent failure

Correct operation

permanent failure

Handling Conditions (Power OFF)

Figure 4. Ratings vs. Operating Requirements (VPWR pin)

The device’s digital circuitry is powered by the voltage applied to the VCC pin. If VCC is disconnected, the logic part is supplied

by the VPWR pin.

The output driver for SPI signals, CLK pin (wake feedback), and OUT6 are supplied by the VCC pin only. This pin shall be

protected externally in case of a reverse polarity, and in case of a high-voltage disturbance.

Fatal Range

Not Operating Range Degraded Operating Normal Operating

Degraded Operating

Range

Fatal Range

Probable

Range

Probable

permanent failure

Reduced

Full performance Reduced performance permanent failure

performance

Operating Range

Figure 5. Ratings vs. Operating Requirements (VCC pin)

MC07XSF517

Analog Integrated Circuit Device Data

Freescale Semiconductor

9

4.2

Maximum Ratings

Table 3. Maximum Ratings

All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent

damage to the device.

Symbol

Description (Rating)

Min.

Max.

Unit

Notes

ELECTRICAL RATINGS

V_PWR

V_PWRVoltage Range

-16

40

V

VCC Logic Supply Voltage

-0.3

7.0

CC

(2)

V

Digital Input Voltage

IN

• IN1… IN4 and LIMP

-0.3

40

20

• CLK, SI, SCLK, CSB, and RSTB

V

Digital Output Voltage

V

OUT

• SO, CSNS, SYNC, OUT6, CLK

-0.3

–

20

(3)

(4)

I

Negative Digital Input Clamp Current

5.0

mA

A

CL

I_OUT

Power Channel Current

• 7.0 mchannel

• 17 m channel

–

11

5.5

(5)

E

Power Channel Clamp Energy Capability

mJ

CL

• 7.0 m channel - Initial T_J= 25 °C

–

200

100

50

• 7.0 m channel - Initial T_J= 150 °C

• 17 m channel - Initial T_J= 25 °C

• 17 m channel - Initial T_J= 150 °C

(6)

V

ESD Voltage

V

ESD

• Human Body Model (HBM) - VPWR, Power Channel, and GND pins

• Human Body Model (HBM) - All other pins

• Charge Device Model (CDM) - Corner pins

• Charge Device Model (CDM) - All other pins

-8000

-2000

-750

+8000

+2000

+750

-500

+500

Notes

2. Exceeding voltage limits on those pins may cause a malfunction or permanent damage to the device.

3. Maximum current in negative clamping for IN1… IN4, LIMP, RSTB, CLK, SI, SO, SCLK, and CSB pins

4. Continuous high side output current rating so long as maximum junction temperature is not exceeded. Calculation of maximum output

current using package thermal resistance is required.

5. Active clamp energy using single-pulse method (L = 2.0 mH, R_L= 0 , V_PWR= 14 V). Please refer to Output Clamps section.

6. ESD testing is performed in accordance with the Human Body Model (HBM) (C_ZAP= 100 pF, R_ZAP= 1500 ), and the Charge Device

Model.

MC07XSF517

Analog Integrated Circuit Device Data

10

Freescale Semiconductor

4.3

Thermal Characteristics

Table 4. Thermal Ratings

All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent

damage to the device.

Symbol

Description (Rating)

Min.

Max.

Unit

Notes

THERMAL RATINGS

(7)

Operating Temperature

°C

T_A

T_J

• Ambient

• Junction

-40

+125

+150

T_STG

Storage Temperature

-55

–

+ 150

260

°C

(8) (9)

T_PPRT

Peak Package Reflow Temperature During Reflow

THERMAL RESISTANCE AND PACKAGE DISSIPATION RATINGS

(10)

(11) (12)

(13)

R_JB

R_JA

R_JC

Junction-to-Board (1]Soldered to Board)

–

2.5

°/W

Junction-to-Ambient, Natural Convection, Four-Layer Board (2s2p)

Junction-to-Case (Case top surface)

17.4

10.6

Notes

7. To achieve high reliability over 10 years of continuous operation, the device's continuous operating junction temperature should not

exceed 125C.

8. Pin soldering temperature limit is for 10 seconds maximum duration. Not designed for immersion soldering. Exceeding these limits may

cause malfunction or permanent damage to the device.

9. Freescale’s Package Reflow capability meets Pb-free requirements for JEDEC standard J-STD-020C. For Peak Package Reflow

Temperature and Moisture Sensitivity Levels (MSL), Go to www.freescale.com, search by part number [e.g. remove prefixes/suffixes

and enter the core ID to view all orderable parts. (i.e. MC33xxxD enter 33xxx), and review parametrics.

10. Thermal resistance between the die and the printed circuit board per JEDEC JESD51-8. Board temperature is measured on the top

surface of the board near the package.

11. Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature,

ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance.

12. Per JEDEC JESD51-6 with the board (JESD51-7) horizontal.

13. Thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1).

4.4

Operating Conditions

This section describes the operating conditions of the device. Conditions apply to all the following data, unless otherwise noted.

Table 5. Operating Conditions

All voltages are with respect to ground unless otherwise noted. Exceeding these ratings may cause a malfunction or permanent

damage to the device.

Symbol

Ratings

Min

Max

Unit

Notes

Functional operating supply voltage - Device is fully

functional. All features are operating.

7.0

18

V

V_PWR

Overvoltage range

• Jump Start

V

–

28

40

• Load dump

Reverse Supply

-16

4.5

–

V

V_CC

Functional operating supply voltage - Device is fully

functional. All features are operating.

5.5

MC07XSF517

Analog Integrated Circuit Device Data

Freescale Semiconductor

11

4.5

Supply Currents

This section describes the current consumption characteristics of the device.

Table 6. Supply Currents

Characteristics noted under conditions 4.5 V  V_CC 5.5 V, -40 C  T_A 125 C, GND = 0 V, unless otherwise noted. Typical

values noted reflect the approximate parameter means at T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Ratings

Min

Typ.

Max

Unit

Notes

VPWR CURRENT CONSUMPTIONS

I_QVPWRSleep mode measured at V_PWR= 12 V

• T_A= 25 °C

(14) (15)

(15)

–

1.2

10

5.0

30

µA

• T_A= 125 °C

I_VPWR

VCC CURRENT CONSUMPTIONS

I_QVCCSleep mode measured at V_CC= 5.5 V

I_VCC

Operating mode measured at V_PWR= 18 V

7.0

8.0

mA

–

0.05

2.8

5.0

4.0

µA

Operating mode measured at V_PWR= 5.5 V (SPI frequency

5.0 MHz)

mA

Notes

14. With the OUT1… OUT5 power channels grounded.

15. With the OUT1… OUT5 power channels opened.

MC07XSF517

Analog Integrated Circuit Device Data

12

Freescale Semiconductor

5

General IC Functional Description and Application

Information

5.1

Introduction

The 07XSF517 is an evolution of the successful Gen3 by providing improved features of a complete family of devices using

Freescale's latest and unique technologies for the controller and the power stages.

It consists of a scalable family of devices compatible in terms of software driver and package footprint. It allows diagnosing the

light-emitting diodes (LEDs) with an enhanced current sense precision with synchronization pin, as well as driving high power

motors with a perfect control of its current consumption. It combines flexibility through daisy chainable SPI 5.0 MHz, extended

digital and analog feedbacks, safety, and robustness. It integrates an enhanced PWM module with 8-bit duty cycle capability and

PWM frequency prescaler per power channel.

5.2

Features

The main attributes of 07XSF517 are:

•

Penta high side switches with overload, overtemperature and undervoltage protection

control output for 1 external smart power switch

16 Bit SPI communication interface with daisy chain capability

integrated Fail mode (ASIL B compliant functional safety behavior)

dedicated control inputs for use in Fail mode

analog feedback pin with SPI programmable multiplexer and sync signal

channel diagnosis by SPI communication

advanced current sense mode for LED usage

synchronous PWM module with external clock, prescaler and multiphase feature

excellent EMC behavior

power net and reverse polarity protection

ultra low power mode

scalable and flexible family concept

board layout compatible SOIC54 package with exposed pad

MC07XSF517

Analog Integrated Circuit Device Data

Freescale Semiconductor

13

5.3

Block Diagram

The choice of multi-die technology in SOIC exposed pad package including low cost vertical trench FET power die associated

with Smart Power control die lead to an optimized solution.

Gen4 - Functional Block Diagram

Power Supply

MCU Interface & Device Control

SPI Interface

Self-Protected

High Side

Switches

OUT[x]

Parallel Control Inputs

PWM Controller

MCU

Interface

Supply

MCU Interface & Output Control

Self-Protected High Side Switches

Figure 6. Functional Block Diagram

5.3.1 Self-protected High Side Switches

OUT1… OUT5 are the output pins of the power switches. The power channels are protected against various kinds of short-

circuits and have active clamp circuitry that may be activated when switching off inductive loads. Many protective and diagnostic

functions are available.

5.3.2 Power Supply

The device operates with supply voltages from 5.5 to 40 V (V_PWR), but is full spec. compliant only between 7.0 and 18 V. The

VPWR pin supplies power to the internal regulator, analog, and logic circuit blocks. The VCC pin (5.0 V typ.) supplies the output

register of the serial peripheral interface (SPI). Consequently, the SPI registers cannot be read without presence of V_CC. The

employed IC architecture guarantees a low quiescent current in Sleep mode.

5.3.3 MCU Interface and Device Control

In Normal mode the power output channels are controlled by the embedded PWM module, which is configured by the SPI register

settings. For bidirectional SPI communication, V_CChas to be in the authorized range. Failure diagnostics and configuration are

also performed through the SPI port. The reported failure types are: open-load, short-circuit to supply, severe short-circuit to

ground, overcurrent, overtemperature, clock-fail, and under and overvoltage.

The device allows driving loads at different frequencies up to 400 Hz.

5.4

Functional Description

The device has four fundamental operating modes: Sleep, Normal, Fail, and Power off. It possesses multiple high side switches

(power channels) each of which can be controlled independently:

•

in Normal mode by SPI interface. For bidirectional SPI communication, a second supply voltage (V_CC) is required.

in Fail mode by the corresponding the direct inputs IN1… IN4. The OUT5 for the Penta version and the OUT6

are off in this mode.

MC07XSF517

Analog Integrated Circuit Device Data

14

Freescale Semiconductor

5.5

Modes of Operation

The operating modes are based on the signals:

•

wake = (IN1_ON) OR (IN2_ON) OR (IN3_ON) OR (IN4_ON) OR (RST\). More details in Logic I/O Plausibility

Check section.

•

fail = (SPI_fail) OR (LIMP). More details in Loss of Communication Interface section.

Sleep

wake = [0]

wake = [1]

(V_PWR< V_PWRPOR) and

(V_CC< V_CCPOR

(V_PWR> V_PWRPOR) or

(V_CC> V_CCPOR

)

(V_PWR< V_PWRPOR) and

(V_CC< V_CCPOR

(V_PWR< V_PWRPOR) and

(V_CC< V_CCPOR

Power

off

)

Normal

fail = [0] and valid watchdog toggle

fail = [1]

Fail

Figure 7. General IC Operating Modes

5.5.1 Power Off Mode

The power off mode is applied when V_PWRand V_CCare below the power on reset threshold (V_{PWR POR}, V_{CC POR}).

In power off, no functionality is available but the device is protected by the clamping circuits. Refer to Supply Voltages

Disconnection section.

5.5.2 Sleep Mode

The Sleep mode is used to provide ultra low current consumption. During Sleep mode:

•

the component is inactive and all outputs are disabled

the outputs are protected by the clamping circuits

the pull-up / pull-down resistors are present

The Sleep mode is the default mode of the device after applying the supply voltages (V_PWRor V_CC) prior to any wake-up condition

(wake = [0]).

The wake-up from Sleep mode is provided by the wake signal.

5.5.3 Normal Mode

The Normal mode is the regular operating mode of the device. The device is in Normal mode, when the device is in the wake

state (wake = [1]) and no fail condition (fail = [0]) is detected.

During Normal mode:

•

the power outputs are under control of the SPI

the power outputs are controlled by the programmable PWM module

MC07XSF517

Analog Integrated Circuit Device Data

Freescale Semiconductor

15

•

the power outputs are protected by the overload protection circuit

the control of the power outputs by SPI programming

the digital diagnostic feature transfers status of the smart switch via the SPI

the analog feedback output (CSNS and CSNS SYNC) can be controlled by SPI

The channel control (CHx) can be summarized:

•

CH1… 4 controlled by ONx or iINx (if ir is programmed by SPI)

CH5… 6 controlled by ONx

Rising CHx by definition means starting over current window for OUT1… 5.

5.5.4 Fail Mode

The device enters the Fail mode, when

•

the LIMP input pin is high (logic [1])

or a SPI failure is detected

During Fail mode (wake = [1] & fail = [1]):

•

the OUT1… OUT4 outputs are directly controlled by the corresponding control inputs (IN1… IN4)

the OUT5… OUT6 are turned off

the PWM module is not available

while no SPI control is feasible, the SPI diagnosis is functional (depending on the fail mode condition):

the SO shall report the content of SO register defined by SOA0 to 3 bits

the outputs are fully protected in case of an overload, overtemperature, and undervoltage

no analog feedback is available

the max. output overcurrent profile is activated (OCLO and window times)

in case of an overload condition or undervoltage, the autorestart feature controls the OUT1… OUT4 outputs

in case of an overtemperature condition, OCHI1 detection, or severe short-circuit detection, the corresponding

output is latched OFF until a new wake-up event.

•

The channel control (CHx) can be summarized:

•

CH1… 4 controlled by iINx, while the overcurrent windows are controlled by IN_ONx

CH5… 6 are off

5.5.5 Mode Transitions

After a wake-up:

•

a power on reset is applied and all SPI SI and SO registers are cleared (logic[0])

the faults are blanked during t_BLANKING

The device enters in Normal mode after start-up if following sequence is provided:

•

V_PWRand V_CCpower supplies must be above their undervoltage thresholds (Sleep mode)

generate wake-up event (wake =1) setting RSTB from 0 to 1

The device initialization will be completed after 50 µsec (typ). During this time, the device is robust in case of V_PWRinterrupts

higher than 150nsec.

The transition from “Normal mode” to “Fail mode” is executed immediately when a fail condition is detected.

During the transition, the SPI SI settings are cleared and the SPI SO registers are not cleared.

When the Fail mode condition was a:

•

LIMP input, WD toggle timeout, WD toggle sequence, or a SPI modulo 16 error, the SPI diagnosis is available

during Fail mode

•

SI / SO stuck to static level, the SPI diagnosis is not available during Fail mode

The transition from “Fail mode” to “Normal mode” is enabled, when

•

the fail condition is removed and

two SPI commands are sent within a valid watchdog cycle (first WD=[0] and then WD=[1])

MC07XSF517

Analog Integrated Circuit Device Data

Freescale Semiconductor

16

During this transition:

•

all SPI SI and SO registers are cleared (logic[0])

the DSF (device status flag) in the registers #1… #7 and the RCF (Register Clearer flag) in the device status

register #1 are set (logic[1])

To delatch the RCF diagnosis, a read command of the quick status register #1 must be performed.

5.6

SPI Interface and Configurations

5.6.1 Introduction

The SPI is used to

•

control the device in case of Normal mode

provide diagnostics in case of Normal and Fail mode

The SPI is a 16 Bit full-duplex synchronous data transfer interface with daisy chain capability.

The interface consists of four I/O lines with 5.0 V CMOS logic levels and termination resistors:

•

The SCLK pin clocks the internal shift registers of the device

The SI pin accepts data into the input shift register on the rising edge of the SCLK signal

The SO pin changes its state on the rising edge of SCLK and reads out on the falling edge

The CSB enables the SPI interface

•

with the leading edge of CS\ the registers are loaded

•

while CSB is logic [0] SI/SO data are shifted

with the trailing edge of the CSB signal, SPI data is latched into the internal registers

when CSB is logic [1], the signals at the SCLK and SI pins are ignored and SO is high-impedance

When the RSTB input is

•

low (logic [0]), the SPI and the fault registers are reset. The Wake state then depends on the status of the input

pins (IN_ON1… IN_ON4)

•

high (logic[1]), the device is in Wake status and the SPI is enabled

The functionality of the SPI is checked by a plausibility check. In case of a SPI failure the device enters the Fail mode.

5.6.2 SPI Input Register and Bit Descriptions

The first nibble of the 16 bit data word (D15… D12) serves as address bits.

Register

SI address

SI data

#

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

4 Bi t ad ress

WD

11 Bi t d at a

name

11 bits (D10… D1) are used as data bits.

The D11 bit is the WD toggle bit. This bit has to be toggled with each write command.

When the toggling of the bit is not executed within the WD timeout, a SPI fail is detected.

All register values are logic [0] after a reset. The predefined value is off / inactive unless otherwise noted.

MC07XSF517

Analog Integrated Circuit Device Data

Freescale Semiconductor

17

Register

SI address

SI data

D15

D 14

D13

D 12

D 11

D 10

D9

D 8

D 7

D 6

D 5

D4

D 3

D2

D 1

D 0

#

SYNC

EN1

SYNC

EN0

SOA

MODE

O CHI

OD3

0

1

0

1

0

1

0

1

0

1

0

1

0

W D

WD SEL

OCHI

MUX2

M UX1

MUX0

SOA3

SOA2

SOA1

SOA0

Ini tia lisa tion 1

ini tia lisa tion 2

CH1 control

CH2 control

CH3 control

CH4 control

CH5 control

0

1

2

3

4

5

6

O CHI

OD5

OCHI

OD4

OCHI

OD2

OCHI

O D1

PWM

sync

O TW

SE L

OCHI

NO HID1 NO HID0

THERMAL TRANSIENT

PH11

PH12

PH13

PH14

PH15

PH01

PH02

PH03

PH04

PH05

ON1

ON2

ON3

ON4

ON5

PW M71 PWM61 PW M51 PWM41 PW M31 PWM 21 PWM11 PW M01

PW M72 PWM62 PW M52 PWM42 PW M32 PWM 22 PWM12 PW M02

PW M73 PWM63 PW M53 PWM43 PW M33 PWM 23 PWM13 PW M03

PW M74 PWM64 PW M54 PWM44 PW M34 PWM 24 PWM14 PW M04

PW M75 PWM65 PW M55 PWM45 PW M35 PWM 25 PWM15 PW M05

0

1

0

1

0

1

0

1

0

1

W D

PH16

PH06

PSF 4

X

ON6

PSF3

X

PW M76 PWM66 PW M56 PWM46 PW M36 PWM 26 PWM16 PW M06

CH6 control

7

output

contr ol

PSF5

PSF2

X

PSF1

X

ON6

ON5

ON4

O N3

ON2

ON1

8

G PW M

EN6

GPWM

EN5

GPW M

EN4

GPWM

EN3

GPWM

EN2

GPW M

EN1

0

1

0

1

0

9-1

9-2

10-1

10-2

11

Global P WM

contr ol

X

GPW M7 GPWM 6 GPW M5 GPWM4 GPWM3 G PW M2 GPWM 1 GPW M0

ACM

EN5

ACM

EN4

ACM

EN3

ACM

EN2

ACM

EN1

OCLO5 OCLO4

OCLO 3 OCLO2 O CLO1

ov er curr ent

contr ol

NO

SHO RT SHORT SHORT SHORT SHORT

OCHI5 OCHI4 OCHI3 O CHI2 OCHI1

OCHI5

O CHI4

OCHI3

OCHI2

OCHI1

X

INEN14 INEN04 INEN13 INEN03 INEN12 INEN02 INEN11 INEN01

input enable

1

0

1

W D

0

1

0

1

PRS15

X

PRS05

X

PRS14

X

PRS04

X

PRS13

X

PRS03

X

PRS12

PRS02

PRS11

PRS01

12-1

12-2

13-1

13-2

presca ler

settings

X

PRS16

OLOF F

PRS06

OLOFF

O LO N

DGL5

OLON

DG L4

OLON

DGL3

OLON

DGL2

OLON

DGL1

OLOFF

EN5

OLO FF

OLOFF

OL control

EN4

OLLED

EN4

EN3

OLLED

EN3

EN2

OLLED

EN2

EN1

OLLED

EN1

OLLED OLLED

TRIG EN5

res

OLLE D control

incr eme nt /

dercrement

testmode

INCR

SG N

1

0

1

W D

X

INCR15 INCR05 INCR14 INCR04 INCR13 INCR03 INCR12 INCR02 INCR11 INCR01

14

15

X

WD

#0 ~# 14 = watchdog tog gle bit

#0

SYNC SYNC Sync status

SO A0 ~ SOA3

#0

= address of nex t SO data word

EN1

EN0

SOA MO DE

= s ing le read a ddress of nex t SO data word

0

sy nc off

MUX0 ~ MUX2

#0

= CSN S m ultip lexer s etti ng

= S YNC d ela y setti ng

0

1

0

valid

trig0

SYNC EN0~ SYNC EN1

WD SEL

#0

#1

= watchdog tim eout select

= over temperature warning threshold selection

= r eset clock module

= OC H I windo w on l oad de man d

= HID outpu ts s elec ti on

1

trig1/2

OTW SEL

PW M S Y NC

OCHI ODx

#1

NO HID1NO HID0D Selection

0

1

av aila ble for all c han nels

av ailable for channe l 3 only

NO HIDx

OCHI THERMAL

OCHIT RA NSIENT

#1

= OCH I1 level de pen ding on control die temp erature

= OCH I1 level ad jus ted durin g OFF to ON tra nsitio n

1

0

1

av ailable for channe ls 3 and 4 o nly

unava ilab le for all ch anne ls

PWM0x ~ PWM 7x

PH0x ~ PH1x

#2~ #7 = P WM val ue (8Bi t)

#2~#7 = p has e con tro l

#2~#7

#11

PH 1x PH 0x Phase

0

1

0 °

90°

ONx #2~ #8 = c han nel on /o ff inc l. OC HI c ont rol

PS Fx

#8 = puls e skipping feature forpower output channels

GPWM ENx # 9-1 = g lob al PWM en abl e

1

0

1

180°

27 0°

GPWM1 ~ G PWM7

#9-2 = global PWM value (8Bit)

#10 -1 = adva nced curre nt s ense m ode e nable

#10 -1 = OCLO lev el contr ol

GPWM

E Nx

IN x= 0

I Nx= 1

ONx INEN1x INE N0x

ACM ENx

OCLOx

OUTx PWMx OUTx PWMx

0

x

OFF

ON

OFF

ON

x

OFF

ON

x

individual

SHORT OCHIx #10 -2 = use short OC HI window time

0

gl obal

individual

gl obal

global

individual

global

NO OCHIx #10-2 = start with OCLO thres hold

1

0

1

0

1

0

INE N0x ~ INE N1x

#1 1 = inpu t en able c ontrol

0

1

0

PRS0x ~ PRS1x

#1 2 = p re sca ler se tting

1

OLOF F ENx

individual

#13 -1 = OL load in off state enab le

OLO N DGLx

gl obal

global

#13 -1 = OL ON degl itch ti me

individual

OLL ED ENx #13 -2 = OL L ED mode enable

OLL ED TRIG #13 -2 = trigger for OLLED detetcio n in 100% d.c.

1

gl obal

individual

1

INCR SGN

#1 4 = P WM inc reme nt / dec reme nt si gn

#12

PRS 1x PRS 0x PRSdivider

INCR0x ~ INCR1x

#1 4 = P WM inc reme nt / dec reme nt se ttin g

0

1

0

1

/4

/2

/1

2 5Hz .... 10 0H z

50Hz .... 200Hz

100Hz.... 400Hz

x

#0

MUX2 MUX1 MUX0 CSNS

0

1

0

1

0

1

off

#14

INCR SGN

inc reme nt/decrement

OUT1 cur rent

OUT2 cur rent

OUT3 current

0

1

decrem ent

increm ent

INC R 1x INCR 0x inc reme nt/decrement

1

0

1

OUT4 current

OUT5 current

0

1

no i ncrem ent/dec reme nt

4 LSB

VPWR monitor

con tro l die temperature

1

0

1

VBAT m onitor

1

0

1

8 LSB

16 LSB

MC07XSF517

Analog Integrated Circuit Device Data

18

Freescale Semiconductor

5.6.3 SPI Output Register and Bit Descriptions

The first nibble of the 16 Bit data word (D12… D15) serves as address bits.

All register values are logic [0] after a reset, except DSF and RCF bits. The predefined value is off / inactive unless otherwise

noted.

#2~#6

QSFx

CLKF

RCF

#1

= quick s tatus (OC or OTW or OTS or OLON or OLOFF)

= PWM clock fail flag

OC2x O C1x OC0x ove r cur rent st atus

0

1

0

1

0

1

0

1

0

1

0

1

0

1

no ove rcu rrent

OCHI1

= reg ister c lear fla g

CPF

= charge pum p fl ag

OCHI2

OLF #1 ~# 7 = open lo ad flag (wi red or of all OL s ign als )

OVLF #1 ~# 7 = ov er loa d flag (wired or of all OC a nd OTS sig nal s)

DSF #1 ~# 7 = devic e status flag ( UVF or OVF or CP F or RCF or CLKF or TM F)

FM #1 ~# 8 = fail m ode fla g

OCHI3

OCLO

OCHIOD

SSC

OLOFFx #2 ~# 6 = open lo ad in o ff state status bit

OLONx #2 ~# 6 = open lo ad in o n state status bit

OTWx #2 ~# 6 = ov er te mp eratur e warnin g bit

not u sed

#9

DEVID2 DEV ID1 DEVID0 device type

0

1

0

1

0

1

0

1

0

1

0

1

0

1

P enta3 /2

P enta0 /5

Qu ad2 /2

Quad0/4

Trip le1 /2

Trip le0 /3

re s

OTSx #2 ~# 6 = ov er te mp eratur e shutdown bit

iLIM P

SPIF

#7

#8

#9

= status o f LIM P input after deglitc her (re ported in real tim e)

= SPI fail flag

UVF

= under v oltage flag

OVF

= ov er volta ge flag

TMF

= testmo de activa ti on flag

status of VPWR/2 comparator (reported in real time)

= status o f VB AT/2 c omparator (reporte d in rea l time)

OUTx

re s

iINx

= status o f INx pin after deglitc her (reported in real tim e)

= status o f INx _ON s ignals (IN1_O N or IN2 _ON or IN 3_ON or IN4_ ON)

= devic e ty pe

TOGGLE

DEVID0 ~ DE VID2

DEVID3 ~ DE VID4

DEVID5 ~ DE VID7

= devic e fa mil y

= design status (incre men te d numbe r)

MC07XSF517

Analog Integrated Circuit Device Data

Freescale Semiconductor

19

5.6.4 Timing Diagrams

RSTB

V

IH

IL

10% V_CC

t

CS

ENBL

t

WRST

CSB

90% V_CC

V

IH

IL

10% V_CC

t

RSI

t

WSCLKh

t

LAG

t

LEAD

V

IH

IL

90% V_CC

10% V_CC

SCLK

t

SI(SU)

t

WSCLKl

t

FSI

t

SI(H)

V

IH

IL

90% V_CC

10% V_CC

SI

Must be Valid

Don’t Care

Must be Valid

Don’t Care

t

SOEN

SODIS

V

IH

IL

Tri-stated

SO

Figure 8. Timing Requirements During SPI Communication

t

FSI

RSI

V

OH

90% V_CC

50%

SCLK

10% V_CC

V

OL

OH

10% V_CC

SO

V

OL

t

RSO

Low to High

t

VALID

t

FSO

SO

V

OH

OL

High To Low

90% V_CC

10% V_C

Figure 9. Timing Diagram for Serial Output (SO) Data Communication

MC07XSF517

Analog Integrated Circuit Device Data

20

Freescale Semiconductor

5.6.5 Electrical Characterization

Table 7. Electrical Characteristics

Characteristics noted under conditions 4.5 V  V_CC 5.5 V, -40 C  T_A 125 C, GND = 0 V, unless otherwise noted. Typical

values noted reflect the approximate parameter means at T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min

Typ

Max

Unit Notes

SPI SIGNALS CSB, SI, SO, SCLK, SO

SPI Clock Frequency

f_SPI

V_IH

0.5

–

5.0

–

MHz

V

Logic Input High State Level (SI, SCLK, CSB, RSTB)

Logic Input High State Level for wake-up (RSTB)

Logic Input Low State Level (SI, SCLK, CSB, RSTB)

Logic Output High State Level (SO)

3.5

V_IH(WAKE)

V_IL

3.75

–

V

–

VCC - 0.4

–

0.85

–

V

V_OH

V

Logic Output Low State Level (SO)

V_OL

0.4

+0.5

V

Logic Input Leakage Current in Inactive State (SI = SCLK = RSTB = [0] and

CSB = [1])

I_IN

-0.5

µA

Logic Output Tri-state Leakage Current (SO from 0 V to V_CC

Logic Input Pull-up / Pull-down Resistor

Logic Input Capacitance

)

I_OUT

R_PULL

C_IN

-10

25

–

+1.0

100

20

12.5

20

–

µA

k

(16)

–

pF

RSTB deglitch Time

t_{RST_DGL}

t_SO

7.5

–

10

–

µs

ns

µs

SO Rising and Falling Edges with 80 pF

Required High State Duration of SCLK (Required Setup Time)

Required Low State Duration of SCLK (Required Setup Time)

t_WCLKh

t_WCLKl

t_CS

80

1.0

–

Required duration from the Rising to the Falling Edge of CSB (Required

Setup Time)

–

Required Low State Duration for reset RST\

t_RST

t_LEAD

t_LAG

1.0

320

100

20

–

µs

ns

Falling Edge of CSB to Rising Edge of SCLK (Required Setup Time)

Falling Edge of SCLK to Rising Edge of CSB (Required Setup lag Time)

SI to Falling Edge of SCLK (Required Setup Time)

–

t_SI(SU)

t_SI(H)

t_RSI

–

Falling Edge of SCLK to SI (Required hold Time of the SI signal)

SI, CSB, SCLK, Max. Rise Time Allowing Operation at Maximum f_SPI

SI, CSB, SCLK, Max. Fall Time Allowing Operation at Maximum f_SPI

–

20

–

50

60

t_FSI

–

Time from Falling Edge of CS\ to Reach Low-impedance on SO (access

time)

t_SO(EN)

–

Time from Rising Edge of CSB to Reach Tri-state on SO

t_SO(DIS)

–

60

ns

Notes

16. Parameter is derived from simulations.

MC07XSF517

Analog Integrated Circuit Device Data

Freescale Semiconductor

21

6

Functional Block Requirements and Behaviors

6.1

Self-protected High Side Switches Description and Application

Information

6.1.1 Features

Up to five power outputs are foreseen to drive light as well as DC motor applications. The outputs are optimized for driving bulbs,

but also HID ballasts, LEDs, and other resistive or low inductive loads.

The smart switches are controlled by use of high sophisticated gate drivers. The gate drivers provide:

•

output pulse shaping

output protections

active clamps

output diagnostics

6.1.2 Output Pulse Shaping

The outputs are controlled with a closed loop active pulse shaping to provide the best compromise between:

•

low switching losses

low EMC emission performance

minimum propagation delay time

Depending on the programming of the prescaler setting register #12-1, #12-2, the switching speeds of the outputs are adjusted

to the output frequency range of each channel.

The edge shaping shall be designed according the following table:

divider

factor

PWM freq [Hz]

PWM period [ms]

d.c. range [hex]

d.c. range [LSB]

min. on/off duty

cycle time [µs]

min

max

min

max

min

max

min

max

25

50

100

200

10

5

40

20

4

8

252

248

4

2

1

03

07

FB

F7

156

78

100

400

2, 5

10

8

248

The edge shaping provides full symmetry for rising and falling transition:

•

the slopes for the rising and falling edge are matched to provide the best EMC emission performance

the shaping of the upper edges and the lower edges are matched to provide the best EMC emission performance

the propagation delay time for the rising edge and the falling edge is matched to provide true duty cycle control

of the output duty cycle error, < 1 LSB at max. frequency

•

a digital regulation loop is used to minimize the duty cycle error of the output signal

MC07XSF517

Analog Integrated Circuit Device Data

22

Freescale Semiconductor

Figure 10. Typical Power Output Switching (slow & fast slew rate)

6.1.2.1

SPI Control and Configuration

For optimized control of the outputs, a synchronous clock module is integrated. The PWM frequency and output timing during

Normal mode are generated from the clock input (CLK) by the integrated PWM module. In case of clock fail (very low frequency,

very high frequency), the output duty cycle is 100%.

Each output (OUT1… OUT6) can be controlled by an individual channel control register:

Register

SI address

SI data

#

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

C Hx contr ol

2~7

channel address

WD

PH1x

PH0x

Onx

PWM7x PWM6x PWM5x PWM4x PWM3x PWM2x PWM1x PWM0x

where:

•

PH0x… PH1x: phase assignment of the output channel x

ONx: on/off control including overcurrent window control of the output channel x

PWM0x… PWM7x: 8-bit PWM value individually for each output channel x

The ONx bits are duplicated in the output control register #8 to control the outputs with either the CHx control register or the output

control register.

The PRS1x… PRS0x prescaler settings can be set in the prescaler settings register #12-1 and #12-2.

The following changes of the duty cycle are performed asynchronous (with pos. edge of CSB signal)

•

turn on with 100% duty cycle (CHx = ON)

change of duty cycle value to 100%

turn off (CHx = OFF)

phase setting (PH0x… PH1x)

prescaler setting (PRS1x… PRS0x)

A change in phase setting or prescaler setting during CHx = ON may cause an unwanted long ON-time. Therefore it is

recommended to turn off the output(s) before execution of this change.

INCR SGN increment/decrement

0

1

decrement

increment

The following changes of the duty cycle are performed synchronous (with the next PWM cycle)

•

turn on with less than 100% duty cycle (OUTx = ONx)

change of duty cycle value to less than 100%

MC07XSF517

Analog Integrated Circuit Device Data

Freescale Semiconductor

23

A change of the duty cycle value can be achieved by a change of the

•

PWM0x… PWM7x bits in individual channel control register #2… #7

GPWM EN1… GPWM EN6 bits (change between individual PWM and global PWM settings) in global PWM

control register #9-1

•

incremental/decremental register #14

The synchronization of the switching phases between different devices is provided by the PWM SYNC bit in the initialization 2

register #1.

On a SPI write into initialization 2 register (#1):

•

initialization when the bit D1 (PWM SYNC) is logic[1], all counters of the PWM module are reset with the positive

edge of the CSB, i.e. the phase synchronization is performed immediately within one SPI frame. It could help to

synchronize different Gen4 devices in the board.

•

when the bit D1 is logic[0], no action is executed

The switching frequency can be adjusted for the corresponding channel as described in the following table:

CLK fr eq. [kHz]

prescalersetting

div ider

PWM freq [Hz]

sl ew

rate

PWM resolution

min.

max.

PRS1x

PRS0x

factor

min

25

max

100

200

400

[Bit]

[steps]

0

1

0

1

4

2

1

slow

fast

25,6

102,4

50

8

256

X

100

PWMduty cycle

pulse skippingframe

S0 S1 S2 S3 S4 S5 S6 S7

FF FF FF FF FF FF FF FF

F7 FF FF FF FF FF FF FF

F7 FF FF FF F7 FF FF FF

F7 FF F7 FF F7 FF FF FF

F7 FF F7 FF F7 FF F7 FF

F7 F7 F7 FF F7 FF F7 FF

F7 F7 F7 FF F7 F7 F7 FF

F7 F7 F7 F7 F7 F7 F7 FF

hex

dec

256

255

254

253

252

251

250

249

248

247

246

[%]

FF

FE

FD

FC

FB

FA

F9

F8

F7

F6

F5

100,00%

99,61%

99,22%

98,83%

98,44%

98,05%

97,66%

97,27%

96,88%

96,48%

96,09%

245

F4

95,70%

.

4

3

2

1

03

02

01

00

1,56%

1,17%

0,78%

0,39%

No PWM feature is provided in case of:

•

Fail mode

clock input signal failure

6.1.2.2

Global PWM Control

In addition to the individual PWM register, each channel can be assigned independently to a global PWM register.

The setting is controlled by the GPWM EN bits inside the global PWM control register #9-1. When no control by direct input pin

is enabled and the GPWM EN bit is

•

low (logic[0]), the output is assigned to individual PWM (default status)

high (logic[1]), the output is assigned to global PWM

The PWM value of the global PWM channel is controlled by the global PWM control register #9-2.

MC07XSF517

Analog Integrated Circuit Device Data

Freescale Semiconductor

24

iINx=0

iINx=1

GPWM

ENx

ONx

INEN1x INEN0x

CHx

PWMx

x

CHx

PWMx

x

0

x

0

1

0

1

0

1

OF F

ON

OFF

ON

individual

global

individual

global

0

ON

0

1

0

OF F

ON

individual

global

individual

global

1

individual

global

1

ON

individual

When a channel is assigned to global PWM, the switching phase the prescaler and the pulse skipping are according the

corresponding output channel setting.

6.1.2.3

Incremental PWM Control

To reduce the control overhead during soft start/stop of bulbs or DC motors (e.g. theatre dimming), an incremental PWM control

feature is implemented.

With the incremental PWM control feature the PWM values of all internal channels OUT1… OUT5 can be incremented or

decremented with one SPI frame.

The incremental PWM feature is not available for

•

the global PWM channel

the external channel OUT6

The control is according the increment/decrement register #14:

•

INCR SGN: sign of incremental dimming (valid for all channels)

INCR 1x, INCR 0x increment/decrement

INCR 1x INCR 0x increment/decrement

0

1

0

1

0

1

no increment/decrement

4

8

16

This feature limits the duty cycle to the rails (00 resp. FF) to avoid any overflow.

6.1.2.4

Pulse Skipping

Due to the output pulse shaping feature and the resulting switching delay time of the smart switches, duty cycles close to 0%

resp. 100% can not be generated by the device. Therefore the pulse skipping feature (PSF) is integrated to interpolate this output

duty cycle range in Normal mode.

The pulse skipping provides a fixed duty cycle pattern with eight states to interpolate the duty cycle values between F7 (Hex) and

FF (Hex). The range between 00 (Hex) and 07 (Hex) is not considered to be provided.

The pulse skipping feature

•

is available individually for the power output channels (OUT1… OUT5)

is not available for the external channel (OUT6).

The feature is enabled with the PSF bits in the output control register #8.

When the corresponding PSF bit is

•

low (logic[0]), the pulse skipping feature is disabled on this channel (default status)

high (logic[1]), the pulse skipping feature is enabled on this channel

MC07XSF517

Analog Integrated Circuit Device Data

Freescale Semiconductor

25

6.1.2.5

Input Control

Up to four dedicated control inputs (IN1… IN4) are foreseen to

•

wake-up the device

fully control the corresponding output in case of Fail mode

control the corresponding output in case of Normal mode

The control during Normal mode is according the INEN0x and INEN1x bits in the input enable register #11 and according

following logic table:

An input deglitcher is provided at each control input to avoid high frequency control of the outputs. The internal signal is called

iINx.

The channel control (CHx) can be summarized:

•

Normal mode:

•

CH1… 4 controlled by ONx or INx (if it is programmed by the SPI)

CH5… 6 controlled by ONx

Rising CHx by definition means starting overcurrent window for OUT1… 5

Fail mode:

•

CH1… 4 controlled by iINx, while the over current windows are controlled by IN_ONx

CH5… 6 are off

Even so, the input thresholds are logic level compatible, the input structure of the pins shall be able to withstand supply voltage

level (max.40 V) without damage. External current limit resistors (i.e. 1.0 k...10 k) can be used to handle reverse current

conditions.

The inputs have an integrated pull-down resistor.

6.1.2.6

Electrical Characterization

Table 8. Electrical Characteristics

Characteristics noted under conditions 7.0 V  V_PWR 18 V, -40 C  T_A 125 C, GND = 0 V, unless otherwise noted. Typical

values noted reflect the approximate parameter means at T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min

Typ

Max

Unit Notes

POWER OUTPUTS OUT1… OUT5

ON-Resistance, Drain-to-Source for 7m Power Channel

R_DS(ON)

m

• T_J= 25 °C, V_PWR> 12 V

–

7.0

–

8.0

12.9

10.5

13

• T_J= 150 °C, V_PWR> 12 V

• T_J= 25 °C, V_PWR= 7.0 V

• T_J= 25 °C, V_PWR= -12 V

• T_J= 150 °C, V_PWR= -12 V

–

18.2

ON-Resistance, Drain-to-Source for 17 m Power Channel

R_DS(ON)

m

• T_J= 25 °C, V_PWR> 12 V

–

17

–

19

30.9

25.5

31

• T_J= 150 °C, V_PWR> 12 V

• T_J= 25 °C, V_PWR= 7.0 V

• T_J= 25 °C, V_PWR= -12 V

• T_J= 150 °C, V_PWR= -12 V

–

43.5

Sleep Mode Output Leakage Current (Output shorted to GND) per Channel

• T_J= 25 °C, V_PWR= 12 V

I_{LEAK SLEEP}

µA

–

0.5

5.0

25

• T_J= 125 °C, V_PWR= 12 V

• T_J= 25 °C, V_PWR= 35 V

• T_J= 125 °C, V_PWR= 35 V

MC07XSF517

Analog Integrated Circuit Device Data

26

Freescale Semiconductor

Table 8. Electrical Characteristics

Characteristics noted under conditions 7.0 V  V_PWR 18 V, -40 C  T_A 125 C, GND = 0 V, unless otherwise noted. Typical

values noted reflect the approximate parameter means at T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min

Typ

Max

Unit Notes

POWER OUTPUTS OUT1… OUT5 (Continued)

Operational Output Leakage Current in OFF-State per Channel

I_{OUT OFF}

µA

• T_J= 25 °C, V_PWR= 18 V

• T_J= 125 °C, V_PWR= 18 V

–

10

20

Output PWM Duty Cycle Range (measured at V_OUT= V_PWR/2)

• Low Frequency Range (25 to 100 Hz)

_PWM

LSB

4.0

8.0

–

252

248

• Medium Frequency Range (50 to 200 Hz)

• High Frequency Range (100 to 400 Hz)

(17)

Rising and Falling Edges Slew-Rate at V_PWR= 14 V (measured from

SR

V/µs

V

_OUT= 2.5 V to V_PWR- 2.5 V)

• Low Frequency Range

• Medium Frequency Range

• High Frequency Range

0.25

0.55

0.42

0.84

0.6

1.25

(17)

Rising and Falling Edges Slew Rate Matching at V_PWR= 14 V (SRr / SRf)

SR

0.9

1.0

1.1

(17)

Turn-on and Turn-off Delay Times at V_PWR= 14 V

• Low Frequency Range

t_DLY

µs

20

10

60

30

100

50

• Medium Frequency Range

• High Frequency Range

(17)

Turn-on and Turn-off Delay Times Matching at V_PWR= 14 V

• Low Frequency Range

t_DLY

µs

-20

-10

0.0

20

10

• Medium Frequency Range

• High Frequency Range

Shutdown Delay Time in case of Fault

t_{OUTPUT SD}

0.5

2.5

4.5

µs

REFERENCE PWM CLOCK

Clock Input Frequency Range

f_CLK

Notes

25.6

–

102.4

kHz

17. With nominal resistive load: 2.5  and 5.0  respectively for 7.0 m and 17 m channel.

6.1.3 Output Protections

The power outputs are protected against fault conditions in Normal and Fail mode in case of

•

overload conditions

harness short-circuit

•

overcurrent protection against ultra-low resistive short-circuit conditions thanks to smart overcurrent profile &

severe short-circuit protection

•

overtemperature protection including overtemperature warning

under and overvoltage protections

charge pump monitoring

reverse supply protection

In case a fault condition is detected, the corresponding output is commanded off immediately after the deglitch time t_{FAULT SD}

.

The turn off in case of a fault shutdown (OCHI1, OCHI2, OCHI3, OCLO, OTS, UV, CPF, OLOFF) is provided by the FTO feature

(fast turn off).

MC07XSF517

Analog Integrated Circuit Device Data

Freescale Semiconductor

27

The FTO:

•

does not use edge shaping

is provided with high slew rate to minimize the output turn-off time t_{OUTPUT SD}, in regards to the detected fault

uses a latch which keeps the FTO active during an undervoltage condition (0 < V_PWR< V_{PWR UVF}

)

Figure 11. Power Output Switching in Nominal Operation and In Case of Fault

Normal mode

In case of a fault condition during Normal mode

the status is reported in the quick status register #1 and the corresponding channel status register #2… #6.

To restart the output

•

the channel must be restarted by writing the corresponding ON bit in the channel control register #2… #6 or

output control register #8.

MC07XSF517

Analog Integrated Circuit Device Data

28

Freescale Semiconductor

OLOFF

OUTx = 1

(Ioutx > I oloff thres) or (t > t oloff)

(OLOFF ENx = 1)

(rewrite CHx=1) & (tochi1+tochi2< t <tochi1+tochi2+tochi3)

(rewrite CHx=1) & (tochi1< t<tochi1+tochi2)

[(set CHx=1) & (fault x=0)] or

[(rewrite CHx=1) & (t<tochi1)]

(t>tochi1 + tochi2)

& (faultx=0)

(t > tochi1) & (fault x=0)

off

OCHI1

OCHI2

OCHI3

OUTx = HSONx

OUT x = HSONx

OUTx = HSONx

OUTx = off

(CHx=0) or (fault x=1)

(OCLOx=1) & (OCHI ODx= 1)

(NO OCHIx=1) & (fault x=0)

(NO OCHIx =1) & (fault x=0)

(CHx=0) or (fault x=1)

OCLO

OUTx = HSONx

[(t > tochi1+tochi2+tochi3) & (fault x=0)] or

[(NO OCHIx=1) & (fault x=0)]

[(rewrite CHx=1) & (t>tochi1+tochi2+tochi3)] or

[(set CHx=1) & (NO OCHIx=1)]

Definitions of key logic signals:

remark:

(fault x):= (UV) or (OCHI1x) or (OCHI2x) or (OCHI3x) or (OCLOx) or (OTx) or (SSCx)

(set CHx=1):= [(ONx=0) then (ONx=1)] or [(iINx=0) then (iINx=1)]

(rewrite CHx=1):= (rewrite ONx=1) after (fault x=1)

SSCx:= severe short circuit detection

Figure 12. Output Control Diagram in Normal Mode

MC07XSF517

Analog Integrated Circuit Device Data

Freescale Semiconductor

29

Fail mode

In case of an overcurrent (OCHI2, OCHI3, OCLO) or undervoltage, the restart is controlled by the autorestart feature

I_threshold

I_OCHI2

driver turned off incaseof

fault_fail x ( =OC or UV)

event during autorestart

I_OCHI3

driver turned on againwith

OCHI2 after fault_fail x

I_OCLO

In case of successful autorestart

(nofault_fail x event)

time

OCLO remains active

t_OCHI2

t _AUTORESTART

Figure 13. Autorestart in Fail Mode

In case of overtemperature (OTSx), severe short-circuit (SSCx), or OCHI1 overcurrent, the corresponding output enters latch off

state until the next wake-up cycle or mode change.

auto

(INx_ON=0)

restart

autorestart x=1

OC_fail x=0

OUTx=off

(UV =1) or

(OCLOx=1)

(UV =1)

(UV =1) or

(OCHI3x=1)

(UV =1) or

(OCHI2x=1)

(UV=0) &

(t > t autorestart)

(t > tochi1+tochi2)

& (autorestart=1)

(INx _O N=1)

(INx_ON=0)

(t >tochi1+

tochi2+ tochi3)

off

OCHI1

OUTx=iINx

OCHI2

OUTx=iINx

OCHI3

OUTx=iINx

OCLO

OUTx=iINx

(t > tochi1+tochi2)

& (autorestart x=0)

(t > tochi1)

OUTx=off

autorestart x=0

(INx_ON=0)

(OTSx=1) or

(SSCx=1)

(OTSx=1) or

(SSCx=1)

(OTSx=1) or

(SSC x=1) or

(OCHI1x=1)

(OTSx=1) or

(SSCx=1)

latch

OFF

OUTx=off

Definition of key logic signals:

remark:

iINx:= external Inputs IN1~IN4 after deglitcher

SSCx := severe short circuit detection

Figure 14. Output Control Diagram in Fail Mode

MC07XSF517

Analog Integrated Circuit Device Data

30

Freescale Semiconductor

6.1.3.1

Overcurrent Protections

Each output channel is protected against overload conditions by use of a multilevel overcurrent shutdown.

current

I

OCHI1

I

OCHI2

Over Current Threshold Profile

OCHI3

I

OCLO

Lamp Current

tOCHI2

tOC HI3

tOC HI1

Figure 15. Transient Overcurrent Profile

The current thresholds and the threshold window times are fixed for each type of power channel.

When the output is in PWM mode, the clock for the OCHI time counters (t_OCHI1… t_OCHI3) is gated (logic AND) with the referring

output control signal:

•

the clock for the t_OCHIcounter is activated when the output = [1] respectively CHx = 1

the clock for the t_OCHIcounter is stopped when the output = [0] respectively CHx= 0

current

I

OCHI1

I

OCHI2

OCHI3

I

OCLO

time

cumulative

t

OCHI1

t

OCHI2

tO CHI3

Figure 16. Transient Over Current Profile in PWM mode

This strategy counts the OCHI time only when the bulb is actually heated up. The window counting is stopped in case of UV, CPF

and OTS.

A severe short-circuit protection (SSC) is implemented in order to limit the power dissipation in Normal and Fail modes, in case

of severe short-circuit event. This feature is active only for a very short period of time, during OFF-to-ON transition. The load

impedance is monitored during the output turn-on.

MC07XSF517

Analog Integrated Circuit Device Data

Freescale Semiconductor

31

Normal mode

The enabling of the high current window (OCHI1… OCHI3) is dependent on CHx signal.

When no control input pin is enabled, the control of the over current window depends on the ON bits inside channel control

registers #2… #7 or the output control register #8.

When the corresponding CHx signal is

•

toggled (turn OFF and then ON), the OCHI window counter is reset and the full OCHI windows are applied

current

IOCHI1

Overcurrent Threshold Profile

IOCHI2

IOCHI3

OCLO fault detection

IOCLO

Channel Current

time

ON bit =0

ON bit=1

Figure 17. Resetable Overcurrent Profile

•

rewritten (logic [1]), the OCHI window time is proceeding without reset of the OCHI counter

current

OCLO fault detection

IOCLO

time

ON bit=1 rewriting

Figure 18. Overcurrent Level Fixed to OCLO

Fail mode

The enabling of the high current window (OCHI1… OCHI3) is dependent on INx_ON toggle signal.

The enabling of output (OUT1… 5) is dependent on CHx signal.

MC07XSF517

Analog Integrated Circuit Device Data

Freescale Semiconductor

32

6.1.3.1.1

Over Current Control Programming

A set of overcurrent control programming functions are implemented to provide a flexible and robust system behavior:

HID Ballast Profile (NO_HID)

A smart overcurrent window control strategy is implemented to turn on an HID ballast, even in the case of a long power on reset

time.

When the output is in 100% PWM mode (including PWM clock failure in Normal mode and iINx=1 in Fail mode), the clock for the

OCHI2 time counter is divided by 8, when no load current is demanded from the output driver.

•

the clock for the t_OCHI2counter is divided by 8 when the open load signal is high (logic[1]), to accommodate the

HID ballast while in power on reset mode

•

the clock for the t_OCHI2counter is connected directly to the window time counter when the OpenLoad signal is

low (logic[0]), to accommodate the HID demanding load current from the output

current

IOCHI1

IOCHI2

Over Current Threshold Profile

IOCHI3

IOCLO

Channel Current

8 x tOCHI2

tOCHI3

time

tOCHI1

Figure 19. HID Ballast Overcurrent Profile

This feature extends the OCHI2 time, depending on the status of the HID ballast, and ensures to bypass even a long power on

reset time of HID ballast. Nominal t_OCHI2duration is up to 64 ms (instead of 8.0 ms).

This feature is automatically active at the beginning of smart overcurrent window, except for OCHI On Demand as described by

the following.

The functionality is controlled by the NO_HID1 and NO_HID0 bits inside the initialization #2 register.

When the NO_HID1 and NO_HID0 bits are respectively:

•

[0 0]: smart HID feature is available for all channels (default status and during Fail mode)

[0 1]: smart HID feature is available for channel 3 only

[1 0]: smart HID feature is available for channels 3 and 4 only

[1 1]: smart HID feature is not available for any channel

OCHI On Demand (OCHI OD)

In some instances, a lamp might be de-powered when its supply is interrupted by the opening of a switch (as in a door), or by

disconnecting the load (as in a trailer harness). In these cases, the driver should be tolerant of the inrush current that will occur

when the load is reconnected. The OCHI On Demand feature allows such control individually for each channel through the OCHI

ODx bits inside the Initialization #2 register.

MC07XSF517

Analog Integrated Circuit Device Data

Freescale Semiconductor

33

When the OCHI ODx bit is:

•

low (logic[0]), the channel operates in its Normal, Default mode. After end of OCHI window timeout the output is

protected with an OCLO threshold

•

high (logic[1], the channel operates in the OCHI On Demand mode and uses the OCHI2 and OCHI3 windows

and times after an OCLO event

To reset the OCHI ODx bit (logic[0]) and change the response of the channel, first change the bit in the Initialization #2 register

and then turn the channel off. The OCHI ODx bit is also reset after an overcurrent event at the corresponding output.

The fault detection status is reported in the quick status register #1 and the corresponding channel status registers #2… #6, as

presented in Figure 20.

current

solid line: nominal operation

OCHI2 fault reported

dotted lines: fault conditions

IOCHI2

OCHI3 fault reported

IOCHI3

OCLO fault reported

IOCLO

OCHI OD fault reported

tOCHI2

tOCHI3

time

Figure 20. OCHI On Demand Profile

OCLO Threshold Setting

The static overcurrent threshold can be programmed individually for each output in two levels to adapt low duty cycle dimming

and a variety of loads.

The CSNS recopy factor and OCLO threshold depend on OCLO and ACM settings.

The OCLO setting is controlled by the OCLOx bits inside the overcurrent control register #10-1.

When the OCLOx bit is

•

low (logic[0]), the output is protected with the higher OCLO threshold (default status and during Fail mode)

high (logic[1]), the lower OCLO threshold is applied

SHORT OCHI

The length of the OCHI windows can be shortened by a factor of 2, to accelerate the availability of the CSNS diagnosis and to

reduce the potential stress inside the switch during an overload condition.

The setting is controlled individually for each output by the SHORT OCHIx bits inside the overload control register #10-2.

When the SHORT OCHIx bit is

•

low (logic[0]), the default OCHI window times are applied (default status and during Fail mode)

high (logic[1]), the short OCHI window times are applied (50% of the regular OCHI window time)

NO OCHI

The switch on process of an output can be done without an OCHI window, to accelerate the availability of the CSNS diagnosis.

The setting is controlled individually for each channel by the NO OCHIx bits inside the overcurrent control register #10-2.

When the NO OCHIx bit is

•

low (logic[0]), the regular OCHI window is applied (default status and during Fail mode)

high (logic[1]), the turn on of the output is provided without OCHI windows

The NO OCHI bit is applied in real time. The OCHI window is left immediately when the NO OCHI is high (logic[1]).

MC07XSF517

Analog Integrated Circuit Device Data

Freescale Semiconductor

34

The overcurrent threshold i set to OCLO when:

•

the NO OCHIx bit is set to logic [1] while CHx is ON or

CHx turns ON if NO OCHIx is already set

THERMAL OCHI

To minimize the electro-thermal stress inside the device in case of a short-circuit, the OCHI1 level can be automatically adjusted

in regards to the control die temperature.

The functionality is controlled for all channels by the OCHI THERMAL bit inside the initialization 2.

When the OCHI THERMAL bit is:

•

low (logic[0]), the output is protected with default OCHI1 level

high (logic[1]), the output is protected with the OCHI1 level reduced by R_{THERMAL OCHI}= 15% (typ) when the

control die temperature is above T_{THERMAL OCHI}= 63 °C (typ)

TRANSIENT OCHI

To minimize the electro-thermal stress inside the device in case of a short-circuit, the OCHIx levels can be dynamically evaluated

during the OFF-to-ON output transition.

The functionality is controlled for all channels by the OCHI TRANSIENT bit inside the initialization 2 register.

When the OCHI TRANSIENT bit is:

•

low (logic[0]), the output is protected with default OCHIx levels

high (logic[1]), the output is protected with an OCHIx levels depending on the output voltage (V_OUT):

OCHIx level reduced by R_{TRANSIENT OCHI}= 50% typ for 0 < V_OUT< V_{OUT DETECT}(V_PWR/ 2 typ),

Default OCHIx level for V_{OUT DETECT}< V_OUT

•

In case the resistive load is less than V_{PWR OCHI1}, the overcurrent threshold will be exceeded before output reaches V_PWR/ 2,

/I

and the output current reaches I_OCHI1. The output is then switched off at much lower and safer currents.

When the load has significant series inductance, the output current transition falls behind voltage with L_LOAD/R_LOADconstant

time. The intermediate overcurrent threshold could not reach and the output current continues to rise up to OCHIx levels.

6.1.3.1.2

Electrical Characterization

Table 9. Electrical Characteristics

Characteristics noted under conditions 7.0V  V_PWR 18V, -40C  T_A 125C, GND = 0V, unless otherwise noted. Typical

values noted reflect the approximate parameter means at T_A= 25°C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min

Typ

Max

Unit Notes

POWER OUTPUTS OUT1… OUT5

High Overcurrent Level 1 for 7.0 m Power Channel

I_OCHI1

A

• T_J= -40 °C and 25 °C

100

96

111

106

126.5

• T_J= 150 °C

High Overcurrent Level 2 for 7.0 m Power Channel

I_OCHI2

A

• T_J= -40 °C and 25 °C

61.2

60

70

69

77.5

• T_J= 150 °C

High Overcurrent Level 3 for 7.0 m Power Channel

I_OCHI3

I_OCLO

34

39

43.5

A

Low Overcurrent for 7.0 m Power Channel

• High Level

17.6

8.8

21.9

10.8

26.4

13.2

• Low Level

Low Overcurrent for 7.0 m Power Channel in ACM Mode

I_{OCLO ACM}

A

• High Level

• Low Level

8.8

4.4

10.8

5.5

13.2

6.6

High Overcurrent Level 1 for 17 m Power Channel

I_OCHI1

• T_J= -40 °C and 25 °C

42

40

48

46

54.4

• T_J= 150 °C

MC07XSF517

Analog Integrated Circuit Device Data

Freescale Semiconductor

35

Table 9. Electrical Characteristics

Characteristics noted under conditions 7.0V  V_PWR 18V, -40C  T_A 125C, GND = 0V, unless otherwise noted. Typical

values noted reflect the approximate parameter means at T_A= 25°C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min

Typ

Max

Unit Notes

POWER OUTPUTS OUT1… OUT5 (Continued)

High Overcurrent Level 2 for 17 m Power Channel

I_OCHI2

I_OCHI3

I_OCLO

24.5

14.8

28.2

17.3

32.2

19.5

A

High Overcurrent Level 3 for 17 m Power Channel

Low Overcurrent for 17 m Power Channel

• High Level

8.8

4.4

10.8

5.3

13.2

6.6

• Low Level

Low Overcurrent for 17 m Power Channel in ACM Mode

I_{OCLO ACM}

A

• High Level

• Low Level

4.4

2.2

5.3

2.6

6.6

3.3

High Overcurrent Ratio 1

R_TRANSIENT

0.45

0.835

50

0.5

0.85

63

0.55

0.865

70

OCHI

High Overcurrent Ratio 2

R_THERMAL

OCHI

Temperature Threshold for IOCHI1 Level Adjustment

T_THERMAL

°C

OCHI

High Overcurrent Time 1

• Default Value

t_OCHI1

ms

1.5

2.0

1.0

2.5

• SHORT OCHI option

0.75

1.25

High Overcurrent Time 2

• Default Value

t_OCHI2

ms

6.0

3.0

8.0

4.0

10

• SHORT OCHI option

5.0

High Overcurrent Time 3

• Default Value

t_OCHI3

48

24

64

32

80

40

• SHORT OCHI option

Minimum Severe Short-circuit Detection

• 7.0 m Power Channel

R_{SC MIN}

m

5.0

10

–

• 17 m Power Channel

(18)

Fault Deglitch Time

t_{fault SD}

µs

• OCLO and OCHI OD

• OCHI1… 3 and SSC

1.0

2.0

3.0

Fault Autorestart Time in Fail Mode

Fault Blanking Time after Wake-up

t_autorestart

t_BLANKING

Notes

48

–

64

50

80

ms

µs

100

18. Guaranteed by testmode.

6.1.3.2

Overtemperature Protection

A dedicated temperature sensor is located on each power transistor, to protect the transistors and provide SPI status monitoring.

The protection is based on a two stage strategy.

When the temperature at the sensor exceeds the:

•

selectable overtemperature warning threshold (T_OTW1, T_OTW2), the output stays on and the event is reported in

the SPI

•

overtemperature threshold (T_OTS), the output is switched off immediately after the deglitch time t_{FAULT SD}and the

event is reported in the SPI after the deglitch time t_{FAULT SD}

.

MC07XSF517

Analog Integrated Circuit Device Data

36

Freescale Semiconductor

6.1.3.2.1

Overtemperature Warning (OTW)

In case of overtemperature warning:

•

the output remains in current state

the status is reported in the quick status register #1 and the corresponding channel status register #2… #6

The OTW threshold can be selected by the OTW SEL bit inside the initialization 2 register #1.

When the bit is:

•

low (logic[0]), the high overtemperature threshold is enabled (default status)

high (logic[1]), the low overtemperature threshold is enabled

To delatch the OTW bit (OTWx):

•

the temperature has to drop below the corresponding overtemperature warning threshold

a read command of the corresponding channel status register #2… #6 must be performed

6.1.3.2.2

Overtemperature Shutdown (OTS)

During an overtemperature shutdown:

•

the corresponding output is disabled immediately after the deglitch time t_{FAULT SD}

the status is reported after t_{FAULT SD}in the quick status register #1 and the corresponding channel status register

#2… #6.

To restart the output after an overtemperature shutdown event in Normal mode:

•

the overtemperature condition must be removed, and the channel must be restarted by a write command of the

ON bit in the corresponding channel control register #2… #6, or in the output control register #8

To delatch the diagnosis:

•

the overtemperature condition must be removed:

a read command of the corresponding channel status register #2… #6 must be performed

To restart the output after an overtemperature shutdown event in Fail mode:

•

a mode transition is needed. Refer to Mode Transitions section

6.1.3.2.3

Electrical Characterization

Table 10. Electrical Characteristics

Characteristics noted under conditions 7.0 V  V_PWR 18 V, -40 C  T_A 125 C, GND = 0 V, unless otherwise noted. Typical

values noted reflect the approximate parameter means at T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min

Typ

Max

Unit Notes

POWER OUTPUTS OUT1… OUT5

(19)

Overtemperature Warning

• T_OW1level

T_OW

°C

100

120

115

135

130

150

• T_OW2level

(19)

Overtemperature Shutdown

T_OTS

155

2.0

170

5.0

185

10

°C

Fault Deglitch Time

• OTS

t_{FAULT SD}

µs

Notes

19. Guaranteed by testmode.

MC07XSF517

Analog Integrated Circuit Device Data

Freescale Semiconductor

37

6.1.3.3

Undervoltage and Overvoltage Protections

Undervoltage

6.1.3.3.1

During an undervoltage condition (V_PWRPOR< V_PWR< V_{PWR UVF}), all outputs (OUT1… OUT5) are switched off immediately after

deglitch time t_{FAULT SD}

The undervoltage condition is reported after the deglitch time t_{FAULT SD}

.

•

in the device status flag (DSF) in the registers #1… #7

in the undervoltage flag (UVF) inside the device status register #7

Normal mode

The reactivation of the outputs is controlled by the microcontroller.

To restart, the output the undervoltage condition must be removed and:

•

a write command of the ON Bit must be performed in the corresponding channel control register #2… #6 or in the

output control register #8

To delatch the diagnosis

•

the undervoltage condition must be removed

a read command of the device status register #7 must be performed

Fail mode

When the device is in Fail mode, the restart of the outputs is controlled by the autorestart feature.

6.1.3.3.2

Overvoltage

The device is protected against overvoltage on V_PWR

.

During:

•

jump start condition, the device may be operated, but with respect to the device limits

load dump condition (V_{PWR LD MAX}= 40 V) the device does not conduct energy to the loads

The overvoltage condition (V_PWR> V_{PWR OVF}) is reported in the

•

device status flag (DSF) in the registers #1… #7

overvoltage flag (OVF) inside the device status register #7

To delatch the diagnosis

•

the overvoltage condition must be removed

a read command of the device status register #7 must be performed

In case of an overvoltage (V_PWR> V_{PWR HIGH}), the device is not “short-circuit“ proof

6.1.3.3.3

Electrical Characterization

Table 11. Electrical Characteristics

Characteristics noted under conditions 7.0 V  V_PWR 18 V, -40 C  T_A 125 C, GND = 0 V, unless otherwise noted. Typical

values noted reflect the approximate parameter means at T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min

Typ

Max

Unit Notes

SUPPLY VPWR

Supply Undervoltage

Supply Undervoltage Hysteresis

V_{PWR UVF}

5.0

5.25

350

5.5

V

V_{PWR UVF}

200

500

mV

HYS

Supply Overvoltage

V_{PWR OVF}

28

30

32

V

Supply Overvoltage Hysteresis

V_{PWR OVF}

0.5

1.0

1.5

HYS

Supply Load Dump Voltage (2.0 min at 25 °C)

V_{PWR LD MAX}

40

–

V

MC07XSF517

Analog Integrated Circuit Device Data

38

Freescale Semiconductor

Table 11. Electrical Characteristics

Characteristics noted under conditions 7.0 V  V_PWR 18 V, -40 C  T_A 125 C, GND = 0 V, unless otherwise noted. Typical

values noted reflect the approximate parameter means at T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min

Typ

Max

Unit Notes

SUPPLY VPWR (Continued)

Maximum Supply Voltage for Short-circuit Protection

V_{PWR HIGH}

t_{FAULT SD}

32

–

V

Fault Deglitch Time

• UV and OV

µs

2.0

3.5

5.5

6.1.3.4

Charge Pump Protection

The charge pump voltage is monitored in order to protect the smart switches in case of:

•

power up

failure of external capacitor

failure of charge pump circuitry

During power up, when the charge pump voltage has not yet settled to its nominal output voltage range, the outputs can not be

turned on. Any turn on command during this phase is executed immediately after settling of the charge pump.

When the charge pump voltage is not within its nominal output voltage range:

•

the power outputs are disabled immediately after the deglitch time t_{FAULT SD}

the failure status is reported after t_{FAULT SD}in the device status flag DSF in the registers #1… #7 and the CPF in

the quick status register #1

•

Any turn on command during this phase is executed including the OCHI windows immediately after the charge

pump output voltage has reached its valid range

To delatch the diagnosis:

•

the charge pump failure condition must be removed

a read command of the quick status register #1 is necessary

6.1.3.4.1

Electrical Characterization

Table 12. Electrical Characteristics

Characteristics noted under conditions 7.0 V  V_PWR 18 V, -40 C  T_A 125 C, GND = 0 V, unless otherwise noted. Typical

values noted reflect the approximate parameter means at T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min

Typ

Max

Unit Notes

CHARGE PUMP CP

Charge Pump Capacitor Range (Ceramic type X7R)

Maximum Charge Pump Voltage

C_CP

47

–

220

16

nF

V

V_{CP MAX}

t_{FAULT SD}

Fault Deglitch Time

• CPF

µs

–

4.0

6.0

6.1.3.5

Reverse Supply Protection

The device is protected against reverse polarity of the V_PWRline.

In reverse polarity condition:

•

the output transistors OUT1… 5 are turned ON in order to prevent the device from thermal overload

the OUT6 pin is pulled down to GND. An external current limit resistor shall be added in series with OUT6 pin

no output protection is available in this condition

MC07XSF517

Analog Integrated Circuit Device Data

Freescale Semiconductor

39

6.1.4 Output Clamps

6.1.4.1

Negative Output Clamp

In case of an inductive load (L), the energy is dissipated after the turn-off inside the N-channel MOSFET.

When t_CL(=Io x L / V_CL) > 1.0 ms, the turn-off waveform can be simplified with a rectangle as shown in Figure 21.

Output Current

Io

time

tCL

Output Voltage

V

BAT

PWR

time

VVCL

PWR

Figure 21. Simplified Negative Output Clamp Waveform

The energy dissipated in the N-Channel MOSFET is: E_CL= 1/2 x L x Io² x (1+ V_PWR/ |V_CL|).

In the case of t_CL< 1.0 ms, please contact the factory for guidance.

6.1.4.2

Supply Clamp

The device is protected against dynamic overvoltage on the V_PWRline by means of an active gate clamp, which activates the

output transistors in order to limit the supply voltage (V_DCClamp).

In case of an overload on an output the corresponding switch is turned off, which leads to high voltage at V_PWRwith an inductive

V_PWRline. The maximum V_PWRvoltage is limited at V_DCCLAMPby active clamp circuitry through the load.

In case of an OpenLoad condition, the positive transient pulses (acc. automotive specification ISO 7637 / pulse 2 and inductive

supply line) shall be handled by the application. In case of negative transients on the V_PWRline (acc. ISO7637-2 / pulse 1), the

energy of the pulses are dissipated inside the load, or shall be drained by an external clamping circuit, during a high ohmic load.

6.1.4.3

Electrical Characterization

Table 13. Electrical Characteristics

Characteristics noted under conditions 7.0 V  V_PWR 18 V, -40 C  T_A 125 C, GND = 0 V, unless otherwise noted. Typical

values noted reflect the approximate parameter means at T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min

Typ

Max

Unit Notes

SUPPLY VPWR

Supply Clamp Voltage

V_DCCLAMP

41

–

50

V

POWER OUTPUTS OUT1… OUT5

Negative Power Channel Clamp Voltage

V_CL

• 7.0 m

• 17 m

-20.5

-21

–

-17.5

-18

MC07XSF517

Analog Integrated Circuit Device Data

40

Freescale Semiconductor

6.1.5 Digital Diagnostics

The device offers several modes for load status detection in on state and off state through SPI.

6.1.5.1

OpenLoad Detections

OpenLoad in ON State

6.1.5.1.1

OpenLoad detection during ON state is provided for each power output (OUT1… OUT5), based on the current monitoring circuit.

The detection is activated automatically when the output is in on state.

The detection threshold is dependent on:

•

the OLLED EN bits inside the OLLED control register #13-2

The detection result is reported in:

•

the corresponding QSFx bit in the quick status register #1

the global open load flag OLF (registers #1… #7)

the OLON bit of the corresponding channel status registers #2… #6

To delatch the diagnosis:

•

the openload condition must be removed

a read command of the corresponding channel status register #2… #6 must be performed

When an open load has been detected, the output remains in on state.

The deglitch time of the OpenLoad in on state can be controlled individually for each output in order to be compliant with different

load types.

The setting is dependent on the OLON DGL bits inside the OpenLoad control register #13-1:

•

low (logic[0]) the deglitch time is t_{OLON DGL}= 64 µs typ (bulb mode)

high (logic[1]) the deglitch time is t_{OLON DGL}= 2.0 ms typ (converter mode)

The deglitching filter is reset whenever output falls low and is only active when the output is high.

6.1.5.1.2

OpenLoad in ON State for LED

For detection of small load currents (e.g. LED) in on state of the switch a special low current detection mode is implemented by

using the OLLED EN bit.

The detection principle is based on a digital decision during regular switch off of the output.

Thereby a current source (I_OLLED) is switched on and the falling edge of the output voltage is evaluated by a comparator at 

V_PWR- 0.75 V (typ).

V_PWR

Figure 22. OpenLoad in ON State Diagram for LED

MC07XSF517

Analog Integrated Circuit Device Data

Freescale Semiconductor

41

The OLLED fault is reported when the output voltage is above V_PWR- 0.75 V after 2.0 ms off-time or at each turn-on command

in case of off-time < 2.0 ms.

The detection mode is enabled individually for each channel with the OLLED EN bits inside the LED control register #13-2.

When the corresponding OLLED EN bit is:

•

low (logic[0]), the standard OpenLoad in on state (OLON) is enabled

high (logic[1]), the OLLED detection is enabled

The detection result is reported in:

•

the corresponding QSFx bit in the quick status register #1

the global open load flag OLF (register #1… #7)

the OLON bit of the corresponding channel status register #2… #6

When an OpenLoad has been detected, the output remains in on state.

When output is in PWM operation:

•

the detection is performed at the end of the on time of each PWM cycle

the detection is active during the off time of the PWM signal, up to 2.0 ms max.

The current source (I_OLLED) is disabled after “no OLLED” detection or after 2.0 ms.

hson_1

128*DCLOCK (prescaler=‘0’)

En_OLLed_1

OUT_1

V_{PWR - 0.75}

V_BAT-0.75

OUT_high

check

Analog Comparator output

1 : olled detected

0 : no olled detected

TimeOut = 2.0 msec

Figure 23. OpenLoad in ON State for LED in PWM Operation (OFF time > 2.0 ms)

MC07XSF517

Analog Integrated Circuit Device Data

Freescale Semiconductor

42

hson_1

128*DCLOCK(prescaler=‘0’)

En_OLLed_1

OUT_1

V_{PWR - 0.75}

V_BAT-0.75

OUT_high

check

Analog Comparator output

1 : olled detected

0 : no olled detected

TimeOut = 2.0 msec

Figure 24. Openload in ON State for LED in PWM Operation (OFF time < 2.0 ms)

When output is in fully ON operation (100% PWM):

•

the detection on all outputs is triggered by setting the OLLED TRIG bit inside the LED control register #13-2

at the end of detection time, the current source (I_OLLED) is disabled 100 µsec (typ.) after the output reactivation

OLLED TRIG 1

Note: OLLED TRIG bit is reset after the detection

ONoff & PWM

hson_1

FF

100 sec

En_OLLed_1

V_{PWR - 0.75}

V_BAT-0.75

OUT_1

check

OUT_high

Analog Comparator output

Check

Precision ~9600 ns

1 : olled detected

0 : no olled detected

TimeOut = 2.0 msec

Figure 25. Openload in ON State for LED in Fully ON Operation

The OLLED TRIG bit is reset after the detection.

To delatch the diagnosis:

•

a read command of the corresponding channel status register #2… #6 must be performed

A false “open” result could be reported in the OLON bit:

•

for high duty cycles, the PWM off-time becomes too short

for capacitive load, the output voltage slope becomes too slow

MC07XSF517

Analog Integrated Circuit Device Data

Freescale Semiconductor

43

6.1.5.1.3

OpenLoad in OFF State

An OpenLoad in off state detection is provided individually for each power output (OUT1… OUT5).

The detection is enabled individually for each channel by the OLOFF EN bits inside the open load control register #13-1.

When the corresponding OLOFF EN is:

•

low (logic[0]), the diagnosis mode is disabled (default status)

high (logic[1]), the diagnosis mode is started for t_OLOFF. It is not possible to restart any OLOFF or disable the

diagnosis mode during active OLOFF state

This detection can be activated independently for each power output (OUT1… OUT5). When it is activated, it is always activated

synchronously for all selected outputs (with positive edge of CS\).

When the detection is started, the corresponding output channel is turned on with a fixed overcurrent threshold of I_OLOFF

threshold.

When this overcurrent threshold is:

•

reached within the detection timeout t_OLOFF, the output is turned off and the OLOFF EN bit is reset. No OCLOx

and no OLOFFx will be reported.

•

not reached within the detection timeout t_OLOFF, the output is turned off after t_OLOFFand the OLOFF EN bit is

reset. The OLOFFx will be reported.

The overcurrent behavior as commanded by the overcurrent control settings (NO OCHIx, OCHI ODx, SHORTOCHIx, OCLOx,

and ACM ENx) is not be affected by applying the OLOFF ENx bit. The same is true for the output current feedback and the current

sense synchronization.

The detection result is reported in:

•

the corresponding QSFx bit in the quick status register #1

the global open load flag OLF (register #1… #7)

the OLOFF bit of the corresponding channel status register #2… #6

To delatch the diagnosis, a read command of the corresponding channel status register #2… #6 must be performed.

In case any fault during t_OLOFF(OTS, UV, CPF,), the OpenLoad in off state detection is disabled and the output(s) is (are) turned

off after the deglitch time t_{FAULT SD}. The corresponding fault is reported in the SPI SO registers.

6.1.5.1.4

Electrical Characterization

Table 14. Electrical Characteristics

Characteristics noted under conditions 7.0 V  V_PWR 18 V, -40 C  T_A 125 C, GND = 0 V, unless otherwise noted. Typical

values noted reflect the approximate parameter means at T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min

Typ

Max

Unit Notes

POWER OUTPUTS OUT1… OUT5

Openload Current Threshold in ON State

I_OL

mA

• 7.0 m Power Channel at T_J= -40 °C

50

100

30

200

100

350

300

160

150

• 7.0 m Power Channel at T_J= 25 °C and 125 °C

• 17 m Power Channel at T_J= -40 °C

50

• 17 m Power Channel at T_J= 25 °C and 125 °C

Output PWM Duty Cycle Range for Openload Detection in ON state

• Low Frequency Range (25 to 100 Hz)

_{PWM OLON}

LSB

18

17

–

• Medium Frequency Range (100 to 200 Hz)

• High Frequency Range (200 to 400 Hz)

Openload Current Threshold in ON state / OLLED mode

Maximum Openload Detection Time / OLLED mode with 100% duty cycle

Openload Detection Time in OFF State

I_OLLED

t_OLLED100

t_OLOFF

2.0

1.5

0.9

4.0

2.0

1.2

5.0

2.6

1.5

mA

ms

MC07XSF517

Analog Integrated Circuit Device Data

44

Freescale Semiconductor

Table 14. Electrical Characteristics

Characteristics noted under conditions 7.0 V  V_PWR 18 V, -40 C  T_A 125 C, GND = 0 V, unless otherwise noted. Typical

values noted reflect the approximate parameter means at T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min

Typ

Max

Unit Notes

POWER OUTPUTS OUT1… OUT5 (Continued)

Fault Deglitch Time

t_{FAULT SD}

• OLOFF

2.0

48

3.3

64

5.0

80

µs

ms

• OLON with OLON DGL = 0

• OLON with OLON DGL = 1

1.5

2.0

2.5

Openload Current Threshold in OFF state

I_OLOFF

0.385

0.55

0.715

A

6.1.5.2

Output Shorted to VPWR in OFF State

A short to V_PWRdetection during OFF state is provided individually for each power output OUT1… OUT5, based on an output

voltage comparator referenced to V_PWR/ 2 (V_{OUT DETECT}) and an external pull-down circuitry.

The detection result is reported in the OUTx bits of the I/O status register #8 in real time.

In case of UVF, the OUTx bits are undefined.

6.1.5.2.1

Electrical Characterization

Table 15. Electrical Characteristics

Characteristics noted under conditions 7.0 V  V_PWR 18 V, -40 C  T_A 125 C, GND = 0 V, unless otherwise noted. Typical

values noted reflect the approximate parameter means at T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min

Typ

Max

Unit Notes

POWER OUTPUTS OUT1… OUT5

Output Voltage Comparator Threshold

V_{OUT detect}

0.42

0.5

0.58

V_PWR

6.1.5.3

SPI Fault Reporting

Protection and monitoring of the outputs during normal mode is provided by digital switch diagnosis via the SPI.

The selection of the SO data word is controlled by the SOA0… SOA3 bits inside the initialization 1 register #0.

The device provides two different reading modes, depending on the SOA MODE bit.

When the SOA MODE bit is:

•

low (logic[0]), the programmed SO address will be used for a single read command. After the reading the SO

address returns to quick status register #1 (default state)

•

high (logic[1]), the programmed SO address will be used for the next and all further read commands until a new

programming

The “quick status register” #1 provides one glance failure overview. As long as no failure flag is set (logic[1]), no control action

by the microcontroller is necessary.

Register

SO address

SO data

#

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

quick status

1

0

1

FM

DSF

OVLF

OLF

CPF

RCF

CLKF

QSF5

QSF4

QSF3

QSF2

QSF1

•

FM: Fail mode indication. This bit is also present in all other SO data words, and indicates the fail mode by a

logic[1]. When the device is in Normal mode, the bit is logic[0]

•

global device status flags (D10… D8): These flags are also present in the channel status registers #2… #6, the

device status register #7, and are cleared when all fault bits are cleared by reading the registers #2… #7

MC07XSF517

Analog Integrated Circuit Device Data

Freescale Semiconductor

45

•

DSF = device status flag (RCF, or UVF, or OVF, or CPF, or CLKF, or TMF). UVF and TMF are also reported in the

device status register #7

•

OVLF = over load flag (wired OR of all OC and OTS signals)

OLF = openload flag

CPF: charge pump flag

RCF: registers clear flag: this flag is set (logic[1]) when all SI and SO registers are reset

CLKF: clock fail flag. Refer to Logic I/O Plausibility Check section

QSF1… QSF5: channel quick status flags (QSFx = OC0x, or OC1x, or OC2x, or OTWx, or OTSx, or OLONx, or

OLOFFx)

The SOA address #0 is also mapped to register #1 (D15… D12 bits will report logic [0001]).

When a fault condition is indicated by one of the quick status bits (QSF1… QSF5, OVLF, OLF), the detailed status can be

evaluated by reading of the corresponding channel status registers #2… #6.

Register

SO address

SO data

#

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

2

0

1

0

1

F M

DSF

OVLF

OLF

res

OTS1

OTS2

OTW1

OTW2

OC21

OC22

OC11

OC12

OC01

OC02

OLON1 OLOFF 1

OLON2 OLOFF 2

CH 1 status

CH 2 status

3

4

0

1

0

F M

DSF

OVLF

OLF

res

OTS3

OTW3

OC23

OC13

OC03

OLON3 OLOFF 3

CH 3 status

CH 4 status

5

6

0

1

0

1

0

F M

DSF

OVLF

OLF

res

OTS4

OTS5

OTW4

OTW5

OC24

OC25

OC14

OC15

OC04

OC05

OLON4 OLOFF 4

OLON5 OLOFF 5

CH 5 status

•

OTSx: overtemperature shutdown flag

OTWx: overtemperature warning flag

OC0x… OC2x: overcurrent status flags

OLONx: OpenLoad in on state flag

OLOFFx: OpenLoad in off state flag

The most recent OC fault is reported by the OC0x… OC2x bits, if a new OC occurs before an old OC on the same output that

was read.

When a fault condition is indicated by one of the global status bits (FM, DSF), the detailed status can be evaluated by reading of

the device status registers #7:

Register

SO address

SO data

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

#

7

0

1

FM

DSF

OVLF

OLF

res

TMF

OVF

UVF

SPIF

iLIMP

device status

•

TMF: testmode activation flag. Testmode is used for manufacturing testing only. If this bit is set to logic [1], the

MCU shall reset the device.

•

OVF: overvoltage flag

UVF: undervoltage flag

SPIF: SPI fail flag

iLIMP (real time reporting after the t_{IN_DGL}, not latched)

The I/O status register #8 can be used for system test, fail mode test and the power down procedure:

Register

SO address

SO data

#

D15

D14

D13

D12

D11

D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

8

1

0

FM

res

TOGGLE

iIN4

iIN3

iIN2

iIN1

OUT5

OUT4

OUT3

OUT2

OUT1

I/O stat us

MC07XSF517

Analog Integrated Circuit Device Data

46

Freescale Semiconductor

The register provides the status of the control inputs, the toggle signal, and the power outputs state in real time (not latched).

•

TOGGLE = status of the 4 input toggle signals (IN1_ON, or IN2_ON, or IN3_ON, or IN4_ON), reported in real time

iINx = status of iINx signal (real time reporting after the t_{IN_DGL}, not latched)

OUTx = status of output pins OUTx (the detection threshold is V_PWR/2) when undervoltage condition does not

occur

The device can be clearly identified by the device ID register #9 when the supply voltage is within its nominal range:

Register

SO address

SO data

#

D15

D14

D13

D12

D11

D10

D9

D8

D 7

D 6

D5

D4

D3

D2

D1

D0

DEVID

7

DEVID

6

DEVID

5

DEVID

4

DEVID

3

DEVID

2

DEVID

1

DEVID

0

device ID

9

1

0

1

X

#2~#6

OC2x OC1x OC0x over currentstatus

0

1

0

1

0

1

0

1

0

1

0

1

0

1

no ov erc urrent

OCHI1

OCHI2

OCHI3

OCLO

OCHIOD

SSC

not us ed

The register delivers DEVIDx bits = 40hex for the 07XSF517.

During undervoltage condition (UVF = 1), DEVIDx bits report 00hex.

6.1.6 Analog Diagnostics

The analog feedback circuit (CSNS) is implemented to provide load and device diagnostics during Normal mode. During Fail and

Sleep modes, the analog feedback is not available.

The routing of the integrated multiplexer is controlled by MUX0… MUX2 bits inside the initialization 1 register #0.

6.1.6.1

Output Current Monitoring

The current sense monitor provides a current proportional to the current of the selected output (OUT1… OUT5). CSNS output

delivers 1.0 mA full scale range current source reporting channel 1… 5 current feedback (I_FSR).

I_CSNS

1.0 mA

I_CSNS/ I_OUT= 1.0 mA / (100% FSR) typ

Note: FSR value depends on SPI setting

I_OUT

0 mA

1% FSR

Figure 26. Output Current Sensing

100% FSR

MC07XSF517

Analog Integrated Circuit Device Data

Freescale Semiconductor

47

The feedback is suppressed during OCHI window (t < t_OCHI1+ t_OCHI2+ t_OCHI3) and only enabled during low overcurrent shutdown

threshold (OCLO).

During PWM operation, the current feedback circuit (CSNS) delivers current only during the on time of the output switch.

Current sense settling time, t_CSNS(SET), varies with current amplitude. Current sense valid time, t_CSNS(VAL), depends on the PWM

frequency (see Electrical Characterization).

An advanced current sense mode (ACM) is implemented in order to diagnose LED loads in Normal mode and to improve current

sense accuracy for low current loads.

In the ACM mode, the offset sign of current sense amplifier is toggled on every CSNS SYNCB rising edge.

The error amplifier offset contribution to the CSNS error can be fully eliminated from the measurement result by averaging each

two sequential current sense measurements.

The ACM mode is enabled with the ACM ENx bits inside the ACM control register #10-1.

When the ACM ENx bit is:

•

low (logic[0]), ACM disabled (default status and during Fail mode)

high (logic[1]), ACM enabled

In ACM mode:

•

the precision of the current recopy feature (CSNS) is improved especially at low output current by averaging

CSNS reporting on sequential PWM periods

•

the current sense full scale range (FSR) is reduced by a factor of two

the overcurrent protection threshold OCLO is reduced by a factor of two

Figure 27 describes the timings between the selected channel current and the analog feedback current. Current sense validation

time pertains to stabilization time needed after turn on. Current sense settling time pertains to the stabilization time needed after

the load current changes while the output is continuously on or when another output signal is selected.

HSONx

time

tDLY(ON)

tDLY(OFF)

IOUTx

tCSNS(SET)

tCSNS(VAL)

CSNS

+/- 5% of new value

Figure 27. Current Sensing Response Time

Internal circuitry limits the voltage of the CSNS pin when its sense resistor is absent. This feature prevents damage to other

circuitry sharing that electrical node, such as a microcontroller pin, for example.

Several 07XSF517 may be connected to one shared CSNS resistor.

MC07XSF517

Analog Integrated Circuit Device Data

48

Freescale Semiconductor

6.1.6.2

Supply Voltage Monitoring

The V_PWRmonitor provides a voltage proportional to the supply tab. The CSNS voltage is proportional to the V_PWRvoltage as

shown in Figure 28.

V_CSNS

5.0 V

V_CSNS/ V_PWR= ¼ typ

VPWR

0 V

VPWRPOR

20 V

Figure 28. Supply Voltage Reporting

6.1.6.3

Temperature Monitoring

The average temperature of the control die is monitored by an analog temperature sensor. The CSNS pin can report the voltage

of this sensor.

The chip temperature monitor output voltage is independent of the resistor connected to the CSNS pin, provided the resistor is

within the min/max range of 5.0 k to 50 k. Temperature feedback range, T_FB, -40 °C to 150 °C.

V_CSNS

V_CSNS/ T_J= V_FBS

VFB

T_J

25°C

Figure 29. Temperature Reporting

-40°C

150°C

MC07XSF517

Analog Integrated Circuit Device Data

Freescale Semiconductor

49

6.1.6.4

Analog Diagnostic Synchronization

A current sense synchronization pin is provided to simplify the synchronous sampling of the CSNS signal.

The CSNS SYNCB pin is an open drain requiring an external 5.0 k (min) pull-up resistor to V_CC

.

The CSNS SYNC signal is

•

available during Normal mode only

behavior depends on the type of signal selected by the MUX2 … MUX0 bits in the initialization 1 register #0. This

signal is either a current proportional to an output current or a voltage proportional to temperature or the supply

voltage

Current sense signal

When a current sense signal is selected:

•

the pin delivers a recopy of the output control signal during on phase of the PWM defined by the SYNC EN0,

SYNC EN1 bits inside the initialization 1 register #0

.

OUT1

OUT2

time

CSNS SYNC\ blanked

CSNS SYNC\

active (low)

CSNS

SYNCB

t_DLY(ON)+t_CSNS(SET)

change of CSNS MUX

from OUT1 to OUT2

OUT1 for

OUT2 for CSNS selected

CSNS selected

Figure 30. CSNS SYNC\ Valid Setting

MC07XSF517

Analog Integrated Circuit Device Data

50

Freescale Semiconductor

OUT1

OUT2

time

CSNS SYNC\ blanked until

rising edge of the 1^st

complete PWM cycle

CSNS

SYNC\

change of CSNS MUX

from OUT1 to OUT2

OUT1 for

OUT2 for CSNS selected

CSNS selected

Figure 31. CSNS SYNC\ TRIG0 Setting

OUT1

OUT2

time

CSNS SYNC\ blanked until 1^rstvalid edge

generated in the middle of the OUT2 pulse

CSNS

SYNC\

change of CSNS MUX

from OUT1 to OUT2

OUT1 for

OUT2 for CSNS selected

CSNS selected

Figure 32. CSNS SYNC\ TRIG1/2 Setting

the CSNS SYNC\ pulse is suppressed during OCHI and during OFF phase of the PWM

the CSNS SYNC\ is blanked during settling time of the CSNS multiplexer and ACM switching by a fixed time of

_dly(on)+ t_CSNS(SET)

•

t

MC07XSF517

Analog Integrated Circuit Device Data

Freescale Semiconductor

51

•

when a PWM clock fail is detected, the CSNS SYNCB delivers a signal with 50% duty cycle at a fixed period of

6.5 ms.

when the output is programmed with 100% PWM, the CSNS SYNCB delivers a logic[0] a high pulse with the

length of 100 µs (typ.) during the PWM counter overflow for TRIG0 and TRIG1/2 settings, as shown in Figure 33.

OUT1

time

OUT2

time

CSNS

SYNC\

t_DLY(ON)+t_CSNS(SET)

time

change of CSNS MUX

from OUT1 to OUT2

OUT1 for

OUT2 for CSNS selected

CSNS selected

Figure 33. CSNS SYNC\ when the output is programmed with 100%

•

In case of output fault, the CSNS SYNCB signal for current sensing does not deliver a trigger signal until the

output is enabled again.

Temperature signal or V_PWRmonitor signal

When a voltage signal (average control die temperature or supply voltage) is selected:

•

the CSNS SYNCB delivers a signal with 50% duty cycle and the period of the lowest prescaler setting 

(f_CLK/ 1024).

•

and a PWM clock fail is detected, the CSNS SYNC\ delivers a signal with 50% duty cycle at a fixed period of

6.5 ms (t_{SYNC DEFAULT}).

6.1.6.5

Electrical Characterization

Table 16. Electrical Characteristics

Characteristics noted under conditions 7.0 V  V_PWR 18 V, -40 C  T_A 125 C, GND = 0 V, unless otherwise noted. Typical

values noted reflect the approximate parameter means at T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min

Typ

Max

Unit Notes

CURRENT SENSE CSNS

Current Sense Resistor Range

R_CSNS

I_{CSNS LEAK}

V_CS

5.0

-1.0

6.0

–

50

+1.0

8.0

k

µA

V

Current Sense Leakage Current when CSNS is disabled

Current Sense Clamp Voltage

MC07XSF517

Analog Integrated Circuit Device Data

52

Freescale Semiconductor

Table 16. Electrical Characteristics

Characteristics noted under conditions 7.0 V  V_PWR 18 V, -40 C  T_A 125 C, GND = 0 V, unless otherwise noted. Typical

values noted reflect the approximate parameter means at T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min

Typ

Max

Unit Notes

CURRENT SENSE CSNS (Continued)

Current Sense Full Scale Range for 7.0 m Power Channel

• High OCLO and ACM = 0

I_FSR

A

–

22

11

5.5

–

• Low OCLO and ACM = 0

• High OCLO and ACM = 1

• Low OCLO and ACM = 1

Current Sense Accuracy for 9.0 V < V_PWR< 18 V for 7.0 m Power

ACC I_CSNS

%

Channel

-11

-14

-20

-29

–

+11

+14

+20

+29

• I_OUT= 80% FSR with ACM = 0

• I_OUT= 25% FSR with ACM = 0

• I_OUT= 10% FSR with ACM = 0

• I_OUT= 5.0% FSR with ACM = 0

-14

-18

-25

-40

-16

-22

-40

-60

–

+14

+18

+25

+40

+16

+22

+40

+60

• I_OUT= 80% FSR with High OCLO and ACM = 1

• I_OUT= 25% FSR with High OCLO and ACM = 1

• I_OUT= 10% FSR with High OCLO and ACM = 1

• I_OUT= 5.0% FSR with High OCLO and ACM = 1

• I_OUT= 80% FSR with Low OCLO and ACM = 1

• I_OUT= 25% FSR with Low OCLO and ACM = 1

• I_OUT= 10% FSR with Low OCLO and ACM = 1

• I_OUT= 5.0% FSR with Low OCLO and ACM = 1

(24) (22)

Current Sense Accuracy for 9.0 V < V_PWR< 18 V with 1 calibration point at

ACC I_{CSNS 1}

%

25 °C for 50% FSR and V_PWR= 14 V for 7.0 m Power Channel

CAL

• I_OUT= 80% FSR

• I_OUT= 25% FSR

• I_OUT= 10% FSR

• I_OUT= 5.0% FSR

-7.0

-20

-29

–

+7.0

+20

+29

(24) (22)

Current Sense Accuracy for 9.0 V < V_PWR< 18 V with 2 calibration points

at 25 °C for 2.0% and 50% FSR and V_PWR= 14 V for 7.0 m Power

Channel

ACC I_{CSNS 2}

%

CAL

-6.0

-8.0

-21

–

+6.0

+8.0

+21

• I_OUT= 80% FSR

• I_OUT= 25% FSR

• I_OUT= 10% FSR

• I_OUT= 5.0% FSR

Minimum Current Sense Reporting for 17 m

I_CSNSMIN

%

A

• 9.0 V < V_PWR< 12 V

–

2.0

3.0

• 9.0 V < V_PWR< 18 V

Current Sense Full Scale Range for 17 m Power Channel

• High OCLO and ACM = 0

I_FSR

–

11

5.5

–

• Low OCLO and ACM = 0

• High OCLO and ACM = 1

5.5

• Low OCLO and ACM = 1

2.75

MC07XSF517

Analog Integrated Circuit Device Data

Freescale Semiconductor

53

Table 16. Electrical Characteristics

Characteristics noted under conditions 7.0 V  V_PWR 18 V, -40 C  T_A 125 C, GND = 0 V, unless otherwise noted. Typical

values noted reflect the approximate parameter means at T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min

Typ

Max

Unit Notes

CURRENT SENSE CSNS (Continued)

(20)

Current Sense Accuracy for 9.0 V < V_PWR< 18 V for 17 m Power

ACC I_CSNS

%

Channel

-11

-14

-20

-29

–

+11

+14

+20

+29

• I_OUT= 80% FSR

• I_OUT= 25% FSR

• I_OUT= 10% FSR

• I_OUT= 5.0% FSR

(20) (22)

Current Sense Accuracy for 9.0 V < V_PWR< 18 V with 1 calibration point at

ACC I_{CSNS 1}

%

25 °C for 50% FSR and V_PWR= 14 V for 17 m Power Channel

CAL

• I_OUT= 80% FSR

• I_OUT= 25% FSR

• I_OUT= 10% FSR

• I_OUT= 5.0% FSR

-7.0

-20

-29

–

+7.0

+20

+29

(20) (22)

Current Sense Accuracy for 9.0 V < V_PWR< 18 V with 2 calibration points

at 25 °C for 2.0% and 50% FSR and V_PWR= 14 V for 17 m Power

Channel

ACC I_{CSNS 2}

%

CAL

-6.0

-8.0

-11

–

+6.0

+8.0

+11

• I_OUT= 80% FSR

• I_OUT= 25% FSR

• I_OUT= 10% FSR

• I_OUT= 5.0% FSR

(20) (23)

Minimum Current Sense Reporting for 17 m

I_CSNSMIN

%

• for 9.0 V < V_PWR< 18 V, max. = 1%

–

1.0

20

Supply Voltage Feedback Range

V_PWR

V_PWRMAX

V

(22)

Supply Feedback Precision

ACC V_PWR

%

• Default

-5.0

-1.0

-2.2

–

+5.0

+1.0

+2.2

• 1 calibration point at 25 °C and V_PWR= 12 V, for 7.0 V < V_PWR< 20 V

• 1 calibration point at 25 °C and V_PWR= 12 V, for 6.0 V < V_PWR

7.0 V

<

(21)

Temperature Feedback Range

T_FB

V_FB

-40

–

150

–

°C

Temperature Feedback Voltage at 25 °C

Temperature Feedback Thermal Coefficient

2.31

7.72

V

(22)

COEF V_FB

ACCT_FB

–

mV/°C

(22)

Temperature Feedback Voltage Precision

• Default

°C

-15

–

+15

• 1 calibration point at 25 °C and V_PWR= 7.0 V

-5.0

+5.0

(21)

Current Sense Settling Time

t_CSNS(SET)

µs

• Current Sensing Feedback for I_OUTfrom 75% FSR to 50% FSR

• Current Sensing Feedback for I_OUTfrom 10% FSR to 1.0% FSR

Temperature and Supply Voltage Feedbacks

–

40

260

10

Notes

20. Precision either OCLO and ACM setting.

21. Parameter is derived mainly from simulations.

22. Parameter is guaranteed by design characterization. Measurements are taken from a statistically relevant sample size across process

variations.

23. Error of 100% without calibration and 50% with 1 calibration point done at 25 °C.

MC07XSF517

Analog Integrated Circuit Device Data

54

Freescale Semiconductor

Table 16. Electrical Characteristics

Characteristics noted under conditions 7.0 V  V_PWR 18 V, -40 C  T_A 125 C, GND = 0 V, unless otherwise noted. Typical

values noted reflect the approximate parameter means at T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min

Typ

Max

Unit Notes

CURRENT SENSE CSNS (Continued)

(24)

Current Sense Valid Time

Current Sensing Feedback

t_CSNS(VAL)

µs

• Low / Medium Frequency Ranges for I_OUT> 20% FSR

• Low / Medium Frequency Ranges for I_OUT< 20% FSR

• High Frequency Range for I_OUT> 20% FSR

10

70

5.0

70

–

150

300

75

300

10

• High Frequency Range for I_OUT< 20% FSR

Temperature Voltage Feedback

Supply Voltage Feedback

–

15

Current Sense Synchronization Period for PWM Clock Failure

t_SYNC

4.8

6.5

8.2

ms

DEFAULT

CURRENT SENSE SYNCHRONIZATION CSNS SYNCB

Pull-up Current Sense Synchronization Resistor Range

R_{CSNS SYNC}

5.0

–

k

V

Current Sense Synchronization Logic Output Low State Level at 1.0 mA

V_OL

0.4

Current Sense Synchronization Leakage Current in Tri-state (CSNS SYNC

from 0 to 5.5 V)

I_{OUT max}

-1.0

+1.0

µA

Notes

24. Tested at 5% of final value @ V_PWR= 14 V, current step from 0 A to 2.8 A (or 5.6 A). Parameter guaranteed by design at 1% of final value.

6.2

Power Supply Functional Block Description and Application

Information

6.2.1 Introduction

The device is functional when wake = [1] with supply voltages from 5.5 to 40 V (V_PWR), but is fully specification compliant only

between 7.0 and 18 V. The VPWR pin supplies power to the internal regulator, analog, and logic circuit blocks. The VCC pin (5.0

V typ.) supplies the output register of the Serial Peripheral Interface (SPI) and the OUT6 driver. Consequently, the SPI registers

cannot be read without presence of V_CC. The employed IC architecture guarantees a low quiescent current in Sleep mode

(wake= [0]).

6.2.2 Wake State Reporting

The CLK input/output pin is also used to report the wake state of the device to the microcontroller as long as RSTB is logic [0].

When the device is in:

•

“wake state” and RSTB is inactive, the CLK pin reports a high signal (logic[1])

“sleep mode” or the device is wake by the RSTB pin, the CLK is an input pin

MC07XSF517

Analog Integrated Circuit Device Data

Freescale Semiconductor

55

6.2.2.1

Electrical Characterization

Table 17. Electrical Characteristics

Characteristics noted under conditions 7.0 V  V_PWR 18 V, -40 C  T_A 125 C, GND = 0 V, unless otherwise noted. Typical

values noted reflect the approximate parameter means at T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min

Typ

Max

Unit Notes

CLOCK INPUT/OUTPUT CLK

Logic Output High State Level (CLK) at 1.0 mA

V_OH

VCC -

0.6

–

V

6.2.3 Supply Voltages Disconnection

6.2.3.1 Loss of V_PWR

In case of V_PWRdisconnection (V_PWR< V_{PWR POR}) the device behavior depends on V_CCvoltage value:

•

V_CC< V_{CC POR}: the device enters the power off mode. All outputs are shut off immediately. All registers and faults

are cleared.

•

V_CC> V_{CC POR}: all registers and faults are maintained. OUT1… 5 are shut off immediately. The ON/OFF state of

OUT6 depends on the current SPI configuration. SPI reporting is available when V_CCremains within its operating

voltage range (4.5 to 5.5 V).

The wake-up event is not reported to the CLK pin.

The clamping structures (supply clamp, negative output clamp) are available to protect the device.

No current is conducted from V_CCto V_PWR

.

An external current path shall be available to drain the energy from an inductive load, in case a supply disconnection occurs when

an output is ON.

6.2.3.2

Loss of V_CC

In case of a V_CCdisconnection, the device behavior depends on V_PWRvoltage:

•

V_PWR< V_{PWR POR}: the device enters the power off mode. All outputs are shut off immediately. All registers and

faults are cleared.

•

V_PWR> V_{PWR POR}: the SPI is not available. Therefore, the device will enter WD timeout.

The clamping structures (supply clamp, negative output clamp) are available to protect the device.

No current is conducted from V_PWRto V_CC

.

6.2.3.3

Loss of Device GND

During loss of ground, the device cannot drive the loads, therefore the OUT1… OUT5 outputs are switched off and the OUT6

voltage is pulled up.

The device shall not be damaged by this failure condition.

For protection of the digital inputs series resistors (1.0 k typ) can be provided externally in order to limit the current to I

.

CL

MC07XSF517

Analog Integrated Circuit Device Data

56

Freescale Semiconductor

6.2.3.4

Electrical Characterization

Table 18. Electrical Characteristics

Characteristics noted under conditions 7.0 V  V_PWR 18 V, -40 C  T_A 125 C, GND = 0 V, unless otherwise noted. Typical

values noted reflect the approximate parameter means at T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min

Typ

Max

Unit Notes

SUPPLY VPWR

Supply Power On Reset

V_{PWR POR}

VCC

2.0

3.0

–

4.0

V

VCC Power On Reset

V_{CC POR}

GROUND GND

Maximum Ground Shift between GND Pin and Load Grounds

V_{GND SHIFT}

-1.5

+1.5

6.3

Communication Interface and Device Control Functional Block

Description and Application Information

6.3.1 Introduction

In Normal mode, the power output channels are controlled by the embedded PWM module, which is configured by the SPI

register settings. For bidirectional SPI communication, V_CChas to be in the authorized range. Failure diagnostics and

configuration are also performed through the SPI port. The reported failure types are: OpenLoad, short-circuit to supply, severe

short-circuit to ground, overcurrent, overtemperature, clock fail, and under and overvoltage.

For direct input control, the device shall be in Fail-safe mode. V_CCis not required and this mode can be forced by the LIMP input

pin.

6.3.2 Fail Mode Input (LIMP)

The Fail mode of the component can be activated by LIMP direct input. The Fail mode is activated when the input is logic [1].

In Fail mode, the channel power outputs are controlled by the corresponding inputs. Even though the input thresholds are logic

level compatible, the input structure of the pins are able to withstand supply voltage level (max. 40 V) without damage. External

current limit resistors (i.e. 1.0 k...10 k) can be used to handle reverse current conditions. The direct inputs have an integrated

pull-down resistor.

The LIMP input has an integrated pull-down resistor. The status of the LIMP input can be monitored by the LIMP IN bit inside the

device status register #7.

6.3.2.1

Electrical Characterization

Table 19. Electrical Characteristics

Characteristics noted under conditions 4.5 V  V_PWR 5.5 V, -40 C  T_A 125 C, GND = 0 V, unless otherwise noted. Typical

values noted reflect the approximate parameter means at T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min

Typ

Max

Unit Notes

FAIL MODE INPUT LIMP

Logic Input High State Level

Logic Input Low State Level

V_IH

V_IL

3.5

–

V

1.5

Logic Input Leakage Current in Inactive State (LIMP = [0])

Logic Input Pull-down Resistor

I_IN

-0.5

25

+0.5

100

µA

k

R_PULL

MC07XSF517

Analog Integrated Circuit Device Data

Freescale Semiconductor

57

Table 19. Electrical Characteristics

Characteristics noted under conditions 4.5 V  V_PWR 5.5 V, -40 C  T_A 125 C, GND = 0 V, unless otherwise noted. Typical

values noted reflect the approximate parameter means at T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min

Typ

Max

Unit Notes

(25)

Logic Input Capacitance

C_IN

–

20

pF

DIRECT INPUTS IN1… IN4

Logic Input High State Level

V_IH

V_IH(WAKE)

V_IL

3.5

3.75

–

V

Logic Input High State Level for wake-up

Logic Input Low State Level

1.5

+0.5

100

20

V

Logic Input Leakage Current in Inactive State (forced to [0])

Logic Input Pull-down Resistor

I_IN

-0.5

25

µA

k

R_PULL

C_IN

Notes

(25)

Logic Input Capacitance

–

pF

25. Parameter is derived mainly from simulations.

6.3.3 MCU Communication Interface Protections

6.3.3.1

Loss of Communication Interface

If a SPI communication error occurs, the device is switched into Fail mode.

A SPI communication fault is detected if:

•

the WD bit is not toggled with each SPI message or

WD timeout is reached or

protocol length error (modulo 16 check)

The SI stuck to static levels during CSB period and VCC fail (SPI not functional) are indirectly detected by a WD toggle error.

The SPI communication error is reported in:

•

SPI failure flag (SPIF) inside the device status register #7 in the next SPI communication

As long as the device is in Fail mode, the SPIF bit retains its state.

The SPIF bit is delatched during the transition from fail-to-normal modes.

6.3.3.2

Logic I/O Plausibility Check

The logic and signal I/O are protected against fatal mistreatment by a signal plausibility check, according following table:

I/O

Signal check strategy

IN1 ~ IN4

LIMP

frequency above limit (low pass filter)

RST\

CLK

The LIMP and IN1… IN4 have an input symmetrically deglitch time t_{IN_DGL}= 200 µs (typ).

If the LIMP input is set to logic [1] for a delay longer than 200 µs typ, the device is switched into Fail mode (internal signal called

iLIMP).

MC07XSF517

Analog Integrated Circuit Device Data

58

Freescale Semiconductor

LIMP

iLIMP

tIN_DGL

200µs typ.

t^IN_DGL

200µs typ.

time

Figure 34. LIMP and iLIMP signal

In case the INx input is set to logic [1] for a delay longer than 200 µs (typ.), the corresponding channel is controlled by the direct

signal (internal signal called iINx).

INx

tIN_DGL

time

tIN_DGL

iINx

200µs typ.

time

ttoggle

1024ms typ.

ttoggle

INx_ON

time

Figure 35. IN, iIN and IN_ON signal

The RSTB has an input deglitch time t_{RST_DGL}= 10 µs (typ) for the falling edge only.

The CLK has an input symmetrically deglitch time t_{CLK_DGL}= 2.0 µs (typ). Due to the input deglitcher (at the CLK input) a very

high input frequency leads to a clock fail detection.

The CLK fail detection (clock input frequency detection f_{CLK LOW}) is started immediately with the positive edge of RSTB signal.

If the CLK frequency is below f_{CLK LOW}limit, the output state will depend on the corresponding CHx signal.

As soon as the CLK signal is valid, the output duty cycle depends on the corresponding SPI configuration.

To delatch the CLK fail diagnosis

•

the clock failure condition must be removed

a read command of the quick status register #1 must be performed

MC07XSF517

Analog Integrated Circuit Device Data

Freescale Semiconductor

59

6.3.3.3

Electrical Characterization

Table 20. Electrical Characteristics

Characteristics noted under conditions 7.0V  V_PWR 18V, -40C  T_A 125C, GND = 0V, unless otherwise noted. Typical

values noted reflect the approximate parameter means at T_A= 25°C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min

Typ

Max

Unit Notes

LOGIC I/O LIMP IN1… IN4 CLK

SPI Watchdog Timeout

• WD SEL = 0

t_WD

ms

24

96

32

40

• WD SEL = 1

128

160

Input Toggle Time for IN1… IN4

t_TOGGLE

t_DGL

768

1024

1280

ms

µs

Input Deglitching Time

• LIMP and IN1… IN4

• CLK

150

1.5

7.5

200

2.0

10

250

2.5

• RST\

12.5

Clock Low Frequency Detection

f_{CLOCK LOW}

50

100

200

Hz

6.3.4 External Smart Power Control (OUT6)

The device provides a control output to drive an external smart power device in Normal mode only.

The control is according to the channel 6 settings in the SPI input data register.

•

The protection and current feedback of the external SmartMOS device are under the responsibility of the

microcontroller.

•

The output delivers a 5.0 V CMOS logic signal from V_CC

.

The output is protected against overvoltage.

An external current limit resistor (i.e. 1.0 k...10 k) shall be used to handle negative output voltage conditions.

The output has an integrated pull-down resistor to provide a stable OFF condition in Sleep mode and Fail mode.

In case of a ground disconnection, the OUT6 voltage is pulled up. External components are mandatory to define the state of

external smart power device and to limit possible reverse OUT6 current (i.e. resistor in series).

6.3.4.1

Electrical Characterization

Table 21. Electrical Characteristics

Characteristics noted under conditions 7.0 V  V_PWR 18 V, -40 C  T_A 125 C, GND = 0 V, unless otherwise noted. Typical

values noted reflect the approximate parameter means at T_A= 25 °C under nominal conditions, unless otherwise noted.

Symbol

Characteristic

Min

Typ

Max

Unit Notes

EXTERNAL SMART POWER OUTPUT OUT6

OUT6 Rising Edge for 100 pF capacitive load

t_{OUT6 RISE}

R_{OUT6 DWN}

V_OH

–

10

–

5.0

20

–

µs

k

V

OUT6 Pull-down Resistor

5.0

Logic Output High State Level (OUT6)

VCC -

0.6

Logic Output Low State Level (OUT6)

V_OL

–

0.6

V

MC07XSF517

Analog Integrated Circuit Device Data

60

Freescale Semiconductor

7

Typical Applications

7.1

Introduction

The 07XSF517 is the latest achievement in drivers for all types of centralized lighting applications.

7.1.1 Application Diagram

V

RIGHT

VBAT RIGHT

PWR

20V

5V Regulator

VVBPAWTR

VCC

10µ

10n…100n

100n

GND

100n

5k

VCC VBAT

VCC

SI

CP

SO

CS\

OUT1

OUT2

OUT3

OUT4

OUT5

OUT6

10n

Parking Light

Flasher

SCLK

SI

SCLK

VCC

SO

Main MCU

VCC Clamp

RST\

CLK

CSNS

SYNC\

LIMP

IN1

GND

CLK

A/D1

Low Beam

Fog Light

High Beam

Spare

10k

TRIG1

A/D2

A/D3

GND

10n

IN2

1k

5k

VVPBWATR

IN3

IN

OUT

10n

1k

IN4

Smart Power

CSNS

GND

1k

GND

CSNS

GND

IN4

Smart Power

IN OUT

Spare

High Beam

Fog Light

1k

IN3

OUT6

OUT5

OUT4

OUT3

OUT2

OUT1

VPWR

VBAT

10n

IN2

IN1

10n

LIMP

SYNC\

CSNS

CLK

RST\

SO

10n

Low Beam

Flasher

VBAT

VPWR

LIMP

IN1

1k

10n

1k

SCLK

CS\

Parking Light

IN2

Watchdog

IN3

IN4

SI

CP

VCC VBAT

GND

100n

10n…100n

100n

20V

V

LEFT

VBAT LEFT

PWR

Figure 36. Typical Front Lighting Application for Automotive

MC07XSF517

Analog Integrated Circuit Device Data

Freescale Semiconductor

61

7.1.2 Application Instructions

7.1.3 Bill of Material

Table 22. 07XSF517 Bill of Material ⁽²⁶⁾

Signal

Location

Mission

Value

close to Gen4

reduction of emission and immunity

V_PWR

100 nF (X7R 50 V)

eXtreme Switch

close to Gen4

eXtreme Switch

charge pump tank capacitor

CP

V_CC

100 nF (X7R 50 V)

10 to 100 nF (X7R 16 V)

10 to 22 nF (X7R 50 V)

5.0 k (1.0%)

close to Gen4

eXtreme Switch

reduction of emission and immunity

sustain ESG gun and fast transient pulses

close to output

connector

OUT1… OUT5

close to MCU

output current sensing

CSNS

low pass filter removing noise

10 k (1.0%) &

10 nF (X7R 16V)

N/A

pull-up resistor for the synchronization of A/D conversion

sustain high-voltage

CSNS SYNCB

IN1… IN4

OUT6

5.0 k (1.0%)

1.0 k (1.0%)

sustain reverse supply

To Increase Fast Transient Pulses Robustness

close to connector sustain pulse #1 in case of LED loads or without loads

V_PWR

20 V zener diode and diode in series

per supply line

close to Gen4

sustain pulse #2 without loads

V_PWR

additional 10 µF (X7R 50 V)

eXtreme Switch

To Sustain 5.0 V Voltage Regulator Failure Mode

prevent high-voltage application on the MCU

close to 5.0 V

voltage regulator

V_CC

5.0 V zener diode and a bipolar

transistor

Notes

26. Freescale does not assume liability, endorse, or warrant components from external manufacturers that are referenced in circuit drawings

or tables. While Freescale offers component recommendations in this configuration, it is the customer’s responsibility to validate their

application.

MC07XSF517

Analog Integrated Circuit Device Data

62

Freescale Semiconductor

7.2

EMC and EMI Considerations

7.2.1 EMC/EMI Tests

This paragraph gives EMC/EMI performances, according to automotive specifications. Further generic design recommendations

can be e.g. found on the Freescale website www.freescale.com.

Table 23. 07XSF517 EMC/EMI Performances

Automotive

Test

Signals

Conditions

Criteria

Standard

VPWR

CISPR25

Class 5

150  Method

Global pins: V_PWRand OUT1… OUT5

150  Method

Global pins: 12-K level

Local pins: 10-J level

Conducted Emission

IEC 61967-4

IEC 62132-4

outputs off

outputs on

in PWM

Local pins: V_CC, CP, and CSNS

Global pins: V_PWRand OUT1… OUT5

Local pins: V_CC

Class A related to the outputs state and

the analog diagnostics (20%)

Conducted Immunity

30 dBm for Global pins

12 dBm for Local pins

7.2.2 Fast Transient Pulse Tests

This paragraph gives the device performances.against fast transient disturbances.

Table 24. 07XSF517 Fast Transient Capability on VPWR

Automotive

Criteria

Test

Conditions

Standard

Pulse 1

Pulse 2a

outputs loaded with lamps

other cases with external transient voltage suppressor

ISO 7637-2

Class A

Pulse 3a / 3b

Pulse 5b (40 V)

outputs loaded

outputs unloaded

MC07XSF517

Analog Integrated Circuit Device Data

Freescale Semiconductor

63

7.3

Robustness Considerations

The short-circuit protections embedded in 07XSF517 are preferred to conventional current limitations, to minimize the thermal

overstress within the device in case of an overload condition. The junction temperature elevation is drastically reduced to a value

which does not affect the device’s reliability. Moreover, the availability of the lighting is guaranteed in fail mode by the unlimited

autorestart feature.

The chapter 12 of AEC-Q100 specification published by the Automotive Electronics Council, presents turn-on into short-circuit

condition. It is not enough, because the short-circuit event can also occur in on-state. The 07XSF517 test plan at T_A= 70 °C is

presented in Table 25. The tests are performed on 30 parts from three engineering lots (total 90 pieces).

Table 25. 07XSF517 Repetitive Short-circuit Test Results at T_A= 70 °C

7.0 m output cycle 17 m output cycle

Short-circuit Case

Supply Voltage

Supply Line

Load Line

without Failure

5.0 m /1.0 mm²

0.3 m / 1.0 mm²

5.0 m /1.0 mm²

0.3 m / 1.0 mm²

500 k

0.3 m /2.5 mm²

5.0 m /2.5 mm²

0.3 m /2.5 mm²

5.0 m /2.5 mm²

Turn-on into short-circuit

condition

16 V

Short-circuit in On-state ⁽²⁷⁾

14 V

2.6 m / 6.0 mm²

in series with

0.3 m / 1.0 mm²

On-state overload 95% of

min OCHI1/2/3 levels

16 V

1.0 m / 6.0 mm²

250 k

500 k

On-state overload 95% of

min OCHI1/2/3 levels with

thermal OCHI feature active

2.6 m / 6.0 mm²

in series with

0.3 m / 1.0 mm²

Notes

27. The channel was loaded in the on-state with 100 mA.

Table 26. 07XSF517 AECQ100-12 Reliability Test Results at T_A= 85 °C and Supply Voltage = 14 V

Short-circuit Case

Supply Line

Load Line

AECQ100-12 Grade

Load short-circuit on 7.0 mOutput

Load short-circuit on 17.0 mOutput

5.0 H/50 m

5.0 H/100 m

D

5.0 H/10 m

For either condition, contact our local Field Application Engineer (email: support@freescale.com).

MC07XSF517

Analog Integrated Circuit Device Data

64

Freescale Semiconductor

7.4

PCB Layout Recommendations

This new generation of high-side switch products family facilitates ECU design thanks to compatible MCU software and PCB foot

print for each device variant. The PCB Copper layer is similar for all devices in the family, only the solder Stencil opening is

different.

Figure 37. PCB Copper Layer & Solder Stencil Opening Recommendations

MC07XSF517

Analog Integrated Circuit Device Data

Freescale Semiconductor

65

7.5

Thermal Information

This section is to provide thermal information.

7.5.1 Thermal Transient

Figure 38. Transient Thermal Response Curve

7.5.2 R/C Thermal Model

Contact our local Field Application Engineer (email: support@freescale.com).

MC07XSF517

Analog Integrated Circuit Device Data

66

Freescale Semiconductor

8

Packaging

8.1

Marking Information

Device markings indicate information on the week and year of manufacturing. The date is coded with the last four characters of

the nine character build information code (e.g. “CTKAH1229”). The date is coded as four numerical digits where the first two digits

indicate the year and the last two digits indicate the week. For instance, the date code “1229” indicates the 29^thweek of the year

2012.

8.2

Package Mechanical Dimensions

Package dimensions are provided in package drawings. To find the most current package outline drawing, go to

www.freescale.com and perform a keyword search for the drawing’s document number.

Table 27. Package Outline

Package

Suffix

Package Outline Drawing Number

98ASA00367D

54-Pin SOICEP

EK

MC07XSF517

Analog Integrated Circuit Device Data

Freescale Semiconductor

67

EK SUFFIX

54-PIN SOIC-EP

98ASA00367D

ISSUE 0

MC07XSF517

Analog Integrated Circuit Device Data

68

Freescale Semiconductor

EK SUFFIX

54-PIN SOIC-EP

98ASA00367D

ISSUE 0

MC07XSF517

Analog Integrated Circuit Device Data

Freescale Semiconductor

69

EK SUFFIX

54-PIN SOIC-EP

98ASA00367D

ISSUE 0

MC07XSF517

Analog Integrated Circuit Device Data

70

Freescale Semiconductor

9

Revision History

REVISION

1.0

DATE

9/2013

DESCRIPTION OF CHANGES

•

Initial release

Added the note “To achieve high reliability over 10 years of continuous operation, the device's

2.0

continuous operating junction temperature should not exceed 125C.” to Operating Temperature

MC07XSF517

Analog Integrated Circuit Device Data

Freescale Semiconductor

71

Information in this document is provided solely to enable system and software implementers to use Freescale products.

There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based

on the information in this document.

How to Reach Us:

Home Page:

freescale.com

Web Support:

freescale.com/support

Freescale reserves the right to make changes without further notice to any products herein. Freescale makes no

warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does

Freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any

and all liability, including without limitation consequential or incidental damages. “Typical” parameters that may be

provided in Freescale data sheets and/or specifications can and do vary in different applications, and actual performance

may vary over time. All operating parameters, including “typicals,” must be validated for each customer application by

customer’s technical experts. Freescale does not convey any license under its patent rights nor the rights of others.

Freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address:

freescale.com/SalesTermsandConditions.

Freescale and the Freescale logo, are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off.

SMARTMOS is a trademark of Freescale Semiconductor, Inc. All other product or service names are the property of their

respective owners.

Document Number: MC07XSF517

Rev. 2.0

9/2013