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ADC081C021, ADC081C027  
www.ti.com  
SNAS447C –FEBRUARY 2008–REVISED MARCH 2013  
ADC081C021/ADC081C027 I2C-Compatible, 8-Bit Analog-to-Digital Converter with Alert  
Function  
Check for Samples: ADC081C021, ADC081C027  
1
FEATURES  
DESCRIPTION  
•
I2C-Compatible 2-Wire Interface Which  
Supports Standard (100kHz), Fast (400kHz),  
and High Speed (3.4MHz) Modes  
The ADC081C021 is a low-power, monolithic, 8-bit,  
analog-to-digital converter (ADC) that operates from a  
+2.7 to 5.5V supply. The converter is based on a  
successive approximation register architecture with  
an internal track-and-hold circuit that can handle input  
frequencies up to 11MHz. The ADC081C021  
operates from a single supply which also serves as  
the reference. The device features an I2C-compatible  
serial interface that operates in all three speed  
modes, including high speed mode (3.4MHz).  
23  
•
•
Extended Power Supply Range (+2.7V to  
+5.5V)  
Up to Nine Pin-Selectable Chip Addresses  
(VSSOP-8 only)  
•
•
Out-of-Range Alert Function  
Automatic Power-Down Mode While Not  
Converting  
The ADC's Alert feature provides an interrupt that is  
activated when the analog input violates  
a
•
•
Very Small SOT-6 and VSSOP-8 Packages  
±8kV HBM ESD Protection (SDA, SCL)  
programmable upper or lower limit value. The device  
features an automatic conversion mode, which frees  
up the controller and I2C interface. In this mode, the  
ADC continuously monitors the analog input for an  
"out-of-range" condition and provides an interrupt if  
the measured voltage goes out-of-range.  
APPLICATIONS  
•
•
•
•
•
System Monitoring  
Peak Detection  
The ADC081C021 comes in two packages: a small  
SOT-6 package with an alert output, and an VSSOP-  
8 package with an alert output and two address  
selection inputs. The ADC081C027 comes in a small  
SOT-6 package with an address selection input. The  
Portable Instruments  
Medical Instruments  
Test Equipment  
ADC081C027  
addresses while the VSSOP-8 version of the  
ADC081C021 provides nine pin-selectable  
addresses. Pin-compatible alternatives to the SOT-6  
options are available with additional address options.  
provides  
three  
pin-selectable  
KEY SPECIFICATIONS  
•
•
•
•
•
Resolution: 8 bits; No Missing Codes  
Conversion Time 1 µs (Typ)  
INL & DNL: ±0.2 LSB (Max)  
Normal power consumption using a +3V or +5V  
supply is 0.26mW or 0.78mW, respectively. The  
automatic power-down feature reduces the power  
consumption to less than 1µW while not converting.  
Operation over the industrial temperature range of  
−40°C to +105°C is ensured. Their low power  
consumption and small packages make this family of  
ADCs an excellent choice for use in battery operated  
equipment.  
Throughput Rate: 188.9 ksps (Max)  
Power Consumption (at 22ksps):  
–
–
3V Supply: 0.26 mW (Typ)  
5V Supply: 0.78 mW (Typ)  
The ADC081C021 and ADC081C027 are part of a  
family of pin-compatible ADCs that also provide 10-  
and 12-bit resolution. For 10-bit ADCs see the  
ADC101C021 and ADC101C027. For 12-bit ADCs  
see the ADC121C021 and ADC121C027.  
1
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
2
3
I2C is a registered trademark of Phillips Corporation..  
All other trademarks are the property of their respective owners.  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of the Texas  
Instruments standard warranty. Production processing does not  
necessarily include testing of all parameters.  
Copyright © 2008–2013, Texas Instruments Incorporated  
ADC081C021, ADC081C027  
SNAS447C –FEBRUARY 2008–REVISED MARCH 2013  
www.ti.com  
Table 1. Pin-Compatible AlternativesAll devices are fully pin and function compatible.  
Resolution  
12-bit  
SOT-6 (Alert only) and VSSOP-8  
ADC121C021  
SOT-6 (Addr only)  
ADC121C027  
10-bit  
ADC101C021  
ADC101C027  
8-bit  
ADC081C021  
ADC081C027  
Connection Diagrams  
1
2
3
6
5
4
SCL  
1
2
8
7
SDA  
1
2
3
6
5
4
SDA  
SCL  
SDA  
V
A
V
A
ALERT  
GND  
SCL  
VSSOP  
SOT  
GND  
SOT  
GND  
ADR0  
ADR1  
3
4
6
5
V
V
A
ADDR  
ALERT  
IN  
V
IN  
V
IN  
ADC081C027  
ADC081C021  
ADC081C021  
Figure 1. SOT (Alert Only) – See  
Package Number DDC  
Figure 2. SOT (Addr Only) – See  
Package Number DDC  
Figure 3. VSSOP – See Package  
Number DGK  
2
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Copyright © 2008–2013, Texas Instruments Incorporated  
Product Folder Links: ADC081C021 ADC081C027  
ADC081C021, ADC081C027  
www.ti.com  
SNAS447C –FEBRUARY 2008–REVISED MARCH 2013  
Block Diagram  
V
V
IN  
A
ADC081C021/  
ADC081C027  
REF  
Oscillator  
8-Bit  
Successive  
T/H  
Approximation  
ADC  
Conversion Result  
Highest Conversion  
Lowest Conversion  
Configuration  
Pointer  
Register  
and  
Decode  
Logic  
Alert Status  
Hysteresis  
High Limit  
Low Limit  
Alert  
Set-Point  
Comparator  
ALERT*  
SDA  
SCL  
2
ADDR*  
I C Serial Interface  
GND  
* Note: The ADC081C021 has the ALERT pin but no ADDR pin.  
The ADC081C027 has the ADDR pin but no ALERT pin.  
PIN DESCRIPTIONS  
Symbol  
VA  
Type  
Supply  
Ground  
Equivalent Circuit  
Description  
Power and unbufferred reference voltage. VA must be free  
of noise and decoupled to GND.  
GND  
Ground for all on-chip circuitry.  
VIN  
Analog Input  
See Figure 22  
Analog input. This signal can range from GND to VA.  
Copyright © 2008–2013, Texas Instruments Incorporated  
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3
Product Folder Links: ADC081C021 ADC081C027  
ADC081C021, ADC081C027  
SNAS447C –FEBRUARY 2008–REVISED MARCH 2013  
www.ti.com  
PIN DESCRIPTIONS (continued)  
Symbol  
Type  
Equivalent Circuit  
Description  
Alert output. Can be configured as active high or active low.  
This is an open drain data line that must be pulled to the  
supply (VA) with an external pull-up resistor.  
ALERT  
Digital Output  
Serial Clock Input. SCL is used together with SDA to control  
the transfer of data in and out of the device. This is an open  
drain data line that must be pulled to the supply (VA) with an  
external pull-up resistor. This pin's extended ESD tolerance(  
8kV HBM) allows extension of the I2C bus across multiple  
boards without extra ESD protection.  
PIN  
SCL  
Digital Input  
D1  
Snap  
Back  
Serial Data bi-directional connection. Data is clocked into or  
out of the internal 16-bit register with SCL. This is an open  
drain data line that must be pulled to the supply (VA) with an  
external pull-up resistor. This pin's extended ESD tolerance(  
8kV HBM) allows extension of the I2C bus across multiple  
boards without extra ESD protection.  
GND  
Digital  
Input/Output  
SDA  
Tri-level Address Selection Input. Sets Bits A0 & A1 of the  
7-bit slave address. (see Table 2)  
ADDR0  
V+  
PIN  
41.5k  
2.1k  
Digital Input,  
three levels  
D1  
Snap  
Back  
Tri-level Address Selection Input. Sets Bits A2 & A3 of the  
7-bit slave address. (see Table 2)  
ADDR1  
41.5k  
GND  
Package Pinouts  
VA  
1
GND  
VIN  
3
ALERT  
SCL  
SDA  
ADR0  
ADR1  
N/A  
N/A  
6
ADC081C021 (SOT-6)  
ADC081C027 (SOT-6)  
ADC081C021 (VSSOP-8)  
2
2
7
4
N/A  
2
5
5
1
6
6
8
N/A  
4
1
3
5
4
3
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam  
during storage or handling to prevent electrostatic damage to the MOS gates.  
4
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Copyright © 2008–2013, Texas Instruments Incorporated  
Product Folder Links: ADC081C021 ADC081C027  
ADC081C021, ADC081C027  
www.ti.com  
SNAS447C –FEBRUARY 2008–REVISED MARCH 2013  
Absolute Maximum Ratings(1)(2)(3)  
(4)  
Supply Voltage, VA  
-0.3V to +6.5V  
−0.3V to (VA +0.3V)  
−0.3V to 6.5V  
±15 mA  
Voltage on any Analog Input Pin to GND  
Voltage on any Digital Input Pin to GND  
Input Current at Any Pin(5)  
Package Input Current(5)  
±20 mA  
Power Dissipation at TA = 25°C  
See(6)  
Human Body Model  
2500V  
250V  
VA, GND, VIN, ALERT, ADR pins  
Machine Model  
ESD Susceptibility(7)  
Charged Device Model (CDM)  
Human Body Model  
Machine Model  
1250V  
8000V  
SDA, SCL pins  
400V  
Junction Temperature  
Storage Temperature  
+150°C  
−65°C to +150°C  
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for  
which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the  
Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may  
degrade when the device is not operated under the listed test conditions. Operation of the device beyond the maximum Operating  
Ratings is not recommended.  
(2) All voltages are measured with respect to GND = 0V, unless otherwise specified.  
(3) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and  
specifications.  
(4) To ensure accuracy, it is required that VA be well bypassed and free of noise.  
(5) When the input voltage at any pin exceeds 5.5V or is less than GND, the current at that pin should be limited per the Absolute Maximum  
Ratings. The maximum package input current rating limits the number of pins that can safely exceed the power supplies.  
(6) The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by  
TJmax, the junction-to-ambient thermal resistance (θJA), and the ambient temperature (TA), and can be calculated using the formula  
PDMAX = (TJmax − TA) / θJA. The values for maximum power dissipation will be reached only when the device is operated in a severe  
fault condition (e.g., when input or output pins are driven beyond the operating ratings, or the power supply polarity is reversed).  
(7) Human body model is a 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is a 220 pF capacitor discharged  
through 0 Ω. Charged device model simulates a pin slowly acquiring charge (such as from a device sliding down the feeder in an  
automated assembler) then rapidly being discharged.  
Operating Ratings(1)(2)  
Operating Temperature Range  
−40°C ≤ TA ≤ +105°C  
+2.7V to 5.5V  
0V to VA  
Supply Voltage, VA  
Analog Input Voltage, VIN  
Digital Input Voltage(3)  
Sample Rate  
0V to 5.5V  
up to 188.9 ksps  
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for  
which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the  
Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may  
degrade when the device is not operated under the listed test conditions. Operation of the device beyond the maximum Operating  
Ratings is not recommended.  
(2) All voltages are measured with respect to GND = 0V, unless otherwise specified.  
(3) The inputs are protected as shown below. Input voltage magnitudes up to 5.5V, regardless of VA, will not cause errors in the conversion  
result. For example, if VA is 3V, the digital input pins can be driven with a 5V logic device.  
I/O  
TO INTERNAL  
CIRCUITRY  
GND  
Copyright © 2008–2013, Texas Instruments Incorporated  
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5
Product Folder Links: ADC081C021 ADC081C027  
ADC081C021, ADC081C027  
SNAS447C –FEBRUARY 2008–REVISED MARCH 2013  
www.ti.com  
Package Thermal Resistances(1)(2)  
Package  
6-Lead SOT  
8-Lead VSSOP  
θJA  
250°C/W  
200°C/W  
(1) Soldering process must comply with Reflow Temperature Profile specifications. Refer to www.ti.com/packaging.  
(2) Reflow temperature profiles are different for lead-free packages.  
Electrical Characteristics  
The following specifications apply for VA = +2.7V to +5.5V, GND = 0V, fSCL up to 3.4MHz, fIN = 1kHz for fSCL up to 400kHz, fIN  
= 10kHz for fSCL = 3.4MHz unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C  
unless otherwise noted.  
Symbol  
Parameter  
Conditions  
Typical(1)  
Limits(1)  
Units (Limits)  
STATIC CONVERTER CHARACTERISTICS  
Resolution with No Missing Codes  
8
Bits  
VA = +2.7V to +3.6V  
VA = +2.7V to +5.5V. fSCL up to 400kHz(2)  
±0.04  
±0.1  
±0.2  
±0.25  
±0.2  
±0.25  
±0.5  
±0.5  
±0.4  
LSB (max)  
LSB (max)  
LSB (max)  
LSB (max)  
LSB (max)  
LSB (max)  
LSB (max)  
Integral Non-Linearity (End Point  
Method)  
INL  
VA = +2.7V to +3.6V  
+0.04  
±0.08  
+0.26  
+0.25  
-0.01  
DNL  
Differential Non-Linearity  
VA = +2.7V to +5.5V. fSCL up to 400kHz(2)  
VA = +2.7V to +3.6V  
VA = +2.7V to +5.5V. fSCL up to 400kHz(2)  
VOFF  
GE  
Offset Error  
Gain Error  
DYNAMIC CONVERTER CHARACTERISTICS  
ENOB  
SNR  
Effective Number of Bits  
7.98  
49.8  
7.8  
49  
Bits (min)  
dB (min)  
dB (max)  
dB (min)  
dB (min)  
Signal-to-Noise Ratio  
THD  
Total Harmonic Distortion  
Signal-to-Noise Plus Distortion Ratio  
Spurious-Free Dynamic Range  
−70.6  
49.8  
−64  
49  
SINAD  
SFDR  
-68.8  
65  
Intermodulation Distortion, Second  
Order Terms (IMD2)  
IMD  
VA = +3.0V, fa = 1.035 kHz, fb = 1.135 kHz  
VA = +3.0V, fa = 1.035 kHz, fb = 1.135 kHz  
−75.5  
−71.8  
dB  
dB  
Intermodulation Distortion, Third  
Order Terms (IMD3)  
VA = +3.0V  
VA = +5.0V  
8
MHz  
MHz  
FPBW  
Full Power Bandwidth (−3dB)  
11  
ANALOG INPUT CHARACTERISTICS  
VIN  
Input Range  
DC Leakage Current(3)  
0 to VA  
V
µA (max)  
pF  
IDCL  
±1  
Track Mode  
Hold Mode  
30  
3
CINA  
Input Capacitance  
pF  
SERIAL INTERFACE INPUT CHARACTERISTICS (SCL, SDA)  
VIH  
VIL  
Input High Voltage  
Input Low Voltage  
Input Current(3)  
0.7 x VA  
0.3 x VA  
±1  
V (min)  
V (max)  
µA (max)  
pF  
IIN  
CIN  
Input Pin Capacitance  
Input Hysteresis  
3
VHYST  
0.1 x VA  
V (min)  
ADDRESS SELECTION INPUT CHARACTERISTICS (ADDR)  
VIH  
VIL  
Input High Voltage  
Input Low Voltage  
VA - 0.5V  
0.5  
V (min)  
V (max)  
(1) Typical figures are at TJ = 25°C, and represent most likely parametric norms. Test limits are specified to AOQL (Average Outgoing  
Quality Level).  
(2) The ADC will meet Minimum/Maximum specifications for fSCL up to 3.4MHz and VA = 2.7V to 3.6V when operating in the QUIET  
INTERFACE MODE.  
(3) This parameter is specified by design and/or characterization and is not tested in production.  
6
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Copyright © 2008–2013, Texas Instruments Incorporated  
Product Folder Links: ADC081C021 ADC081C027  
ADC081C021, ADC081C027  
www.ti.com  
SNAS447C –FEBRUARY 2008–REVISED MARCH 2013  
Electrical Characteristics (continued)  
The following specifications apply for VA = +2.7V to +5.5V, GND = 0V, fSCL up to 3.4MHz, fIN = 1kHz for fSCL up to 400kHz, fIN  
= 10kHz for fSCL = 3.4MHz unless otherwise noted. Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C  
unless otherwise noted.  
Symbol  
Parameter  
Input Current(3)  
Conditions  
Typical(1)  
Limits(1)  
Units (Limits)  
IIN  
±1  
µA (max)  
LOGIC OUTPUT CHARACTERISTICS, OPEN-DRAIN (SDA, ALERT)  
ISINK = 3 mA  
0.4  
0.6  
V (max)  
V (max)  
VOL  
IOZ  
Output Low Voltage  
ISINK = 6 mA  
High-Impedence Output Leakage  
Current(3)  
±1  
µA (max)  
Output Coding  
Straight (Natural) Binary  
POWER REQUIREMENTS  
Supply Voltage Minimum  
Supply Voltage Maximum  
Continuous Operation Mode -- 2-wire interface active.  
2.7  
5.5  
V (min)  
VA  
V (max)  
VA = 2.7V to 3.6V  
VA = 4.5V to 5.5V  
VA = 2.7V to 3.6V  
VA = 4.5V to 5.5V  
VA = 3.0V  
0.08  
0.16  
0.37  
0.74  
0.26  
0.78  
1.22  
3.67  
0.14  
0.30  
0.55  
0.99  
mA (max)  
mA (max)  
mA (max)  
mA (max)  
mW  
fSCL=400kHz  
fSCL=3.4MHz  
fSCL=400kHz  
fSCL=3.4MHz  
IN  
Supply Current  
VA = 5.0V  
mW  
PN  
Power Consumption  
VA = 3.0V  
mW  
VA = 5.0V  
mW  
Automatic Conversion Mode -- 2-wire interface stopped and quiet (SCL = SDA = VA). fSAMPLE = TCONVERT * 32  
VA = 2.7V to 3.6V  
VA = 4.5V to 5.5V  
VA = 3.0V  
0.41  
0.78  
1.35  
3.91  
0.59  
1.2  
mA (max)  
mA (max)  
mW  
IA  
Supply Current  
PA  
Power Consumption  
VA = 5.0V  
mW  
Power Down Mode (PD1) -- 2-wire interface stopped and quiet. (SCL = SDA = VA).(4)  
IPD1  
Supply Current  
0.1  
0.5  
0.2  
0.9  
µA (max)  
µW (max)  
PPD1  
Power Consumption  
Power Down Mode (PD2) -- 2-wire interface active. Master communicating with a different device on the bus.  
VA = 2.7V to 3.6V  
VA = 4.5V to 5.5V  
VA = 2.7V to 3.6V  
VA = 4.5V to 5.5V  
VA = 3.0V  
13  
27  
45  
80  
µA (max)  
µA (max)  
µA (max)  
µA (max)  
mW  
fSCL=400kHz  
fSCL=3.4MHz  
fSCL=400kHz  
fSCL=3.4MHz  
IPD2  
Supply Current  
89  
150  
250  
168  
0.04  
0.14  
0.29  
0.84  
VA = 5.0V  
mW  
PPD2  
Power Consumption  
VA = 3.0V  
mW  
VA = 5.0V  
mW  
(4) This parameter is specified by design and/or characterization and is not tested in production.  
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A.C. and Timing Characteristics  
The following specifications apply for VA = +2.7V to +5.5V. Boldface limits apply for TMIN ≤ TA ≤ TMAX and all other limits are  
at TA = 25°C, unless otherwise specified.  
Units  
(Limits)  
Symbol  
Parameter  
Conditions(1)  
Typical(2)  
Limits(1)(2)  
CONVERSION RATE  
Conversion Time  
1
µs  
fSCL = 100kHz  
fSCL = 400kHz  
fSCL = 1.7MHz  
fSCL = 3.4MHz  
5.56  
22.2  
94.4  
188.9  
ksps  
ksps  
ksps  
ksps  
fCONV  
Conversion Rate  
DIGITAL TIMING SPECS (SCL, SDA)  
Standard Mode  
Fast Mode  
High Speed Mode, Cb = 100pF  
High Speed Mode, Cb = 400pF  
100  
400  
3.4  
1.7  
kHz (max)  
kHz (max)  
MHz (max)  
MHz (max)  
fSCL  
Serial Clock Frequency  
SCL Low Time  
Standard Mode  
Fast Mode  
High Speed Mode, Cb = 100pF  
High Speed Mode, Cb = 400pF  
4.7  
1.3  
160  
320  
us (min)  
us (min)  
ns (min)  
ns (min)  
tLOW  
Standard Mode  
Fast Mode  
High Speed Mode, Cb = 100pF  
High Speed Mode, Cb = 400pF  
4.0  
0.6  
60  
us (min)  
us (min)  
ns (min)  
ns (min)  
tHIGH  
SCL High Time  
120  
Standard Mode  
Fast Mode  
High Speed Mode  
250  
100  
10  
ns (min)  
ns (min)  
ns (min)  
tSU;DAT  
Data Setup Time  
0
3.45  
us (min)  
us (max)  
Standard Mode(3)  
0
0.9  
us (min)  
us (max)  
Fast Mode(3)  
tHD;DAT  
Data Hold Time  
0
70  
ns (min)  
ns (max)  
High Speed Mode, Cb = 100pF  
High Speed Mode, Cb = 400pF  
0
150  
ns (min)  
ns (max)  
Standard Mode  
Fast Mode  
High Speed Mode  
4.7  
0.6  
160  
us (min)  
us (min)  
ns (min)  
Setup time for a start or a repeated  
start condition  
tSU;STA  
Standard Mode  
Fast Mode  
High Speed Mode  
4.0  
0.6  
160  
us (min)  
us (min)  
ns (min)  
Hold time for a start or a repeated start  
condition  
tHD;STA  
Bus free time between a stop and start Standard Mode  
4.7  
1.3  
us (min)  
us (min)  
tBUF  
condition  
Fast Mode  
Standard Mode  
Fast Mode  
High Speed Mode  
4.0  
0.6  
160  
us (min)  
us (min)  
ns (min)  
tSU;STO  
Setup time for a stop condition  
Standard Mode  
1000  
ns (max)  
20+0.1Cb  
300  
ns (min)  
ns (max)  
Fast Mode  
trDA  
Rise time of SDA signal  
10  
80  
ns (min)  
ns (max)  
High Speed Mode, Cb = 100pF  
High Speed Mode, Cb = 400pF  
20  
160  
ns (min)  
ns (max)  
(1) Cb refers to the capacitance of one bus line. Cb is expressed in pF units.  
(2) Typical figures are at TJ = 25°C, and represent most likely parametric norms. Test limits are specified to AOQL (Average Outgoing  
Quality Level).  
(3) The ADC081C021 will provide a minimum data hold time of 300ns to comply with the I2C Specification.  
8
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A.C. and Timing Characteristics (continued)  
The following specifications apply for VA = +2.7V to +5.5V. Boldface limits apply for TMIN ≤ TA ≤ TMAX and all other limits are  
at TA = 25°C, unless otherwise specified.  
Units  
(Limits)  
Symbol  
Parameter  
Conditions(1)  
Standard Mode  
Typical(2)  
Limits(1)(2)  
250  
ns (max)  
20+0.1Cb  
250  
ns (min)  
ns (max)  
Fast Mode  
tfDA  
Fall time of SDA signal  
10  
80  
ns (min)  
ns (max)  
High Speed Mode, Cb = 100pF  
20  
160  
ns (min)  
ns (max)  
High Speed Mode, Cb = 400pF  
Standard Mode  
1000  
ns (max)  
20+0.1Cb  
300  
ns (min)  
ns (max)  
Fast Mode  
trCL  
trCL1  
tfCL  
Rise time of SCL signal  
10  
40  
ns (min)  
ns (max)  
High Speed Mode, Cb = 100pF  
20  
80  
ns (min)  
ns (max)  
High Speed Mode, Cb = 400pF  
Standard Mode  
1000  
ns (max)  
20+0.1Cb  
300  
ns (min)  
ns (max)  
Fast Mode  
Rise time of SCL signal after a  
repeated start condition and after an  
acknowledge bit.  
10  
80  
ns (min)  
ns (max)  
High Speed Mode, Cb = 100pF  
20  
160  
ns (min)  
ns (max)  
High Speed Mode, Cb = 400pF  
Standard Mode  
300  
ns (max)  
20+0.1Cb  
300  
ns (min)  
ns (max)  
Fast Mode  
Fall time of a SCL signal  
10  
40  
ns (min)  
ns (max)  
High Speed Mode, Cb = 100pF  
High Speed Mode, Cb = 400pF  
20  
80  
ns (min)  
ns (max)  
Capacitive load for each bus line (SCL  
and SDA)  
Cb  
400  
pF (max)  
Fast Mode  
High Speed Mode  
50  
10  
ns (max)  
ns (max)  
tSP  
Pulse Width of spike suppressed(4)  
(4) Spike suppression filtering on SCL and SDA will suppress spikes that are less than 50ns for standard and fast modes, and less than  
10ns for hs-mode.  
Timing Diagrams  
SDA  
t
BUF  
t
t
LOW  
t
f
HD;STA  
t
r
t
t
SP  
t
f
r
SCL  
t
t
HD;STA  
SU;STA  
t
SU;STO  
t
HIGH  
t
t
SU;DAT  
HD;DAT  
STOP START  
START  
REPEATED  
START  
Figure 4. Serial Timing Diagram  
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Specification Definitions  
ACQUISITION TIME is the time required for the ADC to acquire the input voltage. During this time, the hold  
capacitor is charged by the input voltage.  
APERTURE DELAY is the time between the start of a conversion and the time when the input signal is internally  
acquired or held for conversion.  
CONVERSION TIME is the time required, after the input voltage is acquired, for the ADC to convert the input  
voltage to a digital word.  
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1  
LSB.  
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise  
and Distortion or SINAD. ENOB is defined as (SINAD - 1.76) / 6.02 and says that the converter is equivalent to a  
perfect ADC of this (ENOB) number of bits.  
FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental  
drops 3 dB below its low frequency value for a full scale input.  
GAIN ERROR is the deviation of the last code transition (111...110) to (111...111) from the ideal (VREF - 1.5  
LSB), after adjusting for offset error.  
INTEGRAL NON-LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from  
negative full scale (½ LSB below the first code transition) through positive full scale (½ LSB above the last code  
transition). The deviation of any given code from this straight line is measured from the center of that code value.  
INTERMODULATION DISTORTION (IMD) is the creation of additional spectral components as a result of two  
sinusoidal frequencies being applied to an individual ADC input at the same time. It is defined as the ratio of the  
power in both the second and third order intermodulation products to the power in one of the original frequencies.  
Second order products are fa ± fb, where fa and fb are the two sine wave input frequencies. Third order products  
are (2fa ± fb ) and (fa ± 2fb). IMD is usually expressed in dB.  
MISSING CODES are those output codes that will never appear at the ADC output. The ADC081C021 is  
ensured not to have any missing codes.  
OFFSET ERROR is the deviation of the first code transition (000...000) to (000...001) from the ideal (i.e. GND +  
0.5 LSB).  
SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal to the rms  
value of the sum of all other spectral components below one-half the sampling frequency, not including  
harmonics or d.c.  
SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD) Is the ratio, expressed in dB, of the rms value of the  
input signal to the rms value of all of the other spectral components below half the clock frequency, including  
harmonics but excluding d.c.  
SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the desired signal  
amplitude to the amplitude of the peak spurious spectral component, where a spurious spectral component is  
any signal present in the output spectrum that is not present at the input and may or may not be a harmonic.  
TOTAL HARMONIC DISTORTION (THD) is the ratio, expressed in dBc, of the rms total of the first n harmonic  
components at the output to the rms level of the input signal frequency as seen at the output. THD is calculated  
as  
2
2
A
+ L + A  
f2  
Fn  
THD = 20 x log  
10  
2
A
f1  
(1)  
where Af1 is the RMS power of the input frequency at the output and Af2 through Afn are the RMS power in the  
first n harmonic frequencies.  
THROUGHPUT TIME is the minimum time required between the start of two successive conversions. It is the  
acquisition time plus the conversion time.  
LEAST SIGNIFICANT BIT (LSB) is the bit that has the smallest value or weight of all bits in a word. This value is  
LSB = VA / 2n  
(2)  
10  
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where VA is the supply voltage for this product, and "n" is the resolution in bits, which is 8 for the ADC081C021.  
MOST SIGNIFICANT BIT (MSB) is the bit that has the largest value or weight of all bits in a word. Its value is  
1/2 of VA.  
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Typical Performance Characteristics  
fSCL = 400kHz, fSAMPLE = 22ksps, fIN = 1kHz, VA = 5.0V, TA = +25°C, unless otherwise stated.  
INL vs. Code - VA=3V  
DNL vs. Code - VA=3V  
Figure 5.  
Figure 6.  
INL vs. Code - VA=5V  
DNL vs. Code - VA=5V  
Figure 7.  
Figure 8.  
INL vs. Supply  
DNL vs. Supply  
Figure 9.  
Figure 10.  
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Typical Performance Characteristics (continued)  
fSCL = 400kHz, fSAMPLE = 22ksps, fIN = 1kHz, VA = 5.0V, TA = +25°C, unless otherwise stated.  
ENOB vs. Supply  
SINAD vs. Supply  
Figure 11.  
Figure 12.  
FFT Plot - VA=3V  
FFT Plot - VA=3V  
Figure 13.  
Figure 14.  
Offset Error vs. Temperature  
Gain Error vs. Temperature  
Figure 15.  
Figure 16.  
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Typical Performance Characteristics (continued)  
fSCL = 400kHz, fSAMPLE = 22ksps, fIN = 1kHz, VA = 5.0V, TA = +25°C, unless otherwise stated.  
Continuous Operation Supply Current vs. VA  
Automatic Conversion Supply Current vs. VA  
Figure 17.  
Figure 18.  
Power Down (PD1) Supply Current vs. VA  
Figure 19.  
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Functional Description  
The ADC081C021 and the ADC081C027 are successive-approximation analog-to-digital converters designed  
around a charge-redistribution digital-to-analog converter. Unless otherwise stated, references to the  
ADC081C021 in this section will apply to both the ADC081C021 and the ADC081C027.  
CONVERTER OPERATION  
Simplified schematics of the ADC081C021 in both track and hold operation are shown in Figure 20 and  
Figure 21 respectively. In Figure 20, the ADC081C021 is in track mode. SW1 connects the sampling capacitor to  
the analog input channel and SW2 equalizes the comparator inputs. The ADC is in this state for approximately  
0.4µs at the beginning of every conversion cycle, which begins at the ACK fall of SDA. Conversions occur when  
the conversion result register is read and when the ADC is in automatic conversion mode. (see AUTOMATIC  
CONVERSION MODE).  
Figure 21 shows the ADC081C021 in hold mode. SW1 connects the sampling capacitor to ground and SW2  
unbalances the comparator. The control logic then instructs the charge-redistribution DAC to add or subtract  
fixed amounts of charge to or from the sampling capacitor until the comparator is balanced. When the  
comparator is balanced, the digital word supplied to the DAC is also the digital representation of the analog input  
voltage. This digital word is stored in the conversion result register and read via the 2-wire interface.  
In the Normal (non-Automatic) Conversion mode, a new conversion is started after the previous conversion result  
is read. In the Automatic Mode, conversions are started at set intervals, as determined by bits D7 through D5 of  
the Configuration Register. The intent of the Automatic mode is to provide a "watchdog" function to ensure that  
the input voltage remains within the limits set in the Alert Limit Registers. The minimum and maximum  
conversion results can then be read from the Lowest Conversion Register and the Highest Conversion Register,  
as described in INTERNAL REGISTERS.  
CHARGE  
REDISTRIBUTION  
DAC  
CHARGE  
REDISTRIBUTION  
DAC  
V
V
IN  
IN  
SAMPLING  
SAMPLING  
CAPACITOR  
CAPACITOR  
SW1  
SW1  
+
-
+
-
CONTROL  
LOGIC  
CONTROL  
LOGIC  
SW2  
SW2  
AGND  
AGND  
V
A
/2  
V /2  
A
Figure 20. ADC081C021 in Track Mode  
Figure 21. ADC081C021 in Hold Mode  
ANALOG INPUT  
An equivalent circuit for the input of the ADC081C021 is shown in Figure 22. The diodes provide ESD protection  
for the analog input. The operating range for the analog input is 0 V to VA. Going beyond this range will cause  
the ESD diodes to conduct and result in erratic operation. For this reason, these diodes should NOT be used to  
clamp the input signal.  
The capacitor C1 in Figure 22 has a typical value of 3 pF and is mainly the package pin capacitance. Resistor R1  
is the on resistance (RON) of the multiplexer and track / hold switch and is typically 500Ω. Capacitor C2 is the  
ADC081C021 sampling capacitor, and is typically 30 pF. The ADC081C021 will deliver best performance when  
driven by a low-impedance source (less than 100Ω). This is especially important when using the ADC081C021 to  
sample dynamic signals. A buffer amplifier may be necessary to limit source impedance. Use a precision op-amp  
to maximize circuit performance. Also important when sampling dynamic signals is a band-pass or low-pass filter  
to reduce noise at the input.  
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V
A
C2  
30 pF  
D1  
D2  
R1  
V
IN  
C1  
3 pF  
Conversion Phase - Switch Open  
Track Phase - Switch Closed  
Figure 22. Equivalent Input Circuit  
The analog input is sampled for eight internal clock cycles, or for typically 400 ns, after the fall of SDA for  
acknowledgement. This time could be as long as about 530 ns. The sampling switch opens and the conversion  
begins this time after the fall of ACK. This time are typical at room temperature and may vary with temperature.  
ADC TRANSFER FUNCTION  
The output format of the ADC081C021 is straight binary. Code transitions occur midway between successive  
integer LSB values. The LSB width for the ADC081C021 is VA / 256. The ideal transfer characteristic is shown in  
Figure 23. The transition from an output code of 0000 0000 0000 to a code of 0000 0000 0001 is at 1/2 LSB, or a  
voltage of VA / 512. Other code transitions occur at intervals of 1 LSB.  
111...111  
111...110  
111...000  
ö
1 LSB = V /256  
A
011...111  
000...010  
000...001  
000...000  
+V - 1.5 LSB  
A
0.5 LSB  
0V  
ANALOG INPUT  
Figure 23. Ideal Transfer Characteristic  
REFERENCE VOLTAGE  
The ADC081C021 uses the supply (VA) as the reference, so VA must be treated as a reference. The analog-to-  
digital conversion will only be as precise as the reference (VA), so the supply voltage should be free of noise. The  
reference should be driven by a low output impedance voltage source.  
The Applications section provides recommended ways to provide the supply voltage appropriately. Refer to  
TYPICAL APPLICATION CIRCUIT for details.  
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POWER-ON RESET  
An internal power-on reset (POR) occurs when the supply voltage transitions above the power-on reset  
threshold. Each of the registers contains a defined value upon POR and this data remains there until any of the  
following occurs:  
•
•
•
The first conversion is completed, causing the Conversion Result and Status registers to be updated.  
A different data word is written to a writeable register.  
The ADC is powered down.  
The internal registers will lose their contents if the supply voltage goes below 2.4V. Should this happen, it is  
important that the VA supply be lowered to a maximum of 200mV before the supply is raised again to properly  
reset the device and ensure that the ADC performs as specified.  
INTERNAL REGISTERS  
The ADC081C021 has 8 internal data registers and one address pointer. The registers provide additional ADC  
functions such as storing minimum and maximum conversion results, setting alert threshold levels, and storing  
data to configure the operation of the device. Figure 24 shows all of the registers and their corresponding  
address pointer values. All of the registers are read/write capable except the conversion result register which is  
read-only.  
Conversion Result  
Pointer = 00000000  
Alert Status  
Pointer = 00000001  
Configuration  
Pointer = 00000010  
Pointer  
Register  
Low Limit  
Pointer = 00000011  
(selects  
register to  
read from  
or write to)  
High Limit  
Pointer = 00000100  
Hysteresis  
Pointer = 00000101  
Lowest Conversion  
Pointer = 00000110  
Highest Conversion  
Pointer = 00000111  
SDA  
SCL  
2
I C Serial Interface  
Figure 24. Register Structure  
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Address Pointer Register  
The address pointer determines which of the data registers is accessed by the I2C interface. The first data byte  
of every write operation is stored in the address pointer register. This value selects the register that the following  
data bytes will be written to or read from. Only the three LSBs of this register are variable. The other bits must  
always be written to as zeros. After a power-on reset, the pointer register defaults to all zeros (conversion result  
register).  
Default Value: 00h  
P7  
P6  
P5  
P4  
P3  
P2  
P1  
P0  
0
0
0
0
0
Register Select  
P2  
P1  
P0  
0
REGISTER  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
Conversion Result (read only)  
Alert Status (read/write)  
1
0
Configuration (read/write)  
Low Limit (read/write)  
1
0
High Limit (read/write)  
1
Hysteresis (read/write)  
0
Lowest Conversion (read/write)  
Highest Conversion (read/write)  
1
Conversion Result Register  
This register holds the result of the most recent conversion. In the normal mode, a new conversion is started  
whenever this register is read. The conversion result data is in straight binary format with the MSB at D11.  
Pointer Address 00h (Read Only)  
Default Value: 0000h  
D15  
D14  
D13  
D12  
D4  
D11  
D3  
D10  
D9  
D8  
D0  
Alert Flag  
Reserved  
Conversion Result [7:4]  
D7  
D6  
D5  
D2  
D1  
Conversion Result [3:0]  
Reserved  
Bits  
Name  
Description  
15  
Alert Flag  
This bit indicates when an alert condition has occurred. When the Alert Bit Enable is set in the  
Configuration Register, this bit will be high if either alert flag is set in the Alert Status Register.  
Otherwise, this bit is a zero. The I2C controller will typically read the Alert Status register and other data  
registers to determine the source of the alert.  
14:12  
11:4  
Reserved  
Always reads zeros.  
Conversion Result  
The Analog-to-Digital conversion result. The Conversion result data is a 8-bit data word in straight  
binary format. The MSB is D11.  
3:0  
Reserved  
Always reads zeros.  
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Alert Status Register  
This register indicates if a high or a low threshold has been violated. The bits of this register are active high. That  
is, a high indicates that the respective limit has been violated.  
Pointer Address 01h (Read/Write)  
Default Value: 00h  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
Reserved  
Over Range  
Alert  
Under Range  
Alert  
Bits  
7:2  
1
Name  
Description  
Always reads zeros. Zeros must be written to these bits.  
Reserved  
Over Range  
Alert Flag  
Bit is set to 1 when the measured voltage exceeds the VHIGH limit stored in the programmable VHIGH  
limit register. Flag is reset to 0 when one of the following two conditions is met: (1) The controller writes  
a one to this bit. (2) The measured voltage decreases below the programmed VHIGH limit minus the  
programmed VHYST value (See Figure 27) . The alert will only self-clear if the Alert Hold bit is cleared in  
the Configuration register. If the Alert Hold bit is set, the only way to clear an over range alert is to write  
a one to this bit.  
0
Under Range  
Alert Flag  
Bit is set to 1 when the measured voltage falls below the VLOW limit stored in the programmable VLOW  
limit register. Flag is reset to 0 when one of the following two conditions is met: (1) The controller writes  
a one to this bit. (2) The measured voltage increases above the programmed VLOW limit plus the  
programmed VHYST value. The alert will only self-clear if the Alert Hold bit is cleared in the  
Configuration register. If the Alert Hold bit is set, the only way to clear an under range alert is to write a  
one to this bit.  
Configuration Register  
Pointer Address 02h (Read/Write)  
Default Value: 00h  
D7  
D6  
D5  
D4  
D3  
D2  
D1  
D0  
Cycle Time [2:0]  
Alert Hold  
Alert Flag Enable  
Alert Pin Enable  
0
Polarity  
Cycle Time[2:0]  
Conversion  
Interval  
Typical fconvert  
(ksps)  
D7  
D6  
0
D5  
0
0
0
0
0
1
1
1
1
Mode Disabled  
Tconvert x 32  
0
0
1
27  
1
0
Tconvert x 64  
13.5  
6.7  
3.4  
1.7  
0.9  
0.4  
1
1
Tconvert x 128  
Tconvert x 256  
Tconvert x 512  
Tconvert x 1024  
Tconvert x 2048  
0
0
0
1
1
0
1
1
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Bits  
Name  
Description  
7:5  
Cycle Time  
Configures Automatic Conversion mode. When these bits are set to zeros, the automatic conversion  
mode is disabled. This is the case at power-up.  
When these bits are set to a non-zero value, the ADC will begin operating in automatic conversion  
mode. (See AUTOMATIC CONVERSION MODE). The Cycle Time table shows how different values  
provide various conversion intervals.  
4
Alert Hold  
0: Alerts will self-clear when the measured voltage moves within the limits by more than the hysteresis  
register value.  
1: Alerts will not self-clear and are only cleared when a one is written to the alert high flag or the alert  
low flag in the Alert Status register.  
3
2
Alert Flag Enable  
Alert Pin Enable  
0: Disables alert status bit [D15] in the Conversion Result register.  
1: Enables alert status bit [D15] in the Conversion Result register.  
0: Disables the ALERT output pin. The ALERT output will TRI-STATE when the pin is disabled.  
1: Enables the ALERT output pin.  
*This bit does not apply to the ADC081C027.  
1
0
Reserved  
Polarity  
Always reads zeros. Zeros must be written to these bits.  
This bit configures the active level polarity of the ALERT output pin.  
0: Sets the ALERT pin to active low.  
1: Sets the ALERT pin to active high.  
*This bit does not apply to the ADC081C027.  
VLOW -- Alert Limit Register - Under Range  
This register holds the lower limit threshold used to determine the alert condition. If the conversion moves lower  
than this limit, a VLOW alert is generated.  
Pointer Address 03h (Read/Write)  
Default Value: 0000h  
D15  
D14  
D13  
D12  
D4  
D11  
D3  
D10  
D9  
D1  
D8  
D0  
Reserved  
VLOW Limit [7:4]  
D7  
D6  
D5  
D2  
VLOW Limit [3:0]  
Reserved  
Bits  
Name  
Description  
Always reads zeros. Zeros must be written to these bits.  
15:12  
11:4  
Reserved  
VLOW Limit  
Sets the lower limit threshold used to determine the alert condition. If the conversion moves lower than  
this limit, a VLOW alert is generated.  
3:0  
Reserved  
Always reads zeros. Zeros must be written to these bits.  
VHIGH -- Alert Limit Register - Over Range  
This register holds the upper limit threshold used to determine the alert condition. If the conversion moves higher  
than this limit, a VHIGH alert is generated.  
Pointer Address 04h (Read/Write)  
Default Value: 0FFFh  
D15  
D14  
D13  
D12  
D4  
D11  
D3  
D10  
D9  
D1  
D8  
D0  
Reserved  
VHIGH Limit [7:4]  
D7  
D6  
D5  
D2  
VHIGH Limit [3:0]  
Reserved  
20  
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Bits  
Name  
Description  
15:12  
11:4  
Reserved  
VHIGH Limit  
Always reads zeros. Zeros must be written to these bits.  
Sets the upper limit threshold used to determine the alert condition. If the conversion moves higher  
than this limit, a VHIGH alert is generated.  
3:0  
Reserved  
Always reads zeros. Zeros must be written to these bits.  
VHYST -- Alert Hysteresis Register  
This register holds the hysteresis value used to determine the alert condition. After a VHIGH or VLOW alert occurs,  
the conversion result must move within the VHIGH or VLOW limit by more than this value to clear the alert  
condition. Note: If the Alert Hold bit is set in the configuration register, alert conditions will not self-clear.  
Pointer Address 05h (Read/Write)  
Default Value: 0000h  
D15  
D14  
D13  
D12  
D4  
D11  
D3  
D10  
D9  
D1  
D8  
D0  
Reserved  
Hysteresis [7:4]  
D7  
D6  
D5  
D2  
Hysteresis [3:0]  
Reserved  
Bits  
15:12  
11:4  
3:0  
Name  
Description  
Reserved  
Hysteresis  
Reserved  
Always reads zeros. Zeros must be written to these bits.  
Hysteresis value. D11 is MSB.  
Always reads zeros. Zeros must be written to these bits.  
VMIN -- Lowest Conversion Register  
This register holds the Lowest Conversion result when in the automatic conversion mode. Each conversion result  
is compared against the contents of this register. If the value is lower, it becomes the lowest conversion and  
replaces the current value. If the value is higher, the register contents remain unchanged. The lowest conversion  
value can be cleared at any time by writing 0FFFh to this register. The value of this register will update  
automatically when the automatic conversion mode is enabled, but is NOT updated in the normal mode.  
Pointer Address 06h (Read/Write)  
Default Value: 0FFFh  
D15  
D14  
D13  
D12  
D4  
D11  
D3  
D10  
D9  
D8  
D0  
Reserved  
Lowest Conversion [7:4]  
D7  
D6  
D5  
D2  
D1  
Lowest Conversion [3:0]  
Reserved  
Bits  
15:12  
11:4  
3:0  
Name  
Description  
Reserved  
Always reads zeros. Zeros must be written to these bits.  
Lowest conversion result data. D11 is MSB.  
Lowest Conversion  
Reserved  
Always reads zeros. Zeros must be written to these bits.  
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VMAX -- Highest Conversion Register  
This register holds the Highest Conversion result when in the Automatic mode. Each conversion result is  
compared against the contents of this register. If the value is higher, it replaces the previous value. If the value is  
lower, the register contents remain unchanged. The highest conversion value can be cleared at any time by  
writing 0000h to this register. The value of this register will update automatically when the automatic conversion  
mode is enabled, but is NOT updated in the normal mode.  
Pointer Address 07h (Read/Write)  
Default Value: 0000h  
D15  
D14  
D13  
D12  
D4  
D11  
D3  
D10  
D9  
D8  
D0  
Reserved  
Highest Conversion [7:4]  
D7  
D6  
D5  
D2  
D1  
Highest Conversion [3:0]  
Reserved  
Bits  
15:12  
11:4  
3:0  
Name  
Description  
Reserved  
Always reads zeros. Zeros must be written to these bits.  
Highest conversion result data. D11 is MSB.  
Highest Conversion  
Reserved  
Always reads zeros. Zeros must be written to these bits.  
SERIAL INTERFACE  
The I2C-compatible interface operates in all three speed modes. Standard mode (100kHz) and Fast mode  
(400kHz) are functionally the same and will be referred to as Standard-Fast mode in this document. High-Speed  
mode (3.4MHz) is an extension of Standard-Fast mode and will be referred to as Hs-mode in this document.  
The following diagrams describe the timing relationships of the clock (SCL) and data (SDA) signals. Pull-up  
resistors or current sources are required on the SCL and SDA busses to pull them high when they are not being  
driven low. A logic zero is transmitted by driving the output low. A logic high is transmitted by releasing the output  
and allowing it to be pulled-up externally. The appropriate pull-up resistor values will depend upon the total bus  
capacitance and operating speed. The ADC081C021 offers extended ESD tolerance (8kV HBM) for the I2C bus  
pins (SCL & SDA) allowing extension of the bus across multiple boards without extra ESD protection.  
Basic I2C Protocol  
The I2C interface is bi-directional and allows multiple devices to operate on the same bus. The bus consists of  
master devices and slave devices which can communicate back and forth over the I2C interface. Master devices  
control the bus and are typically microcontrollers, FPGAs, DSPs, or other digital controllers. Slave devices are  
controlled by a master and are typically peripheral devices such as the ADC081C021. To support multiple  
devices on the same bus, each slave has a unique hardware address which is referred to as the "slave address."  
To communicate with a particular device on the bus, the controller (master) sends the slave address and listens  
for a response from the slave. This response is referred to as an acknowledge bit. If a slave on the bus is  
addressed correctly, it acknowledges (ACKs) the master by driving the SDA bus low. If the address doesn't  
match a device's slave address, it not-acknowledges (NACKs) the master by letting SDA be pulled high. ACKs  
also occur on the bus when data is being transmitted. When the master is writing data, the slave ACKs after  
every data byte is successfully received. When the master is reading data, the master ACKs after every data  
byte is received to let the slave know it wants to receive another data byte. When the master wants to stop  
reading, it NACKs after the last data byte and creates a stop condition on the bus.  
All communication on the bus begins with either a Start condition or a Repeated Start condition. The protocol for  
starting the bus varies between Standard-Fast mode and Hs-mode. In Standard-Fast mode, the master  
generates a Start condition by driving SDA from high to low while SCL is high. In Hs-mode, starting the bus is  
more complicated. Please refer to High-Speed (Hs) Mode for the full details of a Hs-mode Start condition.  
A Repeated Start is generated to address a different device or register, or to switch between read and write  
modes. The master generates a Repeated Start condition by driving SDA low while SCL is high. Following the  
Repeated Start, the master sends out the slave address and a read/write bit as shown in Figure 25. The bus  
continues to operate in the same speed mode as before the Repeated Start condition.  
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All communication on the bus ends with a Stop condition. In either Standard-Fast mode or Hs-Mode, a Stop  
condition occurs when SDA is pulled high while SCL is high. After a Stop condition, the bus remains idle until a  
master generates another Start condition.  
Please refer to the Philips I2C® Specification (Version 2.1 Jan, 2000) for a detailed description of the serial  
interface.  
ACK  
MSB  
N/ACK  
SDA  
SCL  
MSB  
LSB  
LSB  
R/W  
Direction  
Bit  
7-bit Slave Address  
Data Byte  
Acknowledge  
from the Device  
*Acknowledge  
or Not-ACK  
8
9
8
9
1
2
6
7
1
2
Repeated for the Lower Data Byte  
and Additional Data Transfers  
START or  
REPEATED  
START  
STOP  
*Note: In continuous mode, this bit must be an ACK from  
the data receiver. Immediately preceding a STOP  
condition, this bit must be a NACK from the master.  
Figure 25. Basic Operation.  
Standard-Fast Mode  
In Standard-Fast mode, the master generates a start condition by driving SDA from high to low while SCL is  
high. The start condition is always followed by a 7-bit slave address and a Read/Write bit. After these 8 bits have  
been transmitted by the master, SDA is released by the master and the ADC081C021 either ACKs or NACKs the  
address. If the slave address matches, the ADC081C021 ACKs the master. If the address doesn't match, the  
ADC081C021 NACKs the master.  
For a write operation, the master follows the ACK by sending the 8-bit register address pointer to the ADC. Then  
the ADC081C021 ACKs the transfer by driving SDA low. Next, the master sends the upper 8-bits to the  
ADC081C021. Then the ADC081C021 ACKs the transfer by driving SDA low. For a single byte transfer, the  
master should generate a stop condition at this point. For a 2-byte write operation, the lower 8-bits are sent by  
the master. The ADC081C021 then ACKs the transfer, and the master either sends another pair of data bytes,  
generates a Repeated Start condition to read or write another register, or generates a Stop condition to end  
communication.  
A read operation can take place either of two ways:  
If the address pointer is pre-set before the read operation, the desired register can be read immediately following  
the slave address. In this case, the upper 8-bits of the register, set by the pre-set address pointer, are sent out  
by the ADC. For a single byte read operation, the Master sends a NACK to the ADC and generates a Stop  
condition to end communication after receiving 8-bits of data. For a 2-Byte read operation, the Master continues  
the transmission by sending an ACK to the ADC. Then, the ADC sends out the lower 8-bits of the ADC register.  
At this point, the master either sends; an ACK to receive more data or, a NACK followed by a Stop or Repeated  
Start. If the master sends an ACK, the ADC sends the next upper data byte, and the read cycle repeats.  
If the ADC081S021 address pointer needs to be set, the master needs to write to the device and set the address  
pointer before reading from the desired register. This type of read requires a start, the slave address, a write bit,  
the address pointer, a Repeated Start (if appropriate), the slave address, and a read bit (refer to Figure 30).  
Following this sequence, the ADC sends out the upper 8-bits of the register. For a single byte read operation, the  
Master must then send a NACK to the ADC and generate a Stop condition to end communication. For a 2-Byte  
write operation, the Master sends an ACK to the ADC. Then, the ADC sends out the lower 8-bits of the ADC  
register. At this point, the master sends either an ACK to receive more data, or a NACK followed by a Stop or  
Repeated Start. If the master sends an ACK, the ADC sends another pair of data bytes, and the read cycle will  
repeat. The number of data words that can be read is unlimited.  
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High-Speed (Hs) Mode  
For Hs-mode, the sequence of events to begin communication differs slightly from Standard-Fast mode.  
Figure 26 describes this in further detail. Initially, the bus begins running in Standard-Fast mode. The master  
generates a Start condition and sends the 8-bit Hs master code (00001XXX) to the ADC081C021. Next, the  
ADC081C021 responds with a NACK. Once the SCL line has been pulled to a high level, the master switches to  
Hs-mode by increasing the bus speed and generating a second Repeated Start condition (driving SDA low while  
SCL is pulled high). At this point, the master sends the slave address to the ADC081C021, and communication  
continues as shown above in the "Basic Operation" Diagram (see Figure 25).  
When the master generates a Repeated Start condition while in Hs-mode, the bus stays in Hs-mode awaiting the  
slave address from the master. The bus continues to run in Hs-mode until a Stop condition is generated by the  
master. When the master generates a Stop condition on the bus, the bus must be started in Standard-Fast mode  
again before increasing the bus speed and switching to Hs-mode.  
NACK  
SDA  
MSB  
8-bit Master code —00001xxx“  
7-bit Slave  
Address  
Not-Acknowledge  
from the Device  
8
9
1
2
6
7
1
2
SCL  
5
Repeated  
START  
START  
Standard-Fast Mode  
Hs-Mode  
Figure 26. Beginning Hs-Mode Communication  
I2C Slave (Hardware) Address  
The ADC has a seven-bit hardware address which is also referred to as a slave address. For the VSSOP-8  
version of the ADC081C021, this address is configured by the ADR0 and ADR1 addres selection inputs. For the  
ADC081C027, the address is configured by the ADR0 address selection input. ADR0 and ADR1 can be  
grounded, left floating, or tied to VA. If desired, ADR0 can be set to VA/2 rather than left floating. The state of  
these inputs sets the hardware address that the ADC responds to on the I2C bus (see Table 2). For the SOT-6  
version of the ADC081C021, the hardware address is not pin-configurable and is set to 1010100. The diagrams  
in COMMUNICATING WITH THE ADC081C021 describe how the I2C controller should address the ADC via the  
I2C interface.  
Pin compatible alternatives that provide additional address options to the SOT-6 version of the ADC081C021 and  
the ADC081C027 are available.  
Table 2. Slave Addresses  
ADC081C027  
ADC081C021  
ADC081C021  
(SOT-6)  
(SOT-6)  
(VSSOP-8)  
Slave Address  
[A6 - A0]  
ADR0  
Floating  
ALERT  
ADR1  
Floating  
Floating  
Floating  
GND  
GND  
GND  
VA  
ADR0  
Floating  
GND  
VA  
1010000  
1010001  
1010010  
1010100  
1010101  
1010110  
1011000  
1011001  
1011010  
-----------------  
-----------------  
-----------------  
Single Address  
-----------------  
-----------------  
-----------------  
-----------------  
-----------------  
GND  
VA  
-----------------  
-----------------  
-----------------  
-----------------  
-----------------  
-----------------  
Floating  
GND  
VA  
Floating  
GND  
VA  
VA  
VA  
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ALERT FUNCTION  
The ALERT function is an "out-of-range" indicator. At the end of every conversion, the measured voltage is  
compared to the values in the VHIGH and VLOW registers. If the measured voltage exceeds the value stored in  
VHIGH or falls below the value stored in VLOW, an alert condition occurs. The Alert condition is indicated in up to  
three places. First, the alert condition always causes either or both of the alert flags in the Alert Status register to  
go high. If the measured voltage exceeds the VHIGH limit, the Over Range Alert Flag is set. If the measured  
voltage falls below the VLOW limit, the Under Range Alert Flag is set. Second, if the Alert Flag Enable bit is set in  
the Configuration register, the alert condition also sets the MSB of the Conversion Result register. Third, if the  
Alert Pin Enable bit is set in the Configuration register, the ALERT output becomes active (see Figure 27). The  
ALERT output (ADC081S021 only) can be configured as an active high or active low output via the Polarity bit in  
the Configuration register. If the Polarity bit is cleared, the ALERT output is configured as active low. If the  
Polarity bit is set, the ALERT output is configured as active high.  
The Over Range Alert condition is cleared when one of the following two conditions is met:  
1. The controller writes a one to the Over Range Alert Flag bit.  
2. The measured voltage goes below the programmed VHIGH limit minus the programmed VHYST value and the  
Alert Hold bit is cleared in the Configuration register. (see Figure 27). If the Alert Hold bit is set, the alert  
condition persists and only clears when a one is written to the Over Range Alert Flag bit.  
The Under Range Alert condition is cleared when one of the following two conditions is met:  
1. The controller writes a one to the Under Range Alert Flag bit.  
2. The measured voltage goes above the programmed VLOW limit plus the programmed VHYST value and the  
Alert Hold bit is cleared in the Configuration register. If the Alert Hold bit is set, the alert condition persists  
and only clears when a one is written to the Under Range Alert Flag bit.  
If the alert condition has been cleared by writing a one to the alert flag while the measured voltage still violates  
the VHIGH or VLOW limits, an alert condition will occur again after the completion of the next conversion (see  
Figure 28).  
Alert conditions only occur if the input voltage exceeds the VHIGH limit or falls below the VLOW limit at the sample-  
hold instant. The input voltage can exceed the VHIGH limit or fall below the VLOW limit briefly between conversions  
without causing an alert condition.  
Measured Voltage  
V
V
Limit  
HIGH  
- V  
HIGH  
HYST  
ALERT pin  
(Active Low)  
TIME  
Figure 27. Alert condition cleared when measured voltage crosses VHIGH - VHYST  
Over Range Alert  
Flag set to —1“  
Measured Voltage  
V
V
Limit  
HIGH  
- V  
HIGH  
HYST  
ALERT pin  
(Active Low)  
TIME  
Figure 28. Alert condition cleared by writing a "1" to the Alert Flag.  
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AUTOMATIC CONVERSION MODE  
The automatic conversion mode configures the ADC to continually perform conversions without receiving "read"  
instructions from the controller over the I2C interface. The mode is activated by writing a non-zero value into the  
Cycle Time bits - D[7:5] - of the Configuration register (see Configuration Register). Once the ADC081C021  
enters this mode, the internal oscillator is always enabled. The ADC's control logic samples the input at the  
sample rate set by the cycle time bits. Although the conversion result is not transmitted by the 2-wire interface, it  
is stored in the conversion result register and updates the various status registers of the device.  
In automatic conversion mode, the out-of-range alert function is active and updates after every conversion. The  
ADC can operate independently of the controller in automatic conversion mode. When the input signal goes "out-  
of-range", an alert signal is sent to the controller. The controller can then read the status registers and determine  
the source of the alert condition. Also, comparison and updating of the VMIN and VMAX registers occurs after every  
conversion in automatic conversion mode. The controller can occasionally read the VMIN and/or VMAX registers to  
determine the sampled input extremes. These register values persist until the user resets the VMIN and VMAX  
registers. These two features are useful in system monitoring, peak detection, and sensing applications.  
COMMUNICATING WITH THE ADC081C021  
The ADC081C021's data registers are selected by the address pointer (see Address Pointer Register). To  
read/write a specific data register, the pointer must be set to that register's address. The pointer is always written  
at the beginning of a write operation. When the pointer needs to be updated for a read cycle, a write operation  
must precede the read operation to set the pointer address correctly. On the other hand, if the pointer is preset  
correctly, a read operation can occur without writing the address pointer register. The following timing diagrams  
describe the various read and write operations supported by the ADC.  
Reading from a 2-Byte ADC Register  
The following diagrams indicate the sequence of actions required for a 2-Byte read from an ADC081C021  
Register.  
1
9
1
9
1
9
SCL  
SDA  
A6 A5 A4 A3 A2 A1 A0 R/W  
D15 D14 D13 D12 D11 D10 D9 D8  
D7 D6 D5 D4 D3 D2 D1 D0  
ACK  
by  
ADC  
ACK  
by  
Master  
N/ACK* Stop  
Start by  
Master  
by  
by  
Master Master  
Frame 1  
Address Byte  
from Master  
Frame 2  
Data Byte from  
ADC  
Frame 3  
Data Byte from  
ADC  
Repeat Frames  
2 & 3 for  
Continuous Mode  
*Note: In continuous mode, this bit must be an ACK. Immediately  
preceding a STOP condition, this bit must be a NACK.  
Figure 29. (a) Typical Read from a 2-Byte ADC Register with Preset Pointer  
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1
9
1
0
9
SCL  
SDA  
R/W  
A6 A5 A4 A3 A2 A1 A0  
0
0
0
0
P2 P1 P0  
Ack  
by  
ADC  
Ack  
by  
ADC  
Start by  
Master  
Frame 1  
Frame 2  
Address Byte  
from Master  
Pointer Byte  
from Master  
1
9
1
9
1
9
SCL  
(continued)  
SDA  
(continued)  
A6 A5 A4 A3 A2 A1 A0  
Repeat  
D15 D14 D13 D12 D11 D10 D9 D8  
D7 D6 D5 D4 D3 D2 D1 D0  
R/W  
ACK  
by  
ADC  
ACK  
by  
Master  
N/ACK* Stop  
Start by  
Master  
by  
by  
Master Master  
Frame 3  
Frame 4  
Data Byte from  
ADC  
Frame 5  
Data Byte from  
ADC  
Address Byte  
from Master  
Repeat Frames  
4 & 5 for  
Continuous Mode  
*Note: In continuous mode, this bit must be an ACK. Immediately  
preceding a STOP condition, this bit must be a NACK.  
Figure 30. (b) Typical Pointer Set Followed by Immediate Read of a 2-Byte ADC Register  
Reading from a 1-Byte ADC Register  
The following diagrams indicate the sequence of actions required for a single Byte read from an ADC081C021  
Register.  
1
9
1
9
SCL  
SDA  
A6 A5 A4 A3 A2 A1 A0  
D7 D6 D5 D4 D3 D2 D1 D0  
R/W  
ACK  
by  
ADC  
NACK  
by  
Master Master  
Stop  
by  
Start by  
Master  
Frame 1  
Address Byte  
from Master  
Frame 2  
Data Byte from  
ADC  
Figure 31. (a) Typical Read from a 1-Byte ADC Register with Preset Pointer  
1
9
1
0
9
SCL  
SDA  
R/W  
A6 A5 A4 A3 A2 A1 A0  
0
0
0
0
P2 P1 P0  
Ack  
by  
ADC  
Ack  
by  
ADC  
Start by  
Master  
Frame 1  
Frame 2  
Address Byte  
from Master  
Pointer Byte  
from Master  
1
9
1
9
SCL  
(continued)  
SDA  
(continued)  
A6 A5 A4 A3 A2 A1 A0  
Repeat  
D7 D6 D5 D4 D3 D2 D1 D0  
R/W  
ACK  
by  
ADC  
NACK  
by  
Stop  
by  
Start by  
Master  
Master Master  
Frame 3  
Frame 4  
Data Byte from  
ADC  
Address Byte  
from Master  
Figure 32. (b) Typical Pointer Set Followed by Immediate Read of a 1-Byte ADC Register  
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Writing to an ADC Register  
The following diagrams indicate the sequence of actions required for writing to an ADC081C021 Register.  
1
9
1
9
1
9
SCL  
SDA  
R/W  
A6 A5 A4 A3 A2 A1 A0  
0
0
0
0
0
P2 P1 P0  
D7 D6 D5 D4 D3 D2 D1 D0  
Start by  
Master  
ACK  
by  
ACK  
by  
ACK Stop by  
by  
Master  
ADC  
ADC  
ADC  
Frame 1  
Address Byte  
from Master  
Frame 2  
Pointer Byte  
from Master  
Frame 3  
Data Byte  
from Master  
Figure 33. (a) Typical Write to a 1-Byte ADC Register  
1
9
1
0
9
SCL  
SDA  
R/W  
A6 A5 A4 A3 A2 A1 A0  
0
0
0
0
P2 P1 P0  
Ack  
by  
ADC  
Ack  
by  
ADC  
Start by  
Master  
Frame 1  
Frame 2  
Address Byte  
from Master  
Pointer Byte  
from Master  
1
9
1
9
SCL  
(continued)  
SDA  
(continued)  
D15 D14 D13 D12 D11 D10 D9 D8  
D7 D6 D5 D4 D3 D2 D1 D0  
ACK  
by  
NACK  
by  
Stop  
by  
ADC  
Master Master  
Frame 3  
Data Byte  
from Master  
Frame 4  
Data Byte  
from Master  
Figure 34. (b) Typical Write to a 2-Byte ADC Register  
QUIET INTERFACE MODE  
To improve performance at High Speed, operate the ADC in Quiet Interface Mode. This mode provides improved  
INL and DNL performance in I2C Hs-Mode (3.4MHz). The Quiet Interface mode provides a maximum throughput  
rate of 162ksps. Figure 35 describes how to read the conversion result register in this mode. Basically, the  
Master needs to release SCL for at least 1µs before the MSB of every upper data byte. The diagram assumes  
that the address pointer register is set to its default value.  
Quiet Interface mode will only improve INL and DNL performance in Hs-Mode. Standard and Fast mode  
performance is unaffected by the Quiet Interface mode.  
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Interface Delay  
tQuiet 8 1us  
1
9
1
9
SCL  
SDA  
R/W  
A6 A5 A4 A3 A2 A1 A0  
D15 D14 D13 D12 D11 D10 D9 D8  
ACK  
by  
ADC  
ACK  
by  
Master  
Start by  
Master  
Frame 1  
Address Byte  
from Master  
Frame 2  
Upper Data Byte  
from ADC  
Interface Delay  
tQuiet 8 1us  
1
9
1
9
1
9
SCL  
(continued)  
SDA  
(continued)  
D7 D6 D5 D4 D3 D2 D1 D0  
D15 D14 D13 D12 D11 D10 D9 D8  
D7 D6 D5 D4 D3 D2 D1 D0  
ACK  
by  
ACK  
by  
NACK  
by  
Stop  
by  
Master  
Master  
Master Master  
Frame 3  
Lower Data Byte  
from ADC  
Frame 4  
Upper Data Byte  
from ADC  
Frame 5  
Lower Data Byte  
from ADC  
Repeat Frames  
4 and 5 for  
Continuous Mode  
Figure 35. Reading in Quiet Interface Mode  
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APPLICATIONS INFORMATION  
TYPICAL APPLICATION CIRCUIT  
A typical application circuit is shown in Figure 36. The analog supply is bypassed with a capacitor network  
located close to the ADC081C021. The ADC uses the analog supply (VA) as its reference voltage, so it is very  
important that VA be kept as clean as possible. Due to the low power requirements of the ADC081C021, it is  
possible to use a precision reference as a power supply.  
The bus pull-up resistors (RP) should be powered by the controller's supply. It is important that the pull-up  
resistors are pulled to the same voltage potential as VA. This will ensure that the logic levels of all devices on the  
bus are compatible. If the controller's supply is noisy, an appropriate bypass capacitor should be added between  
the controller's supply pin and the pull-up resistors. For Hs-mode applications, this bypass capacitance will  
improve the accuracy of the ADC.  
The value of the pull-up resistors (RP) depends upon the characteristics of each particular I2C bus. The I2C  
specification describes how to choose an appropriate value. As a general rule-of-thumb, we suggest using a 1kΩ  
resistor for Hs-mode bus configurations and a 5kΩ resistor for Standard or Fast Mode bus configurations.  
Depending upon the bus capacitance, these values may or may not be sufficient to meet the timing requirements  
of the I2C bus specification. Please see the I2C specification for further information.  
Regulated Supply  
0.1 mF  
4.7 mF  
5 kW  
R
P
R
P
V
DD  
Controller  
V
A
INTERRUPT  
ALERT  
22W  
INPUT  
V
IN  
ADC081C021  
SDA  
SCL  
SDA  
SCL  
470 pF  
GND  
Figure 36. Typical Application Circuit  
BUFFERED INPUT  
A buffered input application circuit is shown in Figure 37. The analog input is buffered by a TI LMP7731. The  
non-inverting amplifier configuration provides a buffered gain stage for a single ended source. This application  
circuit is good for single-ended sensor interface. The input must have a DC bias level that keeps the ADC input  
signal from swinging below GND or above the supply (+5V in this case).  
The LM4132, with its 0.05% accuracy over temperature, is an excellent choice as a reference source for the  
ADC081C021.  
30  
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SNAS447C –FEBRUARY 2008–REVISED MARCH 2013  
Unregulated  
Supply  
LM4132  
4.7 mF  
0.1 mF  
4.7 mF  
V
A
R
INPUT  
S
+
LMP7731  
-
V
IN  
ADC081C027  
SDA  
SCL  
C
S
ADDR  
GND  
R
1
R
2
Figure 37. Buffered Input Circuit  
INTELLIGENT BATTERY MONITOR  
The ADC081C021 is easily used as an intelligent battery monitor. The simple circuit shown in Figure 38, uses  
the ADC081C021, the LP2980 fixed reference, and a resistor divider to implement an intelligent battery monitor  
with a window supervisory feature. The window supervisory feature is implemented by the "out of range" alert  
function. When the battery is recharging, the Over Range Alert will indicate that the charging cycle is complete  
(see Figure 39). When the battery is nearing depletion, the Under Range Alert will indicate that the battery is low  
(see Figure 40).  
RECHARGE CYCLE  
Measured  
Battery  
REF  
Voltage  
R
[LP2980-2.8]  
V
High  
Limit  
Low  
Battery  
Indicator  
V
A
ALERT  
ADC081C021  
To Controller...  
V
IN  
ALERT pin  
(Active Low)  
SCL  
SDA  
GND  
TIME  
Figure 38. Intelligent Battery Monitor Circuit  
Figure 39. Recharge Cycle  
DISCHARGE CYCLE  
Measured  
Battery  
Voltage  
V
LOW  
Limit  
ALERT pin  
(Active Low)  
TIME  
Figure 40. Discharge Cycle  
In addition to the window supervisory feature, the ADC081C021 will allow the controller to read the battery  
voltage at any time during operation.  
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The accurate voltage reading and the alert feature will allow a controller to improve the efficiency of a battery-  
powered device. During the discharge cycle, the controller can switch to a low-battery mode, safely suspend  
operation, or report a precise battery level to the user. During the recharge cycle, the controller can implement an  
intelligent recharge cycle, decreasing the charge rate when the battery charge nears capacity.  
Trickle Charge Controller  
While a battery is discharging, the ADC081C021 can be used to control a trickle charge to keep the battery near  
full capacity (see Figure 41). When the alert output is active, the battery will recharge. An intelligent recharge  
cycle will prevent over-charging and damaging the battery. With a trickle charge, the battery powered device can  
be disconnected from the charger at any time with a full charge.  
Measured  
Battery Voltage  
V +V  
LOW HYST  
V
LOW  
Limit  
ALERT pin  
(Active Low)  
TIME  
Figure 41. Trickle Charge  
LAYOUT, GROUNDING, AND BYPASSING  
For best accuracy and minimum noise, the printed circuit board containing the ADC081C021 should have  
separate analog and digital areas. The areas are defined by the locations of the analog and digital power planes.  
Both of these planes should be located on the same board layer. A single, solid ground plane is preferred if  
digital return current does not flow through the analog ground area. Frequently a single ground plane design will  
utilize a "fencing" technique to prevent the mixing of analog and digital ground currents. Separate ground planes  
should only be utilized when the fencing technique is inadequate. The separate ground planes must be  
connected in one place, preferably near the ADC121C021. Special care is required to ensure that signals do not  
pass over power plane boundaries. Return currents must always have a continuous return path below their  
traces.  
The ADC081C021 power supply should be bypassed with a 4.7µF and a 0.1µF capacitor as close as possible to  
the device with the 0.1µF right at the device supply pin. The 4.7µF capacitor should be a tantalum type and the  
0.1µF capacitor should be a low ESL type. The power supply for the ADC081C021 should only be used for  
analog circuits.  
Avoid crossover of analog and digital signals and keep the clock and data lines on the component side of the  
board. The clock and data lines should have controlled impedances.  
32  
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SNAS447C –FEBRUARY 2008–REVISED MARCH 2013  
REVISION HISTORY  
Changes from Revision B (March 2013) to Revision C  
Page  
•
Changed layout of National Data Sheet to TI format .......................................................................................................... 32  
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PACKAGE OPTION ADDENDUM  
www.ti.com  
11-Apr-2013  
PACKAGING INFORMATION  
Orderable Device  
Status Package Type Package Pins Package  
Eco Plan Lead/Ball Finish  
MSL Peak Temp  
Op Temp (°C)  
-40 to 105  
Top-Side Markings  
Samples  
Drawing  
Qty  
(1)  
(2)  
(3)  
(4)  
ADC081C021CIMK/NOPB  
ADC081C021CIMKX/NOPB  
ADC081C021CIMM/NOPB  
ADC081C021CIMMX/NOPB  
ADC081C027CIMK/NOPB  
ADC081C027CIMKX/NOPB  
ACTIVE  
SOT  
SOT  
DDC  
6
6
8
8
6
6
1000  
Green (RoHS  
& no Sb/Br)  
CU SN  
CU SN  
CU SN  
CU SN  
CU SN  
CU SN  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
Level-1-260C-UNLIM  
X34C  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
ACTIVE  
DDC  
DGK  
DGK  
DDC  
DDC  
3000  
1000  
3500  
1000  
3000  
Green (RoHS  
& no Sb/Br)  
-40 to 105  
X34C  
X36C  
X36C  
X35C  
X35C  
VSSOP  
VSSOP  
SOT  
Green (RoHS  
& no Sb/Br)  
Green (RoHS  
& no Sb/Br)  
Green (RoHS  
& no Sb/Br)  
-40 to 105  
-40 to 105  
SOT  
Green (RoHS  
& no Sb/Br)  
(1) The marketing status values are defined as follows:  
ACTIVE: Product device recommended for new designs.  
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.  
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.  
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.  
OBSOLETE: TI has discontinued the production of the device.  
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability  
information and additional product content details.  
TBD: The Pb-Free/Green conversion plan has not been defined.  
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that  
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.  
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between  
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.  
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight  
in homogeneous material)  
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.  
(4)  
Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a  
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.  
Addendum-Page 1  
PACKAGE OPTION ADDENDUM  
www.ti.com  
11-Apr-2013  
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information  
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and  
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.  
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.  
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.  
Addendum-Page 2  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
26-Mar-2013  
TAPE AND REEL INFORMATION  
*All dimensions are nominal  
Device  
Package Package Pins  
Type Drawing  
SPQ  
Reel  
Reel  
A0  
B0  
K0  
P1  
W
Pin1  
Diameter Width (mm) (mm) (mm) (mm) (mm) Quadrant  
(mm) W1 (mm)  
ADC081C021CIMK/NOPB SOT  
DDC  
DDC  
6
6
1000  
3000  
178.0  
178.0  
8.4  
8.4  
3.2  
3.2  
3.2  
3.2  
1.4  
1.4  
4.0  
4.0  
8.0  
8.0  
Q3  
Q3  
ADC081C021CIMKX/NOP  
B
SOT  
ADC081C021CIMM/NOP VSSOP  
B
DGK  
DGK  
8
8
1000  
3500  
178.0  
330.0  
12.4  
12.4  
5.3  
5.3  
3.4  
3.4  
1.4  
1.4  
8.0  
8.0  
12.0  
12.0  
Q1  
Q1  
ADC081C021CIMMX/NO VSSOP  
PB  
ADC081C027CIMK/NOPB SOT  
DDC  
DDC  
6
6
1000  
3000  
178.0  
178.0  
8.4  
8.4  
3.2  
3.2  
3.2  
3.2  
1.4  
1.4  
4.0  
4.0  
8.0  
8.0  
Q3  
Q3  
ADC081C027CIMKX/NOP  
B
SOT  
Pack Materials-Page 1  
PACKAGE MATERIALS INFORMATION  
www.ti.com  
26-Mar-2013  
*All dimensions are nominal  
Device  
Package Type Package Drawing Pins  
SPQ  
Length (mm) Width (mm) Height (mm)  
ADC081C021CIMK/NOPB  
SOT  
SOT  
DDC  
DDC  
6
6
1000  
3000  
210.0  
210.0  
185.0  
185.0  
35.0  
35.0  
ADC081C021CIMKX/NOP  
B
ADC081C021CIMM/NOPB  
VSSOP  
VSSOP  
DGK  
DGK  
8
8
1000  
3500  
210.0  
367.0  
185.0  
367.0  
35.0  
35.0  
ADC081C021CIMMX/NOP  
B
ADC081C027CIMK/NOPB  
SOT  
SOT  
DDC  
DDC  
6
6
1000  
3000  
210.0  
210.0  
185.0  
185.0  
35.0  
35.0  
ADC081C027CIMKX/NOP  
B
Pack Materials-Page 2  
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